stats.txt (9312:e05e1b69ebf2) | stats.txt (9314:63e7cfff4188) |
---|---|
1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 1.950813 # Number of seconds simulated 4sim_ticks 1950813247500 # Number of ticks simulated 5final_tick 1950813247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.950814 # Number of seconds simulated 4sim_ticks 1950813955500 # Number of ticks simulated 5final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 1287440 # Simulator instruction rate (inst/s) 8host_op_rate 1287440 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41184614921 # Simulator tick rate (ticks/s) | 7host_inst_rate 770652 # Simulator instruction rate (inst/s) 8host_op_rate 770652 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24652738853 # Simulator tick rate (ticks/s) |
10host_mem_usage 325660 # Number of bytes of host memory used | 10host_mem_usage 325660 # Number of bytes of host memory used |
11host_seconds 47.37 # Real time elapsed on the host 12sim_insts 60982794 # Number of instructions simulated 13sim_ops 60982794 # Number of ops (including micro ops) simulated | 11host_seconds 79.13 # Real time elapsed on the host 12sim_insts 60983017 # Number of instructions simulated 13sim_ops 60983017 # Number of ops (including micro ops) simulated |
14system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory | 14system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory |
15system.physmem.bytes_read::cpu0.data 24727680 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu0.data 24727744 # Number of bytes read from this memory |
16system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory |
18system.physmem.bytes_read::cpu1.data 439808 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28684096 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu1.data 439872 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28684224 # Number of bytes read from this memory |
20system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory | 20system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory |
23system.physmem.bytes_written::writebacks 7706368 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7706368 # Number of bytes written to this memory | 23system.physmem.bytes_written::writebacks 7706496 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7706496 # Number of bytes written to this memory |
25system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory |
26system.physmem.num_reads::cpu0.data 386370 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu0.data 386371 # Number of read requests responded to by this memory |
27system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory |
29system.physmem.num_reads::cpu1.data 6872 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448189 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120412 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120412 # Number of write requests responded to by this memory | 29system.physmem.num_reads::cpu1.data 6873 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448191 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120414 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120414 # Number of write requests responded to by this memory |
33system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) |
34system.physmem.bw_read::cpu0.data 12675575 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1358859 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu0.data 12675603 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1358858 # Total read bandwidth from this memory (bytes/s) |
36system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) |
37system.physmem.bw_read::cpu1.data 225449 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14703661 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu1.data 225481 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14703721 # Total read bandwidth from this memory (bytes/s) |
39system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) | 39system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) |
42system.physmem.bw_write::writebacks 3950336 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3950336 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3950336 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_write::writebacks 3950400 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3950400 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3950400 # Total bandwidth to/from this memory (bytes/s) |
45system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) |
46system.physmem.bw_total::cpu0.data 12675575 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1358859 # Total bandwidth to/from this memory (bytes/s) | 46system.physmem.bw_total::cpu0.data 12675603 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1358858 # Total bandwidth to/from this memory (bytes/s) |
48system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) | 48system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) |
49system.physmem.bw_total::cpu1.data 225449 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18653997 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 448189 # Total number of read requests seen 52system.physmem.writeReqs 120412 # Total number of write requests seen 53system.physmem.cpureqs 599134 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28684096 # Total number of bytes read from memory 55system.physmem.bytesWritten 7706368 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28684096 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7706368 # bytesWritten derated as per pkt->getSize() | 49system.physmem.bw_total::cpu1.data 225481 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18654121 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 448191 # Total number of read requests seen 52system.physmem.writeReqs 120414 # Total number of write requests seen 53system.physmem.cpureqs 599152 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28684224 # Total number of bytes read from memory 55system.physmem.bytesWritten 7706496 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28684224 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7706496 # bytesWritten derated as per pkt->getSize() |
58system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q | 58system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q |
59system.physmem.neitherReadNorWrite 7172 # Reqs where no action is needed | 59system.physmem.neitherReadNorWrite 7175 # Reqs where no action is needed |
60system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis | 60system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis |
75system.physmem.perBankRdReqs::15 27647 # Track reads on a per bank basis | 75system.physmem.perBankRdReqs::15 27649 # Track reads on a per bank basis |
76system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis | 76system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis |
91system.physmem.perBankWrReqs::15 7157 # Track writes on a per bank basis | 91system.physmem.perBankWrReqs::15 7159 # Track writes on a per bank basis |
92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
93system.physmem.numWrRetry 522 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1950759532000 # Total gap between requests | 93system.physmem.numWrRetry 530 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1950760240000 # Total gap between requests |
95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes | 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes |
101system.physmem.readPktSize::6 448189 # Categorize read packet sizes | 101system.physmem.readPktSize::6 448191 # Categorize read packet sizes |
102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes | 102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes |
110system.physmem.writePktSize::6 120934 # categorize write packet sizes | 110system.physmem.writePktSize::6 120944 # categorize write packet sizes |
111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes | 111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes |
119system.physmem.neitherpktsize::6 7172 # categorize neither packet sizes | 119system.physmem.neitherpktsize::6 7175 # categorize neither packet sizes |
120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
122system.physmem.rdQLenPdf::0 409832 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 7493 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 5295 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 2367 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 2815 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2388 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 1774 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 1671 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1601 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1562 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1645 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1753 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1208 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1428 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 874 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 246 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 138 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see | 122system.physmem.rdQLenPdf::0 409750 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 7530 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 5264 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 2349 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 2844 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2407 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 1780 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 2013 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 1657 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 1935 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1586 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1572 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1655 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1735 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1232 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1426 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 881 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 259 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 108 # What read queue length does an incoming req see |
142system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see | 142system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see |
155system.physmem.wrQLenPdf::0 4346 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 5068 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 5119 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 5195 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5208 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5231 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::0 4348 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 4960 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 5066 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 5108 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 5181 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5197 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5228 # What write queue length does an incoming req see |
162system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see |
178system.physmem.wrQLenPdf::23 890 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 41 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see | 178system.physmem.wrQLenPdf::23 888 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 276 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 170 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 128 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 55 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 39 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see |
187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
188system.physmem.totQLat 2865774804 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 10947900804 # Sum of mem lat for all requests 190system.physmem.totBusLat 1792528000 # Total cycles spent in databus access 191system.physmem.totBankLat 6289598000 # Total cycles spent in bank access 192system.physmem.avgQLat 6394.93 # Average queueing delay per request 193system.physmem.avgBankLat 14035.15 # Average bank access latency per request | 188system.physmem.totQLat 2917085023 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 10998617023 # Sum of mem lat for all requests 190system.physmem.totBusLat 1792536000 # Total cycles spent in databus access 191system.physmem.totBankLat 6288996000 # Total cycles spent in bank access 192system.physmem.avgQLat 6509.40 # Average queueing delay per request 193system.physmem.avgBankLat 14033.74 # Average bank access latency per request |
194system.physmem.avgBusLat 4000.00 # Average bus latency per request | 194system.physmem.avgBusLat 4000.00 # Average bus latency per request |
195system.physmem.avgMemAccLat 24430.08 # Average memory access latency | 195system.physmem.avgMemAccLat 24543.14 # Average memory access latency |
196system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s 200system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.12 # Data bus utilization in percentage 202system.physmem.avgRdQLen 0.01 # Average read queue length over time | 196system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s 200system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.12 # Data bus utilization in percentage 202system.physmem.avgRdQLen 0.01 # Average read queue length over time |
203system.physmem.avgWrQLen 10.50 # Average write queue length over time 204system.physmem.readRowHits 428033 # Number of row buffer hits during reads 205system.physmem.writeRowHits 76777 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads | 203system.physmem.avgWrQLen 10.51 # Average write queue length over time 204system.physmem.readRowHits 428061 # Number of row buffer hits during reads 205system.physmem.writeRowHits 76773 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 95.52 # Row buffer hit rate for reads |
207system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes | 207system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes |
208system.physmem.avgGap 3430805.67 # Average gap between requests 209system.l2c.replacements 341333 # number of replacements 210system.l2c.tagsinuse 65247.038846 # Cycle average of tags in use 211system.l2c.total_refs 2438074 # Total number of references to valid blocks. 212system.l2c.sampled_refs 406309 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.000541 # Average number of references to valid blocks. | 208system.physmem.avgGap 3430782.78 # Average gap between requests 209system.l2c.replacements 341335 # number of replacements 210system.l2c.tagsinuse 65247.035905 # Cycle average of tags in use 211system.l2c.total_refs 2438054 # Total number of references to valid blocks. 212system.l2c.sampled_refs 406311 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.000463 # Average number of references to valid blocks. |
214system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. | 214system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. |
215system.l2c.occ_blocks::writebacks 55545.297156 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 4807.218464 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 4686.690338 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 164.376104 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 43.456784 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.847554 # Average percentage of cache occupancy | 215system.l2c.occ_blocks::writebacks 55545.332470 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 4807.217204 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 4686.652945 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 164.376424 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 43.456861 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.847555 # Average percentage of cache occupancy |
221system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy | 221system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy |
226system.l2c.ReadReq_hits::cpu0.inst 674220 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 658221 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 328583 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 113537 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1774561 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 791464 # number of Writeback hits 232system.l2c.Writeback_hits::total 791464 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits | 226system.l2c.ReadReq_hits::cpu0.inst 674205 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 658217 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 328581 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 113535 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1774538 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 791470 # number of Writeback hits 232system.l2c.Writeback_hits::total 791470 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 738 # number of UpgradeReq hits |
236system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits | 236system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits |
237system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 123896 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 48958 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 172854 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 674220 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 782117 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 328583 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 162495 # number of demand (read+write) hits 246system.l2c.demand_hits::total 1947415 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 674220 # number of overall hits 248system.l2c.overall_hits::cpu0.data 782117 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 328583 # number of overall hits 250system.l2c.overall_hits::cpu1.data 162495 # number of overall hits 251system.l2c.overall_hits::total 1947415 # number of overall hits | 237system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 123887 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 48972 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 172859 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 674205 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 782104 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 328581 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 162507 # number of demand (read+write) hits 246system.l2c.demand_hits::total 1947397 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 674205 # number of overall hits 248system.l2c.overall_hits::cpu0.data 782104 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 328581 # number of overall hits 250system.l2c.overall_hits::cpu1.data 162507 # number of overall hits 251system.l2c.overall_hits::total 1947397 # number of overall hits |
252system.l2c.ReadReq_misses::cpu0.inst 12926 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 271631 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 612 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 247 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 285416 # number of ReadReq misses | 252system.l2c.ReadReq_misses::cpu0.inst 12926 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 271631 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 612 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 247 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 285416 # number of ReadReq misses |
257system.l2c.UpgradeReq_misses::cpu0.data 2967 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 1807 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 4774 # number of UpgradeReq misses | 257system.l2c.UpgradeReq_misses::cpu0.data 2969 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 1806 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 4775 # number of UpgradeReq misses |
260system.l2c.SCUpgradeReq_misses::cpu0.data 939 # number of SCUpgradeReq misses | 260system.l2c.SCUpgradeReq_misses::cpu0.data 939 # number of SCUpgradeReq misses |
261system.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 1881 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 115504 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 6643 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 122147 # number of ReadExReq misses | 261system.l2c.SCUpgradeReq_misses::cpu1.data 944 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 1883 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 115505 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 6644 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 122149 # number of ReadExReq misses |
266system.l2c.demand_misses::cpu0.inst 12926 # number of demand (read+write) misses | 266system.l2c.demand_misses::cpu0.inst 12926 # number of demand (read+write) misses |
267system.l2c.demand_misses::cpu0.data 387135 # number of demand (read+write) misses | 267system.l2c.demand_misses::cpu0.data 387136 # number of demand (read+write) misses |
268system.l2c.demand_misses::cpu1.inst 612 # number of demand (read+write) misses | 268system.l2c.demand_misses::cpu1.inst 612 # number of demand (read+write) misses |
269system.l2c.demand_misses::cpu1.data 6890 # number of demand (read+write) misses 270system.l2c.demand_misses::total 407563 # number of demand (read+write) misses | 269system.l2c.demand_misses::cpu1.data 6891 # number of demand (read+write) misses 270system.l2c.demand_misses::total 407565 # number of demand (read+write) misses |
271system.l2c.overall_misses::cpu0.inst 12926 # number of overall misses | 271system.l2c.overall_misses::cpu0.inst 12926 # number of overall misses |
272system.l2c.overall_misses::cpu0.data 387135 # number of overall misses | 272system.l2c.overall_misses::cpu0.data 387136 # number of overall misses |
273system.l2c.overall_misses::cpu1.inst 612 # number of overall misses | 273system.l2c.overall_misses::cpu1.inst 612 # number of overall misses |
274system.l2c.overall_misses::cpu1.data 6890 # number of overall misses 275system.l2c.overall_misses::total 407563 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 713316000 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 11504038499 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 34128500 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 15210000 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 12266692999 # number of ReadReq miss cycles | 274system.l2c.overall_misses::cpu1.data 6891 # number of overall misses 275system.l2c.overall_misses::total 407565 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 706675500 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 11506519500 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 33342000 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 15821000 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 12262358000 # number of ReadReq miss cycles |
281system.l2c.UpgradeReq_miss_latency::cpu0.data 1244500 # number of UpgradeReq miss cycles | 281system.l2c.UpgradeReq_miss_latency::cpu0.data 1244500 # number of UpgradeReq miss cycles |
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308system.l2c.UpgradeReq_accesses::cpu1.data 2374 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 5517 # number of UpgradeReq accesses(hits+misses) | 308system.l2c.UpgradeReq_accesses::cpu1.data 2370 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 5513 # number of UpgradeReq accesses(hits+misses) |
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311system.l2c.SCUpgradeReq_accesses::cpu1.data 965 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 1940 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 239400 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 55601 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 295001 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 687146 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 1169252 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 329195 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 169385 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2354978 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 687146 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 1169252 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 329195 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 169385 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2354978 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.018811 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.292123 # miss rate for ReadReq accesses | 311system.l2c.SCUpgradeReq_accesses::cpu1.data 968 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 1943 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 239392 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 55616 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 295008 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 687131 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 1169240 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 329193 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 169398 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2354962 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 687131 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 1169240 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 329193 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 169398 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2354962 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.018812 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.292124 # miss rate for ReadReq accesses |
328system.l2c.ReadReq_miss_rate::cpu1.inst 0.001859 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.002171 # miss rate for ReadReq accesses | 328system.l2c.ReadReq_miss_rate::cpu1.inst 0.001859 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.002171 # miss rate for ReadReq accesses |
330system.l2c.ReadReq_miss_rate::total 0.138553 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944003 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.761163 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.865325 # miss rate for UpgradeReq accesses | 330system.l2c.ReadReq_miss_rate::total 0.138555 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944639 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.762025 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.866135 # miss rate for UpgradeReq accesses |
334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963077 # miss rate for SCUpgradeReq accesses | 334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963077 # miss rate for SCUpgradeReq accesses |
335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976166 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.969588 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.482473 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.119476 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.414056 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.018811 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.331096 # miss rate for demand accesses | 335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975207 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.969120 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.482493 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.119462 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.414053 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.018812 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.331101 # miss rate for demand accesses |
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347system.l2c.overall_miss_rate::cpu1.inst 0.001859 # miss rate for overall accesses | 347system.l2c.overall_miss_rate::cpu1.inst 0.001859 # miss rate for overall accesses |
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406system.l2c.demand_mshr_misses::cpu1.inst 601 # number of demand (read+write) MSHR misses | 406system.l2c.demand_mshr_misses::cpu1.inst 601 # number of demand (read+write) MSHR misses |
407system.l2c.demand_mshr_misses::cpu1.data 6890 # number of demand (read+write) MSHR misses 408system.l2c.demand_mshr_misses::total 407552 # number of demand (read+write) MSHR misses | 407system.l2c.demand_mshr_misses::cpu1.data 6891 # number of demand (read+write) MSHR misses 408system.l2c.demand_mshr_misses::total 407554 # number of demand (read+write) MSHR misses |
409system.l2c.overall_mshr_misses::cpu0.inst 12926 # number of overall MSHR misses | 409system.l2c.overall_mshr_misses::cpu0.inst 12926 # number of overall MSHR misses |
410system.l2c.overall_mshr_misses::cpu0.data 387135 # number of overall MSHR misses | 410system.l2c.overall_mshr_misses::cpu0.data 387136 # number of overall MSHR misses |
411system.l2c.overall_mshr_misses::cpu1.inst 601 # number of overall MSHR misses | 411system.l2c.overall_mshr_misses::cpu1.inst 601 # number of overall MSHR misses |
412system.l2c.overall_mshr_misses::cpu1.data 6890 # number of overall MSHR misses 413system.l2c.overall_mshr_misses::total 407552 # number of overall MSHR misses 414system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 549819387 # number of ReadReq MSHR miss cycles 415system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7975375490 # number of ReadReq MSHR miss cycles 416system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 25997165 # number of ReadReq MSHR miss cycles 417system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12059975 # number of ReadReq MSHR miss cycles 418system.l2c.ReadReq_mshr_miss_latency::total 8563252017 # number of ReadReq MSHR miss cycles 419system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29825962 # number of UpgradeReq MSHR miss cycles 420system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18084304 # number of UpgradeReq MSHR miss cycles 421system.l2c.UpgradeReq_mshr_miss_latency::total 47910266 # number of UpgradeReq MSHR miss cycles | 412system.l2c.overall_mshr_misses::cpu1.data 6891 # number of overall MSHR misses 413system.l2c.overall_mshr_misses::total 407554 # number of overall MSHR misses 414system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 543164896 # number of ReadReq MSHR miss cycles 415system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7977851486 # number of ReadReq MSHR miss cycles 416system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 25213167 # number of ReadReq MSHR miss cycles 417system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12672975 # number of ReadReq MSHR miss cycles 418system.l2c.ReadReq_mshr_miss_latency::total 8558902524 # number of ReadReq MSHR miss cycles 419system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29845964 # number of UpgradeReq MSHR miss cycles 420system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18081803 # number of UpgradeReq MSHR miss cycles 421system.l2c.UpgradeReq_mshr_miss_latency::total 47927767 # number of UpgradeReq MSHR miss cycles |
422system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9405923 # number of SCUpgradeReq MSHR miss cycles | 422system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9405923 # number of SCUpgradeReq MSHR miss cycles |
423system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9420942 # number of SCUpgradeReq MSHR miss cycles 424system.l2c.SCUpgradeReq_mshr_miss_latency::total 18826865 # number of SCUpgradeReq MSHR miss cycles 425system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4202676375 # number of ReadExReq MSHR miss cycles 426system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 343429954 # number of ReadExReq MSHR miss cycles 427system.l2c.ReadExReq_mshr_miss_latency::total 4546106329 # number of ReadExReq MSHR miss cycles 428system.l2c.demand_mshr_miss_latency::cpu0.inst 549819387 # number of demand (read+write) MSHR miss cycles 429system.l2c.demand_mshr_miss_latency::cpu0.data 12178051865 # number of demand (read+write) MSHR miss cycles 430system.l2c.demand_mshr_miss_latency::cpu1.inst 25997165 # number of demand (read+write) MSHR miss cycles 431system.l2c.demand_mshr_miss_latency::cpu1.data 355489929 # number of demand (read+write) MSHR miss cycles 432system.l2c.demand_mshr_miss_latency::total 13109358346 # number of demand (read+write) MSHR miss cycles 433system.l2c.overall_mshr_miss_latency::cpu0.inst 549819387 # number of overall MSHR miss cycles 434system.l2c.overall_mshr_miss_latency::cpu0.data 12178051865 # number of overall MSHR miss cycles 435system.l2c.overall_mshr_miss_latency::cpu1.inst 25997165 # number of overall MSHR miss cycles 436system.l2c.overall_mshr_miss_latency::cpu1.data 355489929 # number of overall MSHR miss cycles 437system.l2c.overall_mshr_miss_latency::total 13109358346 # number of overall MSHR miss cycles 438system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370389500 # number of ReadReq MSHR uncacheable cycles 439system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18130000 # number of ReadReq MSHR uncacheable cycles 440system.l2c.ReadReq_mshr_uncacheable_latency::total 1388519500 # number of ReadReq MSHR uncacheable cycles 441system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2151186500 # number of WriteReq MSHR uncacheable cycles 442system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 682990000 # number of WriteReq MSHR uncacheable cycles 443system.l2c.WriteReq_mshr_uncacheable_latency::total 2834176500 # number of WriteReq MSHR uncacheable cycles 444system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3521576000 # number of overall MSHR uncacheable cycles 445system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701120000 # number of overall MSHR uncacheable cycles 446system.l2c.overall_mshr_uncacheable_latency::total 4222696000 # number of overall MSHR uncacheable cycles 447system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292123 # mshr miss rate for ReadReq accesses | 423system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9440944 # number of SCUpgradeReq MSHR miss cycles 424system.l2c.SCUpgradeReq_mshr_miss_latency::total 18846867 # number of SCUpgradeReq MSHR miss cycles 425system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4207932893 # number of ReadExReq MSHR miss cycles 426system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 343549452 # number of ReadExReq MSHR miss cycles 427system.l2c.ReadExReq_mshr_miss_latency::total 4551482345 # number of ReadExReq MSHR miss cycles 428system.l2c.demand_mshr_miss_latency::cpu0.inst 543164896 # number of demand (read+write) MSHR miss cycles 429system.l2c.demand_mshr_miss_latency::cpu0.data 12185784379 # number of demand (read+write) MSHR miss cycles 430system.l2c.demand_mshr_miss_latency::cpu1.inst 25213167 # number of demand (read+write) MSHR miss cycles 431system.l2c.demand_mshr_miss_latency::cpu1.data 356222427 # number of demand (read+write) MSHR miss cycles 432system.l2c.demand_mshr_miss_latency::total 13110384869 # number of demand (read+write) MSHR miss cycles 433system.l2c.overall_mshr_miss_latency::cpu0.inst 543164896 # number of overall MSHR miss cycles 434system.l2c.overall_mshr_miss_latency::cpu0.data 12185784379 # number of overall MSHR miss cycles 435system.l2c.overall_mshr_miss_latency::cpu1.inst 25213167 # number of overall MSHR miss cycles 436system.l2c.overall_mshr_miss_latency::cpu1.data 356222427 # number of overall MSHR miss cycles 437system.l2c.overall_mshr_miss_latency::total 13110384869 # number of overall MSHR miss cycles 438system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373080000 # number of ReadReq MSHR uncacheable cycles 439system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18172000 # number of ReadReq MSHR uncacheable cycles 440system.l2c.ReadReq_mshr_uncacheable_latency::total 1391252000 # number of ReadReq MSHR uncacheable cycles 441system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2155311500 # number of WriteReq MSHR uncacheable cycles 442system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 683999000 # number of WriteReq MSHR uncacheable cycles 443system.l2c.WriteReq_mshr_uncacheable_latency::total 2839310500 # number of WriteReq MSHR uncacheable cycles 444system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3528391500 # number of overall MSHR uncacheable cycles 445system.l2c.overall_mshr_uncacheable_latency::cpu1.data 702171000 # number of overall MSHR uncacheable cycles 446system.l2c.overall_mshr_uncacheable_latency::total 4230562500 # number of overall MSHR uncacheable cycles 447system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292124 # mshr miss rate for ReadReq accesses |
449system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses | 449system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses |
451system.l2c.ReadReq_mshr_miss_rate::total 0.138548 # mshr miss rate for ReadReq accesses 452system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944003 # mshr miss rate for UpgradeReq accesses 453system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.761163 # mshr miss rate for UpgradeReq accesses 454system.l2c.UpgradeReq_mshr_miss_rate::total 0.865325 # mshr miss rate for UpgradeReq accesses | 451system.l2c.ReadReq_mshr_miss_rate::total 0.138549 # mshr miss rate for ReadReq accesses 452system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944639 # mshr miss rate for UpgradeReq accesses 453system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.762025 # mshr miss rate for UpgradeReq accesses 454system.l2c.UpgradeReq_mshr_miss_rate::total 0.866135 # mshr miss rate for UpgradeReq accesses |
455system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses | 455system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses |
456system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976166 # mshr miss rate for SCUpgradeReq accesses 457system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969588 # mshr miss rate for SCUpgradeReq accesses 458system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482473 # mshr miss rate for ReadExReq accesses 459system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119476 # mshr miss rate for ReadExReq accesses 460system.l2c.ReadExReq_mshr_miss_rate::total 0.414056 # mshr miss rate for ReadExReq accesses 461system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for demand accesses | 456system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975207 # mshr miss rate for SCUpgradeReq accesses 457system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969120 # mshr miss rate for SCUpgradeReq accesses 458system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482493 # mshr miss rate for ReadExReq accesses 459system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119462 # mshr miss rate for ReadExReq accesses 460system.l2c.ReadExReq_mshr_miss_rate::total 0.414053 # mshr miss rate for ReadExReq accesses 461system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for demand accesses |
463system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses | 463system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses |
464system.l2c.demand_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::total 0.173060 # mshr miss rate for demand accesses 466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for overall accesses 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for overall accesses | 464system.l2c.demand_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::total 0.173062 # mshr miss rate for demand accesses 466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018812 # mshr miss rate for overall accesses 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.331101 # mshr miss rate for overall accesses |
468system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses | 468system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses |
469system.l2c.overall_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::total 0.173060 # mshr miss rate for overall accesses 471system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average ReadReq mshr miss latency 472system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29361.065158 # average ReadReq mshr miss latency 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48825.809717 # average ReadReq mshr miss latency 475system.l2c.ReadReq_avg_mshr_miss_latency::total 30003.861239 # average ReadReq mshr miss latency 476system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.565554 # average UpgradeReq mshr miss latency 477system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10007.915883 # average UpgradeReq mshr miss latency 478system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.665270 # average UpgradeReq mshr miss latency | 469system.l2c.overall_mshr_miss_rate::cpu1.data 0.040679 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::total 0.173062 # mshr miss rate for overall accesses 471system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average ReadReq mshr miss latency 472system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29370.180451 # average ReadReq mshr miss latency 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 51307.591093 # average ReadReq mshr miss latency 475system.l2c.ReadReq_avg_mshr_miss_latency::total 29988.621517 # average ReadReq mshr miss latency 476system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.530818 # average UpgradeReq mshr miss latency 477system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.072536 # average UpgradeReq mshr miss latency 478system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.228691 # average UpgradeReq mshr miss latency |
479system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency 480system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency | 479system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency 480system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency |
481system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.965976 # average SCUpgradeReq mshr miss latency 482system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36385.548336 # average ReadExReq mshr miss latency 483system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51698.021075 # average ReadExReq mshr miss latency 484system.l2c.ReadExReq_avg_mshr_miss_latency::total 37218.321604 # average ReadExReq mshr miss latency 485system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency 486system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency 487system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency 488system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency 489system.l2c.demand_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency 490system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency 491system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency 492system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency 493system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency 494system.l2c.overall_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency | 481system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.957515 # average SCUpgradeReq mshr miss latency 482system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36430.742332 # average ReadExReq mshr miss latency 483system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51708.225768 # average ReadExReq mshr miss latency 484system.l2c.ReadExReq_avg_mshr_miss_latency::total 37261.724165 # average ReadExReq mshr miss latency 485system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency 486system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency 487system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency 488system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency 489system.l2c.demand_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency 490system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42021.112177 # average overall mshr miss latency 491system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31476.753335 # average overall mshr miss latency 492system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41952.024958 # average overall mshr miss latency 493system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51693.865477 # average overall mshr miss latency 494system.l2c.overall_avg_mshr_miss_latency::total 32168.460790 # average overall mshr miss latency |
495system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 496system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 497system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 498system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 499system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 500system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 501system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 502system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 503system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 504system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 505system.iocache.replacements 41696 # number of replacements | 495system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 496system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 497system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 498system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 499system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 500system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 501system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 502system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 503system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 504system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 505system.iocache.replacements 41696 # number of replacements |
506system.iocache.tagsinuse 0.562945 # Cycle average of tags in use | 506system.iocache.tagsinuse 0.562950 # Cycle average of tags in use |
507system.iocache.total_refs 0 # Total number of references to valid blocks. 508system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. 509system.iocache.avg_refs 0 # Average number of references to valid blocks. 510system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. | 507system.iocache.total_refs 0 # Total number of references to valid blocks. 508system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. 509system.iocache.avg_refs 0 # Average number of references to valid blocks. 510system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. |
511system.iocache.occ_blocks::tsunami.ide 0.562945 # Average occupied blocks per requestor | 511system.iocache.occ_blocks::tsunami.ide 0.562950 # Average occupied blocks per requestor |
512system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy 513system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy 514system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 515system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 516system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 517system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 518system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 519system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 520system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 521system.iocache.overall_misses::total 41728 # number of overall misses 522system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles 523system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles | 512system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy 513system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy 514system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 515system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 516system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 517system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 518system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 519system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 520system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 521system.iocache.overall_misses::total 41728 # number of overall misses 522system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles 523system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles |
524system.iocache.WriteReq_miss_latency::tsunami.ide 9455401806 # number of WriteReq miss cycles 525system.iocache.WriteReq_miss_latency::total 9455401806 # number of WriteReq miss cycles 526system.iocache.demand_miss_latency::tsunami.ide 9476670804 # number of demand (read+write) miss cycles 527system.iocache.demand_miss_latency::total 9476670804 # number of demand (read+write) miss cycles 528system.iocache.overall_miss_latency::tsunami.ide 9476670804 # number of overall miss cycles 529system.iocache.overall_miss_latency::total 9476670804 # number of overall miss cycles | 524system.iocache.WriteReq_miss_latency::tsunami.ide 9497531806 # number of WriteReq miss cycles 525system.iocache.WriteReq_miss_latency::total 9497531806 # number of WriteReq miss cycles 526system.iocache.demand_miss_latency::tsunami.ide 9518800804 # number of demand (read+write) miss cycles 527system.iocache.demand_miss_latency::total 9518800804 # number of demand (read+write) miss cycles 528system.iocache.overall_miss_latency::tsunami.ide 9518800804 # number of overall miss cycles 529system.iocache.overall_miss_latency::total 9518800804 # number of overall miss cycles |
530system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 531system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 532system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 533system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 534system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 535system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 536system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 537system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 538system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 539system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 540system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 541system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 542system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 543system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 544system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 545system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 546system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency 547system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency | 530system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 531system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 532system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 533system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 534system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 535system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 536system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 537system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 538system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 539system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 540system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 541system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 542system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 543system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 544system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 545system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 546system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency 547system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency |
548system.iocache.WriteReq_avg_miss_latency::tsunami.ide 227555.877118 # average WriteReq miss latency 549system.iocache.WriteReq_avg_miss_latency::total 227555.877118 # average WriteReq miss latency 550system.iocache.demand_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency 551system.iocache.demand_avg_miss_latency::total 227105.799559 # average overall miss latency 552system.iocache.overall_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency 553system.iocache.overall_avg_miss_latency::total 227105.799559 # average overall miss latency 554system.iocache.blocked_cycles::no_mshrs 186741 # number of cycles access was blocked | 548system.iocache.WriteReq_avg_miss_latency::tsunami.ide 228569.787399 # average WriteReq miss latency 549system.iocache.WriteReq_avg_miss_latency::total 228569.787399 # average WriteReq miss latency 550system.iocache.demand_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency 551system.iocache.demand_avg_miss_latency::total 228115.433378 # average overall miss latency 552system.iocache.overall_avg_miss_latency::tsunami.ide 228115.433378 # average overall miss latency 553system.iocache.overall_avg_miss_latency::total 228115.433378 # average overall miss latency 554system.iocache.blocked_cycles::no_mshrs 188605 # number of cycles access was blocked |
555system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 555system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
556system.iocache.blocked::no_mshrs 23044 # number of cycles access was blocked | 556system.iocache.blocked::no_mshrs 22594 # number of cycles access was blocked |
557system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 557system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
558system.iocache.avg_blocked_cycles::no_mshrs 8.103671 # average number of cycles each access was blocked | 558system.iocache.avg_blocked_cycles::no_mshrs 8.347570 # average number of cycles each access was blocked |
559system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 560system.iocache.fast_writes 0 # number of fast writes performed 561system.iocache.cache_copies 0 # number of cache copies performed 562system.iocache.writebacks::writebacks 41520 # number of writebacks 563system.iocache.writebacks::total 41520 # number of writebacks 564system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 565system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 566system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 567system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 568system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 569system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 570system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 571system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 572system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles 573system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles | 559system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 560system.iocache.fast_writes 0 # number of fast writes performed 561system.iocache.cache_copies 0 # number of cache copies performed 562system.iocache.writebacks::writebacks 41520 # number of writebacks 563system.iocache.writebacks::total 41520 # number of writebacks 564system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 565system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 566system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 567system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 568system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 569system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 570system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 571system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 572system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles 573system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles |
574system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7292629022 # number of WriteReq MSHR miss cycles 575system.iocache.WriteReq_mshr_miss_latency::total 7292629022 # number of WriteReq MSHR miss cycles 576system.iocache.demand_mshr_miss_latency::tsunami.ide 7304745022 # number of demand (read+write) MSHR miss cycles 577system.iocache.demand_mshr_miss_latency::total 7304745022 # number of demand (read+write) MSHR miss cycles 578system.iocache.overall_mshr_miss_latency::tsunami.ide 7304745022 # number of overall MSHR miss cycles 579system.iocache.overall_mshr_miss_latency::total 7304745022 # number of overall MSHR miss cycles | 574system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7334778982 # number of WriteReq MSHR miss cycles 575system.iocache.WriteReq_mshr_miss_latency::total 7334778982 # number of WriteReq MSHR miss cycles 576system.iocache.demand_mshr_miss_latency::tsunami.ide 7346894982 # number of demand (read+write) MSHR miss cycles 577system.iocache.demand_mshr_miss_latency::total 7346894982 # number of demand (read+write) MSHR miss cycles 578system.iocache.overall_mshr_miss_latency::tsunami.ide 7346894982 # number of overall MSHR miss cycles 579system.iocache.overall_mshr_miss_latency::total 7346894982 # number of overall MSHR miss cycles |
580system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 581system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 582system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 583system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 584system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 585system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 586system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 587system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 588system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency 589system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency | 580system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 581system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 582system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 583system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 584system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 585system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 586system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 587system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 588system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency 589system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency |
590system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175506.089286 # average WriteReq mshr miss latency 591system.iocache.WriteReq_avg_mshr_miss_latency::total 175506.089286 # average WriteReq mshr miss latency 592system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency 593system.iocache.demand_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency 594system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency 595system.iocache.overall_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency | 590system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 176520.479929 # average WriteReq mshr miss latency 591system.iocache.WriteReq_avg_mshr_miss_latency::total 176520.479929 # average WriteReq mshr miss latency 592system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency 593system.iocache.demand_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency 594system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 176066.309960 # average overall mshr miss latency 595system.iocache.overall_avg_mshr_miss_latency::total 176066.309960 # average overall mshr miss latency |
596system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 597system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 598system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 599system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 600system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 601system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 602system.disk0.dma_write_txs 395 # Number of DMA write transactions. 603system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 604system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 605system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 606system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 607system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 608system.disk2.dma_write_txs 1 # Number of DMA write transactions. 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 596system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 597system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 598system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 599system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 600system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 601system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 602system.disk0.dma_write_txs 395 # Number of DMA write transactions. 603system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 604system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 605system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 606system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 607system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 608system.disk2.dma_write_txs 1 # Number of DMA write transactions. 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
613system.cpu0.dtb.read_hits 7424678 # DTB read hits | 613system.cpu0.dtb.read_hits 7424685 # DTB read hits |
614system.cpu0.dtb.read_misses 7443 # DTB read misses 615system.cpu0.dtb.read_acv 210 # DTB read access violations 616system.cpu0.dtb.read_accesses 490673 # DTB read accesses | 614system.cpu0.dtb.read_misses 7443 # DTB read misses 615system.cpu0.dtb.read_acv 210 # DTB read access violations 616system.cpu0.dtb.read_accesses 490673 # DTB read accesses |
617system.cpu0.dtb.write_hits 5011102 # DTB write hits | 617system.cpu0.dtb.write_hits 5011105 # DTB write hits |
618system.cpu0.dtb.write_misses 813 # DTB write misses 619system.cpu0.dtb.write_acv 134 # DTB write access violations 620system.cpu0.dtb.write_accesses 187452 # DTB write accesses | 618system.cpu0.dtb.write_misses 813 # DTB write misses 619system.cpu0.dtb.write_acv 134 # DTB write access violations 620system.cpu0.dtb.write_accesses 187452 # DTB write accesses |
621system.cpu0.dtb.data_hits 12435780 # DTB hits | 621system.cpu0.dtb.data_hits 12435790 # DTB hits |
622system.cpu0.dtb.data_misses 8256 # DTB misses 623system.cpu0.dtb.data_acv 344 # DTB access violations 624system.cpu0.dtb.data_accesses 678125 # DTB accesses 625system.cpu0.itb.fetch_hits 3481701 # ITB hits 626system.cpu0.itb.fetch_misses 3871 # ITB misses 627system.cpu0.itb.fetch_acv 184 # ITB acv 628system.cpu0.itb.fetch_accesses 3485572 # ITB accesses 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses | 622system.cpu0.dtb.data_misses 8256 # DTB misses 623system.cpu0.dtb.data_acv 344 # DTB access violations 624system.cpu0.dtb.data_accesses 678125 # DTB accesses 625system.cpu0.itb.fetch_hits 3481701 # ITB hits 626system.cpu0.itb.fetch_misses 3871 # ITB misses 627system.cpu0.itb.fetch_acv 184 # ITB acv 628system.cpu0.itb.fetch_accesses 3485572 # ITB accesses 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses |
641system.cpu0.numCycles 3900399022 # number of cpu cycles simulated | 641system.cpu0.numCycles 3900399041 # number of cpu cycles simulated |
642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
644system.cpu0.committedInsts 47350752 # Number of instructions committed 645system.cpu0.committedOps 47350752 # Number of ops (including micro ops) committed 646system.cpu0.num_int_alu_accesses 43919757 # Number of integer alu accesses | 644system.cpu0.committedInsts 47350784 # Number of instructions committed 645system.cpu0.committedOps 47350784 # Number of ops (including micro ops) committed 646system.cpu0.num_int_alu_accesses 43919786 # Number of integer alu accesses |
647system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses 648system.cpu0.num_func_calls 1188579 # number of times a function call or return occured | 647system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses 648system.cpu0.num_func_calls 1188579 # number of times a function call or return occured |
649system.cpu0.num_conditional_control_insts 5567605 # number of instructions that are conditional controls 650system.cpu0.num_int_insts 43919757 # number of integer instructions | 649system.cpu0.num_conditional_control_insts 5567614 # number of instructions that are conditional controls 650system.cpu0.num_int_insts 43919786 # number of integer instructions |
651system.cpu0.num_fp_insts 206365 # number of float instructions | 651system.cpu0.num_fp_insts 206365 # number of float instructions |
652system.cpu0.num_int_register_reads 60378447 # number of times the integer registers were read 653system.cpu0.num_int_register_writes 32741783 # number of times the integer registers were written | 652system.cpu0.num_int_register_reads 60378491 # number of times the integer registers were read 653system.cpu0.num_int_register_writes 32741801 # number of times the integer registers were written |
654system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read 655system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written | 654system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read 655system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written |
656system.cpu0.num_mem_refs 12475681 # number of memory refs 657system.cpu0.num_load_insts 7451619 # Number of load instructions 658system.cpu0.num_store_insts 5024062 # Number of store instructions 659system.cpu0.num_idle_cycles 3698907701.219057 # Number of idle cycles 660system.cpu0.num_busy_cycles 201491320.780943 # Number of busy cycles 661system.cpu0.not_idle_fraction 0.051659 # Percentage of non-idle cycles 662system.cpu0.idle_fraction 0.948341 # Percentage of idle cycles | 656system.cpu0.num_mem_refs 12475691 # number of memory refs 657system.cpu0.num_load_insts 7451626 # Number of load instructions 658system.cpu0.num_store_insts 5024065 # Number of store instructions 659system.cpu0.num_idle_cycles 3698902228.116945 # Number of idle cycles 660system.cpu0.num_busy_cycles 201496812.883055 # Number of busy cycles 661system.cpu0.not_idle_fraction 0.051661 # Percentage of non-idle cycles 662system.cpu0.idle_fraction 0.948339 # Percentage of idle cycles |
663system.cpu0.kern.inst.arm 0 # number of arm instructions executed 664system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed 665system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed 666system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl 667system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl 668system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl 669system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl 670system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl 671system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl 672system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl 673system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl 674system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl 675system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl 676system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl 677system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl | 663system.cpu0.kern.inst.arm 0 # number of arm instructions executed 664system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed 665system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed 666system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl 667system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl 668system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl 669system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl 670system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl 671system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl 672system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl 673system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl 674system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl 675system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl 676system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl 677system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl |
678system.cpu0.kern.ipl_ticks::0 1898626830000 97.36% 97.36% # number of cycles we spent at this ipl 679system.cpu0.kern.ipl_ticks::21 93050500 0.00% 97.36% # number of cycles we spent at this ipl 680system.cpu0.kern.ipl_ticks::22 759970000 0.04% 97.40% # number of cycles we spent at this ipl 681system.cpu0.kern.ipl_ticks::30 326793000 0.02% 97.42% # number of cycles we spent at this ipl 682system.cpu0.kern.ipl_ticks::31 50392837500 2.58% 100.00% # number of cycles we spent at this ipl 683system.cpu0.kern.ipl_ticks::total 1950199481000 # number of cycles we spent at this ipl | 678system.cpu0.kern.ipl_ticks::0 1898623862000 97.36% 97.36% # number of cycles we spent at this ipl 679system.cpu0.kern.ipl_ticks::21 92984000 0.00% 97.36% # number of cycles we spent at this ipl 680system.cpu0.kern.ipl_ticks::22 759861500 0.04% 97.40% # number of cycles we spent at this ipl 681system.cpu0.kern.ipl_ticks::30 328899000 0.02% 97.42% # number of cycles we spent at this ipl 682system.cpu0.kern.ipl_ticks::31 50393884000 2.58% 100.00% # number of cycles we spent at this ipl 683system.cpu0.kern.ipl_ticks::total 1950199490500 # number of cycles we spent at this ipl |
684system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl 685system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 686system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 687system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 688system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl 689system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl 690system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 691system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed --- 48 unchanged lines hidden (view full) --- 740system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 741system.cpu0.kern.mode_good::kernel 1283 742system.cpu0.kern.mode_good::user 1283 743system.cpu0.kern.mode_good::idle 0 744system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches 745system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 746system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 747system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches | 684system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl 685system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 686system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 687system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 688system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl 689system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl 690system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 691system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed --- 48 unchanged lines hidden (view full) --- 740system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 741system.cpu0.kern.mode_good::kernel 1283 742system.cpu0.kern.mode_good::user 1283 743system.cpu0.kern.mode_good::idle 0 744system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches 745system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 746system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 747system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches |
748system.cpu0.kern.mode_ticks::kernel 1946498286500 99.83% 99.83% # number of ticks spent at the given mode 749system.cpu0.kern.mode_ticks::user 3408187000 0.17% 100.00% # number of ticks spent at the given mode | 748system.cpu0.kern.mode_ticks::kernel 1946502716500 99.83% 99.83% # number of ticks spent at the given mode 749system.cpu0.kern.mode_ticks::user 3403122000 0.17% 100.00% # number of ticks spent at the given mode |
750system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 751system.cpu0.kern.swap_context 3025 # number of times the context was actually changed 752system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 753system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 754system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 755system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 756system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 757system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post --- 17 unchanged lines hidden (view full) --- 775system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 776system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 777system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 778system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 779system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 780system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 781system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 782system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 750system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 751system.cpu0.kern.swap_context 3025 # number of times the context was actually changed 752system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 753system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 754system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 755system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 756system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 757system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post --- 17 unchanged lines hidden (view full) --- 775system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 776system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 777system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 778system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 779system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 780system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 781system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 782system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
783system.cpu0.icache.replacements 686559 # number of replacements 784system.cpu0.icache.tagsinuse 509.179293 # Cycle average of tags in use 785system.cpu0.icache.total_refs 46672188 # Total number of references to valid blocks. 786system.cpu0.icache.sampled_refs 687071 # Sample count of references to valid blocks. 787system.cpu0.icache.avg_refs 67.929207 # Average number of references to valid blocks. | 783system.cpu0.icache.replacements 686544 # number of replacements 784system.cpu0.icache.tagsinuse 509.179305 # Cycle average of tags in use 785system.cpu0.icache.total_refs 46672235 # Total number of references to valid blocks. 786system.cpu0.icache.sampled_refs 687056 # Sample count of references to valid blocks. 787system.cpu0.icache.avg_refs 67.930758 # Average number of references to valid blocks. |
788system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. | 788system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. |
789system.cpu0.icache.occ_blocks::cpu0.inst 509.179293 # Average occupied blocks per requestor | 789system.cpu0.icache.occ_blocks::cpu0.inst 509.179305 # Average occupied blocks per requestor |
790system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy 791system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy | 790system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy 791system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy |
792system.cpu0.icache.ReadReq_hits::cpu0.inst 46672188 # number of ReadReq hits 793system.cpu0.icache.ReadReq_hits::total 46672188 # number of ReadReq hits 794system.cpu0.icache.demand_hits::cpu0.inst 46672188 # number of demand (read+write) hits 795system.cpu0.icache.demand_hits::total 46672188 # number of demand (read+write) hits 796system.cpu0.icache.overall_hits::cpu0.inst 46672188 # number of overall hits 797system.cpu0.icache.overall_hits::total 46672188 # number of overall hits 798system.cpu0.icache.ReadReq_misses::cpu0.inst 687164 # number of ReadReq misses 799system.cpu0.icache.ReadReq_misses::total 687164 # number of ReadReq misses 800system.cpu0.icache.demand_misses::cpu0.inst 687164 # number of demand (read+write) misses 801system.cpu0.icache.demand_misses::total 687164 # number of demand (read+write) misses 802system.cpu0.icache.overall_misses::cpu0.inst 687164 # number of overall misses 803system.cpu0.icache.overall_misses::total 687164 # number of overall misses 804system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9577778500 # number of ReadReq miss cycles 805system.cpu0.icache.ReadReq_miss_latency::total 9577778500 # number of ReadReq miss cycles 806system.cpu0.icache.demand_miss_latency::cpu0.inst 9577778500 # number of demand (read+write) miss cycles 807system.cpu0.icache.demand_miss_latency::total 9577778500 # number of demand (read+write) miss cycles 808system.cpu0.icache.overall_miss_latency::cpu0.inst 9577778500 # number of overall miss cycles 809system.cpu0.icache.overall_miss_latency::total 9577778500 # number of overall miss cycles 810system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359352 # number of ReadReq accesses(hits+misses) 811system.cpu0.icache.ReadReq_accesses::total 47359352 # number of ReadReq accesses(hits+misses) 812system.cpu0.icache.demand_accesses::cpu0.inst 47359352 # number of demand (read+write) accesses 813system.cpu0.icache.demand_accesses::total 47359352 # number of demand (read+write) accesses 814system.cpu0.icache.overall_accesses::cpu0.inst 47359352 # number of overall (read+write) accesses 815system.cpu0.icache.overall_accesses::total 47359352 # number of overall (read+write) accesses 816system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014510 # miss rate for ReadReq accesses 817system.cpu0.icache.ReadReq_miss_rate::total 0.014510 # miss rate for ReadReq accesses 818system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014510 # miss rate for demand accesses 819system.cpu0.icache.demand_miss_rate::total 0.014510 # miss rate for demand accesses 820system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014510 # miss rate for overall accesses 821system.cpu0.icache.overall_miss_rate::total 0.014510 # miss rate for overall accesses 822system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13938.126124 # average ReadReq miss latency 823system.cpu0.icache.ReadReq_avg_miss_latency::total 13938.126124 # average ReadReq miss latency 824system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency 825system.cpu0.icache.demand_avg_miss_latency::total 13938.126124 # average overall miss latency 826system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency 827system.cpu0.icache.overall_avg_miss_latency::total 13938.126124 # average overall miss latency | 792system.cpu0.icache.ReadReq_hits::cpu0.inst 46672235 # number of ReadReq hits 793system.cpu0.icache.ReadReq_hits::total 46672235 # number of ReadReq hits 794system.cpu0.icache.demand_hits::cpu0.inst 46672235 # number of demand (read+write) hits 795system.cpu0.icache.demand_hits::total 46672235 # number of demand (read+write) hits 796system.cpu0.icache.overall_hits::cpu0.inst 46672235 # number of overall hits 797system.cpu0.icache.overall_hits::total 46672235 # number of overall hits 798system.cpu0.icache.ReadReq_misses::cpu0.inst 687149 # number of ReadReq misses 799system.cpu0.icache.ReadReq_misses::total 687149 # number of ReadReq misses 800system.cpu0.icache.demand_misses::cpu0.inst 687149 # number of demand (read+write) misses 801system.cpu0.icache.demand_misses::total 687149 # number of demand (read+write) misses 802system.cpu0.icache.overall_misses::cpu0.inst 687149 # number of overall misses 803system.cpu0.icache.overall_misses::total 687149 # number of overall misses 804system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9571696500 # number of ReadReq miss cycles 805system.cpu0.icache.ReadReq_miss_latency::total 9571696500 # number of ReadReq miss cycles 806system.cpu0.icache.demand_miss_latency::cpu0.inst 9571696500 # number of demand (read+write) miss cycles 807system.cpu0.icache.demand_miss_latency::total 9571696500 # number of demand (read+write) miss cycles 808system.cpu0.icache.overall_miss_latency::cpu0.inst 9571696500 # number of overall miss cycles 809system.cpu0.icache.overall_miss_latency::total 9571696500 # number of overall miss cycles 810system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359384 # number of ReadReq accesses(hits+misses) 811system.cpu0.icache.ReadReq_accesses::total 47359384 # number of ReadReq accesses(hits+misses) 812system.cpu0.icache.demand_accesses::cpu0.inst 47359384 # number of demand (read+write) accesses 813system.cpu0.icache.demand_accesses::total 47359384 # number of demand (read+write) accesses 814system.cpu0.icache.overall_accesses::cpu0.inst 47359384 # number of overall (read+write) accesses 815system.cpu0.icache.overall_accesses::total 47359384 # number of overall (read+write) accesses 816system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014509 # miss rate for ReadReq accesses 817system.cpu0.icache.ReadReq_miss_rate::total 0.014509 # miss rate for ReadReq accesses 818system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014509 # miss rate for demand accesses 819system.cpu0.icache.demand_miss_rate::total 0.014509 # miss rate for demand accesses 820system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014509 # miss rate for overall accesses 821system.cpu0.icache.overall_miss_rate::total 0.014509 # miss rate for overall accesses 822system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13929.579320 # average ReadReq miss latency 823system.cpu0.icache.ReadReq_avg_miss_latency::total 13929.579320 # average ReadReq miss latency 824system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency 825system.cpu0.icache.demand_avg_miss_latency::total 13929.579320 # average overall miss latency 826system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13929.579320 # average overall miss latency 827system.cpu0.icache.overall_avg_miss_latency::total 13929.579320 # average overall miss latency |
828system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 829system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 830system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 831system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 832system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 833system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 834system.cpu0.icache.fast_writes 0 # number of fast writes performed 835system.cpu0.icache.cache_copies 0 # number of cache copies performed | 828system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 829system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 830system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 831system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 832system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 833system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 834system.cpu0.icache.fast_writes 0 # number of fast writes performed 835system.cpu0.icache.cache_copies 0 # number of cache copies performed |
836system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687164 # number of ReadReq MSHR misses 837system.cpu0.icache.ReadReq_mshr_misses::total 687164 # number of ReadReq MSHR misses 838system.cpu0.icache.demand_mshr_misses::cpu0.inst 687164 # number of demand (read+write) MSHR misses 839system.cpu0.icache.demand_mshr_misses::total 687164 # number of demand (read+write) MSHR misses 840system.cpu0.icache.overall_mshr_misses::cpu0.inst 687164 # number of overall MSHR misses 841system.cpu0.icache.overall_mshr_misses::total 687164 # number of overall MSHR misses 842system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8203450500 # number of ReadReq MSHR miss cycles 843system.cpu0.icache.ReadReq_mshr_miss_latency::total 8203450500 # number of ReadReq MSHR miss cycles 844system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8203450500 # number of demand (read+write) MSHR miss cycles 845system.cpu0.icache.demand_mshr_miss_latency::total 8203450500 # number of demand (read+write) MSHR miss cycles 846system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8203450500 # number of overall MSHR miss cycles 847system.cpu0.icache.overall_mshr_miss_latency::total 8203450500 # number of overall MSHR miss cycles 848system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for ReadReq accesses 849system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014510 # mshr miss rate for ReadReq accesses 850system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for demand accesses 851system.cpu0.icache.demand_mshr_miss_rate::total 0.014510 # mshr miss rate for demand accesses 852system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for overall accesses 853system.cpu0.icache.overall_mshr_miss_rate::total 0.014510 # mshr miss rate for overall accesses 854system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average ReadReq mshr miss latency 855system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11938.126124 # average ReadReq mshr miss latency 856system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency 857system.cpu0.icache.demand_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency 858system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency 859system.cpu0.icache.overall_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency | 836system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687149 # number of ReadReq MSHR misses 837system.cpu0.icache.ReadReq_mshr_misses::total 687149 # number of ReadReq MSHR misses 838system.cpu0.icache.demand_mshr_misses::cpu0.inst 687149 # number of demand (read+write) MSHR misses 839system.cpu0.icache.demand_mshr_misses::total 687149 # number of demand (read+write) MSHR misses 840system.cpu0.icache.overall_mshr_misses::cpu0.inst 687149 # number of overall MSHR misses 841system.cpu0.icache.overall_mshr_misses::total 687149 # number of overall MSHR misses 842system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8197398500 # number of ReadReq MSHR miss cycles 843system.cpu0.icache.ReadReq_mshr_miss_latency::total 8197398500 # number of ReadReq MSHR miss cycles 844system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8197398500 # number of demand (read+write) MSHR miss cycles 845system.cpu0.icache.demand_mshr_miss_latency::total 8197398500 # number of demand (read+write) MSHR miss cycles 846system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8197398500 # number of overall MSHR miss cycles 847system.cpu0.icache.overall_mshr_miss_latency::total 8197398500 # number of overall MSHR miss cycles 848system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for ReadReq accesses 849system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014509 # mshr miss rate for ReadReq accesses 850system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for demand accesses 851system.cpu0.icache.demand_mshr_miss_rate::total 0.014509 # mshr miss rate for demand accesses 852system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014509 # mshr miss rate for overall accesses 853system.cpu0.icache.overall_mshr_miss_rate::total 0.014509 # mshr miss rate for overall accesses 854system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average ReadReq mshr miss latency 855system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11929.579320 # average ReadReq mshr miss latency 856system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency 857system.cpu0.icache.demand_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency 858system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11929.579320 # average overall mshr miss latency 859system.cpu0.icache.overall_avg_mshr_miss_latency::total 11929.579320 # average overall mshr miss latency |
860system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 860system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
861system.cpu0.dcache.replacements 1171741 # number of replacements 862system.cpu0.dcache.tagsinuse 505.264481 # Cycle average of tags in use 863system.cpu0.dcache.total_refs 11253752 # Total number of references to valid blocks. 864system.cpu0.dcache.sampled_refs 1172158 # Sample count of references to valid blocks. 865system.cpu0.dcache.avg_refs 9.600883 # Average number of references to valid blocks. | 861system.cpu0.dcache.replacements 1171731 # number of replacements 862system.cpu0.dcache.tagsinuse 505.264467 # Cycle average of tags in use 863system.cpu0.dcache.total_refs 11253773 # Total number of references to valid blocks. 864system.cpu0.dcache.sampled_refs 1172148 # Sample count of references to valid blocks. 865system.cpu0.dcache.avg_refs 9.600983 # Average number of references to valid blocks. |
866system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. | 866system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. |
867system.cpu0.dcache.occ_blocks::cpu0.data 505.264481 # Average occupied blocks per requestor | 867system.cpu0.dcache.occ_blocks::cpu0.data 505.264467 # Average occupied blocks per requestor |
868system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy 869system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy | 868system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy 869system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy |
870system.cpu0.dcache.ReadReq_hits::cpu0.data 6351991 # number of ReadReq hits 871system.cpu0.dcache.ReadReq_hits::total 6351991 # number of ReadReq hits 872system.cpu0.dcache.WriteReq_hits::cpu0.data 4607363 # number of WriteReq hits 873system.cpu0.dcache.WriteReq_hits::total 4607363 # number of WriteReq hits 874system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138394 # number of LoadLockedReq hits 875system.cpu0.dcache.LoadLockedReq_hits::total 138394 # number of LoadLockedReq hits | 870system.cpu0.dcache.ReadReq_hits::cpu0.data 6351999 # number of ReadReq hits 871system.cpu0.dcache.ReadReq_hits::total 6351999 # number of ReadReq hits 872system.cpu0.dcache.WriteReq_hits::cpu0.data 4607371 # number of WriteReq hits 873system.cpu0.dcache.WriteReq_hits::total 4607371 # number of WriteReq hits 874system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138396 # number of LoadLockedReq hits 875system.cpu0.dcache.LoadLockedReq_hits::total 138396 # number of LoadLockedReq hits |
876system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits 877system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits | 876system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits 877system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits |
878system.cpu0.dcache.demand_hits::cpu0.data 10959354 # number of demand (read+write) hits 879system.cpu0.dcache.demand_hits::total 10959354 # number of demand (read+write) hits 880system.cpu0.dcache.overall_hits::cpu0.data 10959354 # number of overall hits 881system.cpu0.dcache.overall_hits::total 10959354 # number of overall hits 882system.cpu0.dcache.ReadReq_misses::cpu0.data 933040 # number of ReadReq misses 883system.cpu0.dcache.ReadReq_misses::total 933040 # number of ReadReq misses 884system.cpu0.dcache.WriteReq_misses::cpu0.data 249280 # number of WriteReq misses 885system.cpu0.dcache.WriteReq_misses::total 249280 # number of WriteReq misses 886system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13436 # number of LoadLockedReq misses 887system.cpu0.dcache.LoadLockedReq_misses::total 13436 # number of LoadLockedReq misses | 878system.cpu0.dcache.demand_hits::cpu0.data 10959370 # number of demand (read+write) hits 879system.cpu0.dcache.demand_hits::total 10959370 # number of demand (read+write) hits 880system.cpu0.dcache.overall_hits::cpu0.data 10959370 # number of overall hits 881system.cpu0.dcache.overall_hits::total 10959370 # number of overall hits 882system.cpu0.dcache.ReadReq_misses::cpu0.data 933038 # number of ReadReq misses 883system.cpu0.dcache.ReadReq_misses::total 933038 # number of ReadReq misses 884system.cpu0.dcache.WriteReq_misses::cpu0.data 249274 # number of WriteReq misses 885system.cpu0.dcache.WriteReq_misses::total 249274 # number of WriteReq misses 886system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13435 # number of LoadLockedReq misses 887system.cpu0.dcache.LoadLockedReq_misses::total 13435 # number of LoadLockedReq misses |
888system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses 889system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses | 888system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses 889system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses |
890system.cpu0.dcache.demand_misses::cpu0.data 1182320 # number of demand (read+write) misses 891system.cpu0.dcache.demand_misses::total 1182320 # number of demand (read+write) misses 892system.cpu0.dcache.overall_misses::cpu0.data 1182320 # number of overall misses 893system.cpu0.dcache.overall_misses::total 1182320 # number of overall misses 894system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20820883000 # number of ReadReq miss cycles 895system.cpu0.dcache.ReadReq_miss_latency::total 20820883000 # number of ReadReq miss cycles 896system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7761604000 # number of WriteReq miss cycles 897system.cpu0.dcache.WriteReq_miss_latency::total 7761604000 # number of WriteReq miss cycles 898system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144502500 # number of LoadLockedReq miss cycles 899system.cpu0.dcache.LoadLockedReq_miss_latency::total 144502500 # number of LoadLockedReq miss cycles 900system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43447000 # number of StoreCondReq miss cycles 901system.cpu0.dcache.StoreCondReq_miss_latency::total 43447000 # number of StoreCondReq miss cycles 902system.cpu0.dcache.demand_miss_latency::cpu0.data 28582487000 # number of demand (read+write) miss cycles 903system.cpu0.dcache.demand_miss_latency::total 28582487000 # number of demand (read+write) miss cycles 904system.cpu0.dcache.overall_miss_latency::cpu0.data 28582487000 # number of overall miss cycles 905system.cpu0.dcache.overall_miss_latency::total 28582487000 # number of overall miss cycles 906system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285031 # number of ReadReq accesses(hits+misses) 907system.cpu0.dcache.ReadReq_accesses::total 7285031 # number of ReadReq accesses(hits+misses) 908system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856643 # number of WriteReq accesses(hits+misses) 909system.cpu0.dcache.WriteReq_accesses::total 4856643 # number of WriteReq accesses(hits+misses) 910system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151830 # number of LoadLockedReq accesses(hits+misses) 911system.cpu0.dcache.LoadLockedReq_accesses::total 151830 # number of LoadLockedReq accesses(hits+misses) | 890system.cpu0.dcache.demand_misses::cpu0.data 1182312 # number of demand (read+write) misses 891system.cpu0.dcache.demand_misses::total 1182312 # number of demand (read+write) misses 892system.cpu0.dcache.overall_misses::cpu0.data 1182312 # number of overall misses 893system.cpu0.dcache.overall_misses::total 1182312 # number of overall misses 894system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20824713000 # number of ReadReq miss cycles 895system.cpu0.dcache.ReadReq_miss_latency::total 20824713000 # number of ReadReq miss cycles 896system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7766651000 # number of WriteReq miss cycles 897system.cpu0.dcache.WriteReq_miss_latency::total 7766651000 # number of WriteReq miss cycles 898system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144248500 # number of LoadLockedReq miss cycles 899system.cpu0.dcache.LoadLockedReq_miss_latency::total 144248500 # number of LoadLockedReq miss cycles 900system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43490500 # number of StoreCondReq miss cycles 901system.cpu0.dcache.StoreCondReq_miss_latency::total 43490500 # number of StoreCondReq miss cycles 902system.cpu0.dcache.demand_miss_latency::cpu0.data 28591364000 # number of demand (read+write) miss cycles 903system.cpu0.dcache.demand_miss_latency::total 28591364000 # number of demand (read+write) miss cycles 904system.cpu0.dcache.overall_miss_latency::cpu0.data 28591364000 # number of overall miss cycles 905system.cpu0.dcache.overall_miss_latency::total 28591364000 # number of overall miss cycles 906system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285037 # number of ReadReq accesses(hits+misses) 907system.cpu0.dcache.ReadReq_accesses::total 7285037 # number of ReadReq accesses(hits+misses) 908system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856645 # number of WriteReq accesses(hits+misses) 909system.cpu0.dcache.WriteReq_accesses::total 4856645 # number of WriteReq accesses(hits+misses) 910system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151831 # number of LoadLockedReq accesses(hits+misses) 911system.cpu0.dcache.LoadLockedReq_accesses::total 151831 # number of LoadLockedReq accesses(hits+misses) |
912system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) 913system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) | 912system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) 913system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) |
914system.cpu0.dcache.demand_accesses::cpu0.data 12141674 # number of demand (read+write) accesses 915system.cpu0.dcache.demand_accesses::total 12141674 # number of demand (read+write) accesses 916system.cpu0.dcache.overall_accesses::cpu0.data 12141674 # number of overall (read+write) accesses 917system.cpu0.dcache.overall_accesses::total 12141674 # number of overall (read+write) accesses | 914system.cpu0.dcache.demand_accesses::cpu0.data 12141682 # number of demand (read+write) accesses 915system.cpu0.dcache.demand_accesses::total 12141682 # number of demand (read+write) accesses 916system.cpu0.dcache.overall_accesses::cpu0.data 12141682 # number of overall (read+write) accesses 917system.cpu0.dcache.overall_accesses::total 12141682 # number of overall (read+write) accesses |
918system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses 919system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses | 918system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses 919system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses |
920system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051328 # miss rate for WriteReq accesses 921system.cpu0.dcache.WriteReq_miss_rate::total 0.051328 # miss rate for WriteReq accesses 922system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088494 # miss rate for LoadLockedReq accesses 923system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088494 # miss rate for LoadLockedReq accesses | 920system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051326 # miss rate for WriteReq accesses 921system.cpu0.dcache.WriteReq_miss_rate::total 0.051326 # miss rate for WriteReq accesses 922system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088487 # miss rate for LoadLockedReq accesses 923system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088487 # miss rate for LoadLockedReq accesses |
924system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses 925system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses | 924system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses 925system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses |
926system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097377 # miss rate for demand accesses 927system.cpu0.dcache.demand_miss_rate::total 0.097377 # miss rate for demand accesses 928system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097377 # miss rate for overall accesses 929system.cpu0.dcache.overall_miss_rate::total 0.097377 # miss rate for overall accesses 930system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22315.102246 # average ReadReq miss latency 931system.cpu0.dcache.ReadReq_avg_miss_latency::total 22315.102246 # average ReadReq miss latency 932system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31136.087933 # average WriteReq miss latency 933system.cpu0.dcache.WriteReq_avg_miss_latency::total 31136.087933 # average WriteReq miss latency 934system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10754.874963 # average LoadLockedReq miss latency 935system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10754.874963 # average LoadLockedReq miss latency 936system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7581.050427 # average StoreCondReq miss latency 937system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7581.050427 # average StoreCondReq miss latency 938system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency 939system.cpu0.dcache.demand_avg_miss_latency::total 24174.916266 # average overall miss latency 940system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency 941system.cpu0.dcache.overall_avg_miss_latency::total 24174.916266 # average overall miss latency | 926system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097376 # miss rate for demand accesses 927system.cpu0.dcache.demand_miss_rate::total 0.097376 # miss rate for demand accesses 928system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097376 # miss rate for overall accesses 929system.cpu0.dcache.overall_miss_rate::total 0.097376 # miss rate for overall accesses 930system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22319.254950 # average ReadReq miss latency 931system.cpu0.dcache.ReadReq_avg_miss_latency::total 22319.254950 # average ReadReq miss latency 932system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31157.084172 # average WriteReq miss latency 933system.cpu0.dcache.WriteReq_avg_miss_latency::total 31157.084172 # average WriteReq miss latency 934system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10736.769632 # average LoadLockedReq miss latency 935system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10736.769632 # average LoadLockedReq miss latency 936system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7588.640726 # average StoreCondReq miss latency 937system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7588.640726 # average StoreCondReq miss latency 938system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency 939system.cpu0.dcache.demand_avg_miss_latency::total 24182.588014 # average overall miss latency 940system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24182.588014 # average overall miss latency 941system.cpu0.dcache.overall_avg_miss_latency::total 24182.588014 # average overall miss latency |
942system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 943system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 944system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 945system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 946system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 947system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 948system.cpu0.dcache.fast_writes 0 # number of fast writes performed 949system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 942system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 943system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 944system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 945system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 946system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 947system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 948system.cpu0.dcache.fast_writes 0 # number of fast writes performed 949system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
950system.cpu0.dcache.writebacks::writebacks 672349 # number of writebacks 951system.cpu0.dcache.writebacks::total 672349 # number of writebacks 952system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933040 # number of ReadReq MSHR misses 953system.cpu0.dcache.ReadReq_mshr_misses::total 933040 # number of ReadReq MSHR misses 954system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249280 # number of WriteReq MSHR misses 955system.cpu0.dcache.WriteReq_mshr_misses::total 249280 # number of WriteReq MSHR misses 956system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13436 # number of LoadLockedReq MSHR misses 957system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13436 # number of LoadLockedReq MSHR misses | 950system.cpu0.dcache.writebacks::writebacks 672345 # number of writebacks 951system.cpu0.dcache.writebacks::total 672345 # number of writebacks 952system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933038 # number of ReadReq MSHR misses 953system.cpu0.dcache.ReadReq_mshr_misses::total 933038 # number of ReadReq MSHR misses 954system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249274 # number of WriteReq MSHR misses 955system.cpu0.dcache.WriteReq_mshr_misses::total 249274 # number of WriteReq MSHR misses 956system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13435 # number of LoadLockedReq MSHR misses 957system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13435 # number of LoadLockedReq MSHR misses |
958system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses 959system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses | 958system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses 959system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses |
960system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182320 # number of demand (read+write) MSHR misses 961system.cpu0.dcache.demand_mshr_misses::total 1182320 # number of demand (read+write) MSHR misses 962system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182320 # number of overall MSHR misses 963system.cpu0.dcache.overall_mshr_misses::total 1182320 # number of overall MSHR misses 964system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18954803000 # number of ReadReq MSHR miss cycles 965system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18954803000 # number of ReadReq MSHR miss cycles 966system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7263044000 # number of WriteReq MSHR miss cycles 967system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7263044000 # number of WriteReq MSHR miss cycles 968system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117630500 # number of LoadLockedReq MSHR miss cycles 969system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117630500 # number of LoadLockedReq MSHR miss cycles 970system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31985000 # number of StoreCondReq MSHR miss cycles 971system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31985000 # number of StoreCondReq MSHR miss cycles 972system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26217847000 # number of demand (read+write) MSHR miss cycles 973system.cpu0.dcache.demand_mshr_miss_latency::total 26217847000 # number of demand (read+write) MSHR miss cycles 974system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26217847000 # number of overall MSHR miss cycles 975system.cpu0.dcache.overall_mshr_miss_latency::total 26217847000 # number of overall MSHR miss cycles 976system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465453500 # number of ReadReq MSHR uncacheable cycles 977system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465453500 # number of ReadReq MSHR uncacheable cycles 978system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285524000 # number of WriteReq MSHR uncacheable cycles 979system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285524000 # number of WriteReq MSHR uncacheable cycles 980system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750977500 # number of overall MSHR uncacheable cycles 981system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750977500 # number of overall MSHR uncacheable cycles | 960system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182312 # number of demand (read+write) MSHR misses 961system.cpu0.dcache.demand_mshr_misses::total 1182312 # number of demand (read+write) MSHR misses 962system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182312 # number of overall MSHR misses 963system.cpu0.dcache.overall_mshr_misses::total 1182312 # number of overall MSHR misses 964system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18958637000 # number of ReadReq MSHR miss cycles 965system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18958637000 # number of ReadReq MSHR miss cycles 966system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7268103000 # number of WriteReq MSHR miss cycles 967system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7268103000 # number of WriteReq MSHR miss cycles 968system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117378500 # number of LoadLockedReq MSHR miss cycles 969system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117378500 # number of LoadLockedReq MSHR miss cycles 970system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32028500 # number of StoreCondReq MSHR miss cycles 971system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32028500 # number of StoreCondReq MSHR miss cycles 972system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26226740000 # number of demand (read+write) MSHR miss cycles 973system.cpu0.dcache.demand_mshr_miss_latency::total 26226740000 # number of demand (read+write) MSHR miss cycles 974system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26226740000 # number of overall MSHR miss cycles 975system.cpu0.dcache.overall_mshr_miss_latency::total 26226740000 # number of overall MSHR miss cycles 976system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465462500 # number of ReadReq MSHR uncacheable cycles 977system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465462500 # number of ReadReq MSHR uncacheable cycles 978system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285670500 # number of WriteReq MSHR uncacheable cycles 979system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285670500 # number of WriteReq MSHR uncacheable cycles 980system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3751133000 # number of overall MSHR uncacheable cycles 981system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3751133000 # number of overall MSHR uncacheable cycles |
982system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses 983system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses | 982system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses 983system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses |
984system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051328 # mshr miss rate for WriteReq accesses 985system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051328 # mshr miss rate for WriteReq accesses 986system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088494 # mshr miss rate for LoadLockedReq accesses 987system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088494 # mshr miss rate for LoadLockedReq accesses | 984system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051326 # mshr miss rate for WriteReq accesses 985system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051326 # mshr miss rate for WriteReq accesses 986system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088487 # mshr miss rate for LoadLockedReq accesses 987system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088487 # mshr miss rate for LoadLockedReq accesses |
988system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses 989system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses | 988system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses 989system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses |
990system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for demand accesses 991system.cpu0.dcache.demand_mshr_miss_rate::total 0.097377 # mshr miss rate for demand accesses 992system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for overall accesses 993system.cpu0.dcache.overall_mshr_miss_rate::total 0.097377 # mshr miss rate for overall accesses 994system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20315.102246 # average ReadReq mshr miss latency 995system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20315.102246 # average ReadReq mshr miss latency 996system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29136.087933 # average WriteReq mshr miss latency 997system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29136.087933 # average WriteReq mshr miss latency 998system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8754.874963 # average LoadLockedReq mshr miss latency 999system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8754.874963 # average LoadLockedReq mshr miss latency 1000system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5581.050427 # average StoreCondReq mshr miss latency 1001system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5581.050427 # average StoreCondReq mshr miss latency 1002system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency 1003system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency 1004system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency 1005system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency | 990system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for demand accesses 991system.cpu0.dcache.demand_mshr_miss_rate::total 0.097376 # mshr miss rate for demand accesses 992system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097376 # mshr miss rate for overall accesses 993system.cpu0.dcache.overall_mshr_miss_rate::total 0.097376 # mshr miss rate for overall accesses 994system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20319.254950 # average ReadReq mshr miss latency 995system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20319.254950 # average ReadReq mshr miss latency 996system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29157.084172 # average WriteReq mshr miss latency 997system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29157.084172 # average WriteReq mshr miss latency 998system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8736.769632 # average LoadLockedReq mshr miss latency 999system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8736.769632 # average LoadLockedReq mshr miss latency 1000system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5588.640726 # average StoreCondReq mshr miss latency 1001system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5588.640726 # average StoreCondReq mshr miss latency 1002system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency 1003system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency 1004system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22182.588014 # average overall mshr miss latency 1005system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22182.588014 # average overall mshr miss latency |
1006system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1007system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1008system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1009system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1010system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1011system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1012system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1013system.cpu1.dtb.fetch_hits 0 # ITB hits 1014system.cpu1.dtb.fetch_misses 0 # ITB misses 1015system.cpu1.dtb.fetch_acv 0 # ITB acv 1016system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1006system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1007system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1008system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1009system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1010system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1011system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1012system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1013system.cpu1.dtb.fetch_hits 0 # ITB hits 1014system.cpu1.dtb.fetch_misses 0 # ITB misses 1015system.cpu1.dtb.fetch_acv 0 # ITB acv 1016system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
1017system.cpu1.dtb.read_hits 2500235 # DTB read hits | 1017system.cpu1.dtb.read_hits 2500361 # DTB read hits |
1018system.cpu1.dtb.read_misses 2992 # DTB read misses 1019system.cpu1.dtb.read_acv 0 # DTB read access violations 1020system.cpu1.dtb.read_accesses 239363 # DTB read accesses | 1018system.cpu1.dtb.read_misses 2992 # DTB read misses 1019system.cpu1.dtb.read_acv 0 # DTB read access violations 1020system.cpu1.dtb.read_accesses 239363 # DTB read accesses |
1021system.cpu1.dtb.write_hits 1820988 # DTB write hits | 1021system.cpu1.dtb.write_hits 1820984 # DTB write hits |
1022system.cpu1.dtb.write_misses 341 # DTB write misses 1023system.cpu1.dtb.write_acv 29 # DTB write access violations 1024system.cpu1.dtb.write_accesses 105247 # DTB write accesses | 1022system.cpu1.dtb.write_misses 341 # DTB write misses 1023system.cpu1.dtb.write_acv 29 # DTB write access violations 1024system.cpu1.dtb.write_accesses 105247 # DTB write accesses |
1025system.cpu1.dtb.data_hits 4321223 # DTB hits | 1025system.cpu1.dtb.data_hits 4321345 # DTB hits |
1026system.cpu1.dtb.data_misses 3333 # DTB misses 1027system.cpu1.dtb.data_acv 29 # DTB access violations 1028system.cpu1.dtb.data_accesses 344610 # DTB accesses 1029system.cpu1.itb.fetch_hits 1990033 # ITB hits 1030system.cpu1.itb.fetch_misses 1216 # ITB misses 1031system.cpu1.itb.fetch_acv 0 # ITB acv 1032system.cpu1.itb.fetch_accesses 1991249 # ITB accesses 1033system.cpu1.itb.read_hits 0 # DTB read hits 1034system.cpu1.itb.read_misses 0 # DTB read misses 1035system.cpu1.itb.read_acv 0 # DTB read access violations 1036system.cpu1.itb.read_accesses 0 # DTB read accesses 1037system.cpu1.itb.write_hits 0 # DTB write hits 1038system.cpu1.itb.write_misses 0 # DTB write misses 1039system.cpu1.itb.write_acv 0 # DTB write access violations 1040system.cpu1.itb.write_accesses 0 # DTB write accesses 1041system.cpu1.itb.data_hits 0 # DTB hits 1042system.cpu1.itb.data_misses 0 # DTB misses 1043system.cpu1.itb.data_acv 0 # DTB access violations 1044system.cpu1.itb.data_accesses 0 # DTB accesses | 1026system.cpu1.dtb.data_misses 3333 # DTB misses 1027system.cpu1.dtb.data_acv 29 # DTB access violations 1028system.cpu1.dtb.data_accesses 344610 # DTB accesses 1029system.cpu1.itb.fetch_hits 1990033 # ITB hits 1030system.cpu1.itb.fetch_misses 1216 # ITB misses 1031system.cpu1.itb.fetch_acv 0 # ITB acv 1032system.cpu1.itb.fetch_accesses 1991249 # ITB accesses 1033system.cpu1.itb.read_hits 0 # DTB read hits 1034system.cpu1.itb.read_misses 0 # DTB read misses 1035system.cpu1.itb.read_acv 0 # DTB read access violations 1036system.cpu1.itb.read_accesses 0 # DTB read accesses 1037system.cpu1.itb.write_hits 0 # DTB write hits 1038system.cpu1.itb.write_misses 0 # DTB write misses 1039system.cpu1.itb.write_acv 0 # DTB write access violations 1040system.cpu1.itb.write_accesses 0 # DTB write accesses 1041system.cpu1.itb.data_hits 0 # DTB hits 1042system.cpu1.itb.data_misses 0 # DTB misses 1043system.cpu1.itb.data_acv 0 # DTB access violations 1044system.cpu1.itb.data_accesses 0 # DTB accesses |
1045system.cpu1.numCycles 3901626495 # number of cpu cycles simulated | 1045system.cpu1.numCycles 3901627911 # number of cpu cycles simulated |
1046system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1047system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1046system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1047system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
1048system.cpu1.committedInsts 13632042 # Number of instructions committed 1049system.cpu1.committedOps 13632042 # Number of ops (including micro ops) committed 1050system.cpu1.num_int_alu_accesses 12571491 # Number of integer alu accesses | 1048system.cpu1.committedInsts 13632233 # Number of instructions committed 1049system.cpu1.committedOps 13632233 # Number of ops (including micro ops) committed 1050system.cpu1.num_int_alu_accesses 12571690 # Number of integer alu accesses |
1051system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses | 1051system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses |
1052system.cpu1.num_func_calls 426717 # number of times a function call or return occured 1053system.cpu1.num_conditional_control_insts 1355011 # number of instructions that are conditional controls 1054system.cpu1.num_int_insts 12571491 # number of integer instructions | 1052system.cpu1.num_func_calls 426713 # number of times a function call or return occured 1053system.cpu1.num_conditional_control_insts 1355142 # number of instructions that are conditional controls 1054system.cpu1.num_int_insts 12571690 # number of integer instructions |
1055system.cpu1.num_fp_insts 180459 # number of float instructions | 1055system.cpu1.num_fp_insts 180459 # number of float instructions |
1056system.cpu1.num_int_register_reads 17311598 # number of times the integer registers were read 1057system.cpu1.num_int_register_writes 9221787 # number of times the integer registers were written | 1056system.cpu1.num_int_register_reads 17311762 # number of times the integer registers were read 1057system.cpu1.num_int_register_writes 9221860 # number of times the integer registers were written |
1058system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read 1059system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written | 1058system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read 1059system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written |
1060system.cpu1.num_mem_refs 4345531 # number of memory refs 1061system.cpu1.num_load_insts 2514982 # Number of load instructions 1062system.cpu1.num_store_insts 1830549 # Number of store instructions 1063system.cpu1.num_idle_cycles 3850258507.998026 # Number of idle cycles 1064system.cpu1.num_busy_cycles 51367987.001974 # Number of busy cycles | 1060system.cpu1.num_mem_refs 4345653 # number of memory refs 1061system.cpu1.num_load_insts 2515108 # Number of load instructions 1062system.cpu1.num_store_insts 1830545 # Number of store instructions 1063system.cpu1.num_idle_cycles 3850258537.998026 # Number of idle cycles 1064system.cpu1.num_busy_cycles 51369373.001974 # Number of busy cycles |
1065system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles 1066system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles 1067system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1068system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed 1069system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed 1070system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl 1071system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl 1072system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl 1073system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl 1074system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl 1075system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl 1076system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl 1077system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl 1078system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl 1079system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl | 1065system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles 1066system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles 1067system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1068system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed 1069system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed 1070system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl 1071system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl 1072system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl 1073system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl 1074system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl 1075system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl 1076system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl 1077system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl 1078system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl 1079system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl |
1080system.cpu1.kern.ipl_ticks::0 1907138262500 97.76% 97.76% # number of cycles we spent at this ipl 1081system.cpu1.kern.ipl_ticks::22 705201000 0.04% 97.80% # number of cycles we spent at this ipl 1082system.cpu1.kern.ipl_ticks::30 364168000 0.02% 97.82% # number of cycles we spent at this ipl 1083system.cpu1.kern.ipl_ticks::31 42604858000 2.18% 100.00% # number of cycles we spent at this ipl 1084system.cpu1.kern.ipl_ticks::total 1950812489500 # number of cycles we spent at this ipl | 1080system.cpu1.kern.ipl_ticks::0 1907137344500 97.76% 97.76% # number of cycles we spent at this ipl 1081system.cpu1.kern.ipl_ticks::22 705261000 0.04% 97.80% # number of cycles we spent at this ipl 1082system.cpu1.kern.ipl_ticks::30 364072500 0.02% 97.82% # number of cycles we spent at this ipl 1083system.cpu1.kern.ipl_ticks::31 42606519500 2.18% 100.00% # number of cycles we spent at this ipl 1084system.cpu1.kern.ipl_ticks::total 1950813197500 # number of cycles we spent at this ipl |
1085system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl 1086system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1087system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1088system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl 1089system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl 1090system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 1091system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 1092system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed --- 20 unchanged lines hidden (view full) --- 1113system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed 1114system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed 1115system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed 1116system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed 1117system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed 1118system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 1119system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 1120system.cpu1.kern.callpal::total 73828 # number of callpals executed | 1085system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl 1086system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1087system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 1088system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl 1089system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl 1090system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 1091system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 1092system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed --- 20 unchanged lines hidden (view full) --- 1113system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed 1114system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed 1115system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed 1116system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed 1117system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed 1118system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 1119system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 1120system.cpu1.kern.callpal::total 73828 # number of callpals executed |
1121system.cpu1.kern.mode_switch::kernel 2126 # number of protection mode switches | 1121system.cpu1.kern.mode_switch::kernel 2125 # number of protection mode switches |
1122system.cpu1.kern.mode_switch::user 465 # number of protection mode switches | 1122system.cpu1.kern.mode_switch::user 465 # number of protection mode switches |
1123system.cpu1.kern.mode_switch::idle 2924 # number of protection mode switches | 1123system.cpu1.kern.mode_switch::idle 2925 # number of protection mode switches |
1124system.cpu1.kern.mode_good::kernel 915 1125system.cpu1.kern.mode_good::user 465 1126system.cpu1.kern.mode_good::idle 450 | 1124system.cpu1.kern.mode_good::kernel 915 1125system.cpu1.kern.mode_good::user 465 1126system.cpu1.kern.mode_good::idle 450 |
1127system.cpu1.kern.mode_switch_good::kernel 0.430386 # fraction of useful protection mode switches | 1127system.cpu1.kern.mode_switch_good::kernel 0.430588 # fraction of useful protection mode switches |
1128system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1128system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
1129system.cpu1.kern.mode_switch_good::idle 0.153899 # fraction of useful protection mode switches | 1129system.cpu1.kern.mode_switch_good::idle 0.153846 # fraction of useful protection mode switches |
1130system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches | 1130system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches |
1131system.cpu1.kern.mode_ticks::kernel 18665784500 0.96% 0.96% # number of ticks spent at the given mode 1132system.cpu1.kern.mode_ticks::user 1711228500 0.09% 1.04% # number of ticks spent at the given mode 1133system.cpu1.kern.mode_ticks::idle 1930435473000 98.96% 100.00% # number of ticks spent at the given mode | 1131system.cpu1.kern.mode_ticks::kernel 18664257000 0.96% 0.96% # number of ticks spent at the given mode 1132system.cpu1.kern.mode_ticks::user 1710579000 0.09% 1.04% # number of ticks spent at the given mode 1133system.cpu1.kern.mode_ticks::idle 1930438358000 98.96% 100.00% # number of ticks spent at the given mode |
1134system.cpu1.kern.swap_context 2086 # number of times the context was actually changed | 1134system.cpu1.kern.swap_context 2086 # number of times the context was actually changed |
1135system.cpu1.icache.replacements 328648 # number of replacements 1136system.cpu1.icache.tagsinuse 446.257828 # Cycle average of tags in use 1137system.cpu1.icache.total_refs 13306209 # Total number of references to valid blocks. 1138system.cpu1.icache.sampled_refs 329160 # Sample count of references to valid blocks. 1139system.cpu1.icache.avg_refs 40.424745 # Average number of references to valid blocks. 1140system.cpu1.icache.warmup_cycle 1948917036000 # Cycle when the warmup percentage was hit. 1141system.cpu1.icache.occ_blocks::cpu1.inst 446.257828 # Average occupied blocks per requestor | 1135system.cpu1.icache.replacements 328646 # number of replacements 1136system.cpu1.icache.tagsinuse 446.257851 # Cycle average of tags in use 1137system.cpu1.icache.total_refs 13306402 # Total number of references to valid blocks. 1138system.cpu1.icache.sampled_refs 329158 # Sample count of references to valid blocks. 1139system.cpu1.icache.avg_refs 40.425577 # Average number of references to valid blocks. 1140system.cpu1.icache.warmup_cycle 1948915489000 # Cycle when the warmup percentage was hit. 1141system.cpu1.icache.occ_blocks::cpu1.inst 446.257851 # Average occupied blocks per requestor |
1142system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy 1143system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy | 1142system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy 1143system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy |
1144system.cpu1.icache.ReadReq_hits::cpu1.inst 13306209 # number of ReadReq hits 1145system.cpu1.icache.ReadReq_hits::total 13306209 # number of ReadReq hits 1146system.cpu1.icache.demand_hits::cpu1.inst 13306209 # number of demand (read+write) hits 1147system.cpu1.icache.demand_hits::total 13306209 # number of demand (read+write) hits 1148system.cpu1.icache.overall_hits::cpu1.inst 13306209 # number of overall hits 1149system.cpu1.icache.overall_hits::total 13306209 # number of overall hits 1150system.cpu1.icache.ReadReq_misses::cpu1.inst 329196 # number of ReadReq misses 1151system.cpu1.icache.ReadReq_misses::total 329196 # number of ReadReq misses 1152system.cpu1.icache.demand_misses::cpu1.inst 329196 # number of demand (read+write) misses 1153system.cpu1.icache.demand_misses::total 329196 # number of demand (read+write) misses 1154system.cpu1.icache.overall_misses::cpu1.inst 329196 # number of overall misses 1155system.cpu1.icache.overall_misses::total 329196 # number of overall misses 1156system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4347354500 # number of ReadReq miss cycles 1157system.cpu1.icache.ReadReq_miss_latency::total 4347354500 # number of ReadReq miss cycles 1158system.cpu1.icache.demand_miss_latency::cpu1.inst 4347354500 # number of demand (read+write) miss cycles 1159system.cpu1.icache.demand_miss_latency::total 4347354500 # number of demand (read+write) miss cycles 1160system.cpu1.icache.overall_miss_latency::cpu1.inst 4347354500 # number of overall miss cycles 1161system.cpu1.icache.overall_miss_latency::total 4347354500 # number of overall miss cycles 1162system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635405 # number of ReadReq accesses(hits+misses) 1163system.cpu1.icache.ReadReq_accesses::total 13635405 # number of ReadReq accesses(hits+misses) 1164system.cpu1.icache.demand_accesses::cpu1.inst 13635405 # number of demand (read+write) accesses 1165system.cpu1.icache.demand_accesses::total 13635405 # number of demand (read+write) accesses 1166system.cpu1.icache.overall_accesses::cpu1.inst 13635405 # number of overall (read+write) accesses 1167system.cpu1.icache.overall_accesses::total 13635405 # number of overall (read+write) accesses 1168system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024143 # miss rate for ReadReq accesses 1169system.cpu1.icache.ReadReq_miss_rate::total 0.024143 # miss rate for ReadReq accesses 1170system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024143 # miss rate for demand accesses 1171system.cpu1.icache.demand_miss_rate::total 0.024143 # miss rate for demand accesses 1172system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024143 # miss rate for overall accesses 1173system.cpu1.icache.overall_miss_rate::total 0.024143 # miss rate for overall accesses 1174system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13205.976075 # average ReadReq miss latency 1175system.cpu1.icache.ReadReq_avg_miss_latency::total 13205.976075 # average ReadReq miss latency 1176system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency 1177system.cpu1.icache.demand_avg_miss_latency::total 13205.976075 # average overall miss latency 1178system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency 1179system.cpu1.icache.overall_avg_miss_latency::total 13205.976075 # average overall miss latency | 1144system.cpu1.icache.ReadReq_hits::cpu1.inst 13306402 # number of ReadReq hits 1145system.cpu1.icache.ReadReq_hits::total 13306402 # number of ReadReq hits 1146system.cpu1.icache.demand_hits::cpu1.inst 13306402 # number of demand (read+write) hits 1147system.cpu1.icache.demand_hits::total 13306402 # number of demand (read+write) hits 1148system.cpu1.icache.overall_hits::cpu1.inst 13306402 # number of overall hits 1149system.cpu1.icache.overall_hits::total 13306402 # number of overall hits 1150system.cpu1.icache.ReadReq_misses::cpu1.inst 329194 # number of ReadReq misses 1151system.cpu1.icache.ReadReq_misses::total 329194 # number of ReadReq misses 1152system.cpu1.icache.demand_misses::cpu1.inst 329194 # number of demand (read+write) misses 1153system.cpu1.icache.demand_misses::total 329194 # number of demand (read+write) misses 1154system.cpu1.icache.overall_misses::cpu1.inst 329194 # number of overall misses 1155system.cpu1.icache.overall_misses::total 329194 # number of overall misses 1156system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4346536000 # number of ReadReq miss cycles 1157system.cpu1.icache.ReadReq_miss_latency::total 4346536000 # number of ReadReq miss cycles 1158system.cpu1.icache.demand_miss_latency::cpu1.inst 4346536000 # number of demand (read+write) miss cycles 1159system.cpu1.icache.demand_miss_latency::total 4346536000 # number of demand (read+write) miss cycles 1160system.cpu1.icache.overall_miss_latency::cpu1.inst 4346536000 # number of overall miss cycles 1161system.cpu1.icache.overall_miss_latency::total 4346536000 # number of overall miss cycles 1162system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635596 # number of ReadReq accesses(hits+misses) 1163system.cpu1.icache.ReadReq_accesses::total 13635596 # number of ReadReq accesses(hits+misses) 1164system.cpu1.icache.demand_accesses::cpu1.inst 13635596 # number of demand (read+write) accesses 1165system.cpu1.icache.demand_accesses::total 13635596 # number of demand (read+write) accesses 1166system.cpu1.icache.overall_accesses::cpu1.inst 13635596 # number of overall (read+write) accesses 1167system.cpu1.icache.overall_accesses::total 13635596 # number of overall (read+write) accesses 1168system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024142 # miss rate for ReadReq accesses 1169system.cpu1.icache.ReadReq_miss_rate::total 0.024142 # miss rate for ReadReq accesses 1170system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024142 # miss rate for demand accesses 1171system.cpu1.icache.demand_miss_rate::total 0.024142 # miss rate for demand accesses 1172system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024142 # miss rate for overall accesses 1173system.cpu1.icache.overall_miss_rate::total 0.024142 # miss rate for overall accesses 1174system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13203.569931 # average ReadReq miss latency 1175system.cpu1.icache.ReadReq_avg_miss_latency::total 13203.569931 # average ReadReq miss latency 1176system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency 1177system.cpu1.icache.demand_avg_miss_latency::total 13203.569931 # average overall miss latency 1178system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13203.569931 # average overall miss latency 1179system.cpu1.icache.overall_avg_miss_latency::total 13203.569931 # average overall miss latency |
1180system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1181system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1182system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1183system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1184system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1185system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1186system.cpu1.icache.fast_writes 0 # number of fast writes performed 1187system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1180system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1181system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1182system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1183system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1184system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1185system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1186system.cpu1.icache.fast_writes 0 # number of fast writes performed 1187system.cpu1.icache.cache_copies 0 # number of cache copies performed |
1188system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329196 # number of ReadReq MSHR misses 1189system.cpu1.icache.ReadReq_mshr_misses::total 329196 # number of ReadReq MSHR misses 1190system.cpu1.icache.demand_mshr_misses::cpu1.inst 329196 # number of demand (read+write) MSHR misses 1191system.cpu1.icache.demand_mshr_misses::total 329196 # number of demand (read+write) MSHR misses 1192system.cpu1.icache.overall_mshr_misses::cpu1.inst 329196 # number of overall MSHR misses 1193system.cpu1.icache.overall_mshr_misses::total 329196 # number of overall MSHR misses 1194system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688962500 # number of ReadReq MSHR miss cycles 1195system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688962500 # number of ReadReq MSHR miss cycles 1196system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688962500 # number of demand (read+write) MSHR miss cycles 1197system.cpu1.icache.demand_mshr_miss_latency::total 3688962500 # number of demand (read+write) MSHR miss cycles 1198system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688962500 # number of overall MSHR miss cycles 1199system.cpu1.icache.overall_mshr_miss_latency::total 3688962500 # number of overall MSHR miss cycles 1200system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for ReadReq accesses 1201system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024143 # mshr miss rate for ReadReq accesses 1202system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for demand accesses 1203system.cpu1.icache.demand_mshr_miss_rate::total 0.024143 # mshr miss rate for demand accesses 1204system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for overall accesses 1205system.cpu1.icache.overall_mshr_miss_rate::total 0.024143 # mshr miss rate for overall accesses 1206system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average ReadReq mshr miss latency 1207system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11205.976075 # average ReadReq mshr miss latency 1208system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency 1209system.cpu1.icache.demand_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency 1210system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency 1211system.cpu1.icache.overall_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency | 1188system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329194 # number of ReadReq MSHR misses 1189system.cpu1.icache.ReadReq_mshr_misses::total 329194 # number of ReadReq MSHR misses 1190system.cpu1.icache.demand_mshr_misses::cpu1.inst 329194 # number of demand (read+write) MSHR misses 1191system.cpu1.icache.demand_mshr_misses::total 329194 # number of demand (read+write) MSHR misses 1192system.cpu1.icache.overall_mshr_misses::cpu1.inst 329194 # number of overall MSHR misses 1193system.cpu1.icache.overall_mshr_misses::total 329194 # number of overall MSHR misses 1194system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688148000 # number of ReadReq MSHR miss cycles 1195system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688148000 # number of ReadReq MSHR miss cycles 1196system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688148000 # number of demand (read+write) MSHR miss cycles 1197system.cpu1.icache.demand_mshr_miss_latency::total 3688148000 # number of demand (read+write) MSHR miss cycles 1198system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688148000 # number of overall MSHR miss cycles 1199system.cpu1.icache.overall_mshr_miss_latency::total 3688148000 # number of overall MSHR miss cycles 1200system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for ReadReq accesses 1201system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024142 # mshr miss rate for ReadReq accesses 1202system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for demand accesses 1203system.cpu1.icache.demand_mshr_miss_rate::total 0.024142 # mshr miss rate for demand accesses 1204system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024142 # mshr miss rate for overall accesses 1205system.cpu1.icache.overall_mshr_miss_rate::total 0.024142 # mshr miss rate for overall accesses 1206system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average ReadReq mshr miss latency 1207system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11203.569931 # average ReadReq mshr miss latency 1208system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency 1209system.cpu1.icache.demand_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency 1210system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11203.569931 # average overall mshr miss latency 1211system.cpu1.icache.overall_avg_mshr_miss_latency::total 11203.569931 # average overall mshr miss latency |
1212system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1212system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
1213system.cpu1.dcache.replacements 172786 # number of replacements 1214system.cpu1.dcache.tagsinuse 487.450805 # Cycle average of tags in use 1215system.cpu1.dcache.total_refs 4146223 # Total number of references to valid blocks. 1216system.cpu1.dcache.sampled_refs 173298 # Sample count of references to valid blocks. 1217system.cpu1.dcache.avg_refs 23.925394 # Average number of references to valid blocks. 1218system.cpu1.dcache.warmup_cycle 62292634000 # Cycle when the warmup percentage was hit. 1219system.cpu1.dcache.occ_blocks::cpu1.data 487.450805 # Average occupied blocks per requestor | 1213system.cpu1.dcache.replacements 172801 # number of replacements 1214system.cpu1.dcache.tagsinuse 487.450819 # Cycle average of tags in use 1215system.cpu1.dcache.total_refs 4146327 # Total number of references to valid blocks. 1216system.cpu1.dcache.sampled_refs 173313 # Sample count of references to valid blocks. 1217system.cpu1.dcache.avg_refs 23.923924 # Average number of references to valid blocks. 1218system.cpu1.dcache.warmup_cycle 62292445000 # Cycle when the warmup percentage was hit. 1219system.cpu1.dcache.occ_blocks::cpu1.data 487.450819 # Average occupied blocks per requestor |
1220system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy 1221system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy | 1220system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy 1221system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy |
1222system.cpu1.dcache.ReadReq_hits::cpu1.data 2329094 # number of ReadReq hits 1223system.cpu1.dcache.ReadReq_hits::total 2329094 # number of ReadReq hits 1224system.cpu1.dcache.WriteReq_hits::cpu1.data 1699243 # number of WriteReq hits 1225system.cpu1.dcache.WriteReq_hits::total 1699243 # number of WriteReq hits | 1222system.cpu1.dcache.ReadReq_hits::cpu1.data 2329216 # number of ReadReq hits 1223system.cpu1.dcache.ReadReq_hits::total 2329216 # number of ReadReq hits 1224system.cpu1.dcache.WriteReq_hits::cpu1.data 1699225 # number of WriteReq hits 1225system.cpu1.dcache.WriteReq_hits::total 1699225 # number of WriteReq hits |
1226system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits 1227system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits 1228system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits 1229system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits | 1226system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits 1227system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits 1228system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits 1229system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits |
1230system.cpu1.dcache.demand_hits::cpu1.data 4028337 # number of demand (read+write) hits 1231system.cpu1.dcache.demand_hits::total 4028337 # number of demand (read+write) hits 1232system.cpu1.dcache.overall_hits::cpu1.data 4028337 # number of overall hits 1233system.cpu1.dcache.overall_hits::total 4028337 # number of overall hits 1234system.cpu1.dcache.ReadReq_misses::cpu1.data 123236 # number of ReadReq misses 1235system.cpu1.dcache.ReadReq_misses::total 123236 # number of ReadReq misses 1236system.cpu1.dcache.WriteReq_misses::cpu1.data 64754 # number of WriteReq misses 1237system.cpu1.dcache.WriteReq_misses::total 64754 # number of WriteReq misses 1238system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9347 # number of LoadLockedReq misses 1239system.cpu1.dcache.LoadLockedReq_misses::total 9347 # number of LoadLockedReq misses 1240system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6143 # number of StoreCondReq misses 1241system.cpu1.dcache.StoreCondReq_misses::total 6143 # number of StoreCondReq misses 1242system.cpu1.dcache.demand_misses::cpu1.data 187990 # number of demand (read+write) misses 1243system.cpu1.dcache.demand_misses::total 187990 # number of demand (read+write) misses 1244system.cpu1.dcache.overall_misses::cpu1.data 187990 # number of overall misses 1245system.cpu1.dcache.overall_misses::total 187990 # number of overall misses 1246system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1493692000 # number of ReadReq miss cycles 1247system.cpu1.dcache.ReadReq_miss_latency::total 1493692000 # number of ReadReq miss cycles 1248system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166299500 # number of WriteReq miss cycles 1249system.cpu1.dcache.WriteReq_miss_latency::total 1166299500 # number of WriteReq miss cycles 1250system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85390000 # number of LoadLockedReq miss cycles 1251system.cpu1.dcache.LoadLockedReq_miss_latency::total 85390000 # number of LoadLockedReq miss cycles 1252system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44515500 # number of StoreCondReq miss cycles 1253system.cpu1.dcache.StoreCondReq_miss_latency::total 44515500 # number of StoreCondReq miss cycles 1254system.cpu1.dcache.demand_miss_latency::cpu1.data 2659991500 # number of demand (read+write) miss cycles 1255system.cpu1.dcache.demand_miss_latency::total 2659991500 # number of demand (read+write) miss cycles 1256system.cpu1.dcache.overall_miss_latency::cpu1.data 2659991500 # number of overall miss cycles 1257system.cpu1.dcache.overall_miss_latency::total 2659991500 # number of overall miss cycles 1258system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452330 # number of ReadReq accesses(hits+misses) 1259system.cpu1.dcache.ReadReq_accesses::total 2452330 # number of ReadReq accesses(hits+misses) 1260system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763997 # number of WriteReq accesses(hits+misses) 1261system.cpu1.dcache.WriteReq_accesses::total 1763997 # number of WriteReq accesses(hits+misses) 1262system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59567 # number of LoadLockedReq accesses(hits+misses) 1263system.cpu1.dcache.LoadLockedReq_accesses::total 59567 # number of LoadLockedReq accesses(hits+misses) 1264system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59070 # number of StoreCondReq accesses(hits+misses) 1265system.cpu1.dcache.StoreCondReq_accesses::total 59070 # number of StoreCondReq accesses(hits+misses) 1266system.cpu1.dcache.demand_accesses::cpu1.data 4216327 # number of demand (read+write) accesses 1267system.cpu1.dcache.demand_accesses::total 4216327 # number of demand (read+write) accesses 1268system.cpu1.dcache.overall_accesses::cpu1.data 4216327 # number of overall (read+write) accesses 1269system.cpu1.dcache.overall_accesses::total 4216327 # number of overall (read+write) accesses 1270system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050253 # miss rate for ReadReq accesses 1271system.cpu1.dcache.ReadReq_miss_rate::total 0.050253 # miss rate for ReadReq accesses 1272system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036709 # miss rate for WriteReq accesses 1273system.cpu1.dcache.WriteReq_miss_rate::total 0.036709 # miss rate for WriteReq accesses 1274system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156916 # miss rate for LoadLockedReq accesses 1275system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156916 # miss rate for LoadLockedReq accesses 1276system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103995 # miss rate for StoreCondReq accesses 1277system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103995 # miss rate for StoreCondReq accesses 1278system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044586 # miss rate for demand accesses 1279system.cpu1.dcache.demand_miss_rate::total 0.044586 # miss rate for demand accesses 1280system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044586 # miss rate for overall accesses 1281system.cpu1.dcache.overall_miss_rate::total 0.044586 # miss rate for overall accesses 1282system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12120.581648 # average ReadReq miss latency 1283system.cpu1.dcache.ReadReq_avg_miss_latency::total 12120.581648 # average ReadReq miss latency 1284system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.234827 # average WriteReq miss latency 1285system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.234827 # average WriteReq miss latency 1286system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.551514 # average LoadLockedReq miss latency 1287system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.551514 # average LoadLockedReq miss latency 1288system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7246.540778 # average StoreCondReq miss latency 1289system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7246.540778 # average StoreCondReq miss latency 1290system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency 1291system.cpu1.dcache.demand_avg_miss_latency::total 14149.643598 # average overall miss latency 1292system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency 1293system.cpu1.dcache.overall_avg_miss_latency::total 14149.643598 # average overall miss latency | 1230system.cpu1.dcache.demand_hits::cpu1.data 4028441 # number of demand (read+write) hits 1231system.cpu1.dcache.demand_hits::total 4028441 # number of demand (read+write) hits 1232system.cpu1.dcache.overall_hits::cpu1.data 4028441 # number of overall hits 1233system.cpu1.dcache.overall_hits::total 4028441 # number of overall hits 1234system.cpu1.dcache.ReadReq_misses::cpu1.data 123241 # number of ReadReq misses 1235system.cpu1.dcache.ReadReq_misses::total 123241 # number of ReadReq misses 1236system.cpu1.dcache.WriteReq_misses::cpu1.data 64769 # number of WriteReq misses 1237system.cpu1.dcache.WriteReq_misses::total 64769 # number of WriteReq misses 1238system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9346 # number of LoadLockedReq misses 1239system.cpu1.dcache.LoadLockedReq_misses::total 9346 # number of LoadLockedReq misses 1240system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6142 # number of StoreCondReq misses 1241system.cpu1.dcache.StoreCondReq_misses::total 6142 # number of StoreCondReq misses 1242system.cpu1.dcache.demand_misses::cpu1.data 188010 # number of demand (read+write) misses 1243system.cpu1.dcache.demand_misses::total 188010 # number of demand (read+write) misses 1244system.cpu1.dcache.overall_misses::cpu1.data 188010 # number of overall misses 1245system.cpu1.dcache.overall_misses::total 188010 # number of overall misses 1246system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1494406500 # number of ReadReq miss cycles 1247system.cpu1.dcache.ReadReq_miss_latency::total 1494406500 # number of ReadReq miss cycles 1248system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166606000 # number of WriteReq miss cycles 1249system.cpu1.dcache.WriteReq_miss_latency::total 1166606000 # number of WriteReq miss cycles 1250system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85391000 # number of LoadLockedReq miss cycles 1251system.cpu1.dcache.LoadLockedReq_miss_latency::total 85391000 # number of LoadLockedReq miss cycles 1252system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44592000 # number of StoreCondReq miss cycles 1253system.cpu1.dcache.StoreCondReq_miss_latency::total 44592000 # number of StoreCondReq miss cycles 1254system.cpu1.dcache.demand_miss_latency::cpu1.data 2661012500 # number of demand (read+write) miss cycles 1255system.cpu1.dcache.demand_miss_latency::total 2661012500 # number of demand (read+write) miss cycles 1256system.cpu1.dcache.overall_miss_latency::cpu1.data 2661012500 # number of overall miss cycles 1257system.cpu1.dcache.overall_miss_latency::total 2661012500 # number of overall miss cycles 1258system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452457 # number of ReadReq accesses(hits+misses) 1259system.cpu1.dcache.ReadReq_accesses::total 2452457 # number of ReadReq accesses(hits+misses) 1260system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763994 # number of WriteReq accesses(hits+misses) 1261system.cpu1.dcache.WriteReq_accesses::total 1763994 # number of WriteReq accesses(hits+misses) 1262system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59566 # number of LoadLockedReq accesses(hits+misses) 1263system.cpu1.dcache.LoadLockedReq_accesses::total 59566 # number of LoadLockedReq accesses(hits+misses) 1264system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59069 # number of StoreCondReq accesses(hits+misses) 1265system.cpu1.dcache.StoreCondReq_accesses::total 59069 # number of StoreCondReq accesses(hits+misses) 1266system.cpu1.dcache.demand_accesses::cpu1.data 4216451 # number of demand (read+write) accesses 1267system.cpu1.dcache.demand_accesses::total 4216451 # number of demand (read+write) accesses 1268system.cpu1.dcache.overall_accesses::cpu1.data 4216451 # number of overall (read+write) accesses 1269system.cpu1.dcache.overall_accesses::total 4216451 # number of overall (read+write) accesses 1270system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050252 # miss rate for ReadReq accesses 1271system.cpu1.dcache.ReadReq_miss_rate::total 0.050252 # miss rate for ReadReq accesses 1272system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036717 # miss rate for WriteReq accesses 1273system.cpu1.dcache.WriteReq_miss_rate::total 0.036717 # miss rate for WriteReq accesses 1274system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156902 # miss rate for LoadLockedReq accesses 1275system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156902 # miss rate for LoadLockedReq accesses 1276system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103980 # miss rate for StoreCondReq accesses 1277system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103980 # miss rate for StoreCondReq accesses 1278system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044590 # miss rate for demand accesses 1279system.cpu1.dcache.demand_miss_rate::total 0.044590 # miss rate for demand accesses 1280system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044590 # miss rate for overall accesses 1281system.cpu1.dcache.overall_miss_rate::total 0.044590 # miss rate for overall accesses 1282system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12125.887489 # average ReadReq miss latency 1283system.cpu1.dcache.ReadReq_avg_miss_latency::total 12125.887489 # average ReadReq miss latency 1284system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.795766 # average WriteReq miss latency 1285system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.795766 # average WriteReq miss latency 1286system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9136.635994 # average LoadLockedReq miss latency 1287system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9136.635994 # average LoadLockedReq miss latency 1288system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7260.175838 # average StoreCondReq miss latency 1289system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7260.175838 # average StoreCondReq miss latency 1290system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency 1291system.cpu1.dcache.demand_avg_miss_latency::total 14153.568959 # average overall miss latency 1292system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14153.568959 # average overall miss latency 1293system.cpu1.dcache.overall_avg_miss_latency::total 14153.568959 # average overall miss latency |
1294system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1295system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1296system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1297system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1298system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1299system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1300system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1301system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1294system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1295system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1296system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1297system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1298system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1299system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1300system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1301system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
1302system.cpu1.dcache.writebacks::writebacks 119115 # number of writebacks 1303system.cpu1.dcache.writebacks::total 119115 # number of writebacks 1304system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123236 # number of ReadReq MSHR misses 1305system.cpu1.dcache.ReadReq_mshr_misses::total 123236 # number of ReadReq MSHR misses 1306system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64754 # number of WriteReq MSHR misses 1307system.cpu1.dcache.WriteReq_mshr_misses::total 64754 # number of WriteReq MSHR misses 1308system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9347 # number of LoadLockedReq MSHR misses 1309system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9347 # number of LoadLockedReq MSHR misses 1310system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6143 # number of StoreCondReq MSHR misses 1311system.cpu1.dcache.StoreCondReq_mshr_misses::total 6143 # number of StoreCondReq MSHR misses 1312system.cpu1.dcache.demand_mshr_misses::cpu1.data 187990 # number of demand (read+write) MSHR misses 1313system.cpu1.dcache.demand_mshr_misses::total 187990 # number of demand (read+write) MSHR misses 1314system.cpu1.dcache.overall_mshr_misses::cpu1.data 187990 # number of overall MSHR misses 1315system.cpu1.dcache.overall_mshr_misses::total 187990 # number of overall MSHR misses 1316system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247220000 # number of ReadReq MSHR miss cycles 1317system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247220000 # number of ReadReq MSHR miss cycles 1318system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036791500 # number of WriteReq MSHR miss cycles 1319system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1036791500 # number of WriteReq MSHR miss cycles 1320system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66696000 # number of LoadLockedReq MSHR miss cycles 1321system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66696000 # number of LoadLockedReq MSHR miss cycles 1322system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32229500 # number of StoreCondReq MSHR miss cycles 1323system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32229500 # number of StoreCondReq MSHR miss cycles 1324system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284011500 # number of demand (read+write) MSHR miss cycles 1325system.cpu1.dcache.demand_mshr_miss_latency::total 2284011500 # number of demand (read+write) MSHR miss cycles 1326system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284011500 # number of overall MSHR miss cycles 1327system.cpu1.dcache.overall_mshr_miss_latency::total 2284011500 # number of overall MSHR miss cycles | 1302system.cpu1.dcache.writebacks::writebacks 119125 # number of writebacks 1303system.cpu1.dcache.writebacks::total 119125 # number of writebacks 1304system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123241 # number of ReadReq MSHR misses 1305system.cpu1.dcache.ReadReq_mshr_misses::total 123241 # number of ReadReq MSHR misses 1306system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64769 # number of WriteReq MSHR misses 1307system.cpu1.dcache.WriteReq_mshr_misses::total 64769 # number of WriteReq MSHR misses 1308system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9346 # number of LoadLockedReq MSHR misses 1309system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9346 # number of LoadLockedReq MSHR misses 1310system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6142 # number of StoreCondReq MSHR misses 1311system.cpu1.dcache.StoreCondReq_mshr_misses::total 6142 # number of StoreCondReq MSHR misses 1312system.cpu1.dcache.demand_mshr_misses::cpu1.data 188010 # number of demand (read+write) MSHR misses 1313system.cpu1.dcache.demand_mshr_misses::total 188010 # number of demand (read+write) MSHR misses 1314system.cpu1.dcache.overall_mshr_misses::cpu1.data 188010 # number of overall MSHR misses 1315system.cpu1.dcache.overall_mshr_misses::total 188010 # number of overall MSHR misses 1316system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247924500 # number of ReadReq MSHR miss cycles 1317system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247924500 # number of ReadReq MSHR miss cycles 1318system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1037068000 # number of WriteReq MSHR miss cycles 1319system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1037068000 # number of WriteReq MSHR miss cycles 1320system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66699000 # number of LoadLockedReq MSHR miss cycles 1321system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66699000 # number of LoadLockedReq MSHR miss cycles 1322system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32308000 # number of StoreCondReq MSHR miss cycles 1323system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32308000 # number of StoreCondReq MSHR miss cycles 1324system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284992500 # number of demand (read+write) MSHR miss cycles 1325system.cpu1.dcache.demand_mshr_miss_latency::total 2284992500 # number of demand (read+write) MSHR miss cycles 1326system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284992500 # number of overall MSHR miss cycles 1327system.cpu1.dcache.overall_mshr_miss_latency::total 2284992500 # number of overall MSHR miss cycles |
1328system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles 1329system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles | 1328system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles 1329system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles |
1330system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723171500 # number of WriteReq MSHR uncacheable cycles 1331system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723171500 # number of WriteReq MSHR uncacheable cycles 1332system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742552500 # number of overall MSHR uncacheable cycles 1333system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742552500 # number of overall MSHR uncacheable cycles 1334system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050253 # mshr miss rate for ReadReq accesses 1335system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050253 # mshr miss rate for ReadReq accesses 1336system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses 1337system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036709 # mshr miss rate for WriteReq accesses 1338system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156916 # mshr miss rate for LoadLockedReq accesses 1339system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156916 # mshr miss rate for LoadLockedReq accesses 1340system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103995 # mshr miss rate for StoreCondReq accesses 1341system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103995 # mshr miss rate for StoreCondReq accesses 1342system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for demand accesses 1343system.cpu1.dcache.demand_mshr_miss_rate::total 0.044586 # mshr miss rate for demand accesses 1344system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for overall accesses 1345system.cpu1.dcache.overall_mshr_miss_rate::total 0.044586 # mshr miss rate for overall accesses 1346system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10120.581648 # average ReadReq mshr miss latency 1347system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10120.581648 # average ReadReq mshr miss latency 1348system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.234827 # average WriteReq mshr miss latency 1349system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.234827 # average WriteReq mshr miss latency 1350system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.551514 # average LoadLockedReq mshr miss latency 1351system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.551514 # average LoadLockedReq mshr miss latency 1352system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5246.540778 # average StoreCondReq mshr miss latency 1353system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5246.540778 # average StoreCondReq mshr miss latency 1354system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency 1355system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency 1356system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency 1357system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency | 1330system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723292500 # number of WriteReq MSHR uncacheable cycles 1331system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723292500 # number of WriteReq MSHR uncacheable cycles 1332system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742673500 # number of overall MSHR uncacheable cycles 1333system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742673500 # number of overall MSHR uncacheable cycles 1334system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050252 # mshr miss rate for ReadReq accesses 1335system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050252 # mshr miss rate for ReadReq accesses 1336system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036717 # mshr miss rate for WriteReq accesses 1337system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036717 # mshr miss rate for WriteReq accesses 1338system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156902 # mshr miss rate for LoadLockedReq accesses 1339system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156902 # mshr miss rate for LoadLockedReq accesses 1340system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103980 # mshr miss rate for StoreCondReq accesses 1341system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103980 # mshr miss rate for StoreCondReq accesses 1342system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for demand accesses 1343system.cpu1.dcache.demand_mshr_miss_rate::total 0.044590 # mshr miss rate for demand accesses 1344system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044590 # mshr miss rate for overall accesses 1345system.cpu1.dcache.overall_mshr_miss_rate::total 0.044590 # mshr miss rate for overall accesses 1346system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10125.887489 # average ReadReq mshr miss latency 1347system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10125.887489 # average ReadReq mshr miss latency 1348system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.795766 # average WriteReq mshr miss latency 1349system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.795766 # average WriteReq mshr miss latency 1350system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7136.635994 # average LoadLockedReq mshr miss latency 1351system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7136.635994 # average LoadLockedReq mshr miss latency 1352system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5260.175838 # average StoreCondReq mshr miss latency 1353system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5260.175838 # average StoreCondReq mshr miss latency 1354system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency 1355system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency 1356system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12153.568959 # average overall mshr miss latency 1357system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12153.568959 # average overall mshr miss latency |
1358system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1359system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1360system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1361system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1362system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1363system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1364system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1365 1366---------- End Simulation Statistics ---------- | 1358system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1359system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1360system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1361system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1362system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1363system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1364system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1365 1366---------- End Simulation Statistics ---------- |