| stats.txt (9289:a31a1243a3ed) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.955746 # Number of seconds simulated 4sim_ticks 1955746240500 # Number of ticks simulated 5final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.950813 # Number of seconds simulated 4sim_ticks 1950813247500 # Number of ticks simulated 5final_tick 1950813247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1240365 # Simulator instruction rate (inst/s) 8host_op_rate 1240364 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39831169965 # Simulator tick rate (ticks/s) 10host_mem_usage 291792 # Number of bytes of host memory used 11host_seconds 49.10 # Real time elapsed on the host 12sim_insts 60902973 # Number of instructions simulated 13sim_ops 60902973 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 830080 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24726528 # Number of bytes read from this memory | 7host_inst_rate 1287440 # Simulator instruction rate (inst/s) 8host_op_rate 1287440 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41184614921 # Simulator tick rate (ticks/s) 10host_mem_usage 325660 # Number of bytes of host memory used 11host_seconds 47.37 # Real time elapsed on the host 12sim_insts 60982794 # Number of instructions simulated 13sim_ops 60982794 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24727680 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory | 16system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 438464 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28681152 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 830080 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 865280 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7699072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7699072 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 12970 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 386352 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu1.inst 38464 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 439808 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28684096 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 827264 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 38464 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 865728 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7706368 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7706368 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 12926 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 386370 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory | 27system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 6851 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448143 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120298 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120298 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 424431 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12643014 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1355431 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 17998 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 224193 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14665068 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 424431 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 17998 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 442430 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3936642 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3936642 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3936642 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 424431 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12643014 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1355431 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 17998 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 224193 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18601710 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 341281 # number of replacements 52system.l2c.tagsinuse 65229.882617 # Cycle average of tags in use 53system.l2c.total_refs 2441318 # Total number of references to valid blocks. 54system.l2c.sampled_refs 406256 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.009309 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 7648586000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 55341.365970 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 4865.877793 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 4868.452553 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 116.161458 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 38.024844 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.844442 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.074247 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.074287 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.001772 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000580 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.995329 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 685804 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 664321 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 316190 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 108937 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1775252 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 793334 # number of Writeback hits 74system.l2c.Writeback_hits::total 793334 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 732 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 126580 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 47318 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 173898 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 685804 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 790901 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 316190 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 156255 # number of demand (read+write) hits 88system.l2c.demand_hits::total 1949150 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 685804 # number of overall hits 90system.l2c.overall_hits::cpu0.data 790901 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 316190 # number of overall hits 92system.l2c.overall_hits::cpu1.data 156255 # number of overall hits 93system.l2c.overall_hits::total 1949150 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 12970 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 271621 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 244 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 285396 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2948 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 1741 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 4689 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 895 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 1787 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 115480 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 6627 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 122107 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 12970 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 387101 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 6871 # number of demand (read+write) misses 112system.l2c.demand_misses::total 407503 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 12970 # number of overall misses 114system.l2c.overall_misses::cpu0.data 387101 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 561 # number of overall misses 116system.l2c.overall_misses::cpu1.data 6871 # number of overall misses 117system.l2c.overall_misses::total 407503 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 679344500 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14131444000 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 29382500 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 12805500 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 14852976500 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2720000 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 22059498 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 24779498 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2047000 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 521500 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 2568500 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 6014286500 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 347569000 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6361855500 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 679344500 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 20145730500 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 29382500 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 360374500 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 21214832000 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 679344500 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 20145730500 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 29382500 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 360374500 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 21214832000 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 698774 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 935942 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 316751 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 109181 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2060648 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 793334 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 793334 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 3131 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 2290 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 5421 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 927 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 917 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 1844 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 242060 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 53945 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 296005 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 698774 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 1178002 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 316751 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 163126 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2356653 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 698774 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 1178002 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 316751 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 163126 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2356653 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.018561 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.290211 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.001771 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.002235 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.138498 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941552 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760262 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.864970 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.962244 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976009 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.969089 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.477072 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.122847 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.412517 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.018561 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.328608 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.001771 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.042121 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.172916 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.018561 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.328608 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.001771 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.042121 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.172916 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52378.141866 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52026.330807 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52375.222816 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 52481.557377 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52043.394091 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 922.659430 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12670.590465 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 5284.601834 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2294.843049 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.681564 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 1437.325126 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52080.762903 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52447.412102 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 52100.661715 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52060.554155 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52060.554155 # average overall miss latency | 28system.physmem.num_reads::cpu1.inst 601 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 6872 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448189 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120412 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120412 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 424061 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12675575 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1358859 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 19717 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 225449 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14703661 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 424061 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 19717 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 443778 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3950336 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3950336 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3950336 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 424061 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12675575 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1358859 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 19717 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 225449 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18653997 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 448189 # Total number of read requests seen 52system.physmem.writeReqs 120412 # Total number of write requests seen 53system.physmem.cpureqs 599134 # Reqs generatd by CPU via cache - shady 54system.physmem.bytesRead 28684096 # Total number of bytes read from memory 55system.physmem.bytesWritten 7706368 # Total number of bytes written to memory 56system.physmem.bytesConsumedRd 28684096 # bytesRead derated as per pkt->getSize() 57system.physmem.bytesConsumedWr 7706368 # bytesWritten derated as per pkt->getSize() 58system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q 59system.physmem.neitherReadNorWrite 7172 # Reqs where no action is needed 60system.physmem.perBankRdReqs::0 28371 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::1 27660 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::2 28102 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::3 27702 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::4 28190 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::5 28020 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::6 27664 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::7 27960 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::8 28118 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::9 28027 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::10 27925 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::11 28196 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::12 28402 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::13 28329 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::14 27819 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::15 27647 # Track reads on a per bank basis 76system.physmem.perBankWrReqs::0 7817 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::1 7270 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::2 7535 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::3 7162 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::4 7656 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::5 7513 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::7 7412 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::8 7610 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::9 7562 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::10 7469 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::11 7772 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::12 8034 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::13 7948 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::14 7345 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::15 7157 # Track writes on a per bank basis 92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 93system.physmem.numWrRetry 522 # Number of times wr buffer was full causing retry 94system.physmem.totGap 1950759532000 # Total gap between requests 95system.physmem.readPktSize::0 0 # Categorize read packet sizes 96system.physmem.readPktSize::1 0 # Categorize read packet sizes 97system.physmem.readPktSize::2 0 # Categorize read packet sizes 98system.physmem.readPktSize::3 0 # Categorize read packet sizes 99system.physmem.readPktSize::4 0 # Categorize read packet sizes 100system.physmem.readPktSize::5 0 # Categorize read packet sizes 101system.physmem.readPktSize::6 448189 # Categorize read packet sizes 102system.physmem.readPktSize::7 0 # Categorize read packet sizes 103system.physmem.readPktSize::8 0 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # categorize write packet sizes 105system.physmem.writePktSize::1 0 # categorize write packet sizes 106system.physmem.writePktSize::2 0 # categorize write packet sizes 107system.physmem.writePktSize::3 0 # categorize write packet sizes 108system.physmem.writePktSize::4 0 # categorize write packet sizes 109system.physmem.writePktSize::5 0 # categorize write packet sizes 110system.physmem.writePktSize::6 120934 # categorize write packet sizes 111system.physmem.writePktSize::7 0 # categorize write packet sizes 112system.physmem.writePktSize::8 0 # categorize write packet sizes 113system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 114system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::6 7172 # categorize neither packet sizes 120system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 121system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 122system.physmem.rdQLenPdf::0 409832 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::1 7493 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::2 5295 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::3 2367 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::4 2815 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::5 2388 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::6 1774 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::7 1998 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::8 1671 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::9 1947 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::10 1601 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::11 1562 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::12 1645 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::13 1753 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::14 1208 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::15 1428 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::16 874 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::17 246 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::18 138 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::19 95 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 155system.physmem.wrQLenPdf::0 4346 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::2 5068 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::3 5119 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::4 5195 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::5 5208 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::6 5231 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::8 5231 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::9 5235 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::10 5235 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::11 5235 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::12 5235 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::13 5235 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::14 5235 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::15 5235 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::16 5235 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::17 5235 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::18 5235 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::19 5235 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::20 5235 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::21 5235 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::22 5235 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::23 890 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::24 273 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::25 168 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::26 117 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::27 41 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 188system.physmem.totQLat 2865774804 # Total cycles spent in queuing delays 189system.physmem.totMemAccLat 10947900804 # Sum of mem lat for all requests 190system.physmem.totBusLat 1792528000 # Total cycles spent in databus access 191system.physmem.totBankLat 6289598000 # Total cycles spent in bank access 192system.physmem.avgQLat 6394.93 # Average queueing delay per request 193system.physmem.avgBankLat 14035.15 # Average bank access latency per request 194system.physmem.avgBusLat 4000.00 # Average bus latency per request 195system.physmem.avgMemAccLat 24430.08 # Average memory access latency 196system.physmem.avgRdBW 14.70 # Average achieved read bandwidth in MB/s 197system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s 198system.physmem.avgConsumedRdBW 14.70 # Average consumed read bandwidth in MB/s 199system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s 200system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 201system.physmem.busUtil 0.12 # Data bus utilization in percentage 202system.physmem.avgRdQLen 0.01 # Average read queue length over time 203system.physmem.avgWrQLen 10.50 # Average write queue length over time 204system.physmem.readRowHits 428033 # Number of row buffer hits during reads 205system.physmem.writeRowHits 76777 # Number of row buffer hits during writes 206system.physmem.readRowHitRate 95.51 # Row buffer hit rate for reads 207system.physmem.writeRowHitRate 63.76 # Row buffer hit rate for writes 208system.physmem.avgGap 3430805.67 # Average gap between requests 209system.l2c.replacements 341333 # number of replacements 210system.l2c.tagsinuse 65247.038846 # Cycle average of tags in use 211system.l2c.total_refs 2438074 # Total number of references to valid blocks. 212system.l2c.sampled_refs 406309 # Sample count of references to valid blocks. 213system.l2c.avg_refs 6.000541 # Average number of references to valid blocks. 214system.l2c.warmup_cycle 6891280002 # Cycle when the warmup percentage was hit. 215system.l2c.occ_blocks::writebacks 55545.297156 # Average occupied blocks per requestor 216system.l2c.occ_blocks::cpu0.inst 4807.218464 # Average occupied blocks per requestor 217system.l2c.occ_blocks::cpu0.data 4686.690338 # Average occupied blocks per requestor 218system.l2c.occ_blocks::cpu1.inst 164.376104 # Average occupied blocks per requestor 219system.l2c.occ_blocks::cpu1.data 43.456784 # Average occupied blocks per requestor 220system.l2c.occ_percent::writebacks 0.847554 # Average percentage of cache occupancy 221system.l2c.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy 222system.l2c.occ_percent::cpu0.data 0.071513 # Average percentage of cache occupancy 223system.l2c.occ_percent::cpu1.inst 0.002508 # Average percentage of cache occupancy 224system.l2c.occ_percent::cpu1.data 0.000663 # Average percentage of cache occupancy 225system.l2c.occ_percent::total 0.995591 # Average percentage of cache occupancy 226system.l2c.ReadReq_hits::cpu0.inst 674220 # number of ReadReq hits 227system.l2c.ReadReq_hits::cpu0.data 658221 # number of ReadReq hits 228system.l2c.ReadReq_hits::cpu1.inst 328583 # number of ReadReq hits 229system.l2c.ReadReq_hits::cpu1.data 113537 # number of ReadReq hits 230system.l2c.ReadReq_hits::total 1774561 # number of ReadReq hits 231system.l2c.Writeback_hits::writebacks 791464 # number of Writeback hits 232system.l2c.Writeback_hits::total 791464 # number of Writeback hits 233system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits 234system.l2c.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits 235system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits 236system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits 237system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 238system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits 239system.l2c.ReadExReq_hits::cpu0.data 123896 # number of ReadExReq hits 240system.l2c.ReadExReq_hits::cpu1.data 48958 # number of ReadExReq hits 241system.l2c.ReadExReq_hits::total 172854 # number of ReadExReq hits 242system.l2c.demand_hits::cpu0.inst 674220 # number of demand (read+write) hits 243system.l2c.demand_hits::cpu0.data 782117 # number of demand (read+write) hits 244system.l2c.demand_hits::cpu1.inst 328583 # number of demand (read+write) hits 245system.l2c.demand_hits::cpu1.data 162495 # number of demand (read+write) hits 246system.l2c.demand_hits::total 1947415 # number of demand (read+write) hits 247system.l2c.overall_hits::cpu0.inst 674220 # number of overall hits 248system.l2c.overall_hits::cpu0.data 782117 # number of overall hits 249system.l2c.overall_hits::cpu1.inst 328583 # number of overall hits 250system.l2c.overall_hits::cpu1.data 162495 # number of overall hits 251system.l2c.overall_hits::total 1947415 # number of overall hits 252system.l2c.ReadReq_misses::cpu0.inst 12926 # number of ReadReq misses 253system.l2c.ReadReq_misses::cpu0.data 271631 # number of ReadReq misses 254system.l2c.ReadReq_misses::cpu1.inst 612 # number of ReadReq misses 255system.l2c.ReadReq_misses::cpu1.data 247 # number of ReadReq misses 256system.l2c.ReadReq_misses::total 285416 # number of ReadReq misses 257system.l2c.UpgradeReq_misses::cpu0.data 2967 # number of UpgradeReq misses 258system.l2c.UpgradeReq_misses::cpu1.data 1807 # number of UpgradeReq misses 259system.l2c.UpgradeReq_misses::total 4774 # number of UpgradeReq misses 260system.l2c.SCUpgradeReq_misses::cpu0.data 939 # number of SCUpgradeReq misses 261system.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses 262system.l2c.SCUpgradeReq_misses::total 1881 # number of SCUpgradeReq misses 263system.l2c.ReadExReq_misses::cpu0.data 115504 # number of ReadExReq misses 264system.l2c.ReadExReq_misses::cpu1.data 6643 # number of ReadExReq misses 265system.l2c.ReadExReq_misses::total 122147 # number of ReadExReq misses 266system.l2c.demand_misses::cpu0.inst 12926 # number of demand (read+write) misses 267system.l2c.demand_misses::cpu0.data 387135 # number of demand (read+write) misses 268system.l2c.demand_misses::cpu1.inst 612 # number of demand (read+write) misses 269system.l2c.demand_misses::cpu1.data 6890 # number of demand (read+write) misses 270system.l2c.demand_misses::total 407563 # number of demand (read+write) misses 271system.l2c.overall_misses::cpu0.inst 12926 # number of overall misses 272system.l2c.overall_misses::cpu0.data 387135 # number of overall misses 273system.l2c.overall_misses::cpu1.inst 612 # number of overall misses 274system.l2c.overall_misses::cpu1.data 6890 # number of overall misses 275system.l2c.overall_misses::total 407563 # number of overall misses 276system.l2c.ReadReq_miss_latency::cpu0.inst 713316000 # number of ReadReq miss cycles 277system.l2c.ReadReq_miss_latency::cpu0.data 11504038499 # number of ReadReq miss cycles 278system.l2c.ReadReq_miss_latency::cpu1.inst 34128500 # number of ReadReq miss cycles 279system.l2c.ReadReq_miss_latency::cpu1.data 15210000 # number of ReadReq miss cycles 280system.l2c.ReadReq_miss_latency::total 12266692999 # number of ReadReq miss cycles 281system.l2c.UpgradeReq_miss_latency::cpu0.data 1244500 # number of UpgradeReq miss cycles 282system.l2c.UpgradeReq_miss_latency::cpu1.data 10405497 # number of UpgradeReq miss cycles 283system.l2c.UpgradeReq_miss_latency::total 11649997 # number of UpgradeReq miss cycles 284system.l2c.SCUpgradeReq_miss_latency::cpu0.data 841000 # number of SCUpgradeReq miss cycles 285system.l2c.SCUpgradeReq_miss_latency::cpu1.data 205500 # number of SCUpgradeReq miss cycles 286system.l2c.SCUpgradeReq_miss_latency::total 1046500 # number of SCUpgradeReq miss cycles 287system.l2c.ReadExReq_miss_latency::cpu0.data 5694760500 # number of ReadExReq miss cycles 288system.l2c.ReadExReq_miss_latency::cpu1.data 427293500 # number of ReadExReq miss cycles 289system.l2c.ReadExReq_miss_latency::total 6122054000 # number of ReadExReq miss cycles 290system.l2c.demand_miss_latency::cpu0.inst 713316000 # number of demand (read+write) miss cycles 291system.l2c.demand_miss_latency::cpu0.data 17198798999 # number of demand (read+write) miss cycles 292system.l2c.demand_miss_latency::cpu1.inst 34128500 # number of demand (read+write) miss cycles 293system.l2c.demand_miss_latency::cpu1.data 442503500 # number of demand (read+write) miss cycles 294system.l2c.demand_miss_latency::total 18388746999 # number of demand (read+write) miss cycles 295system.l2c.overall_miss_latency::cpu0.inst 713316000 # number of overall miss cycles 296system.l2c.overall_miss_latency::cpu0.data 17198798999 # number of overall miss cycles 297system.l2c.overall_miss_latency::cpu1.inst 34128500 # number of overall miss cycles 298system.l2c.overall_miss_latency::cpu1.data 442503500 # number of overall miss cycles 299system.l2c.overall_miss_latency::total 18388746999 # number of overall miss cycles 300system.l2c.ReadReq_accesses::cpu0.inst 687146 # number of ReadReq accesses(hits+misses) 301system.l2c.ReadReq_accesses::cpu0.data 929852 # number of ReadReq accesses(hits+misses) 302system.l2c.ReadReq_accesses::cpu1.inst 329195 # number of ReadReq accesses(hits+misses) 303system.l2c.ReadReq_accesses::cpu1.data 113784 # number of ReadReq accesses(hits+misses) 304system.l2c.ReadReq_accesses::total 2059977 # number of ReadReq accesses(hits+misses) 305system.l2c.Writeback_accesses::writebacks 791464 # number of Writeback accesses(hits+misses) 306system.l2c.Writeback_accesses::total 791464 # number of Writeback accesses(hits+misses) 307system.l2c.UpgradeReq_accesses::cpu0.data 3143 # number of UpgradeReq accesses(hits+misses) 308system.l2c.UpgradeReq_accesses::cpu1.data 2374 # number of UpgradeReq accesses(hits+misses) 309system.l2c.UpgradeReq_accesses::total 5517 # number of UpgradeReq accesses(hits+misses) 310system.l2c.SCUpgradeReq_accesses::cpu0.data 975 # number of SCUpgradeReq accesses(hits+misses) 311system.l2c.SCUpgradeReq_accesses::cpu1.data 965 # number of SCUpgradeReq accesses(hits+misses) 312system.l2c.SCUpgradeReq_accesses::total 1940 # number of SCUpgradeReq accesses(hits+misses) 313system.l2c.ReadExReq_accesses::cpu0.data 239400 # number of ReadExReq accesses(hits+misses) 314system.l2c.ReadExReq_accesses::cpu1.data 55601 # number of ReadExReq accesses(hits+misses) 315system.l2c.ReadExReq_accesses::total 295001 # number of ReadExReq accesses(hits+misses) 316system.l2c.demand_accesses::cpu0.inst 687146 # number of demand (read+write) accesses 317system.l2c.demand_accesses::cpu0.data 1169252 # number of demand (read+write) accesses 318system.l2c.demand_accesses::cpu1.inst 329195 # number of demand (read+write) accesses 319system.l2c.demand_accesses::cpu1.data 169385 # number of demand (read+write) accesses 320system.l2c.demand_accesses::total 2354978 # number of demand (read+write) accesses 321system.l2c.overall_accesses::cpu0.inst 687146 # number of overall (read+write) accesses 322system.l2c.overall_accesses::cpu0.data 1169252 # number of overall (read+write) accesses 323system.l2c.overall_accesses::cpu1.inst 329195 # number of overall (read+write) accesses 324system.l2c.overall_accesses::cpu1.data 169385 # number of overall (read+write) accesses 325system.l2c.overall_accesses::total 2354978 # number of overall (read+write) accesses 326system.l2c.ReadReq_miss_rate::cpu0.inst 0.018811 # miss rate for ReadReq accesses 327system.l2c.ReadReq_miss_rate::cpu0.data 0.292123 # miss rate for ReadReq accesses 328system.l2c.ReadReq_miss_rate::cpu1.inst 0.001859 # miss rate for ReadReq accesses 329system.l2c.ReadReq_miss_rate::cpu1.data 0.002171 # miss rate for ReadReq accesses 330system.l2c.ReadReq_miss_rate::total 0.138553 # miss rate for ReadReq accesses 331system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944003 # miss rate for UpgradeReq accesses 332system.l2c.UpgradeReq_miss_rate::cpu1.data 0.761163 # miss rate for UpgradeReq accesses 333system.l2c.UpgradeReq_miss_rate::total 0.865325 # miss rate for UpgradeReq accesses 334system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963077 # miss rate for SCUpgradeReq accesses 335system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976166 # miss rate for SCUpgradeReq accesses 336system.l2c.SCUpgradeReq_miss_rate::total 0.969588 # miss rate for SCUpgradeReq accesses 337system.l2c.ReadExReq_miss_rate::cpu0.data 0.482473 # miss rate for ReadExReq accesses 338system.l2c.ReadExReq_miss_rate::cpu1.data 0.119476 # miss rate for ReadExReq accesses 339system.l2c.ReadExReq_miss_rate::total 0.414056 # miss rate for ReadExReq accesses 340system.l2c.demand_miss_rate::cpu0.inst 0.018811 # miss rate for demand accesses 341system.l2c.demand_miss_rate::cpu0.data 0.331096 # miss rate for demand accesses 342system.l2c.demand_miss_rate::cpu1.inst 0.001859 # miss rate for demand accesses 343system.l2c.demand_miss_rate::cpu1.data 0.040677 # miss rate for demand accesses 344system.l2c.demand_miss_rate::total 0.173064 # miss rate for demand accesses 345system.l2c.overall_miss_rate::cpu0.inst 0.018811 # miss rate for overall accesses 346system.l2c.overall_miss_rate::cpu0.data 0.331096 # miss rate for overall accesses 347system.l2c.overall_miss_rate::cpu1.inst 0.001859 # miss rate for overall accesses 348system.l2c.overall_miss_rate::cpu1.data 0.040677 # miss rate for overall accesses 349system.l2c.overall_miss_rate::total 0.173064 # miss rate for overall accesses 350system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55184.589200 # average ReadReq miss latency 351system.l2c.ReadReq_avg_miss_latency::cpu0.data 42351.714270 # average ReadReq miss latency 352system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55765.522876 # average ReadReq miss latency 353system.l2c.ReadReq_avg_miss_latency::cpu1.data 61578.947368 # average ReadReq miss latency 354system.l2c.ReadReq_avg_miss_latency::total 42978.294836 # average ReadReq miss latency 355system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 419.447253 # average UpgradeReq miss latency 356system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5758.437742 # average UpgradeReq miss latency 357system.l2c.UpgradeReq_avg_miss_latency::total 2440.301005 # average UpgradeReq miss latency 358system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 895.633653 # average SCUpgradeReq miss latency 359system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 218.152866 # average SCUpgradeReq miss latency 360system.l2c.SCUpgradeReq_avg_miss_latency::total 556.353004 # average SCUpgradeReq miss latency 361system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49303.578231 # average ReadExReq miss latency 362system.l2c.ReadExReq_avg_miss_latency::cpu1.data 64322.369411 # average ReadExReq miss latency 363system.l2c.ReadExReq_avg_miss_latency::total 50120.379543 # average ReadExReq miss latency 364system.l2c.demand_avg_miss_latency::cpu0.inst 55184.589200 # average overall miss latency 365system.l2c.demand_avg_miss_latency::cpu0.data 44425.843695 # average overall miss latency 366system.l2c.demand_avg_miss_latency::cpu1.inst 55765.522876 # average overall miss latency 367system.l2c.demand_avg_miss_latency::cpu1.data 64224.020319 # average overall miss latency 368system.l2c.demand_avg_miss_latency::total 45118.784087 # average overall miss latency 369system.l2c.overall_avg_miss_latency::cpu0.inst 55184.589200 # average overall miss latency 370system.l2c.overall_avg_miss_latency::cpu0.data 44425.843695 # average overall miss latency 371system.l2c.overall_avg_miss_latency::cpu1.inst 55765.522876 # average overall miss latency 372system.l2c.overall_avg_miss_latency::cpu1.data 64224.020319 # average overall miss latency 373system.l2c.overall_avg_miss_latency::total 45118.784087 # average overall miss latency |
| 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed | 374system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 377system.l2c.blocked::no_targets 0 # number of cycles access was blocked 378system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.l2c.fast_writes 0 # number of fast writes performed 381system.l2c.cache_copies 0 # number of cache copies performed |
| 224system.l2c.writebacks::writebacks 78778 # number of writebacks 225system.l2c.writebacks::total 78778 # number of writebacks | 382system.l2c.writebacks::writebacks 78892 # number of writebacks 383system.l2c.writebacks::total 78892 # number of writebacks |
| 226system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 227system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 228system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 229system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 230system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 231system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits | 384system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 385system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 386system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 387system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 388system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 389system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits |
| 232system.l2c.ReadReq_mshr_misses::cpu0.inst 12970 # number of ReadReq MSHR misses 233system.l2c.ReadReq_mshr_misses::cpu0.data 271621 # number of ReadReq MSHR misses 234system.l2c.ReadReq_mshr_misses::cpu1.inst 550 # number of ReadReq MSHR misses 235system.l2c.ReadReq_mshr_misses::cpu1.data 244 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::total 285385 # number of ReadReq MSHR misses 237system.l2c.UpgradeReq_mshr_misses::cpu0.data 2948 # number of UpgradeReq MSHR misses 238system.l2c.UpgradeReq_mshr_misses::cpu1.data 1741 # number of UpgradeReq MSHR misses 239system.l2c.UpgradeReq_mshr_misses::total 4689 # number of UpgradeReq MSHR misses 240system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 892 # number of SCUpgradeReq MSHR misses 241system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 895 # number of SCUpgradeReq MSHR misses 242system.l2c.SCUpgradeReq_mshr_misses::total 1787 # number of SCUpgradeReq MSHR misses 243system.l2c.ReadExReq_mshr_misses::cpu0.data 115480 # number of ReadExReq MSHR misses 244system.l2c.ReadExReq_mshr_misses::cpu1.data 6627 # number of ReadExReq MSHR misses 245system.l2c.ReadExReq_mshr_misses::total 122107 # number of ReadExReq MSHR misses 246system.l2c.demand_mshr_misses::cpu0.inst 12970 # number of demand (read+write) MSHR misses 247system.l2c.demand_mshr_misses::cpu0.data 387101 # number of demand (read+write) MSHR misses 248system.l2c.demand_mshr_misses::cpu1.inst 550 # number of demand (read+write) MSHR misses 249system.l2c.demand_mshr_misses::cpu1.data 6871 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::total 407492 # number of demand (read+write) MSHR misses 251system.l2c.overall_mshr_misses::cpu0.inst 12970 # number of overall MSHR misses 252system.l2c.overall_mshr_misses::cpu0.data 387101 # number of overall MSHR misses 253system.l2c.overall_mshr_misses::cpu1.inst 550 # number of overall MSHR misses 254system.l2c.overall_mshr_misses::cpu1.data 6871 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::total 407492 # number of overall MSHR misses 256system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 519097000 # number of ReadReq MSHR miss cycles 257system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10870382000 # number of ReadReq MSHR miss cycles 258system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 22042500 # number of ReadReq MSHR miss cycles 259system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9816500 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::total 11421338000 # number of ReadReq MSHR miss cycles 261system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 117985500 # number of UpgradeReq MSHR miss cycles 262system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 69640998 # number of UpgradeReq MSHR miss cycles 263system.l2c.UpgradeReq_mshr_miss_latency::total 187626498 # number of UpgradeReq MSHR miss cycles 264system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 35714975 # number of SCUpgradeReq MSHR miss cycles 265system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 35800000 # number of SCUpgradeReq MSHR miss cycles 266system.l2c.SCUpgradeReq_mshr_miss_latency::total 71514975 # number of SCUpgradeReq MSHR miss cycles 267system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4619582000 # number of ReadExReq MSHR miss cycles 268system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 265544000 # number of ReadExReq MSHR miss cycles 269system.l2c.ReadExReq_mshr_miss_latency::total 4885126000 # number of ReadExReq MSHR miss cycles 270system.l2c.demand_mshr_miss_latency::cpu0.inst 519097000 # number of demand (read+write) MSHR miss cycles 271system.l2c.demand_mshr_miss_latency::cpu0.data 15489964000 # number of demand (read+write) MSHR miss cycles 272system.l2c.demand_mshr_miss_latency::cpu1.inst 22042500 # number of demand (read+write) MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu1.data 275360500 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::total 16306464000 # number of demand (read+write) MSHR miss cycles 275system.l2c.overall_mshr_miss_latency::cpu0.inst 519097000 # number of overall MSHR miss cycles 276system.l2c.overall_mshr_miss_latency::cpu0.data 15489964000 # number of overall MSHR miss cycles 277system.l2c.overall_mshr_miss_latency::cpu1.inst 22042500 # number of overall MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu1.data 275360500 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::total 16306464000 # number of overall MSHR miss cycles 280system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370272000 # number of ReadReq MSHR uncacheable cycles 281system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18137500 # number of ReadReq MSHR uncacheable cycles 282system.l2c.ReadReq_mshr_uncacheable_latency::total 1388409500 # number of ReadReq MSHR uncacheable cycles 283system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2141921500 # number of WriteReq MSHR uncacheable cycles 284system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673752500 # number of WriteReq MSHR uncacheable cycles 285system.l2c.WriteReq_mshr_uncacheable_latency::total 2815674000 # number of WriteReq MSHR uncacheable cycles 286system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3512193500 # 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number of overall MSHR miss cycles 437system.l2c.overall_mshr_miss_latency::total 13109358346 # number of overall MSHR miss cycles 438system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370389500 # number of ReadReq MSHR uncacheable cycles 439system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18130000 # number of ReadReq MSHR uncacheable cycles 440system.l2c.ReadReq_mshr_uncacheable_latency::total 1388519500 # number of ReadReq MSHR uncacheable cycles 441system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2151186500 # number of WriteReq MSHR uncacheable cycles 442system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 682990000 # number of WriteReq MSHR uncacheable cycles 443system.l2c.WriteReq_mshr_uncacheable_latency::total 2834176500 # number of WriteReq MSHR uncacheable cycles 444system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3521576000 # number of overall MSHR uncacheable cycles 445system.l2c.overall_mshr_uncacheable_latency::cpu1.data 701120000 # number of overall MSHR uncacheable cycles 446system.l2c.overall_mshr_uncacheable_latency::total 4222696000 # number of overall MSHR uncacheable cycles 447system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for ReadReq accesses 448system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.292123 # mshr miss rate for ReadReq accesses 449system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for ReadReq accesses 450system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002171 # mshr miss rate for ReadReq accesses 451system.l2c.ReadReq_mshr_miss_rate::total 0.138548 # mshr miss rate for ReadReq accesses 452system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944003 # mshr miss rate for UpgradeReq accesses 453system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.761163 # mshr miss rate for UpgradeReq accesses 454system.l2c.UpgradeReq_mshr_miss_rate::total 0.865325 # mshr miss rate for UpgradeReq accesses 455system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.963077 # mshr miss rate for SCUpgradeReq accesses 456system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976166 # mshr miss rate for SCUpgradeReq accesses 457system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969588 # mshr miss rate for SCUpgradeReq accesses 458system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.482473 # mshr miss rate for ReadExReq accesses 459system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119476 # mshr miss rate for ReadExReq accesses 460system.l2c.ReadExReq_mshr_miss_rate::total 0.414056 # mshr miss rate for ReadExReq accesses 461system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for demand accesses 463system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for demand accesses 464system.l2c.demand_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for demand accesses 465system.l2c.demand_mshr_miss_rate::total 0.173060 # mshr miss rate for demand accesses 466system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018811 # mshr miss rate for overall accesses 467system.l2c.overall_mshr_miss_rate::cpu0.data 0.331096 # mshr miss rate for overall accesses 468system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001826 # mshr miss rate for overall accesses 469system.l2c.overall_mshr_miss_rate::cpu1.data 0.040677 # mshr miss rate for overall accesses 470system.l2c.overall_mshr_miss_rate::total 0.173060 # mshr miss rate for overall accesses 471system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average ReadReq mshr miss latency 472system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 29361.065158 # average ReadReq mshr miss latency 473system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average ReadReq mshr miss latency 474system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48825.809717 # average ReadReq mshr miss latency 475system.l2c.ReadReq_avg_mshr_miss_latency::total 30003.861239 # average ReadReq mshr miss latency 476system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10052.565554 # average UpgradeReq mshr miss latency 477system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10007.915883 # average UpgradeReq mshr miss latency 478system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.665270 # average UpgradeReq mshr miss latency 479system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10016.957401 # average SCUpgradeReq mshr miss latency 480system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency 481system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10008.965976 # average SCUpgradeReq mshr miss latency 482system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36385.548336 # average ReadExReq mshr miss latency 483system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51698.021075 # average ReadExReq mshr miss latency 484system.l2c.ReadExReq_avg_mshr_miss_latency::total 37218.321604 # average ReadExReq mshr miss latency 485system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency 486system.l2c.demand_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency 487system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency 488system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency 489system.l2c.demand_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency 490system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42535.926582 # average overall mshr miss latency 491system.l2c.overall_avg_mshr_miss_latency::cpu0.data 31456.860953 # average overall mshr miss latency 492system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43256.514143 # average overall mshr miss latency 493system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51595.055007 # average overall mshr miss latency 494system.l2c.overall_avg_mshr_miss_latency::total 32166.099899 # average overall mshr miss latency |
| 337system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 338system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 339system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 340system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 341system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 342system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 343system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 344system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 345system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 346system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 347system.iocache.replacements 41696 # number of replacements | 495system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 496system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 497system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 498system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 499system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 500system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 501system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 502system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 503system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 504system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 505system.iocache.replacements 41696 # number of replacements |
| 348system.iocache.tagsinuse 0.569930 # Cycle average of tags in use | 506system.iocache.tagsinuse 0.562945 # Cycle average of tags in use |
| 349system.iocache.total_refs 0 # Total number of references to valid blocks. 350system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. 351system.iocache.avg_refs 0 # Average number of references to valid blocks. | 507system.iocache.total_refs 0 # Total number of references to valid blocks. 508system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. 509system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 352system.iocache.warmup_cycle 1749614950000 # Cycle when the warmup percentage was hit. 353system.iocache.occ_blocks::tsunami.ide 0.569930 # Average occupied blocks per requestor 354system.iocache.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy 355system.iocache.occ_percent::total 0.035621 # Average percentage of cache occupancy | 510system.iocache.warmup_cycle 1745713328000 # Cycle when the warmup percentage was hit. 511system.iocache.occ_blocks::tsunami.ide 0.562945 # Average occupied blocks per requestor 512system.iocache.occ_percent::tsunami.ide 0.035184 # Average percentage of cache occupancy 513system.iocache.occ_percent::total 0.035184 # Average percentage of cache occupancy |
| 356system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 357system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 358system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 359system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 360system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 361system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 362system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 363system.iocache.overall_misses::total 41728 # number of overall misses | 514system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 515system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 516system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 517system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 518system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 519system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 520system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 521system.iocache.overall_misses::total 41728 # number of overall misses |
| 364system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles 365system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles 366system.iocache.WriteReq_miss_latency::tsunami.ide 11453563806 # number of WriteReq miss cycles 367system.iocache.WriteReq_miss_latency::total 11453563806 # number of WriteReq miss cycles 368system.iocache.demand_miss_latency::tsunami.ide 11474577804 # number of demand (read+write) miss cycles 369system.iocache.demand_miss_latency::total 11474577804 # number of demand (read+write) miss cycles 370system.iocache.overall_miss_latency::tsunami.ide 11474577804 # number of overall miss cycles 371system.iocache.overall_miss_latency::total 11474577804 # number of overall miss cycles | 522system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles 523system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles 524system.iocache.WriteReq_miss_latency::tsunami.ide 9455401806 # number of WriteReq miss cycles 525system.iocache.WriteReq_miss_latency::total 9455401806 # number of WriteReq miss cycles 526system.iocache.demand_miss_latency::tsunami.ide 9476670804 # number of demand (read+write) miss cycles 527system.iocache.demand_miss_latency::total 9476670804 # number of demand (read+write) miss cycles 528system.iocache.overall_miss_latency::tsunami.ide 9476670804 # number of overall miss cycles 529system.iocache.overall_miss_latency::total 9476670804 # number of overall miss cycles |
| 372system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 373system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 374system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 375system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 376system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 377system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 378system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 379system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 380system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 381system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 382system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 383system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 384system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 385system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 386system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 387system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 530system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 531system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 532system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 533system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 534system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 535system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 536system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 537system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses 538system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 539system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 540system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 541system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 542system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 543system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 544system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 545system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 388system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency 389system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency 390system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275644.103918 # average WriteReq miss latency 391system.iocache.WriteReq_avg_miss_latency::total 275644.103918 # average WriteReq miss latency 392system.iocache.demand_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency 393system.iocache.demand_avg_miss_latency::total 274985.089245 # average overall miss latency 394system.iocache.overall_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency 395system.iocache.overall_avg_miss_latency::total 274985.089245 # average overall miss latency 396system.iocache.blocked_cycles::no_mshrs 199825 # number of cycles access was blocked | 546system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency 547system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency 548system.iocache.WriteReq_avg_miss_latency::tsunami.ide 227555.877118 # average WriteReq miss latency 549system.iocache.WriteReq_avg_miss_latency::total 227555.877118 # average WriteReq miss latency 550system.iocache.demand_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency 551system.iocache.demand_avg_miss_latency::total 227105.799559 # average overall miss latency 552system.iocache.overall_avg_miss_latency::tsunami.ide 227105.799559 # average overall miss latency 553system.iocache.overall_avg_miss_latency::total 227105.799559 # average overall miss latency 554system.iocache.blocked_cycles::no_mshrs 186741 # number of cycles access was blocked |
| 397system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 555system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 398system.iocache.blocked::no_mshrs 24712 # number of cycles access was blocked | 556system.iocache.blocked::no_mshrs 23044 # number of cycles access was blocked |
| 399system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 557system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 400system.iocache.avg_blocked_cycles::no_mshrs 8.086152 # average number of cycles each access was blocked | 558system.iocache.avg_blocked_cycles::no_mshrs 8.103671 # average number of cycles each access was blocked |
| 401system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.iocache.fast_writes 0 # number of fast writes performed 403system.iocache.cache_copies 0 # number of cache copies performed 404system.iocache.writebacks::writebacks 41520 # number of writebacks 405system.iocache.writebacks::total 41520 # number of writebacks 406system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 407system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 408system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 409system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 410system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 411system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 412system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 413system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses | 559system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 560system.iocache.fast_writes 0 # number of fast writes performed 561system.iocache.cache_copies 0 # number of cache copies performed 562system.iocache.writebacks::writebacks 41520 # number of writebacks 563system.iocache.writebacks::total 41520 # number of writebacks 564system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 565system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 566system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 567system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 568system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 569system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 570system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 571system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses |
| 414system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861998 # number of ReadReq MSHR miss cycles 415system.iocache.ReadReq_mshr_miss_latency::total 11861998 # number of ReadReq MSHR miss cycles 416system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9292859806 # number of WriteReq MSHR miss cycles 417system.iocache.WriteReq_mshr_miss_latency::total 9292859806 # number of WriteReq MSHR miss cycles 418system.iocache.demand_mshr_miss_latency::tsunami.ide 9304721804 # number of demand (read+write) MSHR miss cycles 419system.iocache.demand_mshr_miss_latency::total 9304721804 # number of demand (read+write) MSHR miss cycles 420system.iocache.overall_mshr_miss_latency::tsunami.ide 9304721804 # number of overall MSHR miss cycles 421system.iocache.overall_mshr_miss_latency::total 9304721804 # number of overall MSHR miss cycles | 572system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116000 # number of ReadReq MSHR miss cycles 573system.iocache.ReadReq_mshr_miss_latency::total 12116000 # number of ReadReq MSHR miss cycles 574system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 7292629022 # number of WriteReq MSHR miss cycles 575system.iocache.WriteReq_mshr_miss_latency::total 7292629022 # number of WriteReq MSHR miss cycles 576system.iocache.demand_mshr_miss_latency::tsunami.ide 7304745022 # number of demand (read+write) MSHR miss cycles 577system.iocache.demand_mshr_miss_latency::total 7304745022 # number of demand (read+write) MSHR miss cycles 578system.iocache.overall_mshr_miss_latency::tsunami.ide 7304745022 # number of overall MSHR miss cycles 579system.iocache.overall_mshr_miss_latency::total 7304745022 # number of overall MSHR miss cycles |
| 422system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 424system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 425system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 580system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 581system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 582system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 583system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 584system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 585system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 586system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 587system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67397.715909 # average ReadReq mshr miss latency 431system.iocache.ReadReq_avg_mshr_miss_latency::total 67397.715909 # average ReadReq mshr miss latency 432system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223644.103918 # average WriteReq mshr miss latency 433system.iocache.WriteReq_avg_mshr_miss_latency::total 223644.103918 # average WriteReq mshr miss latency 434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency 435system.iocache.demand_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency 436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency 437system.iocache.overall_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency | 588system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68840.909091 # average ReadReq mshr miss latency 589system.iocache.ReadReq_avg_mshr_miss_latency::total 68840.909091 # average ReadReq mshr miss latency 590system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 175506.089286 # average WriteReq mshr miss latency 591system.iocache.WriteReq_avg_mshr_miss_latency::total 175506.089286 # average WriteReq mshr miss latency 592system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency 593system.iocache.demand_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency 594system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 175056.197805 # average overall mshr miss latency 595system.iocache.overall_avg_mshr_miss_latency::total 175056.197805 # average overall mshr miss latency |
| 438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 442system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 443system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 444system.disk0.dma_write_txs 395 # Number of DMA write transactions. 445system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 446system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 447system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 448system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 449system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 450system.disk2.dma_write_txs 1 # Number of DMA write transactions. 451system.cpu0.dtb.fetch_hits 0 # ITB hits 452system.cpu0.dtb.fetch_misses 0 # ITB misses 453system.cpu0.dtb.fetch_acv 0 # ITB acv 454system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 596system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 597system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 598system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 599system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 600system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 601system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 602system.disk0.dma_write_txs 395 # Number of DMA write transactions. 603system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 604system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 605system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 606system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 607system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 608system.disk2.dma_write_txs 1 # Number of DMA write transactions. 609system.cpu0.dtb.fetch_hits 0 # ITB hits 610system.cpu0.dtb.fetch_misses 0 # ITB misses 611system.cpu0.dtb.fetch_acv 0 # ITB acv 612system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 455system.cpu0.dtb.read_hits 7486542 # DTB read hits | 613system.cpu0.dtb.read_hits 7424678 # DTB read hits |
| 456system.cpu0.dtb.read_misses 7443 # DTB read misses 457system.cpu0.dtb.read_acv 210 # DTB read access violations 458system.cpu0.dtb.read_accesses 490673 # DTB read accesses | 614system.cpu0.dtb.read_misses 7443 # DTB read misses 615system.cpu0.dtb.read_acv 210 # DTB read access violations 616system.cpu0.dtb.read_accesses 490673 # DTB read accesses |
| 459system.cpu0.dtb.write_hits 5063820 # DTB write hits | 617system.cpu0.dtb.write_hits 5011102 # DTB write hits |
| 460system.cpu0.dtb.write_misses 813 # DTB write misses 461system.cpu0.dtb.write_acv 134 # DTB write access violations 462system.cpu0.dtb.write_accesses 187452 # DTB write accesses | 618system.cpu0.dtb.write_misses 813 # DTB write misses 619system.cpu0.dtb.write_acv 134 # DTB write access violations 620system.cpu0.dtb.write_accesses 187452 # DTB write accesses |
| 463system.cpu0.dtb.data_hits 12550362 # DTB hits | 621system.cpu0.dtb.data_hits 12435780 # DTB hits |
| 464system.cpu0.dtb.data_misses 8256 # DTB misses 465system.cpu0.dtb.data_acv 344 # DTB access violations 466system.cpu0.dtb.data_accesses 678125 # DTB accesses | 622system.cpu0.dtb.data_misses 8256 # DTB misses 623system.cpu0.dtb.data_acv 344 # DTB access violations 624system.cpu0.dtb.data_accesses 678125 # DTB accesses |
| 467system.cpu0.itb.fetch_hits 3500956 # ITB hits | 625system.cpu0.itb.fetch_hits 3481701 # ITB hits |
| 468system.cpu0.itb.fetch_misses 3871 # ITB misses 469system.cpu0.itb.fetch_acv 184 # ITB acv | 626system.cpu0.itb.fetch_misses 3871 # ITB misses 627system.cpu0.itb.fetch_acv 184 # ITB acv |
| 470system.cpu0.itb.fetch_accesses 3504827 # ITB accesses | 628system.cpu0.itb.fetch_accesses 3485572 # ITB accesses |
| 471system.cpu0.itb.read_hits 0 # DTB read hits 472system.cpu0.itb.read_misses 0 # DTB read misses 473system.cpu0.itb.read_acv 0 # DTB read access violations 474system.cpu0.itb.read_accesses 0 # DTB read accesses 475system.cpu0.itb.write_hits 0 # DTB write hits 476system.cpu0.itb.write_misses 0 # DTB write misses 477system.cpu0.itb.write_acv 0 # DTB write access violations 478system.cpu0.itb.write_accesses 0 # DTB write accesses 479system.cpu0.itb.data_hits 0 # DTB hits 480system.cpu0.itb.data_misses 0 # DTB misses 481system.cpu0.itb.data_acv 0 # DTB access violations 482system.cpu0.itb.data_accesses 0 # DTB accesses | 629system.cpu0.itb.read_hits 0 # DTB read hits 630system.cpu0.itb.read_misses 0 # DTB read misses 631system.cpu0.itb.read_acv 0 # DTB read access violations 632system.cpu0.itb.read_accesses 0 # DTB read accesses 633system.cpu0.itb.write_hits 0 # DTB write hits 634system.cpu0.itb.write_misses 0 # DTB write misses 635system.cpu0.itb.write_acv 0 # DTB write access violations 636system.cpu0.itb.write_accesses 0 # DTB write accesses 637system.cpu0.itb.data_hits 0 # DTB hits 638system.cpu0.itb.data_misses 0 # DTB misses 639system.cpu0.itb.data_acv 0 # DTB access violations 640system.cpu0.itb.data_accesses 0 # DTB accesses |
| 483system.cpu0.numCycles 3910167080 # number of cpu cycles simulated | 641system.cpu0.numCycles 3900399022 # number of cpu cycles simulated |
| 484system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 485system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 642system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 643system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 486system.cpu0.committedInsts 47719039 # Number of instructions committed 487system.cpu0.committedOps 47719039 # Number of ops (including micro ops) committed 488system.cpu0.num_int_alu_accesses 44257119 # Number of integer alu accesses 489system.cpu0.num_fp_alu_accesses 210954 # Number of float alu accesses 490system.cpu0.num_func_calls 1200899 # number of times a function call or return occured 491system.cpu0.num_conditional_control_insts 5607083 # number of instructions that are conditional controls 492system.cpu0.num_int_insts 44257119 # number of integer instructions 493system.cpu0.num_fp_insts 210954 # number of float instructions 494system.cpu0.num_int_register_reads 60839484 # number of times the integer registers were read 495system.cpu0.num_int_register_writes 32982631 # number of times the integer registers were written 496system.cpu0.num_fp_register_reads 102466 # number of times the floating registers were read 497system.cpu0.num_fp_register_writes 104326 # number of times the floating registers were written 498system.cpu0.num_mem_refs 12590587 # number of memory refs 499system.cpu0.num_load_insts 7513713 # Number of load instructions 500system.cpu0.num_store_insts 5076874 # Number of store instructions 501system.cpu0.num_idle_cycles 3701181001.496715 # Number of idle cycles 502system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles 503system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles 504system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles | 644system.cpu0.committedInsts 47350752 # Number of instructions committed 645system.cpu0.committedOps 47350752 # Number of ops (including micro ops) committed 646system.cpu0.num_int_alu_accesses 43919757 # Number of integer alu accesses 647system.cpu0.num_fp_alu_accesses 206365 # Number of float alu accesses 648system.cpu0.num_func_calls 1188579 # number of times a function call or return occured 649system.cpu0.num_conditional_control_insts 5567605 # number of instructions that are conditional controls 650system.cpu0.num_int_insts 43919757 # number of integer instructions 651system.cpu0.num_fp_insts 206365 # number of float instructions 652system.cpu0.num_int_register_reads 60378447 # number of times the integer registers were read 653system.cpu0.num_int_register_writes 32741783 # number of times the integer registers were written 654system.cpu0.num_fp_register_reads 100221 # number of times the floating registers were read 655system.cpu0.num_fp_register_writes 101982 # number of times the floating registers were written 656system.cpu0.num_mem_refs 12475681 # number of memory refs 657system.cpu0.num_load_insts 7451619 # Number of load instructions 658system.cpu0.num_store_insts 5024062 # Number of store instructions 659system.cpu0.num_idle_cycles 3698907701.219057 # Number of idle cycles 660system.cpu0.num_busy_cycles 201491320.780943 # Number of busy cycles 661system.cpu0.not_idle_fraction 0.051659 # Percentage of non-idle cycles 662system.cpu0.idle_fraction 0.948341 # Percentage of idle cycles |
| 505system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 663system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 506system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed 507system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed 508system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl 509system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl 510system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl 511system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl 512system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl 513system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl 514system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl 515system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl 516system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl 517system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl 518system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl 519system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl 520system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl 521system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl 522system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl 523system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl 524system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl 525system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl 526system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl | 664system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed 665system.cpu0.kern.inst.hwrei 162790 # number of hwrei instructions executed 666system.cpu0.kern.ipl_count::0 55943 40.16% 40.16% # number of times we switched to this ipl 667system.cpu0.kern.ipl_count::21 131 0.09% 40.25% # number of times we switched to this ipl 668system.cpu0.kern.ipl_count::22 1971 1.41% 41.66% # number of times we switched to this ipl 669system.cpu0.kern.ipl_count::30 443 0.32% 41.98% # number of times we switched to this ipl 670system.cpu0.kern.ipl_count::31 80829 58.02% 100.00% # number of times we switched to this ipl 671system.cpu0.kern.ipl_count::total 139317 # number of times we switched to this ipl 672system.cpu0.kern.ipl_good::0 55450 49.07% 49.07% # number of times we switched to this ipl from a different ipl 673system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl 674system.cpu0.kern.ipl_good::22 1971 1.74% 50.93% # number of times we switched to this ipl from a different ipl 675system.cpu0.kern.ipl_good::30 443 0.39% 51.32% # number of times we switched to this ipl from a different ipl 676system.cpu0.kern.ipl_good::31 55007 48.68% 100.00% # number of times we switched to this ipl from a different ipl 677system.cpu0.kern.ipl_good::total 113002 # number of times we switched to this ipl from a different ipl 678system.cpu0.kern.ipl_ticks::0 1898626830000 97.36% 97.36% # number of cycles we spent at this ipl 679system.cpu0.kern.ipl_ticks::21 93050500 0.00% 97.36% # number of cycles we spent at this ipl 680system.cpu0.kern.ipl_ticks::22 759970000 0.04% 97.40% # number of cycles we spent at this ipl 681system.cpu0.kern.ipl_ticks::30 326793000 0.02% 97.42% # number of cycles we spent at this ipl 682system.cpu0.kern.ipl_ticks::31 50392837500 2.58% 100.00% # number of cycles we spent at this ipl 683system.cpu0.kern.ipl_ticks::total 1950199481000 # number of cycles we spent at this ipl 684system.cpu0.kern.ipl_used::0 0.991187 # fraction of swpipl calls that actually changed the ipl |
| 527system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 528system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 529system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 685system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 686system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 687system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 530system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl 531system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl | 688system.cpu0.kern.ipl_used::31 0.680535 # fraction of swpipl calls that actually changed the ipl 689system.cpu0.kern.ipl_used::total 0.811114 # fraction of swpipl calls that actually changed the ipl |
| 532system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 533system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 534system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 535system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 536system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 537system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 538system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 539system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 555system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 556system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 557system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 558system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 559system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 560system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 561system.cpu0.kern.syscall::total 222 # number of syscalls executed 562system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 690system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 691system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 692system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 693system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 694system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 695system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 696system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 697system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 713system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 714system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 715system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 716system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 717system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 718system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 719system.cpu0.kern.syscall::total 222 # number of syscalls executed 720system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 563system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed 564system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 565system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 566system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed 567system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed 568system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed 569system.cpu0.kern.callpal::wrent 7 0.00% 2.43% # number of callpals executed 570system.cpu0.kern.callpal::swpipl 134512 89.86% 92.29% # number of callpals executed 571system.cpu0.kern.callpal::rdps 6676 4.46% 96.75% # number of callpals executed 572system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed 573system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed 574system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed 575system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed 576system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed 577system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed | 721system.cpu0.kern.callpal::wripir 525 0.36% 0.36% # number of callpals executed 722system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 723system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 724system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 725system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed 726system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 727system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 728system.cpu0.kern.callpal::swpipl 132461 89.75% 92.20% # number of callpals executed 729system.cpu0.kern.callpal::rdps 6674 4.52% 96.72% # number of callpals executed 730system.cpu0.kern.callpal::wrkgp 1 0.00% 96.72% # number of callpals executed 731system.cpu0.kern.callpal::wrusp 3 0.00% 96.72% # number of callpals executed 732system.cpu0.kern.callpal::rdusp 9 0.01% 96.73% # number of callpals executed 733system.cpu0.kern.callpal::whami 2 0.00% 96.73% # number of callpals executed 734system.cpu0.kern.callpal::rti 4310 2.92% 99.65% # number of callpals executed 735system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed |
| 578system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed | 736system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed |
| 579system.cpu0.kern.callpal::total 149688 # number of callpals executed 580system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches 581system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches | 737system.cpu0.kern.callpal::total 147588 # number of callpals executed 738system.cpu0.kern.mode_switch::kernel 6865 # number of protection mode switches 739system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches |
| 582system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 740system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 583system.cpu0.kern.mode_good::kernel 1285 584system.cpu0.kern.mode_good::user 1285 | 741system.cpu0.kern.mode_good::kernel 1283 742system.cpu0.kern.mode_good::user 1283 |
| 585system.cpu0.kern.mode_good::idle 0 | 743system.cpu0.kern.mode_good::idle 0 |
| 586system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches | 744system.cpu0.kern.mode_switch_good::kernel 0.186890 # fraction of useful protection mode switches |
| 587system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 588system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 745system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 746system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 589system.cpu0.kern.mode_switch_good::total 0.314412 # fraction of useful protection mode switches 590system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode 591system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode | 747system.cpu0.kern.mode_switch_good::total 0.314924 # fraction of useful protection mode switches 748system.cpu0.kern.mode_ticks::kernel 1946498286500 99.83% 99.83% # number of ticks spent at the given mode 749system.cpu0.kern.mode_ticks::user 3408187000 0.17% 100.00% # number of ticks spent at the given mode |
| 592system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 750system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 593system.cpu0.kern.swap_context 3071 # number of times the context was actually changed | 751system.cpu0.kern.swap_context 3025 # number of times the context was actually changed |
| 594system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 595system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 596system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 597system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 598system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 599system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 600system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 601system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 617system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 618system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 619system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 620system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 621system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 622system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 623system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 624system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 752system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 753system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 754system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 755system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 756system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 757system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 758system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 759system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 775system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 776system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 777system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 778system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 779system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 780system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 781system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 782system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 625system.cpu0.icache.replacements 698187 # number of replacements 626system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use 627system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks. 628system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks. 629system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks. 630system.cpu0.icache.warmup_cycle 35739052000 # Cycle when the warmup percentage was hit. 631system.cpu0.icache.occ_blocks::cpu0.inst 508.830635 # Average occupied blocks per requestor 632system.cpu0.icache.occ_percent::cpu0.inst 0.993810 # Average percentage of cache occupancy 633system.cpu0.icache.occ_percent::total 0.993810 # Average percentage of cache occupancy 634system.cpu0.icache.ReadReq_hits::cpu0.inst 47028847 # number of ReadReq hits 635system.cpu0.icache.ReadReq_hits::total 47028847 # number of ReadReq hits 636system.cpu0.icache.demand_hits::cpu0.inst 47028847 # number of demand (read+write) hits 637system.cpu0.icache.demand_hits::total 47028847 # number of demand (read+write) hits 638system.cpu0.icache.overall_hits::cpu0.inst 47028847 # number of overall hits 639system.cpu0.icache.overall_hits::total 47028847 # number of overall hits 640system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses 641system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses 642system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses 643system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses 644system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses 645system.cpu0.icache.overall_misses::total 698792 # number of overall misses 646system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9694162500 # number of ReadReq miss cycles 647system.cpu0.icache.ReadReq_miss_latency::total 9694162500 # number of ReadReq miss cycles 648system.cpu0.icache.demand_miss_latency::cpu0.inst 9694162500 # number of demand (read+write) miss cycles 649system.cpu0.icache.demand_miss_latency::total 9694162500 # number of demand (read+write) miss cycles 650system.cpu0.icache.overall_miss_latency::cpu0.inst 9694162500 # number of overall miss cycles 651system.cpu0.icache.overall_miss_latency::total 9694162500 # number of overall miss cycles 652system.cpu0.icache.ReadReq_accesses::cpu0.inst 47727639 # number of ReadReq accesses(hits+misses) 653system.cpu0.icache.ReadReq_accesses::total 47727639 # number of ReadReq accesses(hits+misses) 654system.cpu0.icache.demand_accesses::cpu0.inst 47727639 # number of demand (read+write) accesses 655system.cpu0.icache.demand_accesses::total 47727639 # number of demand (read+write) accesses 656system.cpu0.icache.overall_accesses::cpu0.inst 47727639 # number of overall (read+write) accesses 657system.cpu0.icache.overall_accesses::total 47727639 # number of overall (read+write) accesses 658system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014641 # miss rate for ReadReq accesses 659system.cpu0.icache.ReadReq_miss_rate::total 0.014641 # miss rate for ReadReq accesses 660system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014641 # miss rate for demand accesses 661system.cpu0.icache.demand_miss_rate::total 0.014641 # miss rate for demand accesses 662system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014641 # miss rate for overall accesses 663system.cpu0.icache.overall_miss_rate::total 0.014641 # miss rate for overall accesses 664system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13872.743964 # average ReadReq miss latency 665system.cpu0.icache.ReadReq_avg_miss_latency::total 13872.743964 # average ReadReq miss latency 666system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency 667system.cpu0.icache.demand_avg_miss_latency::total 13872.743964 # average overall miss latency 668system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency 669system.cpu0.icache.overall_avg_miss_latency::total 13872.743964 # average overall miss latency | 783system.cpu0.icache.replacements 686559 # number of replacements 784system.cpu0.icache.tagsinuse 509.179293 # Cycle average of tags in use 785system.cpu0.icache.total_refs 46672188 # Total number of references to valid blocks. 786system.cpu0.icache.sampled_refs 687071 # Sample count of references to valid blocks. 787system.cpu0.icache.avg_refs 67.929207 # Average number of references to valid blocks. 788system.cpu0.icache.warmup_cycle 32409447000 # Cycle when the warmup percentage was hit. 789system.cpu0.icache.occ_blocks::cpu0.inst 509.179293 # Average occupied blocks per requestor 790system.cpu0.icache.occ_percent::cpu0.inst 0.994491 # Average percentage of cache occupancy 791system.cpu0.icache.occ_percent::total 0.994491 # Average percentage of cache occupancy 792system.cpu0.icache.ReadReq_hits::cpu0.inst 46672188 # number of ReadReq hits 793system.cpu0.icache.ReadReq_hits::total 46672188 # number of ReadReq hits 794system.cpu0.icache.demand_hits::cpu0.inst 46672188 # number of demand (read+write) hits 795system.cpu0.icache.demand_hits::total 46672188 # number of demand (read+write) hits 796system.cpu0.icache.overall_hits::cpu0.inst 46672188 # number of overall hits 797system.cpu0.icache.overall_hits::total 46672188 # number of overall hits 798system.cpu0.icache.ReadReq_misses::cpu0.inst 687164 # number of ReadReq misses 799system.cpu0.icache.ReadReq_misses::total 687164 # number of ReadReq misses 800system.cpu0.icache.demand_misses::cpu0.inst 687164 # number of demand (read+write) misses 801system.cpu0.icache.demand_misses::total 687164 # number of demand (read+write) misses 802system.cpu0.icache.overall_misses::cpu0.inst 687164 # number of overall misses 803system.cpu0.icache.overall_misses::total 687164 # number of overall misses 804system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9577778500 # number of ReadReq miss cycles 805system.cpu0.icache.ReadReq_miss_latency::total 9577778500 # number of ReadReq miss cycles 806system.cpu0.icache.demand_miss_latency::cpu0.inst 9577778500 # number of demand (read+write) miss cycles 807system.cpu0.icache.demand_miss_latency::total 9577778500 # number of demand (read+write) miss cycles 808system.cpu0.icache.overall_miss_latency::cpu0.inst 9577778500 # number of overall miss cycles 809system.cpu0.icache.overall_miss_latency::total 9577778500 # number of overall miss cycles 810system.cpu0.icache.ReadReq_accesses::cpu0.inst 47359352 # number of ReadReq accesses(hits+misses) 811system.cpu0.icache.ReadReq_accesses::total 47359352 # number of ReadReq accesses(hits+misses) 812system.cpu0.icache.demand_accesses::cpu0.inst 47359352 # number of demand (read+write) accesses 813system.cpu0.icache.demand_accesses::total 47359352 # number of demand (read+write) accesses 814system.cpu0.icache.overall_accesses::cpu0.inst 47359352 # number of overall (read+write) accesses 815system.cpu0.icache.overall_accesses::total 47359352 # number of overall (read+write) accesses 816system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014510 # miss rate for ReadReq accesses 817system.cpu0.icache.ReadReq_miss_rate::total 0.014510 # miss rate for ReadReq accesses 818system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014510 # miss rate for demand accesses 819system.cpu0.icache.demand_miss_rate::total 0.014510 # miss rate for demand accesses 820system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014510 # miss rate for overall accesses 821system.cpu0.icache.overall_miss_rate::total 0.014510 # miss rate for overall accesses 822system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13938.126124 # average ReadReq miss latency 823system.cpu0.icache.ReadReq_avg_miss_latency::total 13938.126124 # average ReadReq miss latency 824system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency 825system.cpu0.icache.demand_avg_miss_latency::total 13938.126124 # average overall miss latency 826system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13938.126124 # average overall miss latency 827system.cpu0.icache.overall_avg_miss_latency::total 13938.126124 # average overall miss latency |
| 670system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 671system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 672system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 673system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 674system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 675system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 676system.cpu0.icache.fast_writes 0 # number of fast writes performed 677system.cpu0.icache.cache_copies 0 # number of cache copies performed | 828system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 829system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 830system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 831system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 832system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 833system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 834system.cpu0.icache.fast_writes 0 # number of fast writes performed 835system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 678system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses 679system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses 680system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses 681system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses 682system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses 683system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses 684system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8296578500 # number of ReadReq MSHR miss cycles 685system.cpu0.icache.ReadReq_mshr_miss_latency::total 8296578500 # number of ReadReq MSHR miss cycles 686system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8296578500 # number of demand (read+write) MSHR miss cycles 687system.cpu0.icache.demand_mshr_miss_latency::total 8296578500 # number of demand (read+write) MSHR miss cycles 688system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8296578500 # number of overall MSHR miss cycles 689system.cpu0.icache.overall_mshr_miss_latency::total 8296578500 # number of overall MSHR miss cycles 690system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for ReadReq accesses 691system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014641 # mshr miss rate for ReadReq accesses 692system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for demand accesses 693system.cpu0.icache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses 694system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for overall accesses 695system.cpu0.icache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses 696system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average ReadReq mshr miss latency 697system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11872.743964 # average ReadReq mshr miss latency 698system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency 699system.cpu0.icache.demand_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency 700system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency 701system.cpu0.icache.overall_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency | 836system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687164 # number of ReadReq MSHR misses 837system.cpu0.icache.ReadReq_mshr_misses::total 687164 # number of ReadReq MSHR misses 838system.cpu0.icache.demand_mshr_misses::cpu0.inst 687164 # number of demand (read+write) MSHR misses 839system.cpu0.icache.demand_mshr_misses::total 687164 # number of demand (read+write) MSHR misses 840system.cpu0.icache.overall_mshr_misses::cpu0.inst 687164 # number of overall MSHR misses 841system.cpu0.icache.overall_mshr_misses::total 687164 # number of overall MSHR misses 842system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8203450500 # number of ReadReq MSHR miss cycles 843system.cpu0.icache.ReadReq_mshr_miss_latency::total 8203450500 # number of ReadReq MSHR miss cycles 844system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8203450500 # number of demand (read+write) MSHR miss cycles 845system.cpu0.icache.demand_mshr_miss_latency::total 8203450500 # number of demand (read+write) MSHR miss cycles 846system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8203450500 # number of overall MSHR miss cycles 847system.cpu0.icache.overall_mshr_miss_latency::total 8203450500 # number of overall MSHR miss cycles 848system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for ReadReq accesses 849system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014510 # mshr miss rate for ReadReq accesses 850system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for demand accesses 851system.cpu0.icache.demand_mshr_miss_rate::total 0.014510 # mshr miss rate for demand accesses 852system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014510 # mshr miss rate for overall accesses 853system.cpu0.icache.overall_mshr_miss_rate::total 0.014510 # mshr miss rate for overall accesses 854system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average ReadReq mshr miss latency 855system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11938.126124 # average ReadReq mshr miss latency 856system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency 857system.cpu0.icache.demand_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency 858system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11938.126124 # average overall mshr miss latency 859system.cpu0.icache.overall_avg_mshr_miss_latency::total 11938.126124 # average overall mshr miss latency |
| 702system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 860system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 703system.cpu0.dcache.replacements 1180402 # number of replacements 704system.cpu0.dcache.tagsinuse 505.183019 # Cycle average of tags in use 705system.cpu0.dcache.total_refs 11360683 # Total number of references to valid blocks. 706system.cpu0.dcache.sampled_refs 1180820 # Sample count of references to valid blocks. 707system.cpu0.dcache.avg_refs 9.621012 # Average number of references to valid blocks. 708system.cpu0.dcache.warmup_cycle 99461000 # Cycle when the warmup percentage was hit. 709system.cpu0.dcache.occ_blocks::cpu0.data 505.183019 # Average occupied blocks per requestor 710system.cpu0.dcache.occ_percent::cpu0.data 0.986686 # Average percentage of cache occupancy 711system.cpu0.dcache.occ_percent::total 0.986686 # Average percentage of cache occupancy 712system.cpu0.dcache.ReadReq_hits::cpu0.data 6406782 # number of ReadReq hits 713system.cpu0.dcache.ReadReq_hits::total 6406782 # number of ReadReq hits 714system.cpu0.dcache.WriteReq_hits::cpu0.data 4655760 # number of WriteReq hits 715system.cpu0.dcache.WriteReq_hits::total 4655760 # number of WriteReq hits 716system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140286 # number of LoadLockedReq hits 717system.cpu0.dcache.LoadLockedReq_hits::total 140286 # number of LoadLockedReq hits 718system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147915 # number of StoreCondReq hits 719system.cpu0.dcache.StoreCondReq_hits::total 147915 # number of StoreCondReq hits 720system.cpu0.dcache.demand_hits::cpu0.data 11062542 # number of demand (read+write) hits 721system.cpu0.dcache.demand_hits::total 11062542 # number of demand (read+write) hits 722system.cpu0.dcache.overall_hits::cpu0.data 11062542 # number of overall hits 723system.cpu0.dcache.overall_hits::total 11062542 # number of overall hits 724system.cpu0.dcache.ReadReq_misses::cpu0.data 938249 # number of ReadReq misses 725system.cpu0.dcache.ReadReq_misses::total 938249 # number of ReadReq misses 726system.cpu0.dcache.WriteReq_misses::cpu0.data 251643 # number of WriteReq misses 727system.cpu0.dcache.WriteReq_misses::total 251643 # number of WriteReq misses 728system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13638 # number of LoadLockedReq misses 729system.cpu0.dcache.LoadLockedReq_misses::total 13638 # number of LoadLockedReq misses 730system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5458 # number of StoreCondReq misses 731system.cpu0.dcache.StoreCondReq_misses::total 5458 # number of StoreCondReq misses 732system.cpu0.dcache.demand_misses::cpu0.data 1189892 # number of demand (read+write) misses 733system.cpu0.dcache.demand_misses::total 1189892 # number of demand (read+write) misses 734system.cpu0.dcache.overall_misses::cpu0.data 1189892 # number of overall misses 735system.cpu0.dcache.overall_misses::total 1189892 # number of overall misses 736system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23522563000 # number of ReadReq miss cycles 737system.cpu0.dcache.ReadReq_miss_latency::total 23522563000 # number of ReadReq miss cycles 738system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8201327000 # number of WriteReq miss cycles 739system.cpu0.dcache.WriteReq_miss_latency::total 8201327000 # number of WriteReq miss cycles 740system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 147906000 # number of LoadLockedReq miss cycles 741system.cpu0.dcache.LoadLockedReq_miss_latency::total 147906000 # number of LoadLockedReq miss cycles 742system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 67796500 # number of StoreCondReq miss cycles 743system.cpu0.dcache.StoreCondReq_miss_latency::total 67796500 # number of StoreCondReq miss cycles 744system.cpu0.dcache.demand_miss_latency::cpu0.data 31723890000 # number of demand (read+write) miss cycles 745system.cpu0.dcache.demand_miss_latency::total 31723890000 # number of demand (read+write) miss cycles 746system.cpu0.dcache.overall_miss_latency::cpu0.data 31723890000 # number of overall miss cycles 747system.cpu0.dcache.overall_miss_latency::total 31723890000 # number of overall miss cycles 748system.cpu0.dcache.ReadReq_accesses::cpu0.data 7345031 # number of ReadReq accesses(hits+misses) 749system.cpu0.dcache.ReadReq_accesses::total 7345031 # number of ReadReq accesses(hits+misses) 750system.cpu0.dcache.WriteReq_accesses::cpu0.data 4907403 # number of WriteReq accesses(hits+misses) 751system.cpu0.dcache.WriteReq_accesses::total 4907403 # number of WriteReq accesses(hits+misses) 752system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153924 # number of LoadLockedReq accesses(hits+misses) 753system.cpu0.dcache.LoadLockedReq_accesses::total 153924 # number of LoadLockedReq accesses(hits+misses) 754system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153373 # number of StoreCondReq accesses(hits+misses) 755system.cpu0.dcache.StoreCondReq_accesses::total 153373 # number of StoreCondReq accesses(hits+misses) 756system.cpu0.dcache.demand_accesses::cpu0.data 12252434 # number of demand (read+write) accesses 757system.cpu0.dcache.demand_accesses::total 12252434 # number of demand (read+write) accesses 758system.cpu0.dcache.overall_accesses::cpu0.data 12252434 # number of overall (read+write) accesses 759system.cpu0.dcache.overall_accesses::total 12252434 # number of overall (read+write) accesses 760system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127739 # miss rate for ReadReq accesses 761system.cpu0.dcache.ReadReq_miss_rate::total 0.127739 # miss rate for ReadReq accesses 762system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051278 # miss rate for WriteReq accesses 763system.cpu0.dcache.WriteReq_miss_rate::total 0.051278 # miss rate for WriteReq accesses 764system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088602 # miss rate for LoadLockedReq accesses 765system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088602 # miss rate for LoadLockedReq accesses 766system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035586 # miss rate for StoreCondReq accesses 767system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035586 # miss rate for StoreCondReq accesses 768system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097115 # miss rate for demand accesses 769system.cpu0.dcache.demand_miss_rate::total 0.097115 # miss rate for demand accesses 770system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097115 # miss rate for overall accesses 771system.cpu0.dcache.overall_miss_rate::total 0.097115 # miss rate for overall accesses 772system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25070.704046 # average ReadReq miss latency 773system.cpu0.dcache.ReadReq_avg_miss_latency::total 25070.704046 # average ReadReq miss latency 774system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32591.119165 # average WriteReq miss latency 775system.cpu0.dcache.WriteReq_avg_miss_latency::total 32591.119165 # average WriteReq miss latency 776system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10845.138583 # average LoadLockedReq miss latency 777system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10845.138583 # average LoadLockedReq miss latency 778system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12421.491389 # average StoreCondReq miss latency 779system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12421.491389 # average StoreCondReq miss latency 780system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency 781system.cpu0.dcache.demand_avg_miss_latency::total 26661.150760 # average overall miss latency 782system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency 783system.cpu0.dcache.overall_avg_miss_latency::total 26661.150760 # average overall miss latency | 861system.cpu0.dcache.replacements 1171741 # number of replacements 862system.cpu0.dcache.tagsinuse 505.264481 # Cycle average of tags in use 863system.cpu0.dcache.total_refs 11253752 # Total number of references to valid blocks. 864system.cpu0.dcache.sampled_refs 1172158 # Sample count of references to valid blocks. 865system.cpu0.dcache.avg_refs 9.600883 # Average number of references to valid blocks. 866system.cpu0.dcache.warmup_cycle 93429000 # Cycle when the warmup percentage was hit. 867system.cpu0.dcache.occ_blocks::cpu0.data 505.264481 # Average occupied blocks per requestor 868system.cpu0.dcache.occ_percent::cpu0.data 0.986845 # Average percentage of cache occupancy 869system.cpu0.dcache.occ_percent::total 0.986845 # Average percentage of cache occupancy 870system.cpu0.dcache.ReadReq_hits::cpu0.data 6351991 # number of ReadReq hits 871system.cpu0.dcache.ReadReq_hits::total 6351991 # number of ReadReq hits 872system.cpu0.dcache.WriteReq_hits::cpu0.data 4607363 # number of WriteReq hits 873system.cpu0.dcache.WriteReq_hits::total 4607363 # number of WriteReq hits 874system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138394 # number of LoadLockedReq hits 875system.cpu0.dcache.LoadLockedReq_hits::total 138394 # number of LoadLockedReq hits 876system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145569 # number of StoreCondReq hits 877system.cpu0.dcache.StoreCondReq_hits::total 145569 # number of StoreCondReq hits 878system.cpu0.dcache.demand_hits::cpu0.data 10959354 # number of demand (read+write) hits 879system.cpu0.dcache.demand_hits::total 10959354 # number of demand (read+write) hits 880system.cpu0.dcache.overall_hits::cpu0.data 10959354 # number of overall hits 881system.cpu0.dcache.overall_hits::total 10959354 # number of overall hits 882system.cpu0.dcache.ReadReq_misses::cpu0.data 933040 # number of ReadReq misses 883system.cpu0.dcache.ReadReq_misses::total 933040 # number of ReadReq misses 884system.cpu0.dcache.WriteReq_misses::cpu0.data 249280 # number of WriteReq misses 885system.cpu0.dcache.WriteReq_misses::total 249280 # number of WriteReq misses 886system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13436 # number of LoadLockedReq misses 887system.cpu0.dcache.LoadLockedReq_misses::total 13436 # number of LoadLockedReq misses 888system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5731 # number of StoreCondReq misses 889system.cpu0.dcache.StoreCondReq_misses::total 5731 # number of StoreCondReq misses 890system.cpu0.dcache.demand_misses::cpu0.data 1182320 # number of demand (read+write) misses 891system.cpu0.dcache.demand_misses::total 1182320 # number of demand (read+write) misses 892system.cpu0.dcache.overall_misses::cpu0.data 1182320 # number of overall misses 893system.cpu0.dcache.overall_misses::total 1182320 # number of overall misses 894system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 20820883000 # number of ReadReq miss cycles 895system.cpu0.dcache.ReadReq_miss_latency::total 20820883000 # number of ReadReq miss cycles 896system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7761604000 # number of WriteReq miss cycles 897system.cpu0.dcache.WriteReq_miss_latency::total 7761604000 # number of WriteReq miss cycles 898system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144502500 # number of LoadLockedReq miss cycles 899system.cpu0.dcache.LoadLockedReq_miss_latency::total 144502500 # number of LoadLockedReq miss cycles 900system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43447000 # number of StoreCondReq miss cycles 901system.cpu0.dcache.StoreCondReq_miss_latency::total 43447000 # number of StoreCondReq miss cycles 902system.cpu0.dcache.demand_miss_latency::cpu0.data 28582487000 # number of demand (read+write) miss cycles 903system.cpu0.dcache.demand_miss_latency::total 28582487000 # number of demand (read+write) miss cycles 904system.cpu0.dcache.overall_miss_latency::cpu0.data 28582487000 # number of overall miss cycles 905system.cpu0.dcache.overall_miss_latency::total 28582487000 # number of overall miss cycles 906system.cpu0.dcache.ReadReq_accesses::cpu0.data 7285031 # number of ReadReq accesses(hits+misses) 907system.cpu0.dcache.ReadReq_accesses::total 7285031 # number of ReadReq accesses(hits+misses) 908system.cpu0.dcache.WriteReq_accesses::cpu0.data 4856643 # number of WriteReq accesses(hits+misses) 909system.cpu0.dcache.WriteReq_accesses::total 4856643 # number of WriteReq accesses(hits+misses) 910system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151830 # number of LoadLockedReq accesses(hits+misses) 911system.cpu0.dcache.LoadLockedReq_accesses::total 151830 # number of LoadLockedReq accesses(hits+misses) 912system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151300 # number of StoreCondReq accesses(hits+misses) 913system.cpu0.dcache.StoreCondReq_accesses::total 151300 # number of StoreCondReq accesses(hits+misses) 914system.cpu0.dcache.demand_accesses::cpu0.data 12141674 # number of demand (read+write) accesses 915system.cpu0.dcache.demand_accesses::total 12141674 # number of demand (read+write) accesses 916system.cpu0.dcache.overall_accesses::cpu0.data 12141674 # number of overall (read+write) accesses 917system.cpu0.dcache.overall_accesses::total 12141674 # number of overall (read+write) accesses 918system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128076 # miss rate for ReadReq accesses 919system.cpu0.dcache.ReadReq_miss_rate::total 0.128076 # miss rate for ReadReq accesses 920system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051328 # miss rate for WriteReq accesses 921system.cpu0.dcache.WriteReq_miss_rate::total 0.051328 # miss rate for WriteReq accesses 922system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088494 # miss rate for LoadLockedReq accesses 923system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088494 # miss rate for LoadLockedReq accesses 924system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037878 # miss rate for StoreCondReq accesses 925system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037878 # miss rate for StoreCondReq accesses 926system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097377 # miss rate for demand accesses 927system.cpu0.dcache.demand_miss_rate::total 0.097377 # miss rate for demand accesses 928system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097377 # miss rate for overall accesses 929system.cpu0.dcache.overall_miss_rate::total 0.097377 # miss rate for overall accesses 930system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22315.102246 # average ReadReq miss latency 931system.cpu0.dcache.ReadReq_avg_miss_latency::total 22315.102246 # average ReadReq miss latency 932system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31136.087933 # average WriteReq miss latency 933system.cpu0.dcache.WriteReq_avg_miss_latency::total 31136.087933 # average WriteReq miss latency 934system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10754.874963 # average LoadLockedReq miss latency 935system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10754.874963 # average LoadLockedReq miss latency 936system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7581.050427 # average StoreCondReq miss latency 937system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7581.050427 # average StoreCondReq miss latency 938system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency 939system.cpu0.dcache.demand_avg_miss_latency::total 24174.916266 # average overall miss latency 940system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24174.916266 # average overall miss latency 941system.cpu0.dcache.overall_avg_miss_latency::total 24174.916266 # average overall miss latency |
| 784system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 785system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 786system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 787system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 788system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 789system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.cpu0.dcache.fast_writes 0 # number of fast writes performed 791system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 942system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 943system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 944system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 945system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 946system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 947system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 948system.cpu0.dcache.fast_writes 0 # number of fast writes performed 949system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 792system.cpu0.dcache.writebacks::writebacks 679069 # number of writebacks 793system.cpu0.dcache.writebacks::total 679069 # number of writebacks 794system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938249 # number of ReadReq MSHR misses 795system.cpu0.dcache.ReadReq_mshr_misses::total 938249 # number of ReadReq MSHR misses 796system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251643 # number of WriteReq MSHR misses 797system.cpu0.dcache.WriteReq_mshr_misses::total 251643 # number of WriteReq MSHR misses 798system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13638 # number of LoadLockedReq MSHR misses 799system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13638 # number of LoadLockedReq MSHR misses 800system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5458 # number of StoreCondReq MSHR misses 801system.cpu0.dcache.StoreCondReq_mshr_misses::total 5458 # number of StoreCondReq MSHR misses 802system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189892 # number of demand (read+write) MSHR misses 803system.cpu0.dcache.demand_mshr_misses::total 1189892 # number of demand (read+write) MSHR misses 804system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189892 # number of overall MSHR misses 805system.cpu0.dcache.overall_mshr_misses::total 1189892 # number of overall MSHR misses 806system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21646065000 # number of ReadReq MSHR miss cycles 807system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21646065000 # number of ReadReq MSHR miss cycles 808system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7698041000 # number of WriteReq MSHR miss cycles 809system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7698041000 # number of WriteReq MSHR miss cycles 810system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 120630000 # number of LoadLockedReq MSHR miss cycles 811system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 120630000 # number of LoadLockedReq MSHR miss cycles 812system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56880500 # number of StoreCondReq MSHR miss cycles 813system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56880500 # number of StoreCondReq MSHR miss cycles 814system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29344106000 # number of demand (read+write) MSHR miss cycles 815system.cpu0.dcache.demand_mshr_miss_latency::total 29344106000 # number of demand (read+write) MSHR miss cycles 816system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29344106000 # number of overall MSHR miss cycles 817system.cpu0.dcache.overall_mshr_miss_latency::total 29344106000 # number of overall MSHR miss cycles 818system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465334500 # number of ReadReq MSHR uncacheable cycles 819system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465334500 # number of ReadReq MSHR uncacheable cycles 820system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2275733500 # number of WriteReq MSHR uncacheable cycles 821system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2275733500 # number of WriteReq MSHR uncacheable cycles 822system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3741068000 # number of overall MSHR uncacheable cycles 823system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3741068000 # number of overall MSHR uncacheable cycles 824system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127739 # mshr miss rate for ReadReq accesses 825system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127739 # mshr miss rate for ReadReq accesses 826system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051278 # mshr miss rate for WriteReq accesses 827system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051278 # mshr miss rate for WriteReq accesses 828system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088602 # mshr miss rate for LoadLockedReq accesses 829system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088602 # mshr miss rate for LoadLockedReq accesses 830system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035586 # mshr miss rate for StoreCondReq accesses 831system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035586 # mshr miss rate for StoreCondReq accesses 832system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for demand accesses 833system.cpu0.dcache.demand_mshr_miss_rate::total 0.097115 # mshr miss rate for demand accesses 834system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for overall accesses 835system.cpu0.dcache.overall_mshr_miss_rate::total 0.097115 # mshr miss rate for overall accesses 836system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23070.704046 # average ReadReq mshr miss latency 837system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 23070.704046 # average ReadReq mshr miss latency 838system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30591.119165 # average WriteReq mshr miss latency 839system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency 840system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency 841system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency 842system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency 843system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency 844system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency 845system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency 846system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency 847system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency | 950system.cpu0.dcache.writebacks::writebacks 672349 # number of writebacks 951system.cpu0.dcache.writebacks::total 672349 # number of writebacks 952system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 933040 # number of ReadReq MSHR misses 953system.cpu0.dcache.ReadReq_mshr_misses::total 933040 # number of ReadReq MSHR misses 954system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249280 # number of WriteReq MSHR misses 955system.cpu0.dcache.WriteReq_mshr_misses::total 249280 # number of WriteReq MSHR misses 956system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13436 # number of LoadLockedReq MSHR misses 957system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13436 # number of LoadLockedReq MSHR misses 958system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5731 # number of StoreCondReq MSHR misses 959system.cpu0.dcache.StoreCondReq_mshr_misses::total 5731 # number of StoreCondReq MSHR misses 960system.cpu0.dcache.demand_mshr_misses::cpu0.data 1182320 # number of demand (read+write) MSHR misses 961system.cpu0.dcache.demand_mshr_misses::total 1182320 # number of demand (read+write) MSHR misses 962system.cpu0.dcache.overall_mshr_misses::cpu0.data 1182320 # number of overall MSHR misses 963system.cpu0.dcache.overall_mshr_misses::total 1182320 # number of overall MSHR misses 964system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18954803000 # number of ReadReq MSHR miss cycles 965system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18954803000 # number of ReadReq MSHR miss cycles 966system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7263044000 # number of WriteReq MSHR miss cycles 967system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7263044000 # number of WriteReq MSHR miss cycles 968system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 117630500 # number of LoadLockedReq MSHR miss cycles 969system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 117630500 # number of LoadLockedReq MSHR miss cycles 970system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31985000 # number of StoreCondReq MSHR miss cycles 971system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31985000 # number of StoreCondReq MSHR miss cycles 972system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26217847000 # number of demand (read+write) MSHR miss cycles 973system.cpu0.dcache.demand_mshr_miss_latency::total 26217847000 # number of demand (read+write) MSHR miss cycles 974system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26217847000 # number of overall MSHR miss cycles 975system.cpu0.dcache.overall_mshr_miss_latency::total 26217847000 # number of overall MSHR miss cycles 976system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465453500 # number of ReadReq MSHR uncacheable cycles 977system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465453500 # number of ReadReq MSHR uncacheable cycles 978system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2285524000 # number of WriteReq MSHR uncacheable cycles 979system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2285524000 # number of WriteReq MSHR uncacheable cycles 980system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750977500 # number of overall MSHR uncacheable cycles 981system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750977500 # number of overall MSHR uncacheable cycles 982system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128076 # mshr miss rate for ReadReq accesses 983system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128076 # mshr miss rate for ReadReq accesses 984system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051328 # mshr miss rate for WriteReq accesses 985system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051328 # mshr miss rate for WriteReq accesses 986system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088494 # mshr miss rate for LoadLockedReq accesses 987system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088494 # mshr miss rate for LoadLockedReq accesses 988system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037878 # mshr miss rate for StoreCondReq accesses 989system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037878 # mshr miss rate for StoreCondReq accesses 990system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for demand accesses 991system.cpu0.dcache.demand_mshr_miss_rate::total 0.097377 # mshr miss rate for demand accesses 992system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097377 # mshr miss rate for overall accesses 993system.cpu0.dcache.overall_mshr_miss_rate::total 0.097377 # mshr miss rate for overall accesses 994system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20315.102246 # average ReadReq mshr miss latency 995system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20315.102246 # average ReadReq mshr miss latency 996system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29136.087933 # average WriteReq mshr miss latency 997system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29136.087933 # average WriteReq mshr miss latency 998system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8754.874963 # average LoadLockedReq mshr miss latency 999system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8754.874963 # average LoadLockedReq mshr miss latency 1000system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5581.050427 # average StoreCondReq mshr miss latency 1001system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5581.050427 # average StoreCondReq mshr miss latency 1002system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency 1003system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency 1004system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22174.916266 # average overall mshr miss latency 1005system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22174.916266 # average overall mshr miss latency |
| 848system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 849system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 850system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 851system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 852system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 853system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 854system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 855system.cpu1.dtb.fetch_hits 0 # ITB hits 856system.cpu1.dtb.fetch_misses 0 # ITB misses 857system.cpu1.dtb.fetch_acv 0 # ITB acv 858system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1006system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1007system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1008system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1009system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1010system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1011system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1012system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1013system.cpu1.dtb.fetch_hits 0 # ITB hits 1014system.cpu1.dtb.fetch_misses 0 # ITB misses 1015system.cpu1.dtb.fetch_acv 0 # ITB acv 1016system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 859system.cpu1.dtb.read_hits 2425080 # DTB read hits | 1017system.cpu1.dtb.read_hits 2500235 # DTB read hits |
| 860system.cpu1.dtb.read_misses 2992 # DTB read misses 861system.cpu1.dtb.read_acv 0 # DTB read access violations 862system.cpu1.dtb.read_accesses 239363 # DTB read accesses | 1018system.cpu1.dtb.read_misses 2992 # DTB read misses 1019system.cpu1.dtb.read_acv 0 # DTB read access violations 1020system.cpu1.dtb.read_accesses 239363 # DTB read accesses |
| 863system.cpu1.dtb.write_hits 1761000 # DTB write hits | 1021system.cpu1.dtb.write_hits 1820988 # DTB write hits |
| 864system.cpu1.dtb.write_misses 341 # DTB write misses 865system.cpu1.dtb.write_acv 29 # DTB write access violations 866system.cpu1.dtb.write_accesses 105247 # DTB write accesses | 1022system.cpu1.dtb.write_misses 341 # DTB write misses 1023system.cpu1.dtb.write_acv 29 # DTB write access violations 1024system.cpu1.dtb.write_accesses 105247 # DTB write accesses |
| 867system.cpu1.dtb.data_hits 4186080 # DTB hits | 1025system.cpu1.dtb.data_hits 4321223 # DTB hits |
| 868system.cpu1.dtb.data_misses 3333 # DTB misses 869system.cpu1.dtb.data_acv 29 # DTB access violations 870system.cpu1.dtb.data_accesses 344610 # DTB accesses | 1026system.cpu1.dtb.data_misses 3333 # DTB misses 1027system.cpu1.dtb.data_acv 29 # DTB access violations 1028system.cpu1.dtb.data_accesses 344610 # DTB accesses |
| 871system.cpu1.itb.fetch_hits 1964871 # ITB hits | 1029system.cpu1.itb.fetch_hits 1990033 # ITB hits |
| 872system.cpu1.itb.fetch_misses 1216 # ITB misses 873system.cpu1.itb.fetch_acv 0 # ITB acv | 1030system.cpu1.itb.fetch_misses 1216 # ITB misses 1031system.cpu1.itb.fetch_acv 0 # ITB acv |
| 874system.cpu1.itb.fetch_accesses 1966087 # ITB accesses | 1032system.cpu1.itb.fetch_accesses 1991249 # ITB accesses |
| 875system.cpu1.itb.read_hits 0 # DTB read hits 876system.cpu1.itb.read_misses 0 # DTB read misses 877system.cpu1.itb.read_acv 0 # DTB read access violations 878system.cpu1.itb.read_accesses 0 # DTB read accesses 879system.cpu1.itb.write_hits 0 # DTB write hits 880system.cpu1.itb.write_misses 0 # DTB write misses 881system.cpu1.itb.write_acv 0 # DTB write access violations 882system.cpu1.itb.write_accesses 0 # DTB write accesses 883system.cpu1.itb.data_hits 0 # DTB hits 884system.cpu1.itb.data_misses 0 # DTB misses 885system.cpu1.itb.data_acv 0 # DTB access violations 886system.cpu1.itb.data_accesses 0 # DTB accesses | 1033system.cpu1.itb.read_hits 0 # DTB read hits 1034system.cpu1.itb.read_misses 0 # DTB read misses 1035system.cpu1.itb.read_acv 0 # DTB read access violations 1036system.cpu1.itb.read_accesses 0 # DTB read accesses 1037system.cpu1.itb.write_hits 0 # DTB write hits 1038system.cpu1.itb.write_misses 0 # DTB write misses 1039system.cpu1.itb.write_acv 0 # DTB write access violations 1040system.cpu1.itb.write_accesses 0 # DTB write accesses 1041system.cpu1.itb.data_hits 0 # DTB hits 1042system.cpu1.itb.data_misses 0 # DTB misses 1043system.cpu1.itb.data_acv 0 # DTB access violations 1044system.cpu1.itb.data_accesses 0 # DTB accesses |
| 887system.cpu1.numCycles 3911492481 # number of cpu cycles simulated | 1045system.cpu1.numCycles 3901626495 # number of cpu cycles simulated |
| 888system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 889system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1046system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1047system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 890system.cpu1.committedInsts 13183934 # Number of instructions committed 891system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed 892system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses 893system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses 894system.cpu1.num_func_calls 412685 # number of times a function call or return occured 895system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls 896system.cpu1.num_int_insts 12160396 # number of integer instructions 897system.cpu1.num_fp_insts 172922 # number of float instructions 898system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read 899system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written 900system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read 901system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written 902system.cpu1.num_mem_refs 4209624 # number of memory refs 903system.cpu1.num_load_insts 2439377 # Number of load instructions 904system.cpu1.num_store_insts 1770247 # Number of store instructions 905system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles 906system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles 907system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles 908system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles | 1048system.cpu1.committedInsts 13632042 # Number of instructions committed 1049system.cpu1.committedOps 13632042 # Number of ops (including micro ops) committed 1050system.cpu1.num_int_alu_accesses 12571491 # Number of integer alu accesses 1051system.cpu1.num_fp_alu_accesses 180459 # Number of float alu accesses 1052system.cpu1.num_func_calls 426717 # number of times a function call or return occured 1053system.cpu1.num_conditional_control_insts 1355011 # number of instructions that are conditional controls 1054system.cpu1.num_int_insts 12571491 # number of integer instructions 1055system.cpu1.num_fp_insts 180459 # number of float instructions 1056system.cpu1.num_int_register_reads 17311598 # number of times the integer registers were read 1057system.cpu1.num_int_register_writes 9221787 # number of times the integer registers were written 1058system.cpu1.num_fp_register_reads 94168 # number of times the floating registers were read 1059system.cpu1.num_fp_register_writes 96184 # number of times the floating registers were written 1060system.cpu1.num_mem_refs 4345531 # number of memory refs 1061system.cpu1.num_load_insts 2514982 # Number of load instructions 1062system.cpu1.num_store_insts 1830549 # Number of store instructions 1063system.cpu1.num_idle_cycles 3850258507.998026 # Number of idle cycles 1064system.cpu1.num_busy_cycles 51367987.001974 # Number of busy cycles 1065system.cpu1.not_idle_fraction 0.013166 # Percentage of non-idle cycles 1066system.cpu1.idle_fraction 0.986834 # Percentage of idle cycles |
| 909system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1067system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 910system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed 911system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed 912system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl 913system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl 914system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl 915system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl 916system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl 917system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl 918system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl 919system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl 920system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl 921system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl 922system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl 923system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl 924system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl 925system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl 926system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl 927system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl | 1068system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed 1069system.cpu1.kern.inst.hwrei 80899 # number of hwrei instructions executed 1070system.cpu1.kern.ipl_count::0 27499 38.50% 38.50% # number of times we switched to this ipl 1071system.cpu1.kern.ipl_count::22 1966 2.75% 41.25% # number of times we switched to this ipl 1072system.cpu1.kern.ipl_count::30 525 0.74% 41.99% # number of times we switched to this ipl 1073system.cpu1.kern.ipl_count::31 41433 58.01% 100.00% # number of times we switched to this ipl 1074system.cpu1.kern.ipl_count::total 71423 # number of times we switched to this ipl 1075system.cpu1.kern.ipl_good::0 26615 48.22% 48.22% # number of times we switched to this ipl from a different ipl 1076system.cpu1.kern.ipl_good::22 1966 3.56% 51.78% # number of times we switched to this ipl from a different ipl 1077system.cpu1.kern.ipl_good::30 525 0.95% 52.73% # number of times we switched to this ipl from a different ipl 1078system.cpu1.kern.ipl_good::31 26090 47.27% 100.00% # number of times we switched to this ipl from a different ipl 1079system.cpu1.kern.ipl_good::total 55196 # number of times we switched to this ipl from a different ipl 1080system.cpu1.kern.ipl_ticks::0 1907138262500 97.76% 97.76% # number of cycles we spent at this ipl 1081system.cpu1.kern.ipl_ticks::22 705201000 0.04% 97.80% # number of cycles we spent at this ipl 1082system.cpu1.kern.ipl_ticks::30 364168000 0.02% 97.82% # number of cycles we spent at this ipl 1083system.cpu1.kern.ipl_ticks::31 42604858000 2.18% 100.00% # number of cycles we spent at this ipl 1084system.cpu1.kern.ipl_ticks::total 1950812489500 # number of cycles we spent at this ipl 1085system.cpu1.kern.ipl_used::0 0.967853 # fraction of swpipl calls that actually changed the ipl |
| 928system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 929system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1086system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1087system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 930system.cpu1.kern.ipl_used::31 0.627296 # fraction of swpipl calls that actually changed the ipl 931system.cpu1.kern.ipl_used::total 0.771460 # fraction of swpipl calls that actually changed the ipl | 1088system.cpu1.kern.ipl_used::31 0.629691 # fraction of swpipl calls that actually changed the ipl 1089system.cpu1.kern.ipl_used::total 0.772804 # fraction of swpipl calls that actually changed the ipl |
| 932system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 933system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 934system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 935system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 936system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 937system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 938system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 939system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 940system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 941system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 942system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 943system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 944system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 945system.cpu1.kern.syscall::total 104 # number of syscalls executed 946system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1090system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 1091system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 1092system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 1093system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 1094system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 1095system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 1096system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 1097system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 1098system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 1099system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 1100system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 1101system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 1102system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 1103system.cpu1.kern.syscall::total 104 # number of syscalls executed 1104system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 947system.cpu1.kern.callpal::wripir 420 0.59% 0.59% # number of callpals executed 948system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 949system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 950system.cpu1.kern.callpal::swpctx 1995 2.79% 3.38% # number of callpals executed 951system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed 952system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed 953system.cpu1.kern.callpal::swpipl 63027 88.05% 91.44% # number of callpals executed 954system.cpu1.kern.callpal::rdps 2168 3.03% 94.47% # number of callpals executed 955system.cpu1.kern.callpal::wrkgp 1 0.00% 94.47% # number of callpals executed 956system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed 957system.cpu1.kern.callpal::whami 3 0.00% 94.48% # number of callpals executed 958system.cpu1.kern.callpal::rti 3772 5.27% 99.75% # number of callpals executed 959system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed | 1105system.cpu1.kern.callpal::wripir 443 0.60% 0.60% # number of callpals executed 1106system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed 1107system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed 1108system.cpu1.kern.callpal::swpctx 2085 2.82% 3.43% # number of callpals executed 1109system.cpu1.kern.callpal::tbi 3 0.00% 3.43% # number of callpals executed 1110system.cpu1.kern.callpal::wrent 7 0.01% 3.44% # number of callpals executed 1111system.cpu1.kern.callpal::swpipl 65093 88.17% 91.61% # number of callpals executed 1112system.cpu1.kern.callpal::rdps 2167 2.94% 94.55% # number of callpals executed 1113system.cpu1.kern.callpal::wrkgp 1 0.00% 94.55% # number of callpals executed 1114system.cpu1.kern.callpal::wrusp 4 0.01% 94.55% # number of callpals executed 1115system.cpu1.kern.callpal::whami 3 0.00% 94.56% # number of callpals executed 1116system.cpu1.kern.callpal::rti 3838 5.20% 99.75% # number of callpals executed 1117system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed |
| 960system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 961system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1118system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 1119system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 962system.cpu1.kern.callpal::total 71584 # number of callpals executed 963system.cpu1.kern.mode_switch::kernel 2065 # number of protection mode switches 964system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 965system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches 966system.cpu1.kern.mode_good::kernel 891 967system.cpu1.kern.mode_good::user 464 968system.cpu1.kern.mode_good::idle 427 969system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches | 1120system.cpu1.kern.callpal::total 73828 # number of callpals executed 1121system.cpu1.kern.mode_switch::kernel 2126 # number of protection mode switches 1122system.cpu1.kern.mode_switch::user 465 # number of protection mode switches 1123system.cpu1.kern.mode_switch::idle 2924 # number of protection mode switches 1124system.cpu1.kern.mode_good::kernel 915 1125system.cpu1.kern.mode_good::user 465 1126system.cpu1.kern.mode_good::idle 450 1127system.cpu1.kern.mode_switch_good::kernel 0.430386 # fraction of useful protection mode switches |
| 970system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1128system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 971system.cpu1.kern.mode_switch_good::idle 0.148573 # fraction of useful protection mode switches 972system.cpu1.kern.mode_switch_good::total 0.329817 # fraction of useful protection mode switches 973system.cpu1.kern.mode_ticks::kernel 17893399500 0.91% 0.91% # number of ticks spent at the given mode 974system.cpu1.kern.mode_ticks::user 1709951500 0.09% 1.00% # number of ticks spent at the given mode 975system.cpu1.kern.mode_ticks::idle 1936142128000 99.00% 100.00% # number of ticks spent at the given mode 976system.cpu1.kern.swap_context 1996 # number of times the context was actually changed 977system.cpu1.icache.replacements 316204 # number of replacements 978system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use 979system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks. 980system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks. 981system.cpu1.icache.avg_refs 40.637495 # Average number of references to valid blocks. 982system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit. 983system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor 984system.cpu1.icache.occ_percent::cpu1.inst 0.873938 # Average percentage of cache occupancy 985system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy 986system.cpu1.icache.ReadReq_hits::cpu1.inst 12870545 # number of ReadReq hits 987system.cpu1.icache.ReadReq_hits::total 12870545 # number of ReadReq hits 988system.cpu1.icache.demand_hits::cpu1.inst 12870545 # number of demand (read+write) hits 989system.cpu1.icache.demand_hits::total 12870545 # number of demand (read+write) hits 990system.cpu1.icache.overall_hits::cpu1.inst 12870545 # number of overall hits 991system.cpu1.icache.overall_hits::total 12870545 # number of overall hits 992system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses 993system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses 994system.cpu1.icache.demand_misses::cpu1.inst 316752 # number of demand (read+write) misses 995system.cpu1.icache.demand_misses::total 316752 # number of demand (read+write) misses 996system.cpu1.icache.overall_misses::cpu1.inst 316752 # number of overall misses 997system.cpu1.icache.overall_misses::total 316752 # number of overall misses 998system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4179857000 # number of ReadReq miss cycles 999system.cpu1.icache.ReadReq_miss_latency::total 4179857000 # number of ReadReq miss cycles 1000system.cpu1.icache.demand_miss_latency::cpu1.inst 4179857000 # number of demand (read+write) miss cycles 1001system.cpu1.icache.demand_miss_latency::total 4179857000 # number of demand (read+write) miss cycles 1002system.cpu1.icache.overall_miss_latency::cpu1.inst 4179857000 # number of overall miss cycles 1003system.cpu1.icache.overall_miss_latency::total 4179857000 # number of overall miss cycles 1004system.cpu1.icache.ReadReq_accesses::cpu1.inst 13187297 # number of ReadReq accesses(hits+misses) 1005system.cpu1.icache.ReadReq_accesses::total 13187297 # number of ReadReq accesses(hits+misses) 1006system.cpu1.icache.demand_accesses::cpu1.inst 13187297 # number of demand (read+write) accesses 1007system.cpu1.icache.demand_accesses::total 13187297 # number of demand (read+write) accesses 1008system.cpu1.icache.overall_accesses::cpu1.inst 13187297 # number of overall (read+write) accesses 1009system.cpu1.icache.overall_accesses::total 13187297 # number of overall (read+write) accesses 1010system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024019 # miss rate for ReadReq accesses 1011system.cpu1.icache.ReadReq_miss_rate::total 0.024019 # miss rate for ReadReq accesses 1012system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024019 # miss rate for demand accesses 1013system.cpu1.icache.demand_miss_rate::total 0.024019 # miss rate for demand accesses 1014system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024019 # miss rate for overall accesses 1015system.cpu1.icache.overall_miss_rate::total 0.024019 # miss rate for overall accesses 1016system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13195.992448 # average ReadReq miss latency 1017system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency 1018system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency 1019system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency 1020system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency 1021system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency | 1129system.cpu1.kern.mode_switch_good::idle 0.153899 # fraction of useful protection mode switches 1130system.cpu1.kern.mode_switch_good::total 0.331822 # fraction of useful protection mode switches 1131system.cpu1.kern.mode_ticks::kernel 18665784500 0.96% 0.96% # number of ticks spent at the given mode 1132system.cpu1.kern.mode_ticks::user 1711228500 0.09% 1.04% # number of ticks spent at the given mode 1133system.cpu1.kern.mode_ticks::idle 1930435473000 98.96% 100.00% # number of ticks spent at the given mode 1134system.cpu1.kern.swap_context 2086 # number of times the context was actually changed 1135system.cpu1.icache.replacements 328648 # number of replacements 1136system.cpu1.icache.tagsinuse 446.257828 # Cycle average of tags in use 1137system.cpu1.icache.total_refs 13306209 # Total number of references to valid blocks. 1138system.cpu1.icache.sampled_refs 329160 # Sample count of references to valid blocks. 1139system.cpu1.icache.avg_refs 40.424745 # Average number of references to valid blocks. 1140system.cpu1.icache.warmup_cycle 1948917036000 # Cycle when the warmup percentage was hit. 1141system.cpu1.icache.occ_blocks::cpu1.inst 446.257828 # Average occupied blocks per requestor 1142system.cpu1.icache.occ_percent::cpu1.inst 0.871597 # Average percentage of cache occupancy 1143system.cpu1.icache.occ_percent::total 0.871597 # Average percentage of cache occupancy 1144system.cpu1.icache.ReadReq_hits::cpu1.inst 13306209 # number of ReadReq hits 1145system.cpu1.icache.ReadReq_hits::total 13306209 # number of ReadReq hits 1146system.cpu1.icache.demand_hits::cpu1.inst 13306209 # number of demand (read+write) hits 1147system.cpu1.icache.demand_hits::total 13306209 # number of demand (read+write) hits 1148system.cpu1.icache.overall_hits::cpu1.inst 13306209 # number of overall hits 1149system.cpu1.icache.overall_hits::total 13306209 # number of overall hits 1150system.cpu1.icache.ReadReq_misses::cpu1.inst 329196 # number of ReadReq misses 1151system.cpu1.icache.ReadReq_misses::total 329196 # number of ReadReq misses 1152system.cpu1.icache.demand_misses::cpu1.inst 329196 # number of demand (read+write) misses 1153system.cpu1.icache.demand_misses::total 329196 # number of demand (read+write) misses 1154system.cpu1.icache.overall_misses::cpu1.inst 329196 # number of overall misses 1155system.cpu1.icache.overall_misses::total 329196 # number of overall misses 1156system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4347354500 # number of ReadReq miss cycles 1157system.cpu1.icache.ReadReq_miss_latency::total 4347354500 # number of ReadReq miss cycles 1158system.cpu1.icache.demand_miss_latency::cpu1.inst 4347354500 # number of demand (read+write) miss cycles 1159system.cpu1.icache.demand_miss_latency::total 4347354500 # number of demand (read+write) miss cycles 1160system.cpu1.icache.overall_miss_latency::cpu1.inst 4347354500 # number of overall miss cycles 1161system.cpu1.icache.overall_miss_latency::total 4347354500 # number of overall miss cycles 1162system.cpu1.icache.ReadReq_accesses::cpu1.inst 13635405 # number of ReadReq accesses(hits+misses) 1163system.cpu1.icache.ReadReq_accesses::total 13635405 # number of ReadReq accesses(hits+misses) 1164system.cpu1.icache.demand_accesses::cpu1.inst 13635405 # number of demand (read+write) accesses 1165system.cpu1.icache.demand_accesses::total 13635405 # number of demand (read+write) accesses 1166system.cpu1.icache.overall_accesses::cpu1.inst 13635405 # number of overall (read+write) accesses 1167system.cpu1.icache.overall_accesses::total 13635405 # number of overall (read+write) accesses 1168system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024143 # miss rate for ReadReq accesses 1169system.cpu1.icache.ReadReq_miss_rate::total 0.024143 # miss rate for ReadReq accesses 1170system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024143 # miss rate for demand accesses 1171system.cpu1.icache.demand_miss_rate::total 0.024143 # miss rate for demand accesses 1172system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024143 # miss rate for overall accesses 1173system.cpu1.icache.overall_miss_rate::total 0.024143 # miss rate for overall accesses 1174system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13205.976075 # average ReadReq miss latency 1175system.cpu1.icache.ReadReq_avg_miss_latency::total 13205.976075 # average ReadReq miss latency 1176system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency 1177system.cpu1.icache.demand_avg_miss_latency::total 13205.976075 # average overall miss latency 1178system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13205.976075 # average overall miss latency 1179system.cpu1.icache.overall_avg_miss_latency::total 13205.976075 # average overall miss latency |
| 1022system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1023system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1024system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1025system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1026system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1027system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1028system.cpu1.icache.fast_writes 0 # number of fast writes performed 1029system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1180system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1181system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1182system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1183system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1184system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1185system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1186system.cpu1.icache.fast_writes 0 # number of fast writes performed 1187system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1030system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316752 # number of ReadReq MSHR misses 1031system.cpu1.icache.ReadReq_mshr_misses::total 316752 # number of ReadReq MSHR misses 1032system.cpu1.icache.demand_mshr_misses::cpu1.inst 316752 # number of demand (read+write) MSHR misses 1033system.cpu1.icache.demand_mshr_misses::total 316752 # number of demand (read+write) MSHR misses 1034system.cpu1.icache.overall_mshr_misses::cpu1.inst 316752 # number of overall MSHR misses 1035system.cpu1.icache.overall_mshr_misses::total 316752 # number of overall MSHR misses 1036system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3546353000 # number of ReadReq MSHR miss cycles 1037system.cpu1.icache.ReadReq_mshr_miss_latency::total 3546353000 # number of ReadReq MSHR miss cycles 1038system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3546353000 # number of demand (read+write) MSHR miss cycles 1039system.cpu1.icache.demand_mshr_miss_latency::total 3546353000 # number of demand (read+write) MSHR miss cycles 1040system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3546353000 # number of overall MSHR miss cycles 1041system.cpu1.icache.overall_mshr_miss_latency::total 3546353000 # number of overall MSHR miss cycles 1042system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for ReadReq accesses 1043system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024019 # mshr miss rate for ReadReq accesses 1044system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for demand accesses 1045system.cpu1.icache.demand_mshr_miss_rate::total 0.024019 # mshr miss rate for demand accesses 1046system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for overall accesses 1047system.cpu1.icache.overall_mshr_miss_rate::total 0.024019 # mshr miss rate for overall accesses 1048system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average ReadReq mshr miss latency 1049system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11195.992448 # average ReadReq mshr miss latency 1050system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency 1051system.cpu1.icache.demand_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency 1052system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency 1053system.cpu1.icache.overall_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency | 1188system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 329196 # number of ReadReq MSHR misses 1189system.cpu1.icache.ReadReq_mshr_misses::total 329196 # number of ReadReq MSHR misses 1190system.cpu1.icache.demand_mshr_misses::cpu1.inst 329196 # number of demand (read+write) MSHR misses 1191system.cpu1.icache.demand_mshr_misses::total 329196 # number of demand (read+write) MSHR misses 1192system.cpu1.icache.overall_mshr_misses::cpu1.inst 329196 # number of overall MSHR misses 1193system.cpu1.icache.overall_mshr_misses::total 329196 # number of overall MSHR misses 1194system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3688962500 # number of ReadReq MSHR miss cycles 1195system.cpu1.icache.ReadReq_mshr_miss_latency::total 3688962500 # number of ReadReq MSHR miss cycles 1196system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3688962500 # number of demand (read+write) MSHR miss cycles 1197system.cpu1.icache.demand_mshr_miss_latency::total 3688962500 # number of demand (read+write) MSHR miss cycles 1198system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3688962500 # number of overall MSHR miss cycles 1199system.cpu1.icache.overall_mshr_miss_latency::total 3688962500 # number of overall MSHR miss cycles 1200system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for ReadReq accesses 1201system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024143 # mshr miss rate for ReadReq accesses 1202system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for demand accesses 1203system.cpu1.icache.demand_mshr_miss_rate::total 0.024143 # mshr miss rate for demand accesses 1204system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024143 # mshr miss rate for overall accesses 1205system.cpu1.icache.overall_mshr_miss_rate::total 0.024143 # mshr miss rate for overall accesses 1206system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average ReadReq mshr miss latency 1207system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11205.976075 # average ReadReq mshr miss latency 1208system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency 1209system.cpu1.icache.demand_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency 1210system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11205.976075 # average overall mshr miss latency 1211system.cpu1.icache.overall_avg_mshr_miss_latency::total 11205.976075 # average overall mshr miss latency |
| 1054system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1212system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1055system.cpu1.dcache.replacements 166318 # number of replacements 1056system.cpu1.dcache.tagsinuse 487.121043 # Cycle average of tags in use 1057system.cpu1.dcache.total_refs 4017452 # Total number of references to valid blocks. 1058system.cpu1.dcache.sampled_refs 166830 # Sample count of references to valid blocks. 1059system.cpu1.dcache.avg_refs 24.081113 # Average number of references to valid blocks. 1060system.cpu1.dcache.warmup_cycle 63885131000 # Cycle when the warmup percentage was hit. 1061system.cpu1.dcache.occ_blocks::cpu1.data 487.121043 # Average occupied blocks per requestor 1062system.cpu1.dcache.occ_percent::cpu1.data 0.951408 # Average percentage of cache occupancy 1063system.cpu1.dcache.occ_percent::total 0.951408 # Average percentage of cache occupancy 1064system.cpu1.dcache.ReadReq_hits::cpu1.data 2260833 # number of ReadReq hits 1065system.cpu1.dcache.ReadReq_hits::total 2260833 # number of ReadReq hits 1066system.cpu1.dcache.WriteReq_hits::cpu1.data 1643465 # number of WriteReq hits 1067system.cpu1.dcache.WriteReq_hits::total 1643465 # number of WriteReq hits 1068system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48243 # number of LoadLockedReq hits 1069system.cpu1.dcache.LoadLockedReq_hits::total 48243 # number of LoadLockedReq hits 1070system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50839 # number of StoreCondReq hits 1071system.cpu1.dcache.StoreCondReq_hits::total 50839 # number of StoreCondReq hits 1072system.cpu1.dcache.demand_hits::cpu1.data 3904298 # number of demand (read+write) hits 1073system.cpu1.dcache.demand_hits::total 3904298 # number of demand (read+write) hits 1074system.cpu1.dcache.overall_hits::cpu1.data 3904298 # number of overall hits 1075system.cpu1.dcache.overall_hits::total 3904298 # number of overall hits 1076system.cpu1.dcache.ReadReq_misses::cpu1.data 118301 # number of ReadReq misses 1077system.cpu1.dcache.ReadReq_misses::total 118301 # number of ReadReq misses 1078system.cpu1.dcache.WriteReq_misses::cpu1.data 62725 # number of WriteReq misses 1079system.cpu1.dcache.WriteReq_misses::total 62725 # number of WriteReq misses 1080system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8915 # number of LoadLockedReq misses 1081system.cpu1.dcache.LoadLockedReq_misses::total 8915 # number of LoadLockedReq misses 1082system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5846 # number of StoreCondReq misses 1083system.cpu1.dcache.StoreCondReq_misses::total 5846 # number of StoreCondReq misses 1084system.cpu1.dcache.demand_misses::cpu1.data 181026 # number of demand (read+write) misses 1085system.cpu1.dcache.demand_misses::total 181026 # number of demand (read+write) misses 1086system.cpu1.dcache.overall_misses::cpu1.data 181026 # number of overall misses 1087system.cpu1.dcache.overall_misses::total 181026 # number of overall misses 1088system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440550500 # number of ReadReq miss cycles 1089system.cpu1.dcache.ReadReq_miss_latency::total 1440550500 # number of ReadReq miss cycles 1090system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1113565500 # number of WriteReq miss cycles 1091system.cpu1.dcache.WriteReq_miss_latency::total 1113565500 # number of WriteReq miss cycles 1092system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81445500 # number of LoadLockedReq miss cycles 1093system.cpu1.dcache.LoadLockedReq_miss_latency::total 81445500 # number of LoadLockedReq miss cycles 1094system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 69062000 # number of StoreCondReq miss cycles 1095system.cpu1.dcache.StoreCondReq_miss_latency::total 69062000 # number of StoreCondReq miss cycles 1096system.cpu1.dcache.demand_miss_latency::cpu1.data 2554116000 # number of demand (read+write) miss cycles 1097system.cpu1.dcache.demand_miss_latency::total 2554116000 # number of demand (read+write) miss cycles 1098system.cpu1.dcache.overall_miss_latency::cpu1.data 2554116000 # number of overall miss cycles 1099system.cpu1.dcache.overall_miss_latency::total 2554116000 # number of overall miss cycles 1100system.cpu1.dcache.ReadReq_accesses::cpu1.data 2379134 # number of ReadReq accesses(hits+misses) 1101system.cpu1.dcache.ReadReq_accesses::total 2379134 # number of ReadReq accesses(hits+misses) 1102system.cpu1.dcache.WriteReq_accesses::cpu1.data 1706190 # number of WriteReq accesses(hits+misses) 1103system.cpu1.dcache.WriteReq_accesses::total 1706190 # number of WriteReq accesses(hits+misses) 1104system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57158 # number of LoadLockedReq accesses(hits+misses) 1105system.cpu1.dcache.LoadLockedReq_accesses::total 57158 # number of LoadLockedReq accesses(hits+misses) 1106system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56685 # number of StoreCondReq accesses(hits+misses) 1107system.cpu1.dcache.StoreCondReq_accesses::total 56685 # number of StoreCondReq accesses(hits+misses) 1108system.cpu1.dcache.demand_accesses::cpu1.data 4085324 # number of demand (read+write) accesses 1109system.cpu1.dcache.demand_accesses::total 4085324 # number of demand (read+write) accesses 1110system.cpu1.dcache.overall_accesses::cpu1.data 4085324 # number of overall (read+write) accesses 1111system.cpu1.dcache.overall_accesses::total 4085324 # number of overall (read+write) accesses 1112system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049724 # miss rate for ReadReq accesses 1113system.cpu1.dcache.ReadReq_miss_rate::total 0.049724 # miss rate for ReadReq accesses 1114system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036763 # miss rate for WriteReq accesses 1115system.cpu1.dcache.WriteReq_miss_rate::total 0.036763 # miss rate for WriteReq accesses 1116system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155971 # miss rate for LoadLockedReq accesses 1117system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155971 # miss rate for LoadLockedReq accesses 1118system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103131 # miss rate for StoreCondReq accesses 1119system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103131 # miss rate for StoreCondReq accesses 1120system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044311 # miss rate for demand accesses 1121system.cpu1.dcache.demand_miss_rate::total 0.044311 # miss rate for demand accesses 1122system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044311 # miss rate for overall accesses 1123system.cpu1.dcache.overall_miss_rate::total 0.044311 # miss rate for overall accesses 1124system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12176.993432 # average ReadReq miss latency 1125system.cpu1.dcache.ReadReq_avg_miss_latency::total 12176.993432 # average ReadReq miss latency 1126system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17753.136708 # average WriteReq miss latency 1127system.cpu1.dcache.WriteReq_avg_miss_latency::total 17753.136708 # average WriteReq miss latency 1128system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.782389 # average LoadLockedReq miss latency 1129system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.782389 # average LoadLockedReq miss latency 1130system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11813.547725 # average StoreCondReq miss latency 1131system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11813.547725 # average StoreCondReq miss latency 1132system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency 1133system.cpu1.dcache.demand_avg_miss_latency::total 14109.111398 # average overall miss latency 1134system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency 1135system.cpu1.dcache.overall_avg_miss_latency::total 14109.111398 # average overall miss latency | 1213system.cpu1.dcache.replacements 172786 # number of replacements 1214system.cpu1.dcache.tagsinuse 487.450805 # Cycle average of tags in use 1215system.cpu1.dcache.total_refs 4146223 # Total number of references to valid blocks. 1216system.cpu1.dcache.sampled_refs 173298 # Sample count of references to valid blocks. 1217system.cpu1.dcache.avg_refs 23.925394 # Average number of references to valid blocks. 1218system.cpu1.dcache.warmup_cycle 62292634000 # Cycle when the warmup percentage was hit. 1219system.cpu1.dcache.occ_blocks::cpu1.data 487.450805 # Average occupied blocks per requestor 1220system.cpu1.dcache.occ_percent::cpu1.data 0.952052 # Average percentage of cache occupancy 1221system.cpu1.dcache.occ_percent::total 0.952052 # Average percentage of cache occupancy 1222system.cpu1.dcache.ReadReq_hits::cpu1.data 2329094 # number of ReadReq hits 1223system.cpu1.dcache.ReadReq_hits::total 2329094 # number of ReadReq hits 1224system.cpu1.dcache.WriteReq_hits::cpu1.data 1699243 # number of WriteReq hits 1225system.cpu1.dcache.WriteReq_hits::total 1699243 # number of WriteReq hits 1226system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50220 # number of LoadLockedReq hits 1227system.cpu1.dcache.LoadLockedReq_hits::total 50220 # number of LoadLockedReq hits 1228system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52927 # number of StoreCondReq hits 1229system.cpu1.dcache.StoreCondReq_hits::total 52927 # number of StoreCondReq hits 1230system.cpu1.dcache.demand_hits::cpu1.data 4028337 # number of demand (read+write) hits 1231system.cpu1.dcache.demand_hits::total 4028337 # number of demand (read+write) hits 1232system.cpu1.dcache.overall_hits::cpu1.data 4028337 # number of overall hits 1233system.cpu1.dcache.overall_hits::total 4028337 # number of overall hits 1234system.cpu1.dcache.ReadReq_misses::cpu1.data 123236 # number of ReadReq misses 1235system.cpu1.dcache.ReadReq_misses::total 123236 # number of ReadReq misses 1236system.cpu1.dcache.WriteReq_misses::cpu1.data 64754 # number of WriteReq misses 1237system.cpu1.dcache.WriteReq_misses::total 64754 # number of WriteReq misses 1238system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9347 # number of LoadLockedReq misses 1239system.cpu1.dcache.LoadLockedReq_misses::total 9347 # number of LoadLockedReq misses 1240system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6143 # number of StoreCondReq misses 1241system.cpu1.dcache.StoreCondReq_misses::total 6143 # number of StoreCondReq misses 1242system.cpu1.dcache.demand_misses::cpu1.data 187990 # number of demand (read+write) misses 1243system.cpu1.dcache.demand_misses::total 187990 # number of demand (read+write) misses 1244system.cpu1.dcache.overall_misses::cpu1.data 187990 # number of overall misses 1245system.cpu1.dcache.overall_misses::total 187990 # number of overall misses 1246system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1493692000 # number of ReadReq miss cycles 1247system.cpu1.dcache.ReadReq_miss_latency::total 1493692000 # number of ReadReq miss cycles 1248system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1166299500 # number of WriteReq miss cycles 1249system.cpu1.dcache.WriteReq_miss_latency::total 1166299500 # number of WriteReq miss cycles 1250system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85390000 # number of LoadLockedReq miss cycles 1251system.cpu1.dcache.LoadLockedReq_miss_latency::total 85390000 # number of LoadLockedReq miss cycles 1252system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44515500 # number of StoreCondReq miss cycles 1253system.cpu1.dcache.StoreCondReq_miss_latency::total 44515500 # number of StoreCondReq miss cycles 1254system.cpu1.dcache.demand_miss_latency::cpu1.data 2659991500 # number of demand (read+write) miss cycles 1255system.cpu1.dcache.demand_miss_latency::total 2659991500 # number of demand (read+write) miss cycles 1256system.cpu1.dcache.overall_miss_latency::cpu1.data 2659991500 # number of overall miss cycles 1257system.cpu1.dcache.overall_miss_latency::total 2659991500 # number of overall miss cycles 1258system.cpu1.dcache.ReadReq_accesses::cpu1.data 2452330 # number of ReadReq accesses(hits+misses) 1259system.cpu1.dcache.ReadReq_accesses::total 2452330 # number of ReadReq accesses(hits+misses) 1260system.cpu1.dcache.WriteReq_accesses::cpu1.data 1763997 # number of WriteReq accesses(hits+misses) 1261system.cpu1.dcache.WriteReq_accesses::total 1763997 # number of WriteReq accesses(hits+misses) 1262system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59567 # number of LoadLockedReq accesses(hits+misses) 1263system.cpu1.dcache.LoadLockedReq_accesses::total 59567 # number of LoadLockedReq accesses(hits+misses) 1264system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59070 # number of StoreCondReq accesses(hits+misses) 1265system.cpu1.dcache.StoreCondReq_accesses::total 59070 # number of StoreCondReq accesses(hits+misses) 1266system.cpu1.dcache.demand_accesses::cpu1.data 4216327 # number of demand (read+write) accesses 1267system.cpu1.dcache.demand_accesses::total 4216327 # number of demand (read+write) accesses 1268system.cpu1.dcache.overall_accesses::cpu1.data 4216327 # number of overall (read+write) accesses 1269system.cpu1.dcache.overall_accesses::total 4216327 # number of overall (read+write) accesses 1270system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050253 # miss rate for ReadReq accesses 1271system.cpu1.dcache.ReadReq_miss_rate::total 0.050253 # miss rate for ReadReq accesses 1272system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036709 # miss rate for WriteReq accesses 1273system.cpu1.dcache.WriteReq_miss_rate::total 0.036709 # miss rate for WriteReq accesses 1274system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156916 # miss rate for LoadLockedReq accesses 1275system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156916 # miss rate for LoadLockedReq accesses 1276system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103995 # miss rate for StoreCondReq accesses 1277system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103995 # miss rate for StoreCondReq accesses 1278system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044586 # miss rate for demand accesses 1279system.cpu1.dcache.demand_miss_rate::total 0.044586 # miss rate for demand accesses 1280system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044586 # miss rate for overall accesses 1281system.cpu1.dcache.overall_miss_rate::total 0.044586 # miss rate for overall accesses 1282system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12120.581648 # average ReadReq miss latency 1283system.cpu1.dcache.ReadReq_avg_miss_latency::total 12120.581648 # average ReadReq miss latency 1284system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18011.234827 # average WriteReq miss latency 1285system.cpu1.dcache.WriteReq_avg_miss_latency::total 18011.234827 # average WriteReq miss latency 1286system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.551514 # average LoadLockedReq miss latency 1287system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.551514 # average LoadLockedReq miss latency 1288system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7246.540778 # average StoreCondReq miss latency 1289system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7246.540778 # average StoreCondReq miss latency 1290system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency 1291system.cpu1.dcache.demand_avg_miss_latency::total 14149.643598 # average overall miss latency 1292system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14149.643598 # average overall miss latency 1293system.cpu1.dcache.overall_avg_miss_latency::total 14149.643598 # average overall miss latency |
| 1136system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1137system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1138system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1139system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1140system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1141system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1142system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1143system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1294system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1295system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1296system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1297system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1298system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1299system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1300system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1301system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1144system.cpu1.dcache.writebacks::writebacks 114265 # number of writebacks 1145system.cpu1.dcache.writebacks::total 114265 # number of writebacks 1146system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118301 # number of ReadReq MSHR misses 1147system.cpu1.dcache.ReadReq_mshr_misses::total 118301 # number of ReadReq MSHR misses 1148system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62725 # number of WriteReq MSHR misses 1149system.cpu1.dcache.WriteReq_mshr_misses::total 62725 # number of WriteReq MSHR misses 1150system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8915 # number of LoadLockedReq MSHR misses 1151system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8915 # number of LoadLockedReq MSHR misses 1152system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5846 # number of StoreCondReq MSHR misses 1153system.cpu1.dcache.StoreCondReq_mshr_misses::total 5846 # number of StoreCondReq MSHR misses 1154system.cpu1.dcache.demand_mshr_misses::cpu1.data 181026 # number of demand (read+write) MSHR misses 1155system.cpu1.dcache.demand_mshr_misses::total 181026 # number of demand (read+write) MSHR misses 1156system.cpu1.dcache.overall_mshr_misses::cpu1.data 181026 # number of overall MSHR misses 1157system.cpu1.dcache.overall_mshr_misses::total 181026 # number of overall MSHR misses 1158system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203948500 # number of ReadReq MSHR miss cycles 1159system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203948500 # number of ReadReq MSHR miss cycles 1160system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 988115500 # number of WriteReq MSHR miss cycles 1161system.cpu1.dcache.WriteReq_mshr_miss_latency::total 988115500 # number of WriteReq MSHR miss cycles 1162system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63615500 # number of LoadLockedReq MSHR miss cycles 1163system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63615500 # number of LoadLockedReq MSHR miss cycles 1164system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57370000 # number of StoreCondReq MSHR miss cycles 1165system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57370000 # number of StoreCondReq MSHR miss cycles 1166system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2192064000 # number of demand (read+write) MSHR miss cycles 1167system.cpu1.dcache.demand_mshr_miss_latency::total 2192064000 # number of demand (read+write) MSHR miss cycles 1168system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2192064000 # number of overall MSHR miss cycles 1169system.cpu1.dcache.overall_mshr_miss_latency::total 2192064000 # number of overall MSHR miss cycles 1170system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles 1171system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles 1172system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713392500 # number of WriteReq MSHR uncacheable cycles 1173system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713392500 # number of WriteReq MSHR uncacheable cycles 1174system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732780000 # number of overall MSHR uncacheable cycles 1175system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732780000 # number of overall MSHR uncacheable cycles 1176system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049724 # mshr miss rate for ReadReq accesses 1177system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049724 # mshr miss rate for ReadReq accesses 1178system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036763 # mshr miss rate for WriteReq accesses 1179system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036763 # mshr miss rate for WriteReq accesses 1180system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155971 # mshr miss rate for LoadLockedReq accesses 1181system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155971 # mshr miss rate for LoadLockedReq accesses 1182system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103131 # mshr miss rate for StoreCondReq accesses 1183system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103131 # mshr miss rate for StoreCondReq accesses 1184system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for demand accesses 1185system.cpu1.dcache.demand_mshr_miss_rate::total 0.044311 # mshr miss rate for demand accesses 1186system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for overall accesses 1187system.cpu1.dcache.overall_mshr_miss_rate::total 0.044311 # mshr miss rate for overall accesses 1188system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10176.993432 # average ReadReq mshr miss latency 1189system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10176.993432 # average ReadReq mshr miss latency 1190system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15753.136708 # average WriteReq mshr miss latency 1191system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15753.136708 # average WriteReq mshr miss latency 1192system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.782389 # average LoadLockedReq mshr miss latency 1193system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.782389 # average LoadLockedReq mshr miss latency 1194system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9813.547725 # average StoreCondReq mshr miss latency 1195system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9813.547725 # average StoreCondReq mshr miss latency 1196system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency 1197system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency 1198system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency 1199system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency | 1302system.cpu1.dcache.writebacks::writebacks 119115 # number of writebacks 1303system.cpu1.dcache.writebacks::total 119115 # number of writebacks 1304system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123236 # number of ReadReq MSHR misses 1305system.cpu1.dcache.ReadReq_mshr_misses::total 123236 # number of ReadReq MSHR misses 1306system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 64754 # number of WriteReq MSHR misses 1307system.cpu1.dcache.WriteReq_mshr_misses::total 64754 # number of WriteReq MSHR misses 1308system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9347 # number of LoadLockedReq MSHR misses 1309system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9347 # number of LoadLockedReq MSHR misses 1310system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6143 # number of StoreCondReq MSHR misses 1311system.cpu1.dcache.StoreCondReq_mshr_misses::total 6143 # number of StoreCondReq MSHR misses 1312system.cpu1.dcache.demand_mshr_misses::cpu1.data 187990 # number of demand (read+write) MSHR misses 1313system.cpu1.dcache.demand_mshr_misses::total 187990 # number of demand (read+write) MSHR misses 1314system.cpu1.dcache.overall_mshr_misses::cpu1.data 187990 # number of overall MSHR misses 1315system.cpu1.dcache.overall_mshr_misses::total 187990 # number of overall MSHR misses 1316system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1247220000 # number of ReadReq MSHR miss cycles 1317system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1247220000 # number of ReadReq MSHR miss cycles 1318system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036791500 # number of WriteReq MSHR miss cycles 1319system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1036791500 # number of WriteReq MSHR miss cycles 1320system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66696000 # number of LoadLockedReq MSHR miss cycles 1321system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 66696000 # number of LoadLockedReq MSHR miss cycles 1322system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32229500 # number of StoreCondReq MSHR miss cycles 1323system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32229500 # number of StoreCondReq MSHR miss cycles 1324system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2284011500 # number of demand (read+write) MSHR miss cycles 1325system.cpu1.dcache.demand_mshr_miss_latency::total 2284011500 # number of demand (read+write) MSHR miss cycles 1326system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2284011500 # number of overall MSHR miss cycles 1327system.cpu1.dcache.overall_mshr_miss_latency::total 2284011500 # number of overall MSHR miss cycles 1328system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19381000 # number of ReadReq MSHR uncacheable cycles 1329system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19381000 # number of ReadReq MSHR uncacheable cycles 1330system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723171500 # number of WriteReq MSHR uncacheable cycles 1331system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723171500 # number of WriteReq MSHR uncacheable cycles 1332system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742552500 # number of overall MSHR uncacheable cycles 1333system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742552500 # number of overall MSHR uncacheable cycles 1334system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050253 # mshr miss rate for ReadReq accesses 1335system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050253 # mshr miss rate for ReadReq accesses 1336system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036709 # mshr miss rate for WriteReq accesses 1337system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036709 # mshr miss rate for WriteReq accesses 1338system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156916 # mshr miss rate for LoadLockedReq accesses 1339system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156916 # mshr miss rate for LoadLockedReq accesses 1340system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103995 # mshr miss rate for StoreCondReq accesses 1341system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103995 # mshr miss rate for StoreCondReq accesses 1342system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for demand accesses 1343system.cpu1.dcache.demand_mshr_miss_rate::total 0.044586 # mshr miss rate for demand accesses 1344system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044586 # mshr miss rate for overall accesses 1345system.cpu1.dcache.overall_mshr_miss_rate::total 0.044586 # mshr miss rate for overall accesses 1346system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10120.581648 # average ReadReq mshr miss latency 1347system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10120.581648 # average ReadReq mshr miss latency 1348system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16011.234827 # average WriteReq mshr miss latency 1349system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16011.234827 # average WriteReq mshr miss latency 1350system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.551514 # average LoadLockedReq mshr miss latency 1351system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.551514 # average LoadLockedReq mshr miss latency 1352system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5246.540778 # average StoreCondReq mshr miss latency 1353system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5246.540778 # average StoreCondReq mshr miss latency 1354system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency 1355system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency 1356system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12149.643598 # average overall mshr miss latency 1357system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12149.643598 # average overall mshr miss latency |
| 1200system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1201system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1202system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1203system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1204system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1205system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1206system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1207 1208---------- End Simulation Statistics ---------- | 1358system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1359system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1360system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1361system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1362system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1363system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1364system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1365 1366---------- End Simulation Statistics ---------- |