| stats.txt (9229:65f927bda74d) | stats.txt (9289:a31a1243a3ed) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.962058 # Number of seconds simulated 4sim_ticks 1962057812000 # Number of ticks simulated 5final_tick 1962057812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.955746 # Number of seconds simulated 4sim_ticks 1955746240500 # Number of ticks simulated 5final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1235183 # Simulator instruction rate (inst/s) 8host_op_rate 1235183 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40819911602 # Simulator tick rate (ticks/s) 10host_mem_usage 297060 # Number of bytes of host memory used 11host_seconds 48.07 # Real time elapsed on the host 12sim_insts 59370518 # Number of instructions simulated 13sim_ops 59370518 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 834432 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24593280 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 29312 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 572992 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28680832 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 834432 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 29312 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 863744 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7715456 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7715456 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13038 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 384270 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 458 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 8953 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448138 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120554 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120554 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 425284 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12534432 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1351039 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 14939 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 292036 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14617730 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 425284 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 14939 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 440224 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3932329 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3932329 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3932329 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 425284 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12534432 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1351039 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 14939 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 292036 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18550059 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 341238 # number of replacements 52system.l2c.tagsinuse 65290.171288 # Cycle average of tags in use 53system.l2c.total_refs 2492514 # Total number of references to valid blocks. 54system.l2c.sampled_refs 406253 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.135374 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 55481.148199 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 4824.640956 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 4855.323185 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 116.032373 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 13.026576 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.846575 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.073618 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.001771 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000199 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 902430 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 773977 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 86748 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 31919 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1795074 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 820361 # number of Writeback hits 74system.l2c.Writeback_hits::total 820361 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 161 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 218 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 172410 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 12341 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 184751 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 902430 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 946387 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 86748 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 44260 # number of demand (read+write) hits 88system.l2c.demand_hits::total 1979825 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 902430 # number of overall hits 90system.l2c.overall_hits::cpu0.data 946387 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 86748 # number of overall hits 92system.l2c.overall_hits::cpu1.data 44260 # number of overall hits 93system.l2c.overall_hits::total 1979825 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 13038 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 271462 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 469 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 326 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2435 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 490 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 34 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 107 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 113176 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 8669 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 121845 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 13038 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 384638 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 469 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 8995 # number of demand (read+write) misses 112system.l2c.demand_misses::total 407140 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 13038 # number of overall misses 114system.l2c.overall_misses::cpu0.data 384638 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 469 # number of overall misses 116system.l2c.overall_misses::cpu1.data 8995 # number of overall misses 117system.l2c.overall_misses::total 407140 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 678189500 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14120883000 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 24328000 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 17368000 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 14840768500 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 1412000 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 1560000 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 2972000 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 156000 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 364000 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 5885512000 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 450808000 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6336320000 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 678189500 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 20006395000 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 24328000 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 468176000 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 21177088500 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 678189500 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 20006395000 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 24328000 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 468176000 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 21177088500 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 915468 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 1045439 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 87217 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 32245 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2080369 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 820361 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 820361 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 2596 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 547 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 3143 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 55 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 94 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 149 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 285586 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 21010 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 306596 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 915468 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 1331025 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 87217 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 53255 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2386965 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 915468 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 1331025 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 87217 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 53255 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2386965 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.014242 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.259663 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.005377 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.010110 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.137137 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937982 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.895795 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.930640 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.618182 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.776596 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.718121 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.396294 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.412613 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.397412 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.014242 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.288979 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.005377 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.168904 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.170568 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.014242 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.288979 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.005377 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.168904 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.170568 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52016.375211 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.899374 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51872.068230 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 53276.073620 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52019.027673 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 579.876797 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3183.673469 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 1016.068376 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4588.235294 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2849.315068 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 3401.869159 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52003.180886 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 52003.118716 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52014.266591 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 52016.375211 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52013.568602 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 51872.068230 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 52048.471373 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52014.266591 # average overall miss latency | 7host_inst_rate 1240365 # Simulator instruction rate (inst/s) 8host_op_rate 1240364 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39831169965 # Simulator tick rate (ticks/s) 10host_mem_usage 291792 # Number of bytes of host memory used 11host_seconds 49.10 # Real time elapsed on the host 12sim_insts 60902973 # Number of instructions simulated 13sim_ops 60902973 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 830080 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24726528 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 438464 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28681152 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 830080 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 865280 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7699072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7699072 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 12970 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 386352 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 6851 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448143 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120298 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120298 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 424431 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12643014 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1355431 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 17998 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 224193 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14665068 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 424431 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 17998 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 442430 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3936642 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3936642 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3936642 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 424431 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12643014 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1355431 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 17998 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 224193 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18601710 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 341281 # number of replacements 52system.l2c.tagsinuse 65229.882617 # Cycle average of tags in use 53system.l2c.total_refs 2441318 # Total number of references to valid blocks. 54system.l2c.sampled_refs 406256 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.009309 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 7648586000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 55341.365970 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 4865.877793 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 4868.452553 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 116.161458 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 38.024844 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.844442 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.074247 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.074287 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.001772 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000580 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.995329 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 685804 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 664321 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 316190 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 108937 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1775252 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 793334 # number of Writeback hits 74system.l2c.Writeback_hits::total 793334 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 549 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 732 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 35 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 126580 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 47318 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 173898 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 685804 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 790901 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 316190 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 156255 # number of demand (read+write) hits 88system.l2c.demand_hits::total 1949150 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 685804 # number of overall hits 90system.l2c.overall_hits::cpu0.data 790901 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 316190 # number of overall hits 92system.l2c.overall_hits::cpu1.data 156255 # number of overall hits 93system.l2c.overall_hits::total 1949150 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 12970 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 271621 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 244 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 285396 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2948 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 1741 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 4689 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 895 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 1787 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 115480 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 6627 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 122107 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 12970 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 387101 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 6871 # number of demand (read+write) misses 112system.l2c.demand_misses::total 407503 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 12970 # number of overall misses 114system.l2c.overall_misses::cpu0.data 387101 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 561 # number of overall misses 116system.l2c.overall_misses::cpu1.data 6871 # number of overall misses 117system.l2c.overall_misses::total 407503 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 679344500 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14131444000 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 29382500 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 12805500 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 14852976500 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2720000 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 22059498 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 24779498 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 2047000 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 521500 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 2568500 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 6014286500 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 347569000 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6361855500 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 679344500 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 20145730500 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 29382500 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 360374500 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 21214832000 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 679344500 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 20145730500 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 29382500 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 360374500 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 21214832000 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 698774 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 935942 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 316751 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 109181 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2060648 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 793334 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 793334 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 3131 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 2290 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 5421 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 927 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 917 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 1844 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 242060 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 53945 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 296005 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 698774 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 1178002 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 316751 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 163126 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2356653 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 698774 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 1178002 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 316751 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 163126 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2356653 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.018561 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.290211 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.001771 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.002235 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.138498 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941552 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760262 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.864970 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.962244 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976009 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.969089 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.477072 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.122847 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.412517 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.018561 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.328608 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.001771 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.042121 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.172916 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.018561 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.328608 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.001771 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.042121 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.172916 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52378.141866 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52026.330807 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52375.222816 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 52481.557377 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52043.394091 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 922.659430 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12670.590465 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 5284.601834 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2294.843049 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 582.681564 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 1437.325126 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52080.762903 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52447.412102 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 52100.661715 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52060.554155 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 52378.141866 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52042.568994 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 52375.222816 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 52448.624654 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52060.554155 # average overall miss latency |
| 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed | 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed |
| 224system.l2c.writebacks::writebacks 79034 # number of writebacks 225system.l2c.writebacks::total 79034 # number of writebacks | 224system.l2c.writebacks::writebacks 78778 # number of writebacks 225system.l2c.writebacks::total 78778 # number of writebacks |
| 226system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 227system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 228system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 229system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 230system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 231system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits | 226system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 227system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 228system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 229system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 230system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 231system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits |
| 232system.l2c.ReadReq_mshr_misses::cpu0.inst 13038 # number of ReadReq MSHR misses 233system.l2c.ReadReq_mshr_misses::cpu0.data 271462 # number of ReadReq MSHR misses 234system.l2c.ReadReq_mshr_misses::cpu1.inst 458 # number of ReadReq MSHR misses 235system.l2c.ReadReq_mshr_misses::cpu1.data 326 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::total 285284 # number of ReadReq MSHR misses 237system.l2c.UpgradeReq_mshr_misses::cpu0.data 2435 # number of UpgradeReq MSHR misses 238system.l2c.UpgradeReq_mshr_misses::cpu1.data 490 # number of UpgradeReq MSHR misses 239system.l2c.UpgradeReq_mshr_misses::total 2925 # number of UpgradeReq MSHR misses 240system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 34 # number of SCUpgradeReq MSHR misses 241system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses 242system.l2c.SCUpgradeReq_mshr_misses::total 107 # number of SCUpgradeReq MSHR misses 243system.l2c.ReadExReq_mshr_misses::cpu0.data 113176 # number of ReadExReq MSHR misses 244system.l2c.ReadExReq_mshr_misses::cpu1.data 8669 # number of ReadExReq MSHR misses 245system.l2c.ReadExReq_mshr_misses::total 121845 # number of ReadExReq MSHR misses 246system.l2c.demand_mshr_misses::cpu0.inst 13038 # number of demand (read+write) MSHR misses 247system.l2c.demand_mshr_misses::cpu0.data 384638 # number of demand (read+write) MSHR misses 248system.l2c.demand_mshr_misses::cpu1.inst 458 # number of demand (read+write) MSHR misses 249system.l2c.demand_mshr_misses::cpu1.data 8995 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::total 407129 # number of demand (read+write) MSHR misses 251system.l2c.overall_mshr_misses::cpu0.inst 13038 # number of overall MSHR misses 252system.l2c.overall_mshr_misses::cpu0.data 384638 # number of overall MSHR misses 253system.l2c.overall_mshr_misses::cpu1.inst 458 # number of overall MSHR misses 254system.l2c.overall_mshr_misses::cpu1.data 8995 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::total 407129 # number of overall MSHR misses 256system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 521730000 # number of ReadReq MSHR miss cycles 257system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10863339000 # number of ReadReq MSHR miss cycles 258system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 18343000 # number of ReadReq MSHR miss cycles 259system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13456000 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::total 11416868000 # number of ReadReq MSHR miss cycles 261system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 97460000 # number of UpgradeReq MSHR miss cycles 262system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19615000 # number of UpgradeReq MSHR miss cycles 263system.l2c.UpgradeReq_mshr_miss_latency::total 117075000 # number of UpgradeReq MSHR miss cycles 264system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1360000 # number of SCUpgradeReq MSHR miss cycles 265system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2920000 # number of SCUpgradeReq MSHR miss cycles 266system.l2c.SCUpgradeReq_mshr_miss_latency::total 4280000 # number of SCUpgradeReq MSHR miss cycles 267system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4527400000 # number of ReadExReq MSHR miss cycles 268system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 346780000 # number of ReadExReq MSHR miss cycles 269system.l2c.ReadExReq_mshr_miss_latency::total 4874180000 # number of ReadExReq MSHR miss cycles 270system.l2c.demand_mshr_miss_latency::cpu0.inst 521730000 # number of demand (read+write) MSHR miss cycles 271system.l2c.demand_mshr_miss_latency::cpu0.data 15390739000 # number of demand (read+write) MSHR miss cycles 272system.l2c.demand_mshr_miss_latency::cpu1.inst 18343000 # number of demand (read+write) MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu1.data 360236000 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::total 16291048000 # number of demand (read+write) MSHR miss cycles 275system.l2c.overall_mshr_miss_latency::cpu0.inst 521730000 # number of overall MSHR miss cycles 276system.l2c.overall_mshr_miss_latency::cpu0.data 15390739000 # number of overall MSHR miss cycles 277system.l2c.overall_mshr_miss_latency::cpu1.inst 18343000 # number of overall MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu1.data 360236000 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::total 16291048000 # number of overall MSHR miss cycles 280system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1369455000 # number of ReadReq MSHR uncacheable cycles 281system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19250000 # number of ReadReq MSHR uncacheable cycles 282system.l2c.ReadReq_mshr_uncacheable_latency::total 1388705000 # number of ReadReq MSHR uncacheable cycles 283system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1966544000 # number of WriteReq MSHR uncacheable cycles 284system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 505236000 # number of WriteReq MSHR uncacheable cycles 285system.l2c.WriteReq_mshr_uncacheable_latency::total 2471780000 # number of WriteReq MSHR uncacheable cycles 286system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3335999000 # number of overall MSHR uncacheable cycles 287system.l2c.overall_mshr_uncacheable_latency::cpu1.data 524486000 # number of overall MSHR uncacheable cycles 288system.l2c.overall_mshr_uncacheable_latency::total 3860485000 # number of overall MSHR uncacheable cycles 289system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for ReadReq accesses 290system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259663 # mshr miss rate for ReadReq accesses 291system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for ReadReq accesses 292system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.010110 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::total 0.137131 # mshr miss rate for ReadReq accesses 294system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937982 # mshr miss rate for UpgradeReq accesses 295system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.895795 # mshr miss rate for UpgradeReq accesses 296system.l2c.UpgradeReq_mshr_miss_rate::total 0.930640 # mshr miss rate for UpgradeReq accesses 297system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.618182 # mshr miss rate for SCUpgradeReq accesses 298system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.776596 # mshr miss rate for SCUpgradeReq accesses 299system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.718121 # mshr miss rate for SCUpgradeReq accesses 300system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.396294 # mshr miss rate for ReadExReq accesses 301system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.412613 # mshr miss rate for ReadExReq accesses 302system.l2c.ReadExReq_mshr_miss_rate::total 0.397412 # mshr miss rate for ReadExReq accesses 303system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for demand accesses 304system.l2c.demand_mshr_miss_rate::cpu0.data 0.288979 # mshr miss rate for demand accesses 305system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for demand accesses 306system.l2c.demand_mshr_miss_rate::cpu1.data 0.168904 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::total 0.170563 # mshr miss rate for demand accesses 308system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014242 # mshr miss rate for overall accesses 309system.l2c.overall_mshr_miss_rate::cpu0.data 0.288979 # mshr miss rate for overall accesses 310system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005251 # mshr miss rate for overall accesses 311system.l2c.overall_mshr_miss_rate::cpu1.data 0.168904 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::total 0.170563 # mshr miss rate for overall accesses 313system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average ReadReq mshr miss latency 314system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.899374 # average ReadReq mshr miss latency 315system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average ReadReq mshr miss latency 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41276.073620 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::total 40019.307076 # average ReadReq mshr miss latency 318system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.640657 # average UpgradeReq mshr miss latency 319system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.612245 # average UpgradeReq mshr miss latency 320system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.641026 # average UpgradeReq mshr miss latency 321system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency | 232system.l2c.ReadReq_mshr_misses::cpu0.inst 12970 # number of ReadReq MSHR misses 233system.l2c.ReadReq_mshr_misses::cpu0.data 271621 # number of ReadReq MSHR misses 234system.l2c.ReadReq_mshr_misses::cpu1.inst 550 # number of ReadReq MSHR misses 235system.l2c.ReadReq_mshr_misses::cpu1.data 244 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::total 285385 # number of ReadReq MSHR misses 237system.l2c.UpgradeReq_mshr_misses::cpu0.data 2948 # number of UpgradeReq MSHR misses 238system.l2c.UpgradeReq_mshr_misses::cpu1.data 1741 # number of UpgradeReq MSHR misses 239system.l2c.UpgradeReq_mshr_misses::total 4689 # number of UpgradeReq MSHR misses 240system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 892 # number of SCUpgradeReq MSHR misses 241system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 895 # number of SCUpgradeReq MSHR misses 242system.l2c.SCUpgradeReq_mshr_misses::total 1787 # number of SCUpgradeReq MSHR misses 243system.l2c.ReadExReq_mshr_misses::cpu0.data 115480 # number of ReadExReq MSHR misses 244system.l2c.ReadExReq_mshr_misses::cpu1.data 6627 # number of ReadExReq MSHR misses 245system.l2c.ReadExReq_mshr_misses::total 122107 # number of ReadExReq MSHR misses 246system.l2c.demand_mshr_misses::cpu0.inst 12970 # number of demand (read+write) MSHR misses 247system.l2c.demand_mshr_misses::cpu0.data 387101 # number of demand (read+write) MSHR misses 248system.l2c.demand_mshr_misses::cpu1.inst 550 # number of demand (read+write) MSHR misses 249system.l2c.demand_mshr_misses::cpu1.data 6871 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::total 407492 # number of demand (read+write) MSHR misses 251system.l2c.overall_mshr_misses::cpu0.inst 12970 # number of overall MSHR misses 252system.l2c.overall_mshr_misses::cpu0.data 387101 # number of overall MSHR misses 253system.l2c.overall_mshr_misses::cpu1.inst 550 # number of overall MSHR misses 254system.l2c.overall_mshr_misses::cpu1.data 6871 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::total 407492 # number of overall MSHR misses 256system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 519097000 # number of ReadReq MSHR miss cycles 257system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10870382000 # number of ReadReq MSHR miss cycles 258system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 22042500 # number of ReadReq MSHR miss cycles 259system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9816500 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::total 11421338000 # number of ReadReq MSHR miss cycles 261system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 117985500 # number of UpgradeReq MSHR miss cycles 262system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 69640998 # number of UpgradeReq MSHR miss cycles 263system.l2c.UpgradeReq_mshr_miss_latency::total 187626498 # number of UpgradeReq MSHR miss cycles 264system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 35714975 # number of SCUpgradeReq MSHR miss cycles 265system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 35800000 # number of SCUpgradeReq MSHR miss cycles 266system.l2c.SCUpgradeReq_mshr_miss_latency::total 71514975 # number of SCUpgradeReq MSHR miss cycles 267system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4619582000 # number of ReadExReq MSHR miss cycles 268system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 265544000 # number of ReadExReq MSHR miss cycles 269system.l2c.ReadExReq_mshr_miss_latency::total 4885126000 # number of ReadExReq MSHR miss cycles 270system.l2c.demand_mshr_miss_latency::cpu0.inst 519097000 # number of demand (read+write) MSHR miss cycles 271system.l2c.demand_mshr_miss_latency::cpu0.data 15489964000 # number of demand (read+write) MSHR miss cycles 272system.l2c.demand_mshr_miss_latency::cpu1.inst 22042500 # number of demand (read+write) MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu1.data 275360500 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::total 16306464000 # number of demand (read+write) MSHR miss cycles 275system.l2c.overall_mshr_miss_latency::cpu0.inst 519097000 # number of overall MSHR miss cycles 276system.l2c.overall_mshr_miss_latency::cpu0.data 15489964000 # number of overall MSHR miss cycles 277system.l2c.overall_mshr_miss_latency::cpu1.inst 22042500 # number of overall MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu1.data 275360500 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::total 16306464000 # number of overall MSHR miss cycles 280system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1370272000 # number of ReadReq MSHR uncacheable cycles 281system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18137500 # number of ReadReq MSHR uncacheable cycles 282system.l2c.ReadReq_mshr_uncacheable_latency::total 1388409500 # number of ReadReq MSHR uncacheable cycles 283system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2141921500 # number of WriteReq MSHR uncacheable cycles 284system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673752500 # number of WriteReq MSHR uncacheable cycles 285system.l2c.WriteReq_mshr_uncacheable_latency::total 2815674000 # number of WriteReq MSHR uncacheable cycles 286system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3512193500 # number of overall MSHR uncacheable cycles 287system.l2c.overall_mshr_uncacheable_latency::cpu1.data 691890000 # number of overall MSHR uncacheable cycles 288system.l2c.overall_mshr_uncacheable_latency::total 4204083500 # number of overall MSHR uncacheable cycles 289system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for ReadReq accesses 290system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290211 # mshr miss rate for ReadReq accesses 291system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for ReadReq accesses 292system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002235 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::total 0.138493 # mshr miss rate for ReadReq accesses 294system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941552 # mshr miss rate for UpgradeReq accesses 295system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760262 # mshr miss rate for UpgradeReq accesses 296system.l2c.UpgradeReq_mshr_miss_rate::total 0.864970 # mshr miss rate for UpgradeReq accesses 297system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.962244 # mshr miss rate for SCUpgradeReq accesses 298system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976009 # mshr miss rate for SCUpgradeReq accesses 299system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969089 # mshr miss rate for SCUpgradeReq accesses 300system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477072 # mshr miss rate for ReadExReq accesses 301system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122847 # mshr miss rate for ReadExReq accesses 302system.l2c.ReadExReq_mshr_miss_rate::total 0.412517 # mshr miss rate for ReadExReq accesses 303system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for demand accesses 304system.l2c.demand_mshr_miss_rate::cpu0.data 0.328608 # mshr miss rate for demand accesses 305system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for demand accesses 306system.l2c.demand_mshr_miss_rate::cpu1.data 0.042121 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::total 0.172911 # mshr miss rate for demand accesses 308system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018561 # mshr miss rate for overall accesses 309system.l2c.overall_mshr_miss_rate::cpu0.data 0.328608 # mshr miss rate for overall accesses 310system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001736 # mshr miss rate for overall accesses 311system.l2c.overall_mshr_miss_rate::cpu1.data 0.042121 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::total 0.172911 # mshr miss rate for overall accesses 313system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average ReadReq mshr miss latency 314system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40020.403430 # average ReadReq mshr miss latency 315system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average ReadReq mshr miss latency 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40231.557377 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.806980 # average ReadReq mshr miss latency 318system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40022.218453 # average UpgradeReq mshr miss latency 319system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000.573234 # average UpgradeReq mshr miss latency 320system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40014.181702 # average UpgradeReq mshr miss latency 321system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40039.209641 # average SCUpgradeReq mshr miss latency |
| 322system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency | 322system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency |
| 323system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 324system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.180886 # average ReadExReq mshr miss latency 325system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071 # average ReadExReq mshr miss latency 326system.l2c.ReadExReq_avg_mshr_miss_latency::total 40003.118716 # average ReadExReq mshr miss latency 327system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency 328system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency 329system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency 332system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40016.106765 # average overall mshr miss latency 333system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.568602 # average overall mshr miss latency 334system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.218341 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.471373 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::total 40014.462247 # average overall mshr miss latency | 323system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40019.571908 # average SCUpgradeReq mshr miss latency 324system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40003.307932 # average ReadExReq mshr miss latency 325system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40070.016599 # average ReadExReq mshr miss latency 326system.l2c.ReadExReq_avg_mshr_miss_latency::total 40006.928350 # average ReadExReq mshr miss latency 327system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average overall mshr miss latency 328system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.303500 # average overall mshr miss latency 329system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average overall mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40075.753165 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::total 40016.648180 # average overall mshr miss latency 332system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.898998 # average overall mshr miss latency 333system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.303500 # average overall mshr miss latency 334system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40077.272727 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40075.753165 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::total 40016.648180 # average overall mshr miss latency |
| 337system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 338system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 339system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 340system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 341system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 342system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 343system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 344system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 345system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 346system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 337system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 338system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 339system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 340system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 341system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 342system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 343system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 344system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 345system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 346system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 347system.iocache.replacements 41698 # number of replacements 348system.iocache.tagsinuse 0.566822 # Cycle average of tags in use | 347system.iocache.replacements 41696 # number of replacements 348system.iocache.tagsinuse 0.569930 # Cycle average of tags in use |
| 349system.iocache.total_refs 0 # Total number of references to valid blocks. | 349system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 350system.iocache.sampled_refs 41714 # Sample count of references to valid blocks. | 350system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. |
| 351system.iocache.avg_refs 0 # Average number of references to valid blocks. | 351system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 352system.iocache.warmup_cycle 1754521474000 # Cycle when the warmup percentage was hit. 353system.iocache.occ_blocks::tsunami.ide 0.566822 # Average occupied blocks per requestor 354system.iocache.occ_percent::tsunami.ide 0.035426 # Average percentage of cache occupancy 355system.iocache.occ_percent::total 0.035426 # Average percentage of cache occupancy 356system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses 357system.iocache.ReadReq_misses::total 178 # number of ReadReq misses | 352system.iocache.warmup_cycle 1749614950000 # Cycle when the warmup percentage was hit. 353system.iocache.occ_blocks::tsunami.ide 0.569930 # Average occupied blocks per requestor 354system.iocache.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy 355system.iocache.occ_percent::total 0.035621 # Average percentage of cache occupancy 356system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 357system.iocache.ReadReq_misses::total 176 # number of ReadReq misses |
| 358system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 359system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses | 358system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 359system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses |
| 360system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses 361system.iocache.demand_misses::total 41730 # number of demand (read+write) misses 362system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses 363system.iocache.overall_misses::total 41730 # number of overall misses 364system.iocache.ReadReq_miss_latency::tsunami.ide 21239998 # number of ReadReq miss cycles 365system.iocache.ReadReq_miss_latency::total 21239998 # number of ReadReq miss cycles 366system.iocache.WriteReq_miss_latency::tsunami.ide 11448106806 # number of WriteReq miss cycles 367system.iocache.WriteReq_miss_latency::total 11448106806 # number of WriteReq miss cycles 368system.iocache.demand_miss_latency::tsunami.ide 11469346804 # number of demand (read+write) miss cycles 369system.iocache.demand_miss_latency::total 11469346804 # number of demand (read+write) miss cycles 370system.iocache.overall_miss_latency::tsunami.ide 11469346804 # number of overall miss cycles 371system.iocache.overall_miss_latency::total 11469346804 # number of overall miss cycles 372system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) 373system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) | 360system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 361system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 362system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 363system.iocache.overall_misses::total 41728 # number of overall misses 364system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles 365system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles 366system.iocache.WriteReq_miss_latency::tsunami.ide 11453563806 # number of WriteReq miss cycles 367system.iocache.WriteReq_miss_latency::total 11453563806 # number of WriteReq miss cycles 368system.iocache.demand_miss_latency::tsunami.ide 11474577804 # number of demand (read+write) miss cycles 369system.iocache.demand_miss_latency::total 11474577804 # number of demand (read+write) miss cycles 370system.iocache.overall_miss_latency::tsunami.ide 11474577804 # number of overall miss cycles 371system.iocache.overall_miss_latency::total 11474577804 # number of overall miss cycles 372system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 373system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) |
| 374system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 375system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) | 374system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 375system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) |
| 376system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses 377system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses 378system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses 379system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses | 376system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 377system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 378system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 379system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses |
| 380system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 381system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 382system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 383system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 384system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 385system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 386system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 387system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 380system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 381system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 382system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 383system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 384system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 385system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 386system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 387system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 388system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461 # average ReadReq miss latency 389system.iocache.ReadReq_avg_miss_latency::total 119325.831461 # average ReadReq miss latency 390system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275512.774499 # average WriteReq miss latency 391system.iocache.WriteReq_avg_miss_latency::total 275512.774499 # average WriteReq miss latency 392system.iocache.demand_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency 393system.iocache.demand_avg_miss_latency::total 274846.556530 # average overall miss latency 394system.iocache.overall_avg_miss_latency::tsunami.ide 274846.556530 # average overall miss latency 395system.iocache.overall_avg_miss_latency::total 274846.556530 # average overall miss latency 396system.iocache.blocked_cycles::no_mshrs 199371000 # number of cycles access was blocked | 388system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency 389system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency 390system.iocache.WriteReq_avg_miss_latency::tsunami.ide 275644.103918 # average WriteReq miss latency 391system.iocache.WriteReq_avg_miss_latency::total 275644.103918 # average WriteReq miss latency 392system.iocache.demand_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency 393system.iocache.demand_avg_miss_latency::total 274985.089245 # average overall miss latency 394system.iocache.overall_avg_miss_latency::tsunami.ide 274985.089245 # average overall miss latency 395system.iocache.overall_avg_miss_latency::total 274985.089245 # average overall miss latency 396system.iocache.blocked_cycles::no_mshrs 199825 # number of cycles access was blocked |
| 397system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 397system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 398system.iocache.blocked::no_mshrs 24657 # number of cycles access was blocked | 398system.iocache.blocked::no_mshrs 24712 # number of cycles access was blocked |
| 399system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 399system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 400system.iocache.avg_blocked_cycles::no_mshrs 8085.776858 # average number of cycles each access was blocked | 400system.iocache.avg_blocked_cycles::no_mshrs 8.086152 # average number of cycles each access was blocked |
| 401system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.iocache.fast_writes 0 # number of fast writes performed 403system.iocache.cache_copies 0 # number of cache copies performed 404system.iocache.writebacks::writebacks 41520 # number of writebacks 405system.iocache.writebacks::total 41520 # number of writebacks | 401system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.iocache.fast_writes 0 # number of fast writes performed 403system.iocache.cache_copies 0 # number of cache copies performed 404system.iocache.writebacks::writebacks 41520 # number of writebacks 405system.iocache.writebacks::total 41520 # number of writebacks |
| 406system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 407system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses | 406system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 407system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses |
| 408system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 409system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses | 408system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 409system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses |
| 410system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses 411system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses 412system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses 413system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses 414system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11983000 # number of ReadReq MSHR miss cycles 415system.iocache.ReadReq_mshr_miss_latency::total 11983000 # number of ReadReq MSHR miss cycles 416system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9287247000 # number of WriteReq MSHR miss cycles 417system.iocache.WriteReq_mshr_miss_latency::total 9287247000 # number of WriteReq MSHR miss cycles 418system.iocache.demand_mshr_miss_latency::tsunami.ide 9299230000 # number of demand (read+write) MSHR miss cycles 419system.iocache.demand_mshr_miss_latency::total 9299230000 # number of demand (read+write) MSHR miss cycles 420system.iocache.overall_mshr_miss_latency::tsunami.ide 9299230000 # number of overall MSHR miss cycles 421system.iocache.overall_mshr_miss_latency::total 9299230000 # number of overall MSHR miss cycles | 410system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 411system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 412system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 413system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 414system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861998 # number of ReadReq MSHR miss cycles 415system.iocache.ReadReq_mshr_miss_latency::total 11861998 # number of ReadReq MSHR miss cycles 416system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9292859806 # number of WriteReq MSHR miss cycles 417system.iocache.WriteReq_mshr_miss_latency::total 9292859806 # number of WriteReq MSHR miss cycles 418system.iocache.demand_mshr_miss_latency::tsunami.ide 9304721804 # number of demand (read+write) MSHR miss cycles 419system.iocache.demand_mshr_miss_latency::total 9304721804 # number of demand (read+write) MSHR miss cycles 420system.iocache.overall_mshr_miss_latency::tsunami.ide 9304721804 # number of overall MSHR miss cycles 421system.iocache.overall_mshr_miss_latency::total 9304721804 # number of overall MSHR miss cycles |
| 422system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 424system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 425system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 422system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 424system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 425system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719 # average ReadReq mshr miss latency 431system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719 # average ReadReq mshr miss latency 432system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223509.024836 # average WriteReq mshr miss latency 433system.iocache.WriteReq_avg_mshr_miss_latency::total 223509.024836 # average WriteReq mshr miss latency 434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency 435system.iocache.demand_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency 436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222842.798946 # average overall mshr miss latency 437system.iocache.overall_avg_mshr_miss_latency::total 222842.798946 # average overall mshr miss latency | 430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67397.715909 # average ReadReq mshr miss latency 431system.iocache.ReadReq_avg_mshr_miss_latency::total 67397.715909 # average ReadReq mshr miss latency 432system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223644.103918 # average WriteReq mshr miss latency 433system.iocache.WriteReq_avg_mshr_miss_latency::total 223644.103918 # average WriteReq mshr miss latency 434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency 435system.iocache.demand_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency 436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222985.089245 # average overall mshr miss latency 437system.iocache.overall_avg_mshr_miss_latency::total 222985.089245 # average overall mshr miss latency |
| 438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 442system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 443system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 444system.disk0.dma_write_txs 395 # Number of DMA write transactions. 445system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 446system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 447system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 448system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 449system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 450system.disk2.dma_write_txs 1 # Number of DMA write transactions. 451system.cpu0.dtb.fetch_hits 0 # ITB hits 452system.cpu0.dtb.fetch_misses 0 # ITB misses 453system.cpu0.dtb.fetch_acv 0 # ITB acv 454system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 442system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 443system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 444system.disk0.dma_write_txs 395 # Number of DMA write transactions. 445system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 446system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 447system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 448system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 449system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 450system.disk2.dma_write_txs 1 # Number of DMA write transactions. 451system.cpu0.dtb.fetch_hits 0 # ITB hits 452system.cpu0.dtb.fetch_misses 0 # ITB misses 453system.cpu0.dtb.fetch_acv 0 # ITB acv 454system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 455system.cpu0.dtb.read_hits 8658368 # DTB read hits 456system.cpu0.dtb.read_misses 7687 # DTB read misses 457system.cpu0.dtb.read_acv 174 # DTB read access violations 458system.cpu0.dtb.read_accesses 524201 # DTB read accesses 459system.cpu0.dtb.write_hits 6036843 # DTB write hits 460system.cpu0.dtb.write_misses 798 # DTB write misses 461system.cpu0.dtb.write_acv 115 # DTB write access violations 462system.cpu0.dtb.write_accesses 195659 # DTB write accesses 463system.cpu0.dtb.data_hits 14695211 # DTB hits 464system.cpu0.dtb.data_misses 8485 # DTB misses 465system.cpu0.dtb.data_acv 289 # DTB access violations 466system.cpu0.dtb.data_accesses 719860 # DTB accesses 467system.cpu0.itb.fetch_hits 3948323 # ITB hits 468system.cpu0.itb.fetch_misses 3841 # ITB misses 469system.cpu0.itb.fetch_acv 143 # ITB acv 470system.cpu0.itb.fetch_accesses 3952164 # ITB accesses | 455system.cpu0.dtb.read_hits 7486542 # DTB read hits 456system.cpu0.dtb.read_misses 7443 # DTB read misses 457system.cpu0.dtb.read_acv 210 # DTB read access violations 458system.cpu0.dtb.read_accesses 490673 # DTB read accesses 459system.cpu0.dtb.write_hits 5063820 # DTB write hits 460system.cpu0.dtb.write_misses 813 # DTB write misses 461system.cpu0.dtb.write_acv 134 # DTB write access violations 462system.cpu0.dtb.write_accesses 187452 # DTB write accesses 463system.cpu0.dtb.data_hits 12550362 # DTB hits 464system.cpu0.dtb.data_misses 8256 # DTB misses 465system.cpu0.dtb.data_acv 344 # DTB access violations 466system.cpu0.dtb.data_accesses 678125 # DTB accesses 467system.cpu0.itb.fetch_hits 3500956 # ITB hits 468system.cpu0.itb.fetch_misses 3871 # ITB misses 469system.cpu0.itb.fetch_acv 184 # ITB acv 470system.cpu0.itb.fetch_accesses 3504827 # ITB accesses |
| 471system.cpu0.itb.read_hits 0 # DTB read hits 472system.cpu0.itb.read_misses 0 # DTB read misses 473system.cpu0.itb.read_acv 0 # DTB read access violations 474system.cpu0.itb.read_accesses 0 # DTB read accesses 475system.cpu0.itb.write_hits 0 # DTB write hits 476system.cpu0.itb.write_misses 0 # DTB write misses 477system.cpu0.itb.write_acv 0 # DTB write access violations 478system.cpu0.itb.write_accesses 0 # DTB write accesses 479system.cpu0.itb.data_hits 0 # DTB hits 480system.cpu0.itb.data_misses 0 # DTB misses 481system.cpu0.itb.data_acv 0 # DTB access violations 482system.cpu0.itb.data_accesses 0 # DTB accesses | 471system.cpu0.itb.read_hits 0 # DTB read hits 472system.cpu0.itb.read_misses 0 # DTB read misses 473system.cpu0.itb.read_acv 0 # DTB read access violations 474system.cpu0.itb.read_accesses 0 # DTB read accesses 475system.cpu0.itb.write_hits 0 # DTB write hits 476system.cpu0.itb.write_misses 0 # DTB write misses 477system.cpu0.itb.write_acv 0 # DTB write access violations 478system.cpu0.itb.write_accesses 0 # DTB write accesses 479system.cpu0.itb.data_hits 0 # DTB hits 480system.cpu0.itb.data_misses 0 # DTB misses 481system.cpu0.itb.data_acv 0 # DTB access violations 482system.cpu0.itb.data_accesses 0 # DTB accesses |
| 483system.cpu0.numCycles 3924115624 # number of cpu cycles simulated | 483system.cpu0.numCycles 3910167080 # number of cpu cycles simulated |
| 484system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 485system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 484system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 485system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 486system.cpu0.committedInsts 54116505 # Number of instructions committed 487system.cpu0.committedOps 54116505 # Number of ops (including micro ops) committed 488system.cpu0.num_int_alu_accesses 50087098 # Number of integer alu accesses 489system.cpu0.num_fp_alu_accesses 302903 # Number of float alu accesses 490system.cpu0.num_func_calls 1426970 # number of times a function call or return occured 491system.cpu0.num_conditional_control_insts 6243728 # number of instructions that are conditional controls 492system.cpu0.num_int_insts 50087098 # number of integer instructions 493system.cpu0.num_fp_insts 302903 # number of float instructions 494system.cpu0.num_int_register_reads 68610814 # number of times the integer registers were read 495system.cpu0.num_int_register_writes 37122288 # number of times the integer registers were written 496system.cpu0.num_fp_register_reads 149298 # number of times the floating registers were read 497system.cpu0.num_fp_register_writes 152355 # number of times the floating registers were written 498system.cpu0.num_mem_refs 14741096 # number of memory refs 499system.cpu0.num_load_insts 8689646 # Number of load instructions 500system.cpu0.num_store_insts 6051450 # Number of store instructions 501system.cpu0.num_idle_cycles 3676817171.998126 # Number of idle cycles 502system.cpu0.num_busy_cycles 247298452.001874 # Number of busy cycles 503system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles 504system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles | 486system.cpu0.committedInsts 47719039 # Number of instructions committed 487system.cpu0.committedOps 47719039 # Number of ops (including micro ops) committed 488system.cpu0.num_int_alu_accesses 44257119 # Number of integer alu accesses 489system.cpu0.num_fp_alu_accesses 210954 # Number of float alu accesses 490system.cpu0.num_func_calls 1200899 # number of times a function call or return occured 491system.cpu0.num_conditional_control_insts 5607083 # number of instructions that are conditional controls 492system.cpu0.num_int_insts 44257119 # number of integer instructions 493system.cpu0.num_fp_insts 210954 # number of float instructions 494system.cpu0.num_int_register_reads 60839484 # number of times the integer registers were read 495system.cpu0.num_int_register_writes 32982631 # number of times the integer registers were written 496system.cpu0.num_fp_register_reads 102466 # number of times the floating registers were read 497system.cpu0.num_fp_register_writes 104326 # number of times the floating registers were written 498system.cpu0.num_mem_refs 12590587 # number of memory refs 499system.cpu0.num_load_insts 7513713 # Number of load instructions 500system.cpu0.num_store_insts 5076874 # Number of store instructions 501system.cpu0.num_idle_cycles 3701181001.496715 # Number of idle cycles 502system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles 503system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles 504system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles |
| 505system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 505system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 506system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed 507system.cpu0.kern.inst.hwrei 202757 # number of hwrei instructions executed 508system.cpu0.kern.ipl_count::0 72604 40.61% 40.61% # number of times we switched to this ipl 509system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl 510system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl 511system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl 512system.cpu0.kern.ipl_count::31 104050 58.20% 100.00% # number of times we switched to this ipl 513system.cpu0.kern.ipl_count::total 178770 # number of times we switched to this ipl 514system.cpu0.kern.ipl_good::0 71235 49.27% 49.27% # number of times we switched to this ipl from a different ipl 515system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl 516system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl 517system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl 518system.cpu0.kern.ipl_good::31 71229 49.27% 100.00% # number of times we switched to this ipl from a different ipl 519system.cpu0.kern.ipl_good::total 144580 # number of times we switched to this ipl from a different ipl 520system.cpu0.kern.ipl_ticks::0 1900688314000 96.87% 96.87% # number of cycles we spent at this ipl 521system.cpu0.kern.ipl_ticks::21 102511500 0.01% 96.88% # number of cycles we spent at this ipl 522system.cpu0.kern.ipl_ticks::22 795126500 0.04% 96.92% # number of cycles we spent at this ipl 523system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl 524system.cpu0.kern.ipl_ticks::31 60465450000 3.08% 100.00% # number of cycles we spent at this ipl 525system.cpu0.kern.ipl_ticks::total 1962056974000 # number of cycles we spent at this ipl 526system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl | 506system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed 507system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed 508system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl 509system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl 510system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl 511system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl 512system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl 513system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl 514system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl 515system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl 516system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl 517system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl 518system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl 519system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl 520system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl 521system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl 522system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl 523system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl 524system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl 525system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl 526system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl |
| 527system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 528system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 529system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 527system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 528system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 529system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 530system.cpu0.kern.ipl_used::31 0.684565 # fraction of swpipl calls that actually changed the ipl 531system.cpu0.kern.ipl_used::total 0.808749 # fraction of swpipl calls that actually changed the ipl 532system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed 533system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed 534system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed 535system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed 536system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed 537system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed 538system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed 539system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed 540system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed 541system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed 542system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed 543system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed 544system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed 545system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed 546system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed 547system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed 548system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed 549system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed 550system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed 551system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed 552system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed 553system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed 554system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed 555system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed 556system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed 557system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed 558system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed 559system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed 560system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed 561system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed 562system.cpu0.kern.syscall::total 224 # number of syscalls executed | 530system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl 531system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl 532system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 533system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 534system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 535system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 536system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 537system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 538system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 539system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 540system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 541system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 542system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 543system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 544system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 545system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 546system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 547system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 548system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 549system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 550system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 551system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 552system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 553system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 554system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 555system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 556system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 557system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 558system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 559system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 560system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 561system.cpu0.kern.syscall::total 222 # number of syscalls executed |
| 563system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 562system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 564system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed 565system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed 566system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed 567system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed 568system.cpu0.kern.callpal::swpctx 3872 2.06% 2.11% # number of callpals executed 569system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed 570system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed 571system.cpu0.kern.callpal::swpipl 171948 91.52% 93.66% # number of callpals executed 572system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed 573system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed 574system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed 575system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed 576system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed 577system.cpu0.kern.callpal::rti 4705 2.50% 99.73% # number of callpals executed 578system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed 579system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed 580system.cpu0.kern.callpal::total 187881 # number of callpals executed 581system.cpu0.kern.mode_switch::kernel 7233 # number of protection mode switches 582system.cpu0.kern.mode_switch::user 1235 # number of protection mode switches | 563system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed 564system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 565system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 566system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed 567system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed 568system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed 569system.cpu0.kern.callpal::wrent 7 0.00% 2.43% # number of callpals executed 570system.cpu0.kern.callpal::swpipl 134512 89.86% 92.29% # number of callpals executed 571system.cpu0.kern.callpal::rdps 6676 4.46% 96.75% # number of callpals executed 572system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed 573system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed 574system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed 575system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed 576system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed 577system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed 578system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed 579system.cpu0.kern.callpal::total 149688 # number of callpals executed 580system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches 581system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches |
| 583system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 582system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 584system.cpu0.kern.mode_good::kernel 1234 585system.cpu0.kern.mode_good::user 1235 | 583system.cpu0.kern.mode_good::kernel 1285 584system.cpu0.kern.mode_good::user 1285 |
| 586system.cpu0.kern.mode_good::idle 0 | 585system.cpu0.kern.mode_good::idle 0 |
| 587system.cpu0.kern.mode_switch_good::kernel 0.170607 # fraction of useful protection mode switches | 586system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches |
| 588system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 589system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 587system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 588system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 590system.cpu0.kern.mode_switch_good::total 0.291568 # fraction of useful protection mode switches 591system.cpu0.kern.mode_ticks::kernel 1958395542000 99.81% 99.81% # number of ticks spent at the given mode 592system.cpu0.kern.mode_ticks::user 3661425000 0.19% 100.00% # number of ticks spent at the given mode | 589system.cpu0.kern.mode_switch_good::total 0.314412 # fraction of useful protection mode switches 590system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode 591system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode |
| 593system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 592system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 594system.cpu0.kern.swap_context 3873 # number of times the context was actually changed | 593system.cpu0.kern.swap_context 3071 # number of times the context was actually changed |
| 595system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 596system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 597system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 598system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 599system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 600system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 601system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 602system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 618system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 619system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 620system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 621system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 622system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 623system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 624system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 625system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 594system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 595system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 596system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 597system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 598system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 599system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 600system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 601system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 617system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 618system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 619system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 620system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 621system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 622system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 623system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 624system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 626system.cpu0.icache.replacements 914851 # number of replacements 627system.cpu0.icache.tagsinuse 508.781994 # Cycle average of tags in use 628system.cpu0.icache.total_refs 53209789 # Total number of references to valid blocks. 629system.cpu0.icache.sampled_refs 915362 # Sample count of references to valid blocks. 630system.cpu0.icache.avg_refs 58.129777 # Average number of references to valid blocks. 631system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit. 632system.cpu0.icache.occ_blocks::cpu0.inst 508.781994 # Average occupied blocks per requestor 633system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy 634system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy 635system.cpu0.icache.ReadReq_hits::cpu0.inst 53209789 # number of ReadReq hits 636system.cpu0.icache.ReadReq_hits::total 53209789 # number of ReadReq hits 637system.cpu0.icache.demand_hits::cpu0.inst 53209789 # number of demand (read+write) hits 638system.cpu0.icache.demand_hits::total 53209789 # number of demand (read+write) hits 639system.cpu0.icache.overall_hits::cpu0.inst 53209789 # number of overall hits 640system.cpu0.icache.overall_hits::total 53209789 # number of overall hits 641system.cpu0.icache.ReadReq_misses::cpu0.inst 915491 # number of ReadReq misses 642system.cpu0.icache.ReadReq_misses::total 915491 # number of ReadReq misses 643system.cpu0.icache.demand_misses::cpu0.inst 915491 # number of demand (read+write) misses 644system.cpu0.icache.demand_misses::total 915491 # number of demand (read+write) misses 645system.cpu0.icache.overall_misses::cpu0.inst 915491 # number of overall misses 646system.cpu0.icache.overall_misses::total 915491 # number of overall misses 647system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13646549000 # number of ReadReq miss cycles 648system.cpu0.icache.ReadReq_miss_latency::total 13646549000 # number of ReadReq miss cycles 649system.cpu0.icache.demand_miss_latency::cpu0.inst 13646549000 # number of demand (read+write) miss cycles 650system.cpu0.icache.demand_miss_latency::total 13646549000 # number of demand (read+write) miss cycles 651system.cpu0.icache.overall_miss_latency::cpu0.inst 13646549000 # number of overall miss cycles 652system.cpu0.icache.overall_miss_latency::total 13646549000 # number of overall miss cycles 653system.cpu0.icache.ReadReq_accesses::cpu0.inst 54125280 # number of ReadReq accesses(hits+misses) 654system.cpu0.icache.ReadReq_accesses::total 54125280 # number of ReadReq accesses(hits+misses) 655system.cpu0.icache.demand_accesses::cpu0.inst 54125280 # number of demand (read+write) accesses 656system.cpu0.icache.demand_accesses::total 54125280 # number of demand (read+write) accesses 657system.cpu0.icache.overall_accesses::cpu0.inst 54125280 # number of overall (read+write) accesses 658system.cpu0.icache.overall_accesses::total 54125280 # number of overall (read+write) accesses 659system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016914 # miss rate for ReadReq accesses 660system.cpu0.icache.ReadReq_miss_rate::total 0.016914 # miss rate for ReadReq accesses 661system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016914 # miss rate for demand accesses 662system.cpu0.icache.demand_miss_rate::total 0.016914 # miss rate for demand accesses 663system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016914 # miss rate for overall accesses 664system.cpu0.icache.overall_miss_rate::total 0.016914 # miss rate for overall accesses 665system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323 # average ReadReq miss latency 666system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323 # average ReadReq miss latency 667system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency 668system.cpu0.icache.demand_avg_miss_latency::total 14906.262323 # average overall miss latency 669system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency 670system.cpu0.icache.overall_avg_miss_latency::total 14906.262323 # average overall miss latency | 625system.cpu0.icache.replacements 698187 # number of replacements 626system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use 627system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks. 628system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks. 629system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks. 630system.cpu0.icache.warmup_cycle 35739052000 # Cycle when the warmup percentage was hit. 631system.cpu0.icache.occ_blocks::cpu0.inst 508.830635 # Average occupied blocks per requestor 632system.cpu0.icache.occ_percent::cpu0.inst 0.993810 # Average percentage of cache occupancy 633system.cpu0.icache.occ_percent::total 0.993810 # Average percentage of cache occupancy 634system.cpu0.icache.ReadReq_hits::cpu0.inst 47028847 # number of ReadReq hits 635system.cpu0.icache.ReadReq_hits::total 47028847 # number of ReadReq hits 636system.cpu0.icache.demand_hits::cpu0.inst 47028847 # number of demand (read+write) hits 637system.cpu0.icache.demand_hits::total 47028847 # number of demand (read+write) hits 638system.cpu0.icache.overall_hits::cpu0.inst 47028847 # number of overall hits 639system.cpu0.icache.overall_hits::total 47028847 # number of overall hits 640system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses 641system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses 642system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses 643system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses 644system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses 645system.cpu0.icache.overall_misses::total 698792 # number of overall misses 646system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9694162500 # number of ReadReq miss cycles 647system.cpu0.icache.ReadReq_miss_latency::total 9694162500 # number of ReadReq miss cycles 648system.cpu0.icache.demand_miss_latency::cpu0.inst 9694162500 # number of demand (read+write) miss cycles 649system.cpu0.icache.demand_miss_latency::total 9694162500 # number of demand (read+write) miss cycles 650system.cpu0.icache.overall_miss_latency::cpu0.inst 9694162500 # number of overall miss cycles 651system.cpu0.icache.overall_miss_latency::total 9694162500 # number of overall miss cycles 652system.cpu0.icache.ReadReq_accesses::cpu0.inst 47727639 # number of ReadReq accesses(hits+misses) 653system.cpu0.icache.ReadReq_accesses::total 47727639 # number of ReadReq accesses(hits+misses) 654system.cpu0.icache.demand_accesses::cpu0.inst 47727639 # number of demand (read+write) accesses 655system.cpu0.icache.demand_accesses::total 47727639 # number of demand (read+write) accesses 656system.cpu0.icache.overall_accesses::cpu0.inst 47727639 # number of overall (read+write) accesses 657system.cpu0.icache.overall_accesses::total 47727639 # number of overall (read+write) accesses 658system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014641 # miss rate for ReadReq accesses 659system.cpu0.icache.ReadReq_miss_rate::total 0.014641 # miss rate for ReadReq accesses 660system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014641 # miss rate for demand accesses 661system.cpu0.icache.demand_miss_rate::total 0.014641 # miss rate for demand accesses 662system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014641 # miss rate for overall accesses 663system.cpu0.icache.overall_miss_rate::total 0.014641 # miss rate for overall accesses 664system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13872.743964 # average ReadReq miss latency 665system.cpu0.icache.ReadReq_avg_miss_latency::total 13872.743964 # average ReadReq miss latency 666system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency 667system.cpu0.icache.demand_avg_miss_latency::total 13872.743964 # average overall miss latency 668system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13872.743964 # average overall miss latency 669system.cpu0.icache.overall_avg_miss_latency::total 13872.743964 # average overall miss latency |
| 671system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 672system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 673system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 674system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 675system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 676system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 677system.cpu0.icache.fast_writes 0 # number of fast writes performed 678system.cpu0.icache.cache_copies 0 # number of cache copies performed | 670system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 671system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 672system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 673system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 674system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 675system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 676system.cpu0.icache.fast_writes 0 # number of fast writes performed 677system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 679system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915491 # number of ReadReq MSHR misses 680system.cpu0.icache.ReadReq_mshr_misses::total 915491 # number of ReadReq MSHR misses 681system.cpu0.icache.demand_mshr_misses::cpu0.inst 915491 # number of demand (read+write) MSHR misses 682system.cpu0.icache.demand_mshr_misses::total 915491 # number of demand (read+write) MSHR misses 683system.cpu0.icache.overall_mshr_misses::cpu0.inst 915491 # number of overall MSHR misses 684system.cpu0.icache.overall_mshr_misses::total 915491 # number of overall MSHR misses 685system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10899382500 # number of ReadReq MSHR miss cycles 686system.cpu0.icache.ReadReq_mshr_miss_latency::total 10899382500 # number of ReadReq MSHR miss cycles 687system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10899382500 # number of demand (read+write) MSHR miss cycles 688system.cpu0.icache.demand_mshr_miss_latency::total 10899382500 # number of demand (read+write) MSHR miss cycles 689system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10899382500 # number of overall MSHR miss cycles 690system.cpu0.icache.overall_mshr_miss_latency::total 10899382500 # number of overall MSHR miss cycles 691system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for ReadReq accesses 692system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016914 # mshr miss rate for ReadReq accesses 693system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for demand accesses 694system.cpu0.icache.demand_mshr_miss_rate::total 0.016914 # mshr miss rate for demand accesses 695system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016914 # mshr miss rate for overall accesses 696system.cpu0.icache.overall_mshr_miss_rate::total 0.016914 # mshr miss rate for overall accesses 697system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average ReadReq mshr miss latency 698system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.504806 # average ReadReq mshr miss latency 699system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency 700system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency 701system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11905.504806 # average overall mshr miss latency 702system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.504806 # average overall mshr miss latency | 678system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses 679system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses 680system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses 681system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses 682system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses 683system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses 684system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8296578500 # number of ReadReq MSHR miss cycles 685system.cpu0.icache.ReadReq_mshr_miss_latency::total 8296578500 # number of ReadReq MSHR miss cycles 686system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8296578500 # number of demand (read+write) MSHR miss cycles 687system.cpu0.icache.demand_mshr_miss_latency::total 8296578500 # number of demand (read+write) MSHR miss cycles 688system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8296578500 # number of overall MSHR miss cycles 689system.cpu0.icache.overall_mshr_miss_latency::total 8296578500 # number of overall MSHR miss cycles 690system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for ReadReq accesses 691system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014641 # mshr miss rate for ReadReq accesses 692system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for demand accesses 693system.cpu0.icache.demand_mshr_miss_rate::total 0.014641 # mshr miss rate for demand accesses 694system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014641 # mshr miss rate for overall accesses 695system.cpu0.icache.overall_mshr_miss_rate::total 0.014641 # mshr miss rate for overall accesses 696system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average ReadReq mshr miss latency 697system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11872.743964 # average ReadReq mshr miss latency 698system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency 699system.cpu0.icache.demand_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency 700system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11872.743964 # average overall mshr miss latency 701system.cpu0.icache.overall_avg_mshr_miss_latency::total 11872.743964 # average overall mshr miss latency |
| 703system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 702system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 704system.cpu0.dcache.replacements 1337819 # number of replacements 705system.cpu0.dcache.tagsinuse 506.532892 # Cycle average of tags in use 706system.cpu0.dcache.total_refs 13370103 # Total number of references to valid blocks. 707system.cpu0.dcache.sampled_refs 1338331 # Sample count of references to valid blocks. 708system.cpu0.dcache.avg_refs 9.990132 # Average number of references to valid blocks. 709system.cpu0.dcache.warmup_cycle 101834000 # Cycle when the warmup percentage was hit. 710system.cpu0.dcache.occ_blocks::cpu0.data 506.532892 # Average occupied blocks per requestor 711system.cpu0.dcache.occ_percent::cpu0.data 0.989322 # Average percentage of cache occupancy 712system.cpu0.dcache.occ_percent::total 0.989322 # Average percentage of cache occupancy 713system.cpu0.dcache.ReadReq_hits::cpu0.data 7444463 # number of ReadReq hits 714system.cpu0.dcache.ReadReq_hits::total 7444463 # number of ReadReq hits 715system.cpu0.dcache.WriteReq_hits::cpu0.data 5554933 # number of WriteReq hits 716system.cpu0.dcache.WriteReq_hits::total 5554933 # number of WriteReq hits 717system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 175817 # number of LoadLockedReq hits 718system.cpu0.dcache.LoadLockedReq_hits::total 175817 # number of LoadLockedReq hits 719system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191182 # number of StoreCondReq hits 720system.cpu0.dcache.StoreCondReq_hits::total 191182 # number of StoreCondReq hits 721system.cpu0.dcache.demand_hits::cpu0.data 12999396 # number of demand (read+write) hits 722system.cpu0.dcache.demand_hits::total 12999396 # number of demand (read+write) hits 723system.cpu0.dcache.overall_hits::cpu0.data 12999396 # number of overall hits 724system.cpu0.dcache.overall_hits::total 12999396 # number of overall hits 725system.cpu0.dcache.ReadReq_misses::cpu0.data 1037635 # number of ReadReq misses 726system.cpu0.dcache.ReadReq_misses::total 1037635 # number of ReadReq misses 727system.cpu0.dcache.WriteReq_misses::cpu0.data 289296 # number of WriteReq misses 728system.cpu0.dcache.WriteReq_misses::total 289296 # number of WriteReq misses 729system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16772 # number of LoadLockedReq misses 730system.cpu0.dcache.LoadLockedReq_misses::total 16772 # number of LoadLockedReq misses 731system.cpu0.dcache.StoreCondReq_misses::cpu0.data 445 # number of StoreCondReq misses 732system.cpu0.dcache.StoreCondReq_misses::total 445 # number of StoreCondReq misses 733system.cpu0.dcache.demand_misses::cpu0.data 1326931 # number of demand (read+write) misses 734system.cpu0.dcache.demand_misses::total 1326931 # number of demand (read+write) misses 735system.cpu0.dcache.overall_misses::cpu0.data 1326931 # number of overall misses 736system.cpu0.dcache.overall_misses::total 1326931 # number of overall misses 737system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26113637000 # number of ReadReq miss cycles 738system.cpu0.dcache.ReadReq_miss_latency::total 26113637000 # number of ReadReq miss cycles 739system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8963228000 # number of WriteReq miss cycles 740system.cpu0.dcache.WriteReq_miss_latency::total 8963228000 # number of WriteReq miss cycles 741system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 238633000 # number of LoadLockedReq miss cycles 742system.cpu0.dcache.LoadLockedReq_miss_latency::total 238633000 # number of LoadLockedReq miss cycles 743system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4867000 # number of StoreCondReq miss cycles 744system.cpu0.dcache.StoreCondReq_miss_latency::total 4867000 # number of StoreCondReq miss cycles 745system.cpu0.dcache.demand_miss_latency::cpu0.data 35076865000 # number of demand (read+write) miss cycles 746system.cpu0.dcache.demand_miss_latency::total 35076865000 # number of demand (read+write) miss cycles 747system.cpu0.dcache.overall_miss_latency::cpu0.data 35076865000 # number of overall miss cycles 748system.cpu0.dcache.overall_miss_latency::total 35076865000 # number of overall miss cycles 749system.cpu0.dcache.ReadReq_accesses::cpu0.data 8482098 # number of ReadReq accesses(hits+misses) 750system.cpu0.dcache.ReadReq_accesses::total 8482098 # number of ReadReq accesses(hits+misses) 751system.cpu0.dcache.WriteReq_accesses::cpu0.data 5844229 # number of WriteReq accesses(hits+misses) 752system.cpu0.dcache.WriteReq_accesses::total 5844229 # number of WriteReq accesses(hits+misses) 753system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 192589 # number of LoadLockedReq accesses(hits+misses) 754system.cpu0.dcache.LoadLockedReq_accesses::total 192589 # number of LoadLockedReq accesses(hits+misses) 755system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191627 # number of StoreCondReq accesses(hits+misses) 756system.cpu0.dcache.StoreCondReq_accesses::total 191627 # number of StoreCondReq accesses(hits+misses) 757system.cpu0.dcache.demand_accesses::cpu0.data 14326327 # number of demand (read+write) accesses 758system.cpu0.dcache.demand_accesses::total 14326327 # number of demand (read+write) accesses 759system.cpu0.dcache.overall_accesses::cpu0.data 14326327 # number of overall (read+write) accesses 760system.cpu0.dcache.overall_accesses::total 14326327 # number of overall (read+write) accesses 761system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122332 # miss rate for ReadReq accesses 762system.cpu0.dcache.ReadReq_miss_rate::total 0.122332 # miss rate for ReadReq accesses 763system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049501 # miss rate for WriteReq accesses 764system.cpu0.dcache.WriteReq_miss_rate::total 0.049501 # miss rate for WriteReq accesses 765system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087087 # miss rate for LoadLockedReq accesses 766system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087087 # miss rate for LoadLockedReq accesses 767system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002322 # miss rate for StoreCondReq accesses 768system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002322 # miss rate for StoreCondReq accesses 769system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092622 # miss rate for demand accesses 770system.cpu0.dcache.demand_miss_rate::total 0.092622 # miss rate for demand accesses 771system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092622 # miss rate for overall accesses 772system.cpu0.dcache.overall_miss_rate::total 0.092622 # miss rate for overall accesses 773system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.495926 # average ReadReq miss latency 774system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.495926 # average ReadReq miss latency 775system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30982.896411 # average WriteReq miss latency 776system.cpu0.dcache.WriteReq_avg_miss_latency::total 30982.896411 # average WriteReq miss latency 777system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14228.058669 # average LoadLockedReq miss latency 778system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14228.058669 # average LoadLockedReq miss latency 779system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10937.078652 # average StoreCondReq miss latency 780system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10937.078652 # average StoreCondReq miss latency 781system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency 782system.cpu0.dcache.demand_avg_miss_latency::total 26434.580999 # average overall miss latency 783system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26434.580999 # average overall miss latency 784system.cpu0.dcache.overall_avg_miss_latency::total 26434.580999 # average overall miss latency | 703system.cpu0.dcache.replacements 1180402 # number of replacements 704system.cpu0.dcache.tagsinuse 505.183019 # Cycle average of tags in use 705system.cpu0.dcache.total_refs 11360683 # Total number of references to valid blocks. 706system.cpu0.dcache.sampled_refs 1180820 # Sample count of references to valid blocks. 707system.cpu0.dcache.avg_refs 9.621012 # Average number of references to valid blocks. 708system.cpu0.dcache.warmup_cycle 99461000 # Cycle when the warmup percentage was hit. 709system.cpu0.dcache.occ_blocks::cpu0.data 505.183019 # Average occupied blocks per requestor 710system.cpu0.dcache.occ_percent::cpu0.data 0.986686 # Average percentage of cache occupancy 711system.cpu0.dcache.occ_percent::total 0.986686 # Average percentage of cache occupancy 712system.cpu0.dcache.ReadReq_hits::cpu0.data 6406782 # number of ReadReq hits 713system.cpu0.dcache.ReadReq_hits::total 6406782 # number of ReadReq hits 714system.cpu0.dcache.WriteReq_hits::cpu0.data 4655760 # number of WriteReq hits 715system.cpu0.dcache.WriteReq_hits::total 4655760 # number of WriteReq hits 716system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140286 # number of LoadLockedReq hits 717system.cpu0.dcache.LoadLockedReq_hits::total 140286 # number of LoadLockedReq hits 718system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147915 # number of StoreCondReq hits 719system.cpu0.dcache.StoreCondReq_hits::total 147915 # number of StoreCondReq hits 720system.cpu0.dcache.demand_hits::cpu0.data 11062542 # number of demand (read+write) hits 721system.cpu0.dcache.demand_hits::total 11062542 # number of demand (read+write) hits 722system.cpu0.dcache.overall_hits::cpu0.data 11062542 # number of overall hits 723system.cpu0.dcache.overall_hits::total 11062542 # number of overall hits 724system.cpu0.dcache.ReadReq_misses::cpu0.data 938249 # number of ReadReq misses 725system.cpu0.dcache.ReadReq_misses::total 938249 # number of ReadReq misses 726system.cpu0.dcache.WriteReq_misses::cpu0.data 251643 # number of WriteReq misses 727system.cpu0.dcache.WriteReq_misses::total 251643 # number of WriteReq misses 728system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13638 # number of LoadLockedReq misses 729system.cpu0.dcache.LoadLockedReq_misses::total 13638 # number of LoadLockedReq misses 730system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5458 # number of StoreCondReq misses 731system.cpu0.dcache.StoreCondReq_misses::total 5458 # number of StoreCondReq misses 732system.cpu0.dcache.demand_misses::cpu0.data 1189892 # number of demand (read+write) misses 733system.cpu0.dcache.demand_misses::total 1189892 # number of demand (read+write) misses 734system.cpu0.dcache.overall_misses::cpu0.data 1189892 # number of overall misses 735system.cpu0.dcache.overall_misses::total 1189892 # number of overall misses 736system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23522563000 # number of ReadReq miss cycles 737system.cpu0.dcache.ReadReq_miss_latency::total 23522563000 # number of ReadReq miss cycles 738system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8201327000 # number of WriteReq miss cycles 739system.cpu0.dcache.WriteReq_miss_latency::total 8201327000 # number of WriteReq miss cycles 740system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 147906000 # number of LoadLockedReq miss cycles 741system.cpu0.dcache.LoadLockedReq_miss_latency::total 147906000 # number of LoadLockedReq miss cycles 742system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 67796500 # number of StoreCondReq miss cycles 743system.cpu0.dcache.StoreCondReq_miss_latency::total 67796500 # number of StoreCondReq miss cycles 744system.cpu0.dcache.demand_miss_latency::cpu0.data 31723890000 # number of demand (read+write) miss cycles 745system.cpu0.dcache.demand_miss_latency::total 31723890000 # number of demand (read+write) miss cycles 746system.cpu0.dcache.overall_miss_latency::cpu0.data 31723890000 # number of overall miss cycles 747system.cpu0.dcache.overall_miss_latency::total 31723890000 # number of overall miss cycles 748system.cpu0.dcache.ReadReq_accesses::cpu0.data 7345031 # number of ReadReq accesses(hits+misses) 749system.cpu0.dcache.ReadReq_accesses::total 7345031 # number of ReadReq accesses(hits+misses) 750system.cpu0.dcache.WriteReq_accesses::cpu0.data 4907403 # number of WriteReq accesses(hits+misses) 751system.cpu0.dcache.WriteReq_accesses::total 4907403 # number of WriteReq accesses(hits+misses) 752system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 153924 # number of LoadLockedReq accesses(hits+misses) 753system.cpu0.dcache.LoadLockedReq_accesses::total 153924 # number of LoadLockedReq accesses(hits+misses) 754system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153373 # number of StoreCondReq accesses(hits+misses) 755system.cpu0.dcache.StoreCondReq_accesses::total 153373 # number of StoreCondReq accesses(hits+misses) 756system.cpu0.dcache.demand_accesses::cpu0.data 12252434 # number of demand (read+write) accesses 757system.cpu0.dcache.demand_accesses::total 12252434 # number of demand (read+write) accesses 758system.cpu0.dcache.overall_accesses::cpu0.data 12252434 # number of overall (read+write) accesses 759system.cpu0.dcache.overall_accesses::total 12252434 # number of overall (read+write) accesses 760system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127739 # miss rate for ReadReq accesses 761system.cpu0.dcache.ReadReq_miss_rate::total 0.127739 # miss rate for ReadReq accesses 762system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051278 # miss rate for WriteReq accesses 763system.cpu0.dcache.WriteReq_miss_rate::total 0.051278 # miss rate for WriteReq accesses 764system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088602 # miss rate for LoadLockedReq accesses 765system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088602 # miss rate for LoadLockedReq accesses 766system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035586 # miss rate for StoreCondReq accesses 767system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035586 # miss rate for StoreCondReq accesses 768system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097115 # miss rate for demand accesses 769system.cpu0.dcache.demand_miss_rate::total 0.097115 # miss rate for demand accesses 770system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097115 # miss rate for overall accesses 771system.cpu0.dcache.overall_miss_rate::total 0.097115 # miss rate for overall accesses 772system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25070.704046 # average ReadReq miss latency 773system.cpu0.dcache.ReadReq_avg_miss_latency::total 25070.704046 # average ReadReq miss latency 774system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32591.119165 # average WriteReq miss latency 775system.cpu0.dcache.WriteReq_avg_miss_latency::total 32591.119165 # average WriteReq miss latency 776system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10845.138583 # average LoadLockedReq miss latency 777system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10845.138583 # average LoadLockedReq miss latency 778system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12421.491389 # average StoreCondReq miss latency 779system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12421.491389 # average StoreCondReq miss latency 780system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency 781system.cpu0.dcache.demand_avg_miss_latency::total 26661.150760 # average overall miss latency 782system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency 783system.cpu0.dcache.overall_avg_miss_latency::total 26661.150760 # average overall miss latency |
| 785system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 786system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 787system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 788system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 789system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 790system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 791system.cpu0.dcache.fast_writes 0 # number of fast writes performed 792system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 784system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 785system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 786system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 787system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 788system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 789system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.cpu0.dcache.fast_writes 0 # number of fast writes performed 791system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 793system.cpu0.dcache.writebacks::writebacks 785166 # number of writebacks 794system.cpu0.dcache.writebacks::total 785166 # number of writebacks 795system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037635 # number of ReadReq MSHR misses 796system.cpu0.dcache.ReadReq_mshr_misses::total 1037635 # number of ReadReq MSHR misses 797system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289296 # number of WriteReq MSHR misses 798system.cpu0.dcache.WriteReq_mshr_misses::total 289296 # number of WriteReq MSHR misses 799system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16772 # number of LoadLockedReq MSHR misses 800system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16772 # number of LoadLockedReq MSHR misses 801system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 445 # number of StoreCondReq MSHR misses 802system.cpu0.dcache.StoreCondReq_mshr_misses::total 445 # number of StoreCondReq MSHR misses 803system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326931 # number of demand (read+write) MSHR misses 804system.cpu0.dcache.demand_mshr_misses::total 1326931 # number of demand (read+write) MSHR misses 805system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326931 # number of overall MSHR misses 806system.cpu0.dcache.overall_mshr_misses::total 1326931 # number of overall MSHR misses 807system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000669022 # number of ReadReq MSHR miss cycles 808system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000669022 # number of ReadReq MSHR miss cycles 809system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8095339001 # number of WriteReq MSHR miss cycles 810system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8095339001 # number of WriteReq MSHR miss cycles 811system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188317000 # number of LoadLockedReq MSHR miss cycles 812system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188317000 # number of LoadLockedReq MSHR miss cycles 813system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3531001 # number of StoreCondReq MSHR miss cycles 814system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3531001 # number of StoreCondReq MSHR miss cycles 815system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096008023 # number of demand (read+write) MSHR miss cycles 816system.cpu0.dcache.demand_mshr_miss_latency::total 31096008023 # number of demand (read+write) MSHR miss cycles 817system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096008023 # number of overall MSHR miss cycles 818system.cpu0.dcache.overall_mshr_miss_latency::total 31096008023 # number of overall MSHR miss cycles 819system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461823000 # number of ReadReq MSHR uncacheable cycles 820system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461823000 # number of ReadReq MSHR uncacheable cycles 821system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2088243000 # number of WriteReq MSHR uncacheable cycles 822system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2088243000 # number of WriteReq MSHR uncacheable cycles 823system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3550066000 # number of overall MSHR uncacheable cycles 824system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3550066000 # number of overall MSHR uncacheable cycles 825system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122332 # mshr miss rate for ReadReq accesses 826system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122332 # mshr miss rate for ReadReq accesses 827system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049501 # mshr miss rate for WriteReq accesses 828system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049501 # mshr miss rate for WriteReq accesses 829system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087087 # mshr miss rate for LoadLockedReq accesses 830system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087087 # mshr miss rate for LoadLockedReq accesses 831system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002322 # mshr miss rate for StoreCondReq accesses 832system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002322 # mshr miss rate for StoreCondReq accesses 833system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses 834system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses 835system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses 836system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses 837system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.435232 # average ReadReq mshr miss latency 838system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.435232 # average ReadReq mshr miss latency 839system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27982.892957 # average WriteReq mshr miss latency 840system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27982.892957 # average WriteReq mshr miss latency 841system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11228.058669 # average LoadLockedReq mshr miss latency 842system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11228.058669 # average LoadLockedReq mshr miss latency 843system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7934.833708 # average StoreCondReq mshr miss latency 844system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7934.833708 # average StoreCondReq mshr miss latency 845system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency 846system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency 847system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency 848system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency | 792system.cpu0.dcache.writebacks::writebacks 679069 # number of writebacks 793system.cpu0.dcache.writebacks::total 679069 # number of writebacks 794system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938249 # number of ReadReq MSHR misses 795system.cpu0.dcache.ReadReq_mshr_misses::total 938249 # number of ReadReq MSHR misses 796system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251643 # number of WriteReq MSHR misses 797system.cpu0.dcache.WriteReq_mshr_misses::total 251643 # number of WriteReq MSHR misses 798system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13638 # number of LoadLockedReq MSHR misses 799system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13638 # number of LoadLockedReq MSHR misses 800system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5458 # number of StoreCondReq MSHR misses 801system.cpu0.dcache.StoreCondReq_mshr_misses::total 5458 # number of StoreCondReq MSHR misses 802system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189892 # number of demand (read+write) MSHR misses 803system.cpu0.dcache.demand_mshr_misses::total 1189892 # number of demand (read+write) MSHR misses 804system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189892 # number of overall MSHR misses 805system.cpu0.dcache.overall_mshr_misses::total 1189892 # number of overall MSHR misses 806system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21646065000 # number of ReadReq MSHR miss cycles 807system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21646065000 # number of ReadReq MSHR miss cycles 808system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7698041000 # number of WriteReq MSHR miss cycles 809system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7698041000 # number of WriteReq MSHR miss cycles 810system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 120630000 # number of LoadLockedReq MSHR miss cycles 811system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 120630000 # number of LoadLockedReq MSHR miss cycles 812system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56880500 # number of StoreCondReq MSHR miss cycles 813system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56880500 # number of StoreCondReq MSHR miss cycles 814system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29344106000 # number of demand (read+write) MSHR miss cycles 815system.cpu0.dcache.demand_mshr_miss_latency::total 29344106000 # number of demand (read+write) MSHR miss cycles 816system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 29344106000 # number of overall MSHR miss cycles 817system.cpu0.dcache.overall_mshr_miss_latency::total 29344106000 # number of overall MSHR miss cycles 818system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465334500 # number of ReadReq MSHR uncacheable cycles 819system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465334500 # number of ReadReq MSHR uncacheable cycles 820system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2275733500 # number of WriteReq MSHR uncacheable cycles 821system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2275733500 # number of WriteReq MSHR uncacheable cycles 822system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3741068000 # number of overall MSHR uncacheable cycles 823system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3741068000 # number of overall MSHR uncacheable cycles 824system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127739 # mshr miss rate for ReadReq accesses 825system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127739 # mshr miss rate for ReadReq accesses 826system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051278 # mshr miss rate for WriteReq accesses 827system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051278 # mshr miss rate for WriteReq accesses 828system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088602 # mshr miss rate for LoadLockedReq accesses 829system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088602 # mshr miss rate for LoadLockedReq accesses 830system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035586 # mshr miss rate for StoreCondReq accesses 831system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035586 # mshr miss rate for StoreCondReq accesses 832system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for demand accesses 833system.cpu0.dcache.demand_mshr_miss_rate::total 0.097115 # mshr miss rate for demand accesses 834system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for overall accesses 835system.cpu0.dcache.overall_mshr_miss_rate::total 0.097115 # mshr miss rate for overall accesses 836system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23070.704046 # average ReadReq mshr miss latency 837system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 23070.704046 # average ReadReq mshr miss latency 838system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30591.119165 # average WriteReq mshr miss latency 839system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency 840system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency 841system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency 842system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency 843system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency 844system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency 845system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency 846system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency 847system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency |
| 849system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 850system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 851system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 852system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 853system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 854system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 855system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 856system.cpu1.dtb.fetch_hits 0 # ITB hits 857system.cpu1.dtb.fetch_misses 0 # ITB misses 858system.cpu1.dtb.fetch_acv 0 # ITB acv 859system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 848system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 849system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 850system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 851system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 852system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 853system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 854system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 855system.cpu1.dtb.fetch_hits 0 # ITB hits 856system.cpu1.dtb.fetch_misses 0 # ITB misses 857system.cpu1.dtb.fetch_acv 0 # ITB acv 858system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 860system.cpu1.dtb.read_hits 1027530 # DTB read hits 861system.cpu1.dtb.read_misses 2750 # DTB read misses 862system.cpu1.dtb.read_acv 36 # DTB read access violations 863system.cpu1.dtb.read_accesses 205838 # DTB read accesses 864system.cpu1.dtb.write_hits 663193 # DTB write hits 865system.cpu1.dtb.write_misses 356 # DTB write misses 866system.cpu1.dtb.write_acv 48 # DTB write access violations 867system.cpu1.dtb.write_accesses 97040 # DTB write accesses 868system.cpu1.dtb.data_hits 1690723 # DTB hits 869system.cpu1.dtb.data_misses 3106 # DTB misses 870system.cpu1.dtb.data_acv 84 # DTB access violations 871system.cpu1.dtb.data_accesses 302878 # DTB accesses 872system.cpu1.itb.fetch_hits 1394871 # ITB hits 873system.cpu1.itb.fetch_misses 1246 # ITB misses 874system.cpu1.itb.fetch_acv 41 # ITB acv 875system.cpu1.itb.fetch_accesses 1396117 # ITB accesses | 859system.cpu1.dtb.read_hits 2425080 # DTB read hits 860system.cpu1.dtb.read_misses 2992 # DTB read misses 861system.cpu1.dtb.read_acv 0 # DTB read access violations 862system.cpu1.dtb.read_accesses 239363 # DTB read accesses 863system.cpu1.dtb.write_hits 1761000 # DTB write hits 864system.cpu1.dtb.write_misses 341 # DTB write misses 865system.cpu1.dtb.write_acv 29 # DTB write access violations 866system.cpu1.dtb.write_accesses 105247 # DTB write accesses 867system.cpu1.dtb.data_hits 4186080 # DTB hits 868system.cpu1.dtb.data_misses 3333 # DTB misses 869system.cpu1.dtb.data_acv 29 # DTB access violations 870system.cpu1.dtb.data_accesses 344610 # DTB accesses 871system.cpu1.itb.fetch_hits 1964871 # ITB hits 872system.cpu1.itb.fetch_misses 1216 # ITB misses 873system.cpu1.itb.fetch_acv 0 # ITB acv 874system.cpu1.itb.fetch_accesses 1966087 # ITB accesses |
| 876system.cpu1.itb.read_hits 0 # DTB read hits 877system.cpu1.itb.read_misses 0 # DTB read misses 878system.cpu1.itb.read_acv 0 # DTB read access violations 879system.cpu1.itb.read_accesses 0 # DTB read accesses 880system.cpu1.itb.write_hits 0 # DTB write hits 881system.cpu1.itb.write_misses 0 # DTB write misses 882system.cpu1.itb.write_acv 0 # DTB write access violations 883system.cpu1.itb.write_accesses 0 # DTB write accesses 884system.cpu1.itb.data_hits 0 # DTB hits 885system.cpu1.itb.data_misses 0 # DTB misses 886system.cpu1.itb.data_acv 0 # DTB access violations 887system.cpu1.itb.data_accesses 0 # DTB accesses | 875system.cpu1.itb.read_hits 0 # DTB read hits 876system.cpu1.itb.read_misses 0 # DTB read misses 877system.cpu1.itb.read_acv 0 # DTB read access violations 878system.cpu1.itb.read_accesses 0 # DTB read accesses 879system.cpu1.itb.write_hits 0 # DTB write hits 880system.cpu1.itb.write_misses 0 # DTB write misses 881system.cpu1.itb.write_acv 0 # DTB write access violations 882system.cpu1.itb.write_accesses 0 # DTB write accesses 883system.cpu1.itb.data_hits 0 # DTB hits 884system.cpu1.itb.data_misses 0 # DTB misses 885system.cpu1.itb.data_acv 0 # DTB access violations 886system.cpu1.itb.data_accesses 0 # DTB accesses |
| 888system.cpu1.numCycles 3923836552 # number of cpu cycles simulated | 887system.cpu1.numCycles 3911492481 # number of cpu cycles simulated |
| 889system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 890system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 888system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 889system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 891system.cpu1.committedInsts 5254013 # Number of instructions committed 892system.cpu1.committedOps 5254013 # Number of ops (including micro ops) committed 893system.cpu1.num_int_alu_accesses 4921025 # Number of integer alu accesses 894system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses 895system.cpu1.num_func_calls 157600 # number of times a function call or return occured 896system.cpu1.num_conditional_control_insts 506865 # number of instructions that are conditional controls 897system.cpu1.num_int_insts 4921025 # number of integer instructions 898system.cpu1.num_fp_insts 25430 # number of float instructions 899system.cpu1.num_int_register_reads 6827399 # number of times the integer registers were read 900system.cpu1.num_int_register_writes 3700117 # number of times the integer registers were written 901system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read 902system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written 903system.cpu1.num_mem_refs 1700348 # number of memory refs 904system.cpu1.num_load_insts 1033584 # Number of load instructions 905system.cpu1.num_store_insts 666764 # Number of store instructions 906system.cpu1.num_idle_cycles 3903107404.303190 # Number of idle cycles 907system.cpu1.num_busy_cycles 20729147.696810 # Number of busy cycles 908system.cpu1.not_idle_fraction 0.005283 # Percentage of non-idle cycles 909system.cpu1.idle_fraction 0.994717 # Percentage of idle cycles | 890system.cpu1.committedInsts 13183934 # Number of instructions committed 891system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed 892system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses 893system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses 894system.cpu1.num_func_calls 412685 # number of times a function call or return occured 895system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls 896system.cpu1.num_int_insts 12160396 # number of integer instructions 897system.cpu1.num_fp_insts 172922 # number of float instructions 898system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read 899system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written 900system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read 901system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written 902system.cpu1.num_mem_refs 4209624 # number of memory refs 903system.cpu1.num_load_insts 2439377 # Number of load instructions 904system.cpu1.num_store_insts 1770247 # Number of store instructions 905system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles 906system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles 907system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles 908system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles |
| 910system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 909system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 911system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed 912system.cpu1.kern.inst.hwrei 35942 # number of hwrei instructions executed 913system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl 914system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl 915system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl 916system.cpu1.kern.ipl_count::31 17499 60.96% 100.00% # number of times we switched to this ipl 917system.cpu1.kern.ipl_count::total 28706 # number of times we switched to this ipl 918system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl 919system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl 920system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl 921system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl 922system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl 923system.cpu1.kern.ipl_ticks::0 1920766593500 97.90% 97.90% # number of cycles we spent at this ipl 924system.cpu1.kern.ipl_ticks::22 726074500 0.04% 97.94% # number of cycles we spent at this ipl 925system.cpu1.kern.ipl_ticks::30 67017000 0.00% 97.94% # number of cycles we spent at this ipl 926system.cpu1.kern.ipl_ticks::31 40358561000 2.06% 100.00% # number of cycles we spent at this ipl 927system.cpu1.kern.ipl_ticks::total 1961918246000 # number of cycles we spent at this ipl 928system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl | 910system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed 911system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed 912system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl 913system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl 914system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl 915system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl 916system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl 917system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl 918system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl 919system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl 920system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl 921system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl 922system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl 923system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl 924system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl 925system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl 926system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl 927system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl |
| 929system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 930system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 928system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 929system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 931system.cpu1.kern.ipl_used::31 0.516830 # fraction of swpipl calls that actually changed the ipl 932system.cpu1.kern.ipl_used::total 0.705184 # fraction of swpipl calls that actually changed the ipl 933system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed 934system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed 935system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed 936system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed 937system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed 938system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed 939system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed 940system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed 941system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed 942system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed 943system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed 944system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed 945system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed 946system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed 947system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed 948system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed 949system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed 950system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed 951system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed 952system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed 953system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed 954system.cpu1.kern.syscall::total 102 # number of syscalls executed | 930system.cpu1.kern.ipl_used::31 0.627296 # fraction of swpipl calls that actually changed the ipl 931system.cpu1.kern.ipl_used::total 0.771460 # fraction of swpipl calls that actually changed the ipl 932system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 933system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 934system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 935system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 936system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 937system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 938system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 939system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 940system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 941system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 942system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 943system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 944system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 945system.cpu1.kern.syscall::total 104 # number of syscalls executed |
| 955system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 946system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 956system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed 957system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 958system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 959system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed 960system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed 961system.cpu1.kern.callpal::wrent 7 0.02% 1.33% # number of callpals executed 962system.cpu1.kern.callpal::swpipl 24054 81.82% 83.15% # number of callpals executed 963system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed 964system.cpu1.kern.callpal::wrkgp 1 0.00% 90.52% # number of callpals executed 965system.cpu1.kern.callpal::wrusp 3 0.01% 90.53% # number of callpals executed 966system.cpu1.kern.callpal::rdusp 2 0.01% 90.53% # number of callpals executed 967system.cpu1.kern.callpal::whami 3 0.01% 90.54% # number of callpals executed 968system.cpu1.kern.callpal::rti 2587 8.80% 99.34% # number of callpals executed 969system.cpu1.kern.callpal::callsys 161 0.55% 99.89% # number of callpals executed 970system.cpu1.kern.callpal::imb 31 0.11% 100.00% # number of callpals executed | 947system.cpu1.kern.callpal::wripir 420 0.59% 0.59% # number of callpals executed 948system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 949system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 950system.cpu1.kern.callpal::swpctx 1995 2.79% 3.38% # number of callpals executed 951system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed 952system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed 953system.cpu1.kern.callpal::swpipl 63027 88.05% 91.44% # number of callpals executed 954system.cpu1.kern.callpal::rdps 2168 3.03% 94.47% # number of callpals executed 955system.cpu1.kern.callpal::wrkgp 1 0.00% 94.47% # number of callpals executed 956system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed 957system.cpu1.kern.callpal::whami 3 0.00% 94.48% # number of callpals executed 958system.cpu1.kern.callpal::rti 3772 5.27% 99.75% # number of callpals executed 959system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed 960system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed |
| 971system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 961system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 972system.cpu1.kern.callpal::total 29399 # number of callpals executed 973system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches 974system.cpu1.kern.mode_switch::user 515 # number of protection mode switches 975system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches 976system.cpu1.kern.mode_good::kernel 531 977system.cpu1.kern.mode_good::user 515 978system.cpu1.kern.mode_good::idle 16 979system.cpu1.kern.mode_switch_good::kernel 0.604096 # fraction of useful protection mode switches | 962system.cpu1.kern.callpal::total 71584 # number of callpals executed 963system.cpu1.kern.mode_switch::kernel 2065 # number of protection mode switches 964system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 965system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches 966system.cpu1.kern.mode_good::kernel 891 967system.cpu1.kern.mode_good::user 464 968system.cpu1.kern.mode_good::idle 427 969system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches |
| 980system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 970system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 981system.cpu1.kern.mode_switch_good::idle 0.007711 # fraction of useful protection mode switches 982system.cpu1.kern.mode_switch_good::total 0.306140 # fraction of useful protection mode switches 983system.cpu1.kern.mode_ticks::kernel 4075179000 0.21% 0.21% # number of ticks spent at the given mode 984system.cpu1.kern.mode_ticks::user 1593973000 0.08% 0.29% # number of ticks spent at the given mode 985system.cpu1.kern.mode_ticks::idle 1955466537000 99.71% 100.00% # number of ticks spent at the given mode 986system.cpu1.kern.swap_context 366 # number of times the context was actually changed 987system.cpu1.icache.replacements 86678 # number of replacements 988system.cpu1.icache.tagsinuse 419.761864 # Cycle average of tags in use 989system.cpu1.icache.total_refs 5169985 # Total number of references to valid blocks. 990system.cpu1.icache.sampled_refs 87190 # Sample count of references to valid blocks. 991system.cpu1.icache.avg_refs 59.295619 # Average number of references to valid blocks. 992system.cpu1.icache.warmup_cycle 1958463060000 # Cycle when the warmup percentage was hit. 993system.cpu1.icache.occ_blocks::cpu1.inst 419.761864 # Average occupied blocks per requestor 994system.cpu1.icache.occ_percent::cpu1.inst 0.819847 # Average percentage of cache occupancy 995system.cpu1.icache.occ_percent::total 0.819847 # Average percentage of cache occupancy 996system.cpu1.icache.ReadReq_hits::cpu1.inst 5169985 # number of ReadReq hits 997system.cpu1.icache.ReadReq_hits::total 5169985 # number of ReadReq hits 998system.cpu1.icache.demand_hits::cpu1.inst 5169985 # number of demand (read+write) hits 999system.cpu1.icache.demand_hits::total 5169985 # number of demand (read+write) hits 1000system.cpu1.icache.overall_hits::cpu1.inst 5169985 # number of overall hits 1001system.cpu1.icache.overall_hits::total 5169985 # number of overall hits 1002system.cpu1.icache.ReadReq_misses::cpu1.inst 87218 # number of ReadReq misses 1003system.cpu1.icache.ReadReq_misses::total 87218 # number of ReadReq misses 1004system.cpu1.icache.demand_misses::cpu1.inst 87218 # number of demand (read+write) misses 1005system.cpu1.icache.demand_misses::total 87218 # number of demand (read+write) misses 1006system.cpu1.icache.overall_misses::cpu1.inst 87218 # number of overall misses 1007system.cpu1.icache.overall_misses::total 87218 # number of overall misses 1008system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1315004000 # number of ReadReq miss cycles 1009system.cpu1.icache.ReadReq_miss_latency::total 1315004000 # number of ReadReq miss cycles 1010system.cpu1.icache.demand_miss_latency::cpu1.inst 1315004000 # number of demand (read+write) miss cycles 1011system.cpu1.icache.demand_miss_latency::total 1315004000 # number of demand (read+write) miss cycles 1012system.cpu1.icache.overall_miss_latency::cpu1.inst 1315004000 # number of overall miss cycles 1013system.cpu1.icache.overall_miss_latency::total 1315004000 # number of overall miss cycles 1014system.cpu1.icache.ReadReq_accesses::cpu1.inst 5257203 # number of ReadReq accesses(hits+misses) 1015system.cpu1.icache.ReadReq_accesses::total 5257203 # number of ReadReq accesses(hits+misses) 1016system.cpu1.icache.demand_accesses::cpu1.inst 5257203 # number of demand (read+write) accesses 1017system.cpu1.icache.demand_accesses::total 5257203 # number of demand (read+write) accesses 1018system.cpu1.icache.overall_accesses::cpu1.inst 5257203 # number of overall (read+write) accesses 1019system.cpu1.icache.overall_accesses::total 5257203 # number of overall (read+write) accesses 1020system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016590 # miss rate for ReadReq accesses 1021system.cpu1.icache.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses 1022system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016590 # miss rate for demand accesses 1023system.cpu1.icache.demand_miss_rate::total 0.016590 # miss rate for demand accesses 1024system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016590 # miss rate for overall accesses 1025system.cpu1.icache.overall_miss_rate::total 0.016590 # miss rate for overall accesses 1026system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15077.208833 # average ReadReq miss latency 1027system.cpu1.icache.ReadReq_avg_miss_latency::total 15077.208833 # average ReadReq miss latency 1028system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency 1029system.cpu1.icache.demand_avg_miss_latency::total 15077.208833 # average overall miss latency 1030system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency 1031system.cpu1.icache.overall_avg_miss_latency::total 15077.208833 # average overall miss latency | 971system.cpu1.kern.mode_switch_good::idle 0.148573 # fraction of useful protection mode switches 972system.cpu1.kern.mode_switch_good::total 0.329817 # fraction of useful protection mode switches 973system.cpu1.kern.mode_ticks::kernel 17893399500 0.91% 0.91% # number of ticks spent at the given mode 974system.cpu1.kern.mode_ticks::user 1709951500 0.09% 1.00% # number of ticks spent at the given mode 975system.cpu1.kern.mode_ticks::idle 1936142128000 99.00% 100.00% # number of ticks spent at the given mode 976system.cpu1.kern.swap_context 1996 # number of times the context was actually changed 977system.cpu1.icache.replacements 316204 # number of replacements 978system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use 979system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks. 980system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks. 981system.cpu1.icache.avg_refs 40.637495 # Average number of references to valid blocks. 982system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit. 983system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor 984system.cpu1.icache.occ_percent::cpu1.inst 0.873938 # Average percentage of cache occupancy 985system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy 986system.cpu1.icache.ReadReq_hits::cpu1.inst 12870545 # number of ReadReq hits 987system.cpu1.icache.ReadReq_hits::total 12870545 # number of ReadReq hits 988system.cpu1.icache.demand_hits::cpu1.inst 12870545 # number of demand (read+write) hits 989system.cpu1.icache.demand_hits::total 12870545 # number of demand (read+write) hits 990system.cpu1.icache.overall_hits::cpu1.inst 12870545 # number of overall hits 991system.cpu1.icache.overall_hits::total 12870545 # number of overall hits 992system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses 993system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses 994system.cpu1.icache.demand_misses::cpu1.inst 316752 # number of demand (read+write) misses 995system.cpu1.icache.demand_misses::total 316752 # number of demand (read+write) misses 996system.cpu1.icache.overall_misses::cpu1.inst 316752 # number of overall misses 997system.cpu1.icache.overall_misses::total 316752 # number of overall misses 998system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4179857000 # number of ReadReq miss cycles 999system.cpu1.icache.ReadReq_miss_latency::total 4179857000 # number of ReadReq miss cycles 1000system.cpu1.icache.demand_miss_latency::cpu1.inst 4179857000 # number of demand (read+write) miss cycles 1001system.cpu1.icache.demand_miss_latency::total 4179857000 # number of demand (read+write) miss cycles 1002system.cpu1.icache.overall_miss_latency::cpu1.inst 4179857000 # number of overall miss cycles 1003system.cpu1.icache.overall_miss_latency::total 4179857000 # number of overall miss cycles 1004system.cpu1.icache.ReadReq_accesses::cpu1.inst 13187297 # number of ReadReq accesses(hits+misses) 1005system.cpu1.icache.ReadReq_accesses::total 13187297 # number of ReadReq accesses(hits+misses) 1006system.cpu1.icache.demand_accesses::cpu1.inst 13187297 # number of demand (read+write) accesses 1007system.cpu1.icache.demand_accesses::total 13187297 # number of demand (read+write) accesses 1008system.cpu1.icache.overall_accesses::cpu1.inst 13187297 # number of overall (read+write) accesses 1009system.cpu1.icache.overall_accesses::total 13187297 # number of overall (read+write) accesses 1010system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024019 # miss rate for ReadReq accesses 1011system.cpu1.icache.ReadReq_miss_rate::total 0.024019 # miss rate for ReadReq accesses 1012system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024019 # miss rate for demand accesses 1013system.cpu1.icache.demand_miss_rate::total 0.024019 # miss rate for demand accesses 1014system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024019 # miss rate for overall accesses 1015system.cpu1.icache.overall_miss_rate::total 0.024019 # miss rate for overall accesses 1016system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13195.992448 # average ReadReq miss latency 1017system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency 1018system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency 1019system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency 1020system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency 1021system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency |
| 1032system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1033system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1034system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1035system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1036system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1037system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1038system.cpu1.icache.fast_writes 0 # number of fast writes performed 1039system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1022system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1023system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1024system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1025system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1026system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1027system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1028system.cpu1.icache.fast_writes 0 # number of fast writes performed 1029system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1040system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87218 # number of ReadReq MSHR misses 1041system.cpu1.icache.ReadReq_mshr_misses::total 87218 # number of ReadReq MSHR misses 1042system.cpu1.icache.demand_mshr_misses::cpu1.inst 87218 # number of demand (read+write) MSHR misses 1043system.cpu1.icache.demand_mshr_misses::total 87218 # number of demand (read+write) MSHR misses 1044system.cpu1.icache.overall_mshr_misses::cpu1.inst 87218 # number of overall MSHR misses 1045system.cpu1.icache.overall_mshr_misses::total 87218 # number of overall MSHR misses 1046system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1053316500 # number of ReadReq MSHR miss cycles 1047system.cpu1.icache.ReadReq_mshr_miss_latency::total 1053316500 # number of ReadReq MSHR miss cycles 1048system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1053316500 # number of demand (read+write) MSHR miss cycles 1049system.cpu1.icache.demand_mshr_miss_latency::total 1053316500 # number of demand (read+write) MSHR miss cycles 1050system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1053316500 # number of overall MSHR miss cycles 1051system.cpu1.icache.overall_mshr_miss_latency::total 1053316500 # number of overall MSHR miss cycles 1052system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for ReadReq accesses 1053system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses 1054system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses 1055system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses 1056system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses 1057system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses 1058system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average ReadReq mshr miss latency 1059system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12076.824738 # average ReadReq mshr miss latency 1060system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency 1061system.cpu1.icache.demand_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency 1062system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency 1063system.cpu1.icache.overall_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency | 1030system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316752 # number of ReadReq MSHR misses 1031system.cpu1.icache.ReadReq_mshr_misses::total 316752 # number of ReadReq MSHR misses 1032system.cpu1.icache.demand_mshr_misses::cpu1.inst 316752 # number of demand (read+write) MSHR misses 1033system.cpu1.icache.demand_mshr_misses::total 316752 # number of demand (read+write) MSHR misses 1034system.cpu1.icache.overall_mshr_misses::cpu1.inst 316752 # number of overall MSHR misses 1035system.cpu1.icache.overall_mshr_misses::total 316752 # number of overall MSHR misses 1036system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3546353000 # number of ReadReq MSHR miss cycles 1037system.cpu1.icache.ReadReq_mshr_miss_latency::total 3546353000 # number of ReadReq MSHR miss cycles 1038system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3546353000 # number of demand (read+write) MSHR miss cycles 1039system.cpu1.icache.demand_mshr_miss_latency::total 3546353000 # number of demand (read+write) MSHR miss cycles 1040system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3546353000 # number of overall MSHR miss cycles 1041system.cpu1.icache.overall_mshr_miss_latency::total 3546353000 # number of overall MSHR miss cycles 1042system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for ReadReq accesses 1043system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024019 # mshr miss rate for ReadReq accesses 1044system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for demand accesses 1045system.cpu1.icache.demand_mshr_miss_rate::total 0.024019 # mshr miss rate for demand accesses 1046system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for overall accesses 1047system.cpu1.icache.overall_mshr_miss_rate::total 0.024019 # mshr miss rate for overall accesses 1048system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average ReadReq mshr miss latency 1049system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11195.992448 # average ReadReq mshr miss latency 1050system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency 1051system.cpu1.icache.demand_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency 1052system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency 1053system.cpu1.icache.overall_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency |
| 1064system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1054system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1065system.cpu1.dcache.replacements 53530 # number of replacements 1066system.cpu1.dcache.tagsinuse 416.811223 # Cycle average of tags in use 1067system.cpu1.dcache.total_refs 1627239 # Total number of references to valid blocks. 1068system.cpu1.dcache.sampled_refs 53938 # Sample count of references to valid blocks. 1069system.cpu1.dcache.avg_refs 30.168694 # Average number of references to valid blocks. 1070system.cpu1.dcache.warmup_cycle 1941569871000 # Cycle when the warmup percentage was hit. 1071system.cpu1.dcache.occ_blocks::cpu1.data 416.811223 # Average occupied blocks per requestor 1072system.cpu1.dcache.occ_percent::cpu1.data 0.814084 # Average percentage of cache occupancy 1073system.cpu1.dcache.occ_percent::total 0.814084 # Average percentage of cache occupancy 1074system.cpu1.dcache.ReadReq_hits::cpu1.data 982758 # number of ReadReq hits 1075system.cpu1.dcache.ReadReq_hits::total 982758 # number of ReadReq hits 1076system.cpu1.dcache.WriteReq_hits::cpu1.data 626472 # number of WriteReq hits 1077system.cpu1.dcache.WriteReq_hits::total 626472 # number of WriteReq hits 1078system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits 1079system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits 1080system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11707 # number of StoreCondReq hits 1081system.cpu1.dcache.StoreCondReq_hits::total 11707 # number of StoreCondReq hits 1082system.cpu1.dcache.demand_hits::cpu1.data 1609230 # number of demand (read+write) hits 1083system.cpu1.dcache.demand_hits::total 1609230 # number of demand (read+write) hits 1084system.cpu1.dcache.overall_hits::cpu1.data 1609230 # number of overall hits 1085system.cpu1.dcache.overall_hits::total 1609230 # number of overall hits 1086system.cpu1.dcache.ReadReq_misses::cpu1.data 35626 # number of ReadReq misses 1087system.cpu1.dcache.ReadReq_misses::total 35626 # number of ReadReq misses 1088system.cpu1.dcache.WriteReq_misses::cpu1.data 22614 # number of WriteReq misses 1089system.cpu1.dcache.WriteReq_misses::total 22614 # number of WriteReq misses 1090system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1003 # number of LoadLockedReq misses 1091system.cpu1.dcache.LoadLockedReq_misses::total 1003 # number of LoadLockedReq misses 1092system.cpu1.dcache.StoreCondReq_misses::cpu1.data 544 # number of StoreCondReq misses 1093system.cpu1.dcache.StoreCondReq_misses::total 544 # number of StoreCondReq misses 1094system.cpu1.dcache.demand_misses::cpu1.data 58240 # number of demand (read+write) misses 1095system.cpu1.dcache.demand_misses::total 58240 # number of demand (read+write) misses 1096system.cpu1.dcache.overall_misses::cpu1.data 58240 # number of overall misses 1097system.cpu1.dcache.overall_misses::total 58240 # number of overall misses 1098system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 484494000 # number of ReadReq miss cycles 1099system.cpu1.dcache.ReadReq_miss_latency::total 484494000 # number of ReadReq miss cycles 1100system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 694414000 # number of WriteReq miss cycles 1101system.cpu1.dcache.WriteReq_miss_latency::total 694414000 # number of WriteReq miss cycles 1102system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 12192000 # number of LoadLockedReq miss cycles 1103system.cpu1.dcache.LoadLockedReq_miss_latency::total 12192000 # number of LoadLockedReq miss cycles 1104system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 7087000 # number of StoreCondReq miss cycles 1105system.cpu1.dcache.StoreCondReq_miss_latency::total 7087000 # number of StoreCondReq miss cycles 1106system.cpu1.dcache.demand_miss_latency::cpu1.data 1178908000 # number of demand (read+write) miss cycles 1107system.cpu1.dcache.demand_miss_latency::total 1178908000 # number of demand (read+write) miss cycles 1108system.cpu1.dcache.overall_miss_latency::cpu1.data 1178908000 # number of overall miss cycles 1109system.cpu1.dcache.overall_miss_latency::total 1178908000 # number of overall miss cycles 1110system.cpu1.dcache.ReadReq_accesses::cpu1.data 1018384 # number of ReadReq accesses(hits+misses) 1111system.cpu1.dcache.ReadReq_accesses::total 1018384 # number of ReadReq accesses(hits+misses) 1112system.cpu1.dcache.WriteReq_accesses::cpu1.data 649086 # number of WriteReq accesses(hits+misses) 1113system.cpu1.dcache.WriteReq_accesses::total 649086 # number of WriteReq accesses(hits+misses) 1114system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12313 # number of LoadLockedReq accesses(hits+misses) 1115system.cpu1.dcache.LoadLockedReq_accesses::total 12313 # number of LoadLockedReq accesses(hits+misses) 1116system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12251 # number of StoreCondReq accesses(hits+misses) 1117system.cpu1.dcache.StoreCondReq_accesses::total 12251 # number of StoreCondReq accesses(hits+misses) 1118system.cpu1.dcache.demand_accesses::cpu1.data 1667470 # number of demand (read+write) accesses 1119system.cpu1.dcache.demand_accesses::total 1667470 # number of demand (read+write) accesses 1120system.cpu1.dcache.overall_accesses::cpu1.data 1667470 # number of overall (read+write) accesses 1121system.cpu1.dcache.overall_accesses::total 1667470 # number of overall (read+write) accesses 1122system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034983 # miss rate for ReadReq accesses 1123system.cpu1.dcache.ReadReq_miss_rate::total 0.034983 # miss rate for ReadReq accesses 1124system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034840 # miss rate for WriteReq accesses 1125system.cpu1.dcache.WriteReq_miss_rate::total 0.034840 # miss rate for WriteReq accesses 1126system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081459 # miss rate for LoadLockedReq accesses 1127system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081459 # miss rate for LoadLockedReq accesses 1128system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044405 # miss rate for StoreCondReq accesses 1129system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044405 # miss rate for StoreCondReq accesses 1130system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034927 # miss rate for demand accesses 1131system.cpu1.dcache.demand_miss_rate::total 0.034927 # miss rate for demand accesses 1132system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034927 # miss rate for overall accesses 1133system.cpu1.dcache.overall_miss_rate::total 0.034927 # miss rate for overall accesses 1134system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13599.449840 # average ReadReq miss latency 1135system.cpu1.dcache.ReadReq_avg_miss_latency::total 13599.449840 # average ReadReq miss latency 1136system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30707.260989 # average WriteReq miss latency 1137system.cpu1.dcache.WriteReq_avg_miss_latency::total 30707.260989 # average WriteReq miss latency 1138system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12155.533400 # average LoadLockedReq miss latency 1139system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12155.533400 # average LoadLockedReq miss latency 1140system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13027.573529 # average StoreCondReq miss latency 1141system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13027.573529 # average StoreCondReq miss latency 1142system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency 1143system.cpu1.dcache.demand_avg_miss_latency::total 20242.239011 # average overall miss latency 1144system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20242.239011 # average overall miss latency 1145system.cpu1.dcache.overall_avg_miss_latency::total 20242.239011 # average overall miss latency | 1055system.cpu1.dcache.replacements 166318 # number of replacements 1056system.cpu1.dcache.tagsinuse 487.121043 # Cycle average of tags in use 1057system.cpu1.dcache.total_refs 4017452 # Total number of references to valid blocks. 1058system.cpu1.dcache.sampled_refs 166830 # Sample count of references to valid blocks. 1059system.cpu1.dcache.avg_refs 24.081113 # Average number of references to valid blocks. 1060system.cpu1.dcache.warmup_cycle 63885131000 # Cycle when the warmup percentage was hit. 1061system.cpu1.dcache.occ_blocks::cpu1.data 487.121043 # Average occupied blocks per requestor 1062system.cpu1.dcache.occ_percent::cpu1.data 0.951408 # Average percentage of cache occupancy 1063system.cpu1.dcache.occ_percent::total 0.951408 # Average percentage of cache occupancy 1064system.cpu1.dcache.ReadReq_hits::cpu1.data 2260833 # number of ReadReq hits 1065system.cpu1.dcache.ReadReq_hits::total 2260833 # number of ReadReq hits 1066system.cpu1.dcache.WriteReq_hits::cpu1.data 1643465 # number of WriteReq hits 1067system.cpu1.dcache.WriteReq_hits::total 1643465 # number of WriteReq hits 1068system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48243 # number of LoadLockedReq hits 1069system.cpu1.dcache.LoadLockedReq_hits::total 48243 # number of LoadLockedReq hits 1070system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50839 # number of StoreCondReq hits 1071system.cpu1.dcache.StoreCondReq_hits::total 50839 # number of StoreCondReq hits 1072system.cpu1.dcache.demand_hits::cpu1.data 3904298 # number of demand (read+write) hits 1073system.cpu1.dcache.demand_hits::total 3904298 # number of demand (read+write) hits 1074system.cpu1.dcache.overall_hits::cpu1.data 3904298 # number of overall hits 1075system.cpu1.dcache.overall_hits::total 3904298 # number of overall hits 1076system.cpu1.dcache.ReadReq_misses::cpu1.data 118301 # number of ReadReq misses 1077system.cpu1.dcache.ReadReq_misses::total 118301 # number of ReadReq misses 1078system.cpu1.dcache.WriteReq_misses::cpu1.data 62725 # number of WriteReq misses 1079system.cpu1.dcache.WriteReq_misses::total 62725 # number of WriteReq misses 1080system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8915 # number of LoadLockedReq misses 1081system.cpu1.dcache.LoadLockedReq_misses::total 8915 # number of LoadLockedReq misses 1082system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5846 # number of StoreCondReq misses 1083system.cpu1.dcache.StoreCondReq_misses::total 5846 # number of StoreCondReq misses 1084system.cpu1.dcache.demand_misses::cpu1.data 181026 # number of demand (read+write) misses 1085system.cpu1.dcache.demand_misses::total 181026 # number of demand (read+write) misses 1086system.cpu1.dcache.overall_misses::cpu1.data 181026 # number of overall misses 1087system.cpu1.dcache.overall_misses::total 181026 # number of overall misses 1088system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1440550500 # number of ReadReq miss cycles 1089system.cpu1.dcache.ReadReq_miss_latency::total 1440550500 # number of ReadReq miss cycles 1090system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1113565500 # number of WriteReq miss cycles 1091system.cpu1.dcache.WriteReq_miss_latency::total 1113565500 # number of WriteReq miss cycles 1092system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81445500 # number of LoadLockedReq miss cycles 1093system.cpu1.dcache.LoadLockedReq_miss_latency::total 81445500 # number of LoadLockedReq miss cycles 1094system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 69062000 # number of StoreCondReq miss cycles 1095system.cpu1.dcache.StoreCondReq_miss_latency::total 69062000 # number of StoreCondReq miss cycles 1096system.cpu1.dcache.demand_miss_latency::cpu1.data 2554116000 # number of demand (read+write) miss cycles 1097system.cpu1.dcache.demand_miss_latency::total 2554116000 # number of demand (read+write) miss cycles 1098system.cpu1.dcache.overall_miss_latency::cpu1.data 2554116000 # number of overall miss cycles 1099system.cpu1.dcache.overall_miss_latency::total 2554116000 # number of overall miss cycles 1100system.cpu1.dcache.ReadReq_accesses::cpu1.data 2379134 # number of ReadReq accesses(hits+misses) 1101system.cpu1.dcache.ReadReq_accesses::total 2379134 # number of ReadReq accesses(hits+misses) 1102system.cpu1.dcache.WriteReq_accesses::cpu1.data 1706190 # number of WriteReq accesses(hits+misses) 1103system.cpu1.dcache.WriteReq_accesses::total 1706190 # number of WriteReq accesses(hits+misses) 1104system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57158 # number of LoadLockedReq accesses(hits+misses) 1105system.cpu1.dcache.LoadLockedReq_accesses::total 57158 # number of LoadLockedReq accesses(hits+misses) 1106system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56685 # number of StoreCondReq accesses(hits+misses) 1107system.cpu1.dcache.StoreCondReq_accesses::total 56685 # number of StoreCondReq accesses(hits+misses) 1108system.cpu1.dcache.demand_accesses::cpu1.data 4085324 # number of demand (read+write) accesses 1109system.cpu1.dcache.demand_accesses::total 4085324 # number of demand (read+write) accesses 1110system.cpu1.dcache.overall_accesses::cpu1.data 4085324 # number of overall (read+write) accesses 1111system.cpu1.dcache.overall_accesses::total 4085324 # number of overall (read+write) accesses 1112system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049724 # miss rate for ReadReq accesses 1113system.cpu1.dcache.ReadReq_miss_rate::total 0.049724 # miss rate for ReadReq accesses 1114system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036763 # miss rate for WriteReq accesses 1115system.cpu1.dcache.WriteReq_miss_rate::total 0.036763 # miss rate for WriteReq accesses 1116system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155971 # miss rate for LoadLockedReq accesses 1117system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155971 # miss rate for LoadLockedReq accesses 1118system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103131 # miss rate for StoreCondReq accesses 1119system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103131 # miss rate for StoreCondReq accesses 1120system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044311 # miss rate for demand accesses 1121system.cpu1.dcache.demand_miss_rate::total 0.044311 # miss rate for demand accesses 1122system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044311 # miss rate for overall accesses 1123system.cpu1.dcache.overall_miss_rate::total 0.044311 # miss rate for overall accesses 1124system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12176.993432 # average ReadReq miss latency 1125system.cpu1.dcache.ReadReq_avg_miss_latency::total 12176.993432 # average ReadReq miss latency 1126system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17753.136708 # average WriteReq miss latency 1127system.cpu1.dcache.WriteReq_avg_miss_latency::total 17753.136708 # average WriteReq miss latency 1128system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9135.782389 # average LoadLockedReq miss latency 1129system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9135.782389 # average LoadLockedReq miss latency 1130system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11813.547725 # average StoreCondReq miss latency 1131system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11813.547725 # average StoreCondReq miss latency 1132system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency 1133system.cpu1.dcache.demand_avg_miss_latency::total 14109.111398 # average overall miss latency 1134system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14109.111398 # average overall miss latency 1135system.cpu1.dcache.overall_avg_miss_latency::total 14109.111398 # average overall miss latency |
| 1146system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1147system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1148system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1149system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1150system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1151system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1152system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1153system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1136system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1137system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1138system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1139system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1140system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1141system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1142system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1143system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1154system.cpu1.dcache.writebacks::writebacks 35195 # number of writebacks 1155system.cpu1.dcache.writebacks::total 35195 # number of writebacks 1156system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 35626 # number of ReadReq MSHR misses 1157system.cpu1.dcache.ReadReq_mshr_misses::total 35626 # number of ReadReq MSHR misses 1158system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 22614 # number of WriteReq MSHR misses 1159system.cpu1.dcache.WriteReq_mshr_misses::total 22614 # number of WriteReq MSHR misses 1160system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1003 # number of LoadLockedReq MSHR misses 1161system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1003 # number of LoadLockedReq MSHR misses 1162system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 544 # number of StoreCondReq MSHR misses 1163system.cpu1.dcache.StoreCondReq_mshr_misses::total 544 # number of StoreCondReq MSHR misses 1164system.cpu1.dcache.demand_mshr_misses::cpu1.data 58240 # number of demand (read+write) MSHR misses 1165system.cpu1.dcache.demand_mshr_misses::total 58240 # number of demand (read+write) MSHR misses 1166system.cpu1.dcache.overall_mshr_misses::cpu1.data 58240 # number of overall MSHR misses 1167system.cpu1.dcache.overall_mshr_misses::total 58240 # number of overall MSHR misses 1168system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 377607005 # number of ReadReq MSHR miss cycles 1169system.cpu1.dcache.ReadReq_mshr_miss_latency::total 377607005 # number of ReadReq MSHR miss cycles 1170system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 626568004 # number of WriteReq MSHR miss cycles 1171system.cpu1.dcache.WriteReq_mshr_miss_latency::total 626568004 # number of WriteReq MSHR miss cycles 1172system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 9183000 # number of LoadLockedReq MSHR miss cycles 1173system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 9183000 # number of LoadLockedReq MSHR miss cycles 1174system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5455000 # number of StoreCondReq MSHR miss cycles 1175system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5455000 # number of StoreCondReq MSHR miss cycles 1176system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1004175009 # number of demand (read+write) MSHR miss cycles 1177system.cpu1.dcache.demand_mshr_miss_latency::total 1004175009 # number of demand (read+write) MSHR miss cycles 1178system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1004175009 # number of overall MSHR miss cycles 1179system.cpu1.dcache.overall_mshr_miss_latency::total 1004175009 # number of overall MSHR miss cycles 1180system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20565000 # number of ReadReq MSHR uncacheable cycles 1181system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20565000 # number of ReadReq MSHR uncacheable cycles 1182system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534647000 # number of WriteReq MSHR uncacheable cycles 1183system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 534647000 # number of WriteReq MSHR uncacheable cycles 1184system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 555212000 # number of overall MSHR uncacheable cycles 1185system.cpu1.dcache.overall_mshr_uncacheable_latency::total 555212000 # number of overall MSHR uncacheable cycles 1186system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.034983 # mshr miss rate for ReadReq accesses 1187system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.034983 # mshr miss rate for ReadReq accesses 1188system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034840 # mshr miss rate for WriteReq accesses 1189system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034840 # mshr miss rate for WriteReq accesses 1190system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081459 # mshr miss rate for LoadLockedReq accesses 1191system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081459 # mshr miss rate for LoadLockedReq accesses 1192system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044405 # mshr miss rate for StoreCondReq accesses 1193system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.044405 # mshr miss rate for StoreCondReq accesses 1194system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for demand accesses 1195system.cpu1.dcache.demand_mshr_miss_rate::total 0.034927 # mshr miss rate for demand accesses 1196system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034927 # mshr miss rate for overall accesses 1197system.cpu1.dcache.overall_mshr_miss_rate::total 0.034927 # mshr miss rate for overall accesses 1198system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10599.197356 # average ReadReq mshr miss latency 1199system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10599.197356 # average ReadReq mshr miss latency 1200system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27707.084284 # average WriteReq mshr miss latency 1201system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27707.084284 # average WriteReq mshr miss latency 1202system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9155.533400 # average LoadLockedReq mshr miss latency 1203system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9155.533400 # average LoadLockedReq mshr miss latency 1204system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10027.573529 # average StoreCondReq mshr miss latency 1205system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10027.573529 # average StoreCondReq mshr miss latency 1206system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency 1207system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency 1208system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17242.015951 # average overall mshr miss latency 1209system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17242.015951 # average overall mshr miss latency | 1144system.cpu1.dcache.writebacks::writebacks 114265 # number of writebacks 1145system.cpu1.dcache.writebacks::total 114265 # number of writebacks 1146system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118301 # number of ReadReq MSHR misses 1147system.cpu1.dcache.ReadReq_mshr_misses::total 118301 # number of ReadReq MSHR misses 1148system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62725 # number of WriteReq MSHR misses 1149system.cpu1.dcache.WriteReq_mshr_misses::total 62725 # number of WriteReq MSHR misses 1150system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8915 # number of LoadLockedReq MSHR misses 1151system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8915 # number of LoadLockedReq MSHR misses 1152system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5846 # number of StoreCondReq MSHR misses 1153system.cpu1.dcache.StoreCondReq_mshr_misses::total 5846 # number of StoreCondReq MSHR misses 1154system.cpu1.dcache.demand_mshr_misses::cpu1.data 181026 # number of demand (read+write) MSHR misses 1155system.cpu1.dcache.demand_mshr_misses::total 181026 # number of demand (read+write) MSHR misses 1156system.cpu1.dcache.overall_mshr_misses::cpu1.data 181026 # number of overall MSHR misses 1157system.cpu1.dcache.overall_mshr_misses::total 181026 # number of overall MSHR misses 1158system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203948500 # number of ReadReq MSHR miss cycles 1159system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203948500 # number of ReadReq MSHR miss cycles 1160system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 988115500 # number of WriteReq MSHR miss cycles 1161system.cpu1.dcache.WriteReq_mshr_miss_latency::total 988115500 # number of WriteReq MSHR miss cycles 1162system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63615500 # number of LoadLockedReq MSHR miss cycles 1163system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63615500 # number of LoadLockedReq MSHR miss cycles 1164system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57370000 # number of StoreCondReq MSHR miss cycles 1165system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57370000 # number of StoreCondReq MSHR miss cycles 1166system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2192064000 # number of demand (read+write) MSHR miss cycles 1167system.cpu1.dcache.demand_mshr_miss_latency::total 2192064000 # number of demand (read+write) MSHR miss cycles 1168system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2192064000 # number of overall MSHR miss cycles 1169system.cpu1.dcache.overall_mshr_miss_latency::total 2192064000 # number of overall MSHR miss cycles 1170system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles 1171system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles 1172system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713392500 # number of WriteReq MSHR uncacheable cycles 1173system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713392500 # number of WriteReq MSHR uncacheable cycles 1174system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732780000 # number of overall MSHR uncacheable cycles 1175system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732780000 # number of overall MSHR uncacheable cycles 1176system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049724 # mshr miss rate for ReadReq accesses 1177system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049724 # mshr miss rate for ReadReq accesses 1178system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036763 # mshr miss rate for WriteReq accesses 1179system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036763 # mshr miss rate for WriteReq accesses 1180system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155971 # mshr miss rate for LoadLockedReq accesses 1181system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155971 # mshr miss rate for LoadLockedReq accesses 1182system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103131 # mshr miss rate for StoreCondReq accesses 1183system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103131 # mshr miss rate for StoreCondReq accesses 1184system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for demand accesses 1185system.cpu1.dcache.demand_mshr_miss_rate::total 0.044311 # mshr miss rate for demand accesses 1186system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for overall accesses 1187system.cpu1.dcache.overall_mshr_miss_rate::total 0.044311 # mshr miss rate for overall accesses 1188system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10176.993432 # average ReadReq mshr miss latency 1189system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10176.993432 # average ReadReq mshr miss latency 1190system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15753.136708 # average WriteReq mshr miss latency 1191system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15753.136708 # average WriteReq mshr miss latency 1192system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.782389 # average LoadLockedReq mshr miss latency 1193system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.782389 # average LoadLockedReq mshr miss latency 1194system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9813.547725 # average StoreCondReq mshr miss latency 1195system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9813.547725 # average StoreCondReq mshr miss latency 1196system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency 1197system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency 1198system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency 1199system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency |
| 1210system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1211system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1212system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1213system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1214system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1215system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1216system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1217 1218---------- End Simulation Statistics ---------- | 1200system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1201system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1202system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1203system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1204system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1205system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1206system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1207 1208---------- End Simulation Statistics ---------- |