Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 1.954209 # Number of seconds simulated
4sim_ticks 1954209106000 # Number of ticks simulated
5final_tick 1954209106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 1.954210 # Number of seconds simulated
4sim_ticks 1954209529000 # Number of ticks simulated
5final_tick 1954209529000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1820229 # Simulator instruction rate (inst/s)
8host_op_rate 1820228 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 59866957581 # Simulator tick rate (ticks/s)
10host_mem_usage 296900 # Number of bytes of host memory used
11host_seconds 32.64 # Real time elapsed on the host
12sim_insts 59416827 # Number of instructions simulated
13sim_ops 59416827 # Number of ops (including micro ops) simulated

7host_inst_rate 1320479 # Simulator instruction rate (inst/s)
8host_op_rate 1320478 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 43430338961 # Simulator tick rate (ticks/s)
10host_mem_usage 301360 # Number of bytes of host memory used
11host_seconds 45.00 # Real time elapsed on the host
12sim_insts 59416773 # Number of instructions simulated
13sim_ops 59416773 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu0.inst 717056 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 23797184 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.inst 145856 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.data 1424768 # Number of bytes read from this memory
19system.physmem.bytes_read::total 28734208 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu0.inst 717056 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::cpu1.inst 145856 # Number of instructions bytes read from this memory

--- 4 unchanged lines hidden (view full) ---

26system.physmem.num_reads::cpu0.data 371831 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu1.inst 2279 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.data 22262 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 448972 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 121019 # Number of write requests responded to by this memory
32system.physmem.num_writes::total 121019 # Number of write requests responded to by this memory
33system.physmem.bw_read::cpu0.inst 366929 # Total read bandwidth from this memory (bytes/s)

34system.physmem.bw_read::cpu0.data 12177399 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::tsunami.ide 1355712 # Total read bandwidth from this memory (bytes/s)

34system.physmem.bw_read::cpu0.data 12177396 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::tsunami.ide 1355711 # Total read bandwidth from this memory (bytes/s)

36system.physmem.bw_read::cpu1.inst 74637 # Total read bandwidth from this memory (bytes/s)

37system.physmem.bw_read::cpu1.data 729077 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::total 14703753 # Total read bandwidth from this memory (bytes/s)

37system.physmem.bw_read::cpu1.data 729076 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::total 14703750 # Total read bandwidth from this memory (bytes/s)

39system.physmem.bw_inst_read::cpu0.inst 366929 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu1.inst 74637 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 441566 # Instruction read bandwidth from this memory (bytes/s)

42system.physmem.bw_write::writebacks 3963351 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 3963351 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 3963351 # Total bandwidth to/from this memory (bytes/s)

42system.physmem.bw_write::writebacks 3963350 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 3963350 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 3963350 # Total bandwidth to/from this memory (bytes/s)

45system.physmem.bw_total::cpu0.inst 366929 # Total bandwidth to/from this memory (bytes/s)

46system.physmem.bw_total::cpu0.data 12177399 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::tsunami.ide 1355712 # Total bandwidth to/from this memory (bytes/s)

46system.physmem.bw_total::cpu0.data 12177396 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::tsunami.ide 1355711 # Total bandwidth to/from this memory (bytes/s)

48system.physmem.bw_total::cpu1.inst 74637 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu1.data 729077 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 18667104 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu1.data 729076 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 18667100 # Total bandwidth to/from this memory (bytes/s)

51system.l2c.replacements 342059 # number of replacements

52system.l2c.tagsinuse 65268.179703 # Cycle average of tags in use
53system.l2c.total_refs 2559285 # Total number of references to valid blocks.
54system.l2c.sampled_refs 407065 # Sample count of references to valid blocks.
55system.l2c.avg_refs 6.287165 # Average number of references to valid blocks.

52system.l2c.tagsinuse 65268.160318 # Cycle average of tags in use
53system.l2c.total_refs 2559182 # Total number of references to valid blocks.
54system.l2c.sampled_refs 407064 # Sample count of references to valid blocks.
55system.l2c.avg_refs 6.286928 # Average number of references to valid blocks.

56system.l2c.warmup_cycle 7752825000 # Cycle when the warmup percentage was hit.

57system.l2c.occ_blocks::writebacks 55637.656104 # Average occupied blocks per requestor
58system.l2c.occ_blocks::cpu0.inst 3742.496714 # Average occupied blocks per requestor
59system.l2c.occ_blocks::cpu0.data 4175.529809 # Average occupied blocks per requestor
60system.l2c.occ_blocks::cpu1.inst 1176.827938 # Average occupied blocks per requestor
61system.l2c.occ_blocks::cpu1.data 535.669138 # Average occupied blocks per requestor

57system.l2c.occ_blocks::writebacks 55637.634903 # Average occupied blocks per requestor
58system.l2c.occ_blocks::cpu0.inst 3742.497316 # Average occupied blocks per requestor
59system.l2c.occ_blocks::cpu0.data 4175.530834 # Average occupied blocks per requestor
60system.l2c.occ_blocks::cpu1.inst 1176.828105 # Average occupied blocks per requestor
61system.l2c.occ_blocks::cpu1.data 535.669160 # Average occupied blocks per requestor

62system.l2c.occ_percent::writebacks 0.848963 # Average percentage of cache occupancy
63system.l2c.occ_percent::cpu0.inst 0.057106 # Average percentage of cache occupancy
64system.l2c.occ_percent::cpu0.data 0.063714 # Average percentage of cache occupancy
65system.l2c.occ_percent::cpu1.inst 0.017957 # Average percentage of cache occupancy
66system.l2c.occ_percent::cpu1.data 0.008174 # Average percentage of cache occupancy
67system.l2c.occ_percent::total 0.995913 # Average percentage of cache occupancy

68system.l2c.ReadReq_hits::cpu0.inst 478629 # number of ReadReq hits
69system.l2c.ReadReq_hits::cpu0.data 342574 # number of ReadReq hits
70system.l2c.ReadReq_hits::cpu1.inst 511941 # number of ReadReq hits
71system.l2c.ReadReq_hits::cpu1.data 491320 # number of ReadReq hits
72system.l2c.ReadReq_hits::total 1824464 # number of ReadReq hits
73system.l2c.Writeback_hits::writebacks 858732 # number of Writeback hits
74system.l2c.Writeback_hits::total 858732 # number of Writeback hits
75system.l2c.UpgradeReq_hits::cpu0.data 137 # number of UpgradeReq hits

68system.l2c.ReadReq_hits::cpu0.inst 478624 # number of ReadReq hits
69system.l2c.ReadReq_hits::cpu0.data 342590 # number of ReadReq hits
70system.l2c.ReadReq_hits::cpu1.inst 511938 # number of ReadReq hits
71system.l2c.ReadReq_hits::cpu1.data 491329 # number of ReadReq hits
72system.l2c.ReadReq_hits::total 1824481 # number of ReadReq hits
73system.l2c.Writeback_hits::writebacks 858650 # number of Writeback hits
74system.l2c.Writeback_hits::total 858650 # number of Writeback hits
75system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits

76system.l2c.UpgradeReq_hits::cpu1.data 95 # number of UpgradeReq hits

77system.l2c.UpgradeReq_hits::total 232 # number of UpgradeReq hits

77system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits

78system.l2c.SCUpgradeReq_hits::cpu0.data 22 # number of SCUpgradeReq hits
79system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
80system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits

81system.l2c.ReadExReq_hits::cpu0.data 101383 # number of ReadExReq hits
82system.l2c.ReadExReq_hits::cpu1.data 99295 # number of ReadExReq hits
83system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits
84system.l2c.demand_hits::cpu0.inst 478629 # number of demand (read+write) hits
85system.l2c.demand_hits::cpu0.data 443957 # number of demand (read+write) hits
86system.l2c.demand_hits::cpu1.inst 511941 # number of demand (read+write) hits
87system.l2c.demand_hits::cpu1.data 590615 # number of demand (read+write) hits
88system.l2c.demand_hits::total 2025142 # number of demand (read+write) hits
89system.l2c.overall_hits::cpu0.inst 478629 # number of overall hits
90system.l2c.overall_hits::cpu0.data 443957 # number of overall hits
91system.l2c.overall_hits::cpu1.inst 511941 # number of overall hits
92system.l2c.overall_hits::cpu1.data 590615 # number of overall hits
93system.l2c.overall_hits::total 2025142 # number of overall hits

81system.l2c.ReadExReq_hits::cpu0.data 101497 # number of ReadExReq hits
82system.l2c.ReadExReq_hits::cpu1.data 99318 # number of ReadExReq hits
83system.l2c.ReadExReq_hits::total 200815 # number of ReadExReq hits
84system.l2c.demand_hits::cpu0.inst 478624 # number of demand (read+write) hits
85system.l2c.demand_hits::cpu0.data 444087 # number of demand (read+write) hits
86system.l2c.demand_hits::cpu1.inst 511938 # number of demand (read+write) hits
87system.l2c.demand_hits::cpu1.data 590647 # number of demand (read+write) hits
88system.l2c.demand_hits::total 2025296 # number of demand (read+write) hits
89system.l2c.overall_hits::cpu0.inst 478624 # number of overall hits
90system.l2c.overall_hits::cpu0.data 444087 # number of overall hits
91system.l2c.overall_hits::cpu1.inst 511938 # number of overall hits
92system.l2c.overall_hits::cpu1.data 590647 # number of overall hits
93system.l2c.overall_hits::total 2025296 # number of overall hits

94system.l2c.ReadReq_misses::cpu0.inst 11204 # number of ReadReq misses
95system.l2c.ReadReq_misses::cpu0.data 270589 # number of ReadReq misses
96system.l2c.ReadReq_misses::cpu1.inst 2290 # number of ReadReq misses
97system.l2c.ReadReq_misses::cpu1.data 1211 # number of ReadReq misses
98system.l2c.ReadReq_misses::total 285294 # number of ReadReq misses

99system.l2c.UpgradeReq_misses::cpu0.data 2576 # number of UpgradeReq misses

99system.l2c.UpgradeReq_misses::cpu0.data 2582 # number of UpgradeReq misses

100system.l2c.UpgradeReq_misses::cpu1.data 476 # number of UpgradeReq misses

101system.l2c.UpgradeReq_misses::total 3052 # number of UpgradeReq misses

101system.l2c.UpgradeReq_misses::total 3058 # number of UpgradeReq misses

102system.l2c.SCUpgradeReq_misses::cpu0.data 85 # number of SCUpgradeReq misses
103system.l2c.SCUpgradeReq_misses::cpu1.data 88 # number of SCUpgradeReq misses
104system.l2c.SCUpgradeReq_misses::total 173 # number of SCUpgradeReq misses

105system.l2c.ReadExReq_misses::cpu0.data 101598 # number of ReadExReq misses

105system.l2c.ReadExReq_misses::cpu0.data 101602 # number of ReadExReq misses

106system.l2c.ReadExReq_misses::cpu1.data 21093 # number of ReadExReq misses

107system.l2c.ReadExReq_misses::total 122691 # number of ReadExReq misses

107system.l2c.ReadExReq_misses::total 122695 # number of ReadExReq misses

108system.l2c.demand_misses::cpu0.inst 11204 # number of demand (read+write) misses

109system.l2c.demand_misses::cpu0.data 372187 # number of demand (read+write) misses

109system.l2c.demand_misses::cpu0.data 372191 # number of demand (read+write) misses

110system.l2c.demand_misses::cpu1.inst 2290 # number of demand (read+write) misses
111system.l2c.demand_misses::cpu1.data 22304 # number of demand (read+write) misses

112system.l2c.demand_misses::total 407985 # number of demand (read+write) misses

112system.l2c.demand_misses::total 407989 # number of demand (read+write) misses

113system.l2c.overall_misses::cpu0.inst 11204 # number of overall misses

114system.l2c.overall_misses::cpu0.data 372187 # number of overall misses

114system.l2c.overall_misses::cpu0.data 372191 # number of overall misses

115system.l2c.overall_misses::cpu1.inst 2290 # number of overall misses
116system.l2c.overall_misses::cpu1.data 22304 # number of overall misses

117system.l2c.overall_misses::total 407985 # number of overall misses

117system.l2c.overall_misses::total 407989 # number of overall misses

118system.l2c.ReadReq_miss_latency::cpu0.inst 582910000 # number of ReadReq miss cycles
119system.l2c.ReadReq_miss_latency::cpu0.data 14075669000 # number of ReadReq miss cycles
120system.l2c.ReadReq_miss_latency::cpu1.inst 119002000 # number of ReadReq miss cycles
121system.l2c.ReadReq_miss_latency::cpu1.data 63420000 # number of ReadReq miss cycles
122system.l2c.ReadReq_miss_latency::total 14841001000 # number of ReadReq miss cycles
123system.l2c.UpgradeReq_miss_latency::cpu0.data 1144000 # number of UpgradeReq miss cycles
124system.l2c.UpgradeReq_miss_latency::cpu1.data 1924000 # number of UpgradeReq miss cycles
125system.l2c.UpgradeReq_miss_latency::total 3068000 # number of UpgradeReq miss cycles
126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 695000 # number of SCUpgradeReq miss cycles
127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156000 # number of SCUpgradeReq miss cycles
128system.l2c.SCUpgradeReq_miss_latency::total 851000 # number of SCUpgradeReq miss cycles

129system.l2c.ReadExReq_miss_latency::cpu0.data 5283374000 # number of ReadExReq miss cycles

129system.l2c.ReadExReq_miss_latency::cpu0.data 5283582000 # number of ReadExReq miss cycles

130system.l2c.ReadExReq_miss_latency::cpu1.data 1096874000 # number of ReadExReq miss cycles

131system.l2c.ReadExReq_miss_latency::total 6380248000 # number of ReadExReq miss cycles

131system.l2c.ReadExReq_miss_latency::total 6380456000 # number of ReadExReq miss cycles

132system.l2c.demand_miss_latency::cpu0.inst 582910000 # number of demand (read+write) miss cycles

133system.l2c.demand_miss_latency::cpu0.data 19359043000 # number of demand (read+write) miss cycles

133system.l2c.demand_miss_latency::cpu0.data 19359251000 # number of demand (read+write) miss cycles

134system.l2c.demand_miss_latency::cpu1.inst 119002000 # number of demand (read+write) miss cycles
135system.l2c.demand_miss_latency::cpu1.data 1160294000 # number of demand (read+write) miss cycles

136system.l2c.demand_miss_latency::total 21221249000 # number of demand (read+write) miss cycles

136system.l2c.demand_miss_latency::total 21221457000 # number of demand (read+write) miss cycles

137system.l2c.overall_miss_latency::cpu0.inst 582910000 # number of overall miss cycles

138system.l2c.overall_miss_latency::cpu0.data 19359043000 # number of overall miss cycles

138system.l2c.overall_miss_latency::cpu0.data 19359251000 # number of overall miss cycles

139system.l2c.overall_miss_latency::cpu1.inst 119002000 # number of overall miss cycles
140system.l2c.overall_miss_latency::cpu1.data 1160294000 # number of overall miss cycles

141system.l2c.overall_miss_latency::total 21221249000 # number of overall miss cycles
142system.l2c.ReadReq_accesses::cpu0.inst 489833 # number of ReadReq accesses(hits+misses)
143system.l2c.ReadReq_accesses::cpu0.data 613163 # number of ReadReq accesses(hits+misses)
144system.l2c.ReadReq_accesses::cpu1.inst 514231 # number of ReadReq accesses(hits+misses)
145system.l2c.ReadReq_accesses::cpu1.data 492531 # number of ReadReq accesses(hits+misses)
146system.l2c.ReadReq_accesses::total 2109758 # number of ReadReq accesses(hits+misses)
147system.l2c.Writeback_accesses::writebacks 858732 # number of Writeback accesses(hits+misses)
148system.l2c.Writeback_accesses::total 858732 # number of Writeback accesses(hits+misses)
149system.l2c.UpgradeReq_accesses::cpu0.data 2713 # number of UpgradeReq accesses(hits+misses)

141system.l2c.overall_miss_latency::total 21221457000 # number of overall miss cycles
142system.l2c.ReadReq_accesses::cpu0.inst 489828 # number of ReadReq accesses(hits+misses)
143system.l2c.ReadReq_accesses::cpu0.data 613179 # number of ReadReq accesses(hits+misses)
144system.l2c.ReadReq_accesses::cpu1.inst 514228 # number of ReadReq accesses(hits+misses)
145system.l2c.ReadReq_accesses::cpu1.data 492540 # number of ReadReq accesses(hits+misses)
146system.l2c.ReadReq_accesses::total 2109775 # number of ReadReq accesses(hits+misses)
147system.l2c.Writeback_accesses::writebacks 858650 # number of Writeback accesses(hits+misses)
148system.l2c.Writeback_accesses::total 858650 # number of Writeback accesses(hits+misses)
149system.l2c.UpgradeReq_accesses::cpu0.data 2715 # number of UpgradeReq accesses(hits+misses)

150system.l2c.UpgradeReq_accesses::cpu1.data 571 # number of UpgradeReq accesses(hits+misses)

151system.l2c.UpgradeReq_accesses::total 3284 # number of UpgradeReq accesses(hits+misses)

151system.l2c.UpgradeReq_accesses::total 3286 # number of UpgradeReq accesses(hits+misses)

152system.l2c.SCUpgradeReq_accesses::cpu0.data 107 # number of SCUpgradeReq accesses(hits+misses)
153system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses)
154system.l2c.SCUpgradeReq_accesses::total 219 # number of SCUpgradeReq accesses(hits+misses)

155system.l2c.ReadExReq_accesses::cpu0.data 202981 # number of ReadExReq accesses(hits+misses)
156system.l2c.ReadExReq_accesses::cpu1.data 120388 # number of ReadExReq accesses(hits+misses)
157system.l2c.ReadExReq_accesses::total 323369 # number of ReadExReq accesses(hits+misses)
158system.l2c.demand_accesses::cpu0.inst 489833 # number of demand (read+write) accesses
159system.l2c.demand_accesses::cpu0.data 816144 # number of demand (read+write) accesses
160system.l2c.demand_accesses::cpu1.inst 514231 # number of demand (read+write) accesses
161system.l2c.demand_accesses::cpu1.data 612919 # number of demand (read+write) accesses
162system.l2c.demand_accesses::total 2433127 # number of demand (read+write) accesses
163system.l2c.overall_accesses::cpu0.inst 489833 # number of overall (read+write) accesses
164system.l2c.overall_accesses::cpu0.data 816144 # number of overall (read+write) accesses
165system.l2c.overall_accesses::cpu1.inst 514231 # number of overall (read+write) accesses
166system.l2c.overall_accesses::cpu1.data 612919 # number of overall (read+write) accesses
167system.l2c.overall_accesses::total 2433127 # number of overall (read+write) accesses

155system.l2c.ReadExReq_accesses::cpu0.data 203099 # number of ReadExReq accesses(hits+misses)
156system.l2c.ReadExReq_accesses::cpu1.data 120411 # number of ReadExReq accesses(hits+misses)
157system.l2c.ReadExReq_accesses::total 323510 # number of ReadExReq accesses(hits+misses)
158system.l2c.demand_accesses::cpu0.inst 489828 # number of demand (read+write) accesses
159system.l2c.demand_accesses::cpu0.data 816278 # number of demand (read+write) accesses
160system.l2c.demand_accesses::cpu1.inst 514228 # number of demand (read+write) accesses
161system.l2c.demand_accesses::cpu1.data 612951 # number of demand (read+write) accesses
162system.l2c.demand_accesses::total 2433285 # number of demand (read+write) accesses
163system.l2c.overall_accesses::cpu0.inst 489828 # number of overall (read+write) accesses
164system.l2c.overall_accesses::cpu0.data 816278 # number of overall (read+write) accesses
165system.l2c.overall_accesses::cpu1.inst 514228 # number of overall (read+write) accesses
166system.l2c.overall_accesses::cpu1.data 612951 # number of overall (read+write) accesses
167system.l2c.overall_accesses::total 2433285 # number of overall (read+write) accesses

168system.l2c.ReadReq_miss_rate::cpu0.inst 0.022873 # miss rate for ReadReq accesses

169system.l2c.ReadReq_miss_rate::cpu0.data 0.441300 # miss rate for ReadReq accesses

169system.l2c.ReadReq_miss_rate::cpu0.data 0.441289 # miss rate for ReadReq accesses

170system.l2c.ReadReq_miss_rate::cpu1.inst 0.004453 # miss rate for ReadReq accesses
171system.l2c.ReadReq_miss_rate::cpu1.data 0.002459 # miss rate for ReadReq accesses

172system.l2c.ReadReq_miss_rate::total 0.135226 # miss rate for ReadReq accesses
173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.949502 # miss rate for UpgradeReq accesses

172system.l2c.ReadReq_miss_rate::total 0.135225 # miss rate for ReadReq accesses
173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951013 # miss rate for UpgradeReq accesses

174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.833625 # miss rate for UpgradeReq accesses

175system.l2c.UpgradeReq_miss_rate::total 0.929354 # miss rate for UpgradeReq accesses

175system.l2c.UpgradeReq_miss_rate::total 0.930615 # miss rate for UpgradeReq accesses

176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.794393 # miss rate for SCUpgradeReq accesses
177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.785714 # miss rate for SCUpgradeReq accesses
178system.l2c.SCUpgradeReq_miss_rate::total 0.789954 # miss rate for SCUpgradeReq accesses

179system.l2c.ReadExReq_miss_rate::cpu0.data 0.500530 # miss rate for ReadExReq accesses
180system.l2c.ReadExReq_miss_rate::cpu1.data 0.175208 # miss rate for ReadExReq accesses
181system.l2c.ReadExReq_miss_rate::total 0.379415 # miss rate for ReadExReq accesses

179system.l2c.ReadExReq_miss_rate::cpu0.data 0.500258 # miss rate for ReadExReq accesses
180system.l2c.ReadExReq_miss_rate::cpu1.data 0.175175 # miss rate for ReadExReq accesses
181system.l2c.ReadExReq_miss_rate::total 0.379262 # miss rate for ReadExReq accesses

182system.l2c.demand_miss_rate::cpu0.inst 0.022873 # miss rate for demand accesses

183system.l2c.demand_miss_rate::cpu0.data 0.456031 # miss rate for demand accesses

183system.l2c.demand_miss_rate::cpu0.data 0.455961 # miss rate for demand accesses

184system.l2c.demand_miss_rate::cpu1.inst 0.004453 # miss rate for demand accesses

185system.l2c.demand_miss_rate::cpu1.data 0.036390 # miss rate for demand accesses
186system.l2c.demand_miss_rate::total 0.167679 # miss rate for demand accesses

185system.l2c.demand_miss_rate::cpu1.data 0.036388 # miss rate for demand accesses
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197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 444.099379 # average UpgradeReq miss latency

197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 443.067390 # average UpgradeReq miss latency

198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4042.016807 # average UpgradeReq miss latency

199system.l2c.UpgradeReq_avg_miss_latency::total 1005.242464 # average UpgradeReq miss latency

199system.l2c.UpgradeReq_avg_miss_latency::total 1003.270111 # average UpgradeReq miss latency

200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8176.470588 # average SCUpgradeReq miss latency
201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1772.727273 # average SCUpgradeReq miss latency
202system.l2c.SCUpgradeReq_avg_miss_latency::total 4919.075145 # average SCUpgradeReq miss latency

203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736274 # average ReadExReq miss latency

203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736167 # average ReadExReq miss latency

204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52001.801546 # average ReadExReq miss latency

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206system.l2c.demand_avg_miss_latency::cpu0.inst 52026.954659 # average overall miss latency

207system.l2c.demand_avg_miss_latency::cpu0.data 52014.291203 # average overall miss latency

207system.l2c.demand_avg_miss_latency::cpu0.data 52014.291049 # average overall miss latency

208system.l2c.demand_avg_miss_latency::cpu1.inst 51965.938865 # average overall miss latency
209system.l2c.demand_avg_miss_latency::cpu1.data 52021.789813 # average overall miss latency

210system.l2c.demand_avg_miss_latency::total 52014.777504 # average overall miss latency

210system.l2c.demand_avg_miss_latency::total 52014.777359 # average overall miss latency

211system.l2c.overall_avg_miss_latency::cpu0.inst 52026.954659 # average overall miss latency

212system.l2c.overall_avg_miss_latency::cpu0.data 52014.291203 # average overall miss latency

212system.l2c.overall_avg_miss_latency::cpu0.data 52014.291049 # average overall miss latency

213system.l2c.overall_avg_miss_latency::cpu1.inst 51965.938865 # average overall miss latency
214system.l2c.overall_avg_miss_latency::cpu1.data 52021.789813 # average overall miss latency

215system.l2c.overall_avg_miss_latency::total 52014.777504 # average overall miss latency

215system.l2c.overall_avg_miss_latency::total 52014.777359 # average overall miss latency

216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
219system.l2c.blocked::no_targets 0 # number of cycles access was blocked
220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
222system.l2c.fast_writes 0 # number of fast writes performed
223system.l2c.cache_copies 0 # number of cache copies performed

--- 5 unchanged lines hidden (view full) ---

229system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
230system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
231system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
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239system.l2c.UpgradeReq_mshr_misses::total 3058 # number of UpgradeReq MSHR misses

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241system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 88 # number of SCUpgradeReq MSHR misses
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262system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19089000 # number of UpgradeReq MSHR miss cycles
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262system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19058000 # number of UpgradeReq MSHR miss cycles
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265system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3520000 # number of SCUpgradeReq MSHR miss cycles
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268system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 843758000 # number of ReadExReq MSHR miss cycles

269system.l2c.ReadExReq_mshr_miss_latency::total 4907956000 # number of ReadExReq MSHR miss cycles

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273system.l2c.demand_mshr_miss_latency::cpu1.data 892646000 # number of demand (read+write) MSHR miss cycles

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275system.l2c.overall_mshr_miss_latency::cpu0.inst 448459000 # number of overall MSHR miss cycles

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279system.l2c.overall_mshr_miss_latency::total 16325068000 # number of overall MSHR miss cycles

279system.l2c.overall_mshr_miss_latency::total 16325228000 # number of overall MSHR miss cycles

280system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 538312030 # number of ReadReq MSHR uncacheable cycles
281system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 264188000 # number of ReadReq MSHR uncacheable cycles
282system.l2c.ReadReq_mshr_uncacheable_latency::total 802500030 # number of ReadReq MSHR uncacheable cycles

283system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 914387000 # number of WriteReq MSHR uncacheable cycles
284system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 465201000 # number of WriteReq MSHR uncacheable cycles
285system.l2c.WriteReq_mshr_uncacheable_latency::total 1379588000 # number of WriteReq MSHR uncacheable cycles
286system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1452699030 # number of overall MSHR uncacheable cycles
287system.l2c.overall_mshr_uncacheable_latency::cpu1.data 729389000 # number of overall MSHR uncacheable cycles
288system.l2c.overall_mshr_uncacheable_latency::total 2182088030 # number of overall MSHR uncacheable cycles

283system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 914384000 # number of WriteReq MSHR uncacheable cycles
284system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 465175000 # number of WriteReq MSHR uncacheable cycles
285system.l2c.WriteReq_mshr_uncacheable_latency::total 1379559000 # number of WriteReq MSHR uncacheable cycles
286system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1452696030 # number of overall MSHR uncacheable cycles
287system.l2c.overall_mshr_uncacheable_latency::cpu1.data 729363000 # number of overall MSHR uncacheable cycles
288system.l2c.overall_mshr_uncacheable_latency::total 2182059030 # number of overall MSHR uncacheable cycles

289system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for ReadReq accesses

290system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.441300 # mshr miss rate for ReadReq accesses

290system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.441289 # mshr miss rate for ReadReq accesses

291system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for ReadReq accesses
292system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002459 # mshr miss rate for ReadReq accesses

293system.l2c.ReadReq_mshr_miss_rate::total 0.135221 # mshr miss rate for ReadReq accesses
294system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.949502 # mshr miss rate for UpgradeReq accesses

293system.l2c.ReadReq_mshr_miss_rate::total 0.135220 # mshr miss rate for ReadReq accesses
294system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.951013 # mshr miss rate for UpgradeReq accesses

295system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.833625 # mshr miss rate for UpgradeReq accesses

296system.l2c.UpgradeReq_mshr_miss_rate::total 0.929354 # mshr miss rate for UpgradeReq accesses

296system.l2c.UpgradeReq_mshr_miss_rate::total 0.930615 # mshr miss rate for UpgradeReq accesses

297system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.794393 # mshr miss rate for SCUpgradeReq accesses
298system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SCUpgradeReq accesses
299system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.789954 # mshr miss rate for SCUpgradeReq accesses

300system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.500530 # mshr miss rate for ReadExReq accesses
301system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.175208 # mshr miss rate for ReadExReq accesses
302system.l2c.ReadExReq_mshr_miss_rate::total 0.379415 # mshr miss rate for ReadExReq accesses

300system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.500258 # mshr miss rate for ReadExReq accesses
301system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.175175 # mshr miss rate for ReadExReq accesses
302system.l2c.ReadExReq_mshr_miss_rate::total 0.379262 # mshr miss rate for ReadExReq accesses

303system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for demand accesses

304system.l2c.demand_mshr_miss_rate::cpu0.data 0.456031 # mshr miss rate for demand accesses

304system.l2c.demand_mshr_miss_rate::cpu0.data 0.455961 # mshr miss rate for demand accesses

305system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for demand accesses

306system.l2c.demand_mshr_miss_rate::cpu1.data 0.036390 # mshr miss rate for demand accesses
307system.l2c.demand_mshr_miss_rate::total 0.167675 # mshr miss rate for demand accesses

306system.l2c.demand_mshr_miss_rate::cpu1.data 0.036388 # mshr miss rate for demand accesses
307system.l2c.demand_mshr_miss_rate::total 0.167666 # mshr miss rate for demand accesses

308system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for overall accesses

309system.l2c.overall_mshr_miss_rate::cpu0.data 0.456031 # mshr miss rate for overall accesses

309system.l2c.overall_mshr_miss_rate::cpu0.data 0.455961 # mshr miss rate for overall accesses

310system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for overall accesses

311system.l2c.overall_mshr_miss_rate::cpu1.data 0.036390 # mshr miss rate for overall accesses
312system.l2c.overall_mshr_miss_rate::total 0.167675 # mshr miss rate for overall accesses

311system.l2c.overall_mshr_miss_rate::cpu1.data 0.036388 # mshr miss rate for overall accesses
312system.l2c.overall_mshr_miss_rate::total 0.167666 # mshr miss rate for overall accesses

313system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average ReadReq mshr miss latency
314system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.629730 # average ReadReq mshr miss latency
315system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average ReadReq mshr miss latency
316system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40369.942197 # average ReadReq mshr miss latency
317system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.302647 # average ReadReq mshr miss latency

318system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.372671 # average UpgradeReq mshr miss latency
319system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40102.941176 # average UpgradeReq mshr miss latency
320system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40050.131062 # average UpgradeReq mshr miss latency

318system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.405887 # average UpgradeReq mshr miss latency
319system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40037.815126 # average UpgradeReq mshr miss latency
320system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40036.625245 # average UpgradeReq mshr miss latency

321system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40223.529412 # average SCUpgradeReq mshr miss latency
322system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency
323system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40109.826590 # average SCUpgradeReq mshr miss latency

324system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736274 # average ReadExReq mshr miss latency

324system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736167 # average ReadExReq mshr miss latency

325system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40001.801546 # average ReadExReq mshr miss latency

326system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575576 # average ReadExReq mshr miss latency

326system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575492 # average ReadExReq mshr miss latency

327system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average overall mshr miss latency

328system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291203 # average overall mshr miss latency

328system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291049 # average overall mshr miss latency

329system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average overall mshr miss latency
330system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency

331system.l2c.demand_avg_mshr_miss_latency::total 40014.971542 # average overall mshr miss latency

331system.l2c.demand_avg_mshr_miss_latency::total 40014.971396 # average overall mshr miss latency

332system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average overall mshr miss latency

333system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291203 # average overall mshr miss latency

333system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291049 # average overall mshr miss latency

334system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average overall mshr miss latency
335system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency

336system.l2c.overall_avg_mshr_miss_latency::total 40014.971542 # average overall mshr miss latency

336system.l2c.overall_avg_mshr_miss_latency::total 40014.971396 # average overall mshr miss latency

337system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
338system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
339system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
340system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
341system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
342system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
343system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
344system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
345system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
346system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
347system.iocache.replacements 41707 # number of replacements

348system.iocache.tagsinuse 1.261560 # Cycle average of tags in use

348system.iocache.tagsinuse 1.261563 # Cycle average of tags in use

349system.iocache.total_refs 0 # Total number of references to valid blocks.
350system.iocache.sampled_refs 41723 # Sample count of references to valid blocks.
351system.iocache.avg_refs 0 # Average number of references to valid blocks.
352system.iocache.warmup_cycle 1747651126000 # Cycle when the warmup percentage was hit.

353system.iocache.occ_blocks::tsunami.ide 1.261560 # Average occupied blocks per requestor
354system.iocache.occ_percent::tsunami.ide 0.078847 # Average percentage of cache occupancy
355system.iocache.occ_percent::total 0.078847 # Average percentage of cache occupancy

353system.iocache.occ_blocks::tsunami.ide 1.261563 # Average occupied blocks per requestor
354system.iocache.occ_percent::tsunami.ide 0.078848 # Average percentage of cache occupancy
355system.iocache.occ_percent::total 0.078848 # Average percentage of cache occupancy

356system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
357system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
358system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
359system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
360system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses
361system.iocache.demand_misses::total 41728 # number of demand (read+write) misses
362system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses
363system.iocache.overall_misses::total 41728 # number of overall misses
364system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles
365system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles

366system.iocache.WriteReq_miss_latency::tsunami.ide 7626020806 # number of WriteReq miss cycles
367system.iocache.WriteReq_miss_latency::total 7626020806 # number of WriteReq miss cycles
368system.iocache.demand_miss_latency::tsunami.ide 7647034804 # number of demand (read+write) miss cycles
369system.iocache.demand_miss_latency::total 7647034804 # number of demand (read+write) miss cycles
370system.iocache.overall_miss_latency::tsunami.ide 7647034804 # number of overall miss cycles
371system.iocache.overall_miss_latency::total 7647034804 # number of overall miss cycles

366system.iocache.WriteReq_miss_latency::tsunami.ide 7626285806 # number of WriteReq miss cycles
367system.iocache.WriteReq_miss_latency::total 7626285806 # number of WriteReq miss cycles
368system.iocache.demand_miss_latency::tsunami.ide 7647299804 # number of demand (read+write) miss cycles
369system.iocache.demand_miss_latency::total 7647299804 # number of demand (read+write) miss cycles
370system.iocache.overall_miss_latency::tsunami.ide 7647299804 # number of overall miss cycles
371system.iocache.overall_miss_latency::total 7647299804 # number of overall miss cycles

372system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
373system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
374system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
375system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
376system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses
377system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses
378system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses
379system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses
380system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
381system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
382system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
383system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
384system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
385system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
386system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
387system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
388system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency
389system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency

390system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183529.572728 # average WriteReq miss latency
391system.iocache.WriteReq_avg_miss_latency::total 183529.572728 # average WriteReq miss latency
392system.iocache.demand_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency
393system.iocache.demand_avg_miss_latency::total 183259.077933 # average overall miss latency
394system.iocache.overall_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency
395system.iocache.overall_avg_miss_latency::total 183259.077933 # average overall miss latency
396system.iocache.blocked_cycles::no_mshrs 7245000 # number of cycles access was blocked

390system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183535.950279 # average WriteReq miss latency
391system.iocache.WriteReq_avg_miss_latency::total 183535.950279 # average WriteReq miss latency
392system.iocache.demand_avg_miss_latency::tsunami.ide 183265.428585 # average overall miss latency
393system.iocache.demand_avg_miss_latency::total 183265.428585 # average overall miss latency
394system.iocache.overall_avg_miss_latency::tsunami.ide 183265.428585 # average overall miss latency
395system.iocache.overall_avg_miss_latency::total 183265.428585 # average overall miss latency
396system.iocache.blocked_cycles::no_mshrs 7316000 # number of cycles access was blocked

397system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked

398system.iocache.blocked::no_mshrs 7076 # number of cycles access was blocked

398system.iocache.blocked::no_mshrs 7050 # number of cycles access was blocked

399system.iocache.blocked::no_targets 0 # number of cycles access was blocked

400system.iocache.avg_blocked_cycles::no_mshrs 1023.883550 # average number of cycles each access was blocked

400system.iocache.avg_blocked_cycles::no_mshrs 1037.730496 # average number of cycles each access was blocked

401system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
402system.iocache.fast_writes 0 # number of fast writes performed
403system.iocache.cache_copies 0 # number of cache copies performed
404system.iocache.writebacks::writebacks 41531 # number of writebacks
405system.iocache.writebacks::total 41531 # number of writebacks
406system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
407system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
408system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
409system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
410system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses
411system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses
412system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses
413system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses
414system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861000 # number of ReadReq MSHR miss cycles
415system.iocache.ReadReq_mshr_miss_latency::total 11861000 # number of ReadReq MSHR miss cycles

416system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465163000 # number of WriteReq MSHR miss cycles
417system.iocache.WriteReq_mshr_miss_latency::total 5465163000 # number of WriteReq MSHR miss cycles
418system.iocache.demand_mshr_miss_latency::tsunami.ide 5477024000 # number of demand (read+write) MSHR miss cycles
419system.iocache.demand_mshr_miss_latency::total 5477024000 # number of demand (read+write) MSHR miss cycles
420system.iocache.overall_mshr_miss_latency::tsunami.ide 5477024000 # number of overall MSHR miss cycles
421system.iocache.overall_mshr_miss_latency::total 5477024000 # number of overall MSHR miss cycles

416system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465428000 # number of WriteReq MSHR miss cycles
417system.iocache.WriteReq_mshr_miss_latency::total 5465428000 # number of WriteReq MSHR miss cycles
418system.iocache.demand_mshr_miss_latency::tsunami.ide 5477289000 # number of demand (read+write) MSHR miss cycles
419system.iocache.demand_mshr_miss_latency::total 5477289000 # number of demand (read+write) MSHR miss cycles
420system.iocache.overall_mshr_miss_latency::tsunami.ide 5477289000 # number of overall MSHR miss cycles
421system.iocache.overall_mshr_miss_latency::total 5477289000 # number of overall MSHR miss cycles

422system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
424system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
425system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455 # average ReadReq mshr miss latency
431system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455 # average ReadReq mshr miss latency

432system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131525.871198 # average WriteReq mshr miss latency
433system.iocache.WriteReq_avg_mshr_miss_latency::total 131525.871198 # average WriteReq mshr miss latency
434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency
435system.iocache.demand_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency
436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency
437system.iocache.overall_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency

432system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131532.248749 # average WriteReq mshr miss latency
433system.iocache.WriteReq_avg_mshr_miss_latency::total 131532.248749 # average WriteReq mshr miss latency
434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131261.718750 # average overall mshr miss latency
435system.iocache.demand_avg_mshr_miss_latency::total 131261.718750 # average overall mshr miss latency
436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131261.718750 # average overall mshr miss latency
437system.iocache.overall_avg_mshr_miss_latency::total 131261.718750 # average overall mshr miss latency

438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
442system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
443system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
444system.disk0.dma_write_txs 395 # Number of DMA write transactions.
445system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
446system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
447system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
448system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
449system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
450system.disk2.dma_write_txs 1 # Number of DMA write transactions.
451system.cpu0.dtb.fetch_hits 0 # ITB hits
452system.cpu0.dtb.fetch_misses 0 # ITB misses
453system.cpu0.dtb.fetch_acv 0 # ITB acv
454system.cpu0.dtb.fetch_accesses 0 # ITB accesses

455system.cpu0.dtb.read_hits 5733478 # DTB read hits

455system.cpu0.dtb.read_hits 5733461 # DTB read hits

456system.cpu0.dtb.read_misses 7687 # DTB read misses
457system.cpu0.dtb.read_acv 174 # DTB read access violations
458system.cpu0.dtb.read_accesses 524201 # DTB read accesses

459system.cpu0.dtb.write_hits 3961950 # DTB write hits

459system.cpu0.dtb.write_hits 3961949 # DTB write hits

460system.cpu0.dtb.write_misses 798 # DTB write misses
461system.cpu0.dtb.write_acv 115 # DTB write access violations
462system.cpu0.dtb.write_accesses 195659 # DTB write accesses

463system.cpu0.dtb.data_hits 9695428 # DTB hits

463system.cpu0.dtb.data_hits 9695410 # DTB hits

464system.cpu0.dtb.data_misses 8485 # DTB misses
465system.cpu0.dtb.data_acv 289 # DTB access violations
466system.cpu0.dtb.data_accesses 719860 # DTB accesses

467system.cpu0.itb.fetch_hits 3214168 # ITB hits

467system.cpu0.itb.fetch_hits 3214179 # ITB hits

468system.cpu0.itb.fetch_misses 3841 # ITB misses
469system.cpu0.itb.fetch_acv 143 # ITB acv

470system.cpu0.itb.fetch_accesses 3218009 # ITB accesses

470system.cpu0.itb.fetch_accesses 3218020 # ITB accesses

471system.cpu0.itb.read_hits 0 # DTB read hits
472system.cpu0.itb.read_misses 0 # DTB read misses
473system.cpu0.itb.read_acv 0 # DTB read access violations
474system.cpu0.itb.read_accesses 0 # DTB read accesses
475system.cpu0.itb.write_hits 0 # DTB write hits
476system.cpu0.itb.write_misses 0 # DTB write misses
477system.cpu0.itb.write_acv 0 # DTB write access violations
478system.cpu0.itb.write_accesses 0 # DTB write accesses
479system.cpu0.itb.data_hits 0 # DTB hits
480system.cpu0.itb.data_misses 0 # DTB misses
481system.cpu0.itb.data_acv 0 # DTB access violations
482system.cpu0.itb.data_accesses 0 # DTB accesses

483system.cpu0.numCycles 3908418212 # number of cpu cycles simulated

483system.cpu0.numCycles 3908419058 # number of cpu cycles simulated

484system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
485system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed

486system.cpu0.committedInsts 36160823 # Number of instructions committed
487system.cpu0.committedOps 36160823 # Number of ops (including micro ops) committed
488system.cpu0.num_int_alu_accesses 33648358 # Number of integer alu accesses

486system.cpu0.committedInsts 36160769 # Number of instructions committed
487system.cpu0.committedOps 36160769 # Number of ops (including micro ops) committed
488system.cpu0.num_int_alu_accesses 33648309 # Number of integer alu accesses

489system.cpu0.num_fp_alu_accesses 143029 # Number of float alu accesses

490system.cpu0.num_func_calls 874754 # number of times a function call or return occured
491system.cpu0.num_conditional_control_insts 4239281 # number of instructions that are conditional controls
492system.cpu0.num_int_insts 33648358 # number of integer instructions

490system.cpu0.num_func_calls 874750 # number of times a function call or return occured
491system.cpu0.num_conditional_control_insts 4239273 # number of instructions that are conditional controls
492system.cpu0.num_int_insts 33648309 # number of integer instructions

493system.cpu0.num_fp_insts 143029 # number of float instructions

494system.cpu0.num_int_register_reads 46246578 # number of times the integer registers were read
495system.cpu0.num_int_register_writes 25142775 # number of times the integer registers were written

494system.cpu0.num_int_register_reads 46246517 # number of times the integer registers were read
495system.cpu0.num_int_register_writes 25142738 # number of times the integer registers were written

496system.cpu0.num_fp_register_reads 70823 # number of times the floating registers were read
497system.cpu0.num_fp_register_writes 71471 # number of times the floating registers were written

498system.cpu0.num_mem_refs 9726012 # number of memory refs
499system.cpu0.num_load_insts 5755191 # Number of load instructions
500system.cpu0.num_store_insts 3970821 # Number of store instructions
501system.cpu0.num_idle_cycles 3741416410.998085 # Number of idle cycles
502system.cpu0.num_busy_cycles 167001801.001915 # Number of busy cycles

498system.cpu0.num_mem_refs 9725994 # number of memory refs
499system.cpu0.num_load_insts 5755174 # Number of load instructions
500system.cpu0.num_store_insts 3970820 # Number of store instructions
501system.cpu0.num_idle_cycles 3741414636.998085 # Number of idle cycles
502system.cpu0.num_busy_cycles 167004421.001915 # Number of busy cycles

503system.cpu0.not_idle_fraction 0.042729 # Percentage of non-idle cycles
504system.cpu0.idle_fraction 0.957271 # Percentage of idle cycles
505system.cpu0.kern.inst.arm 0 # number of arm instructions executed
506system.cpu0.kern.inst.quiesce 4839 # number of quiesce instructions executed

507system.cpu0.kern.inst.hwrei 129052 # number of hwrei instructions executed

507system.cpu0.kern.inst.hwrei 129053 # number of hwrei instructions executed

508system.cpu0.kern.ipl_count::0 41012 38.31% 38.31% # number of times we switched to this ipl
509system.cpu0.kern.ipl_count::21 131 0.12% 38.43% # number of times we switched to this ipl

510system.cpu0.kern.ipl_count::22 1971 1.84% 40.28% # number of times we switched to this ipl

510system.cpu0.kern.ipl_count::22 1971 1.84% 40.27% # number of times we switched to this ipl

511system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl

512system.cpu0.kern.ipl_count::31 63918 59.71% 100.00% # number of times we switched to this ipl
513system.cpu0.kern.ipl_count::total 107049 # number of times we switched to this ipl

512system.cpu0.kern.ipl_count::31 63919 59.71% 100.00% # number of times we switched to this ipl
513system.cpu0.kern.ipl_count::total 107050 # number of times we switched to this ipl

514system.cpu0.kern.ipl_good::0 40581 48.74% 48.74% # number of times we switched to this ipl from a different ipl
515system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl
516system.cpu0.kern.ipl_good::22 1971 2.37% 51.26% # number of times we switched to this ipl from a different ipl
517system.cpu0.kern.ipl_good::30 17 0.02% 51.28% # number of times we switched to this ipl from a different ipl
518system.cpu0.kern.ipl_good::31 40564 48.72% 100.00% # number of times we switched to this ipl from a different ipl
519system.cpu0.kern.ipl_good::total 83264 # number of times we switched to this ipl from a different ipl

520system.cpu0.kern.ipl_ticks::0 1905787793000 97.52% 97.52% # number of cycles we spent at this ipl
521system.cpu0.kern.ipl_ticks::21 88207500 0.00% 97.53% # number of cycles we spent at this ipl
522system.cpu0.kern.ipl_ticks::22 590484500 0.03% 97.56% # number of cycles we spent at this ipl

520system.cpu0.kern.ipl_ticks::0 1905788612000 97.52% 97.52% # number of cycles we spent at this ipl
521system.cpu0.kern.ipl_ticks::21 88224500 0.00% 97.53% # number of cycles we spent at this ipl
522system.cpu0.kern.ipl_ticks::22 590412500 0.03% 97.56% # number of cycles we spent at this ipl

523system.cpu0.kern.ipl_ticks::30 12827000 0.00% 97.56% # number of cycles we spent at this ipl

524system.cpu0.kern.ipl_ticks::31 47728938000 2.44% 100.00% # number of cycles we spent at this ipl
525system.cpu0.kern.ipl_ticks::total 1954208250000 # number of cycles we spent at this ipl

524system.cpu0.kern.ipl_ticks::31 47728597000 2.44% 100.00% # number of cycles we spent at this ipl
525system.cpu0.kern.ipl_ticks::total 1954208673000 # number of cycles we spent at this ipl

526system.cpu0.kern.ipl_used::0 0.989491 # fraction of swpipl calls that actually changed the ipl
527system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
528system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
529system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl

530system.cpu0.kern.ipl_used::31 0.634626 # fraction of swpipl calls that actually changed the ipl
531system.cpu0.kern.ipl_used::total 0.777812 # fraction of swpipl calls that actually changed the ipl

530system.cpu0.kern.ipl_used::31 0.634616 # fraction of swpipl calls that actually changed the ipl
531system.cpu0.kern.ipl_used::total 0.777805 # fraction of swpipl calls that actually changed the ipl

532system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed
533system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed
534system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed
535system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed
536system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed
537system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed
538system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed
539system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed

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563system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
564system.cpu0.kern.callpal::wripir 91 0.08% 0.08% # number of callpals executed
565system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed
566system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed
567system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed
568system.cpu0.kern.callpal::swpctx 1959 1.72% 1.80% # number of callpals executed
569system.cpu0.kern.callpal::tbi 44 0.04% 1.84% # number of callpals executed
570system.cpu0.kern.callpal::wrent 7 0.01% 1.84% # number of callpals executed

571system.cpu0.kern.callpal::swpipl 101151 88.59% 90.44% # number of callpals executed

571system.cpu0.kern.callpal::swpipl 101152 88.59% 90.44% # number of callpals executed

572system.cpu0.kern.callpal::rdps 6620 5.80% 96.24% # number of callpals executed
573system.cpu0.kern.callpal::wrkgp 1 0.00% 96.24% # number of callpals executed
574system.cpu0.kern.callpal::wrusp 4 0.00% 96.24% # number of callpals executed
575system.cpu0.kern.callpal::rdusp 7 0.01% 96.25% # number of callpals executed
576system.cpu0.kern.callpal::whami 2 0.00% 96.25% # number of callpals executed
577system.cpu0.kern.callpal::rti 3778 3.31% 99.56% # number of callpals executed
578system.cpu0.kern.callpal::callsys 356 0.31% 99.87% # number of callpals executed
579system.cpu0.kern.callpal::imb 149 0.13% 100.00% # number of callpals executed

580system.cpu0.kern.callpal::total 114173 # number of callpals executed

580system.cpu0.kern.callpal::total 114174 # number of callpals executed

581system.cpu0.kern.mode_switch::kernel 5323 # number of protection mode switches

582system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches

582system.cpu0.kern.mode_switch::user 1231 # number of protection mode switches

583system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches

584system.cpu0.kern.mode_good::kernel 1229
585system.cpu0.kern.mode_good::user 1230

584system.cpu0.kern.mode_good::kernel 1230
585system.cpu0.kern.mode_good::user 1231

586system.cpu0.kern.mode_good::idle 0

587system.cpu0.kern.mode_switch_good::kernel 0.230885 # fraction of useful protection mode switches

587system.cpu0.kern.mode_switch_good::kernel 0.231073 # fraction of useful protection mode switches

588system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
589system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches

590system.cpu0.kern.mode_switch_good::total 0.375248 # fraction of useful protection mode switches
591system.cpu0.kern.mode_ticks::kernel 1950524029000 99.81% 99.81% # number of ticks spent at the given mode
592system.cpu0.kern.mode_ticks::user 3684214000 0.19% 100.00% # number of ticks spent at the given mode

590system.cpu0.kern.mode_switch_good::total 0.375496 # fraction of useful protection mode switches
591system.cpu0.kern.mode_ticks::kernel 1950522760000 99.81% 99.81% # number of ticks spent at the given mode
592system.cpu0.kern.mode_ticks::user 3685906000 0.19% 100.00% # number of ticks spent at the given mode

593system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
594system.cpu0.kern.swap_context 1960 # number of times the context was actually changed
595system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
596system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
597system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
598system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
599system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
600system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post

--- 17 unchanged lines hidden (view full) ---

618system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
619system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
620system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
621system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
622system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
623system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
624system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
625system.tsunami.ethernet.droppedPackets 0 # number of packets dropped

626system.cpu0.icache.replacements 489211 # number of replacements
627system.cpu0.icache.tagsinuse 508.795621 # Cycle average of tags in use
628system.cpu0.icache.total_refs 35679745 # Total number of references to valid blocks.
629system.cpu0.icache.sampled_refs 489723 # Sample count of references to valid blocks.
630system.cpu0.icache.avg_refs 72.856993 # Average number of references to valid blocks.

626system.cpu0.icache.replacements 489206 # number of replacements
627system.cpu0.icache.tagsinuse 508.795620 # Cycle average of tags in use
628system.cpu0.icache.total_refs 35679696 # Total number of references to valid blocks.
629system.cpu0.icache.sampled_refs 489718 # Sample count of references to valid blocks.
630system.cpu0.icache.avg_refs 72.857636 # Average number of references to valid blocks.

631system.cpu0.icache.warmup_cycle 36113258000 # Cycle when the warmup percentage was hit.

632system.cpu0.icache.occ_blocks::cpu0.inst 508.795621 # Average occupied blocks per requestor

632system.cpu0.icache.occ_blocks::cpu0.inst 508.795620 # Average occupied blocks per requestor

633system.cpu0.icache.occ_percent::cpu0.inst 0.993741 # Average percentage of cache occupancy
634system.cpu0.icache.occ_percent::total 0.993741 # Average percentage of cache occupancy

635system.cpu0.icache.ReadReq_hits::cpu0.inst 35679745 # number of ReadReq hits
636system.cpu0.icache.ReadReq_hits::total 35679745 # number of ReadReq hits
637system.cpu0.icache.demand_hits::cpu0.inst 35679745 # number of demand (read+write) hits
638system.cpu0.icache.demand_hits::total 35679745 # number of demand (read+write) hits
639system.cpu0.icache.overall_hits::cpu0.inst 35679745 # number of overall hits
640system.cpu0.icache.overall_hits::total 35679745 # number of overall hits
641system.cpu0.icache.ReadReq_misses::cpu0.inst 489853 # number of ReadReq misses
642system.cpu0.icache.ReadReq_misses::total 489853 # number of ReadReq misses
643system.cpu0.icache.demand_misses::cpu0.inst 489853 # number of demand (read+write) misses
644system.cpu0.icache.demand_misses::total 489853 # number of demand (read+write) misses
645system.cpu0.icache.overall_misses::cpu0.inst 489853 # number of overall misses
646system.cpu0.icache.overall_misses::total 489853 # number of overall misses
647system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462564000 # number of ReadReq miss cycles
648system.cpu0.icache.ReadReq_miss_latency::total 7462564000 # number of ReadReq miss cycles
649system.cpu0.icache.demand_miss_latency::cpu0.inst 7462564000 # number of demand (read+write) miss cycles
650system.cpu0.icache.demand_miss_latency::total 7462564000 # number of demand (read+write) miss cycles
651system.cpu0.icache.overall_miss_latency::cpu0.inst 7462564000 # number of overall miss cycles
652system.cpu0.icache.overall_miss_latency::total 7462564000 # number of overall miss cycles
653system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169598 # number of ReadReq accesses(hits+misses)
654system.cpu0.icache.ReadReq_accesses::total 36169598 # number of ReadReq accesses(hits+misses)
655system.cpu0.icache.demand_accesses::cpu0.inst 36169598 # number of demand (read+write) accesses
656system.cpu0.icache.demand_accesses::total 36169598 # number of demand (read+write) accesses
657system.cpu0.icache.overall_accesses::cpu0.inst 36169598 # number of overall (read+write) accesses
658system.cpu0.icache.overall_accesses::total 36169598 # number of overall (read+write) accesses

635system.cpu0.icache.ReadReq_hits::cpu0.inst 35679696 # number of ReadReq hits
636system.cpu0.icache.ReadReq_hits::total 35679696 # number of ReadReq hits
637system.cpu0.icache.demand_hits::cpu0.inst 35679696 # number of demand (read+write) hits
638system.cpu0.icache.demand_hits::total 35679696 # number of demand (read+write) hits
639system.cpu0.icache.overall_hits::cpu0.inst 35679696 # number of overall hits
640system.cpu0.icache.overall_hits::total 35679696 # number of overall hits
641system.cpu0.icache.ReadReq_misses::cpu0.inst 489848 # number of ReadReq misses
642system.cpu0.icache.ReadReq_misses::total 489848 # number of ReadReq misses
643system.cpu0.icache.demand_misses::cpu0.inst 489848 # number of demand (read+write) misses
644system.cpu0.icache.demand_misses::total 489848 # number of demand (read+write) misses
645system.cpu0.icache.overall_misses::cpu0.inst 489848 # number of overall misses
646system.cpu0.icache.overall_misses::total 489848 # number of overall misses
647system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462315000 # number of ReadReq miss cycles
648system.cpu0.icache.ReadReq_miss_latency::total 7462315000 # number of ReadReq miss cycles
649system.cpu0.icache.demand_miss_latency::cpu0.inst 7462315000 # number of demand (read+write) miss cycles
650system.cpu0.icache.demand_miss_latency::total 7462315000 # number of demand (read+write) miss cycles
651system.cpu0.icache.overall_miss_latency::cpu0.inst 7462315000 # number of overall miss cycles
652system.cpu0.icache.overall_miss_latency::total 7462315000 # number of overall miss cycles
653system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169544 # number of ReadReq accesses(hits+misses)
654system.cpu0.icache.ReadReq_accesses::total 36169544 # number of ReadReq accesses(hits+misses)
655system.cpu0.icache.demand_accesses::cpu0.inst 36169544 # number of demand (read+write) accesses
656system.cpu0.icache.demand_accesses::total 36169544 # number of demand (read+write) accesses
657system.cpu0.icache.overall_accesses::cpu0.inst 36169544 # number of overall (read+write) accesses
658system.cpu0.icache.overall_accesses::total 36169544 # number of overall (read+write) accesses

659system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013543 # miss rate for ReadReq accesses
660system.cpu0.icache.ReadReq_miss_rate::total 0.013543 # miss rate for ReadReq accesses
661system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013543 # miss rate for demand accesses
662system.cpu0.icache.demand_miss_rate::total 0.013543 # miss rate for demand accesses
663system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013543 # miss rate for overall accesses
664system.cpu0.icache.overall_miss_rate::total 0.013543 # miss rate for overall accesses

665system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15234.292737 # average ReadReq miss latency
666system.cpu0.icache.ReadReq_avg_miss_latency::total 15234.292737 # average ReadReq miss latency
667system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency
668system.cpu0.icache.demand_avg_miss_latency::total 15234.292737 # average overall miss latency
669system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency
670system.cpu0.icache.overall_avg_miss_latency::total 15234.292737 # average overall miss latency

665system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15233.939916 # average ReadReq miss latency
666system.cpu0.icache.ReadReq_avg_miss_latency::total 15233.939916 # average ReadReq miss latency
667system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15233.939916 # average overall miss latency
668system.cpu0.icache.demand_avg_miss_latency::total 15233.939916 # average overall miss latency
669system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15233.939916 # average overall miss latency
670system.cpu0.icache.overall_avg_miss_latency::total 15233.939916 # average overall miss latency

671system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
672system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
673system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
674system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
675system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
676system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
677system.cpu0.icache.fast_writes 0 # number of fast writes performed
678system.cpu0.icache.cache_copies 0 # number of cache copies performed

679system.cpu0.icache.writebacks::writebacks 58 # number of writebacks
680system.cpu0.icache.writebacks::total 58 # number of writebacks
681system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489853 # number of ReadReq MSHR misses
682system.cpu0.icache.ReadReq_mshr_misses::total 489853 # number of ReadReq MSHR misses
683system.cpu0.icache.demand_mshr_misses::cpu0.inst 489853 # number of demand (read+write) MSHR misses
684system.cpu0.icache.demand_mshr_misses::total 489853 # number of demand (read+write) MSHR misses
685system.cpu0.icache.overall_mshr_misses::cpu0.inst 489853 # number of overall MSHR misses
686system.cpu0.icache.overall_mshr_misses::total 489853 # number of overall MSHR misses
687system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992343500 # number of ReadReq MSHR miss cycles
688system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992343500 # number of ReadReq MSHR miss cycles
689system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992343500 # number of demand (read+write) MSHR miss cycles
690system.cpu0.icache.demand_mshr_miss_latency::total 5992343500 # number of demand (read+write) MSHR miss cycles
691system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992343500 # number of overall MSHR miss cycles
692system.cpu0.icache.overall_mshr_miss_latency::total 5992343500 # number of overall MSHR miss cycles

679system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489848 # number of ReadReq MSHR misses
680system.cpu0.icache.ReadReq_mshr_misses::total 489848 # number of ReadReq MSHR misses
681system.cpu0.icache.demand_mshr_misses::cpu0.inst 489848 # number of demand (read+write) MSHR misses
682system.cpu0.icache.demand_mshr_misses::total 489848 # number of demand (read+write) MSHR misses
683system.cpu0.icache.overall_mshr_misses::cpu0.inst 489848 # number of overall MSHR misses
684system.cpu0.icache.overall_mshr_misses::total 489848 # number of overall MSHR misses
685system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992109500 # number of ReadReq MSHR miss cycles
686system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992109500 # number of ReadReq MSHR miss cycles
687system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992109500 # number of demand (read+write) MSHR miss cycles
688system.cpu0.icache.demand_mshr_miss_latency::total 5992109500 # number of demand (read+write) MSHR miss cycles
689system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992109500 # number of overall MSHR miss cycles
690system.cpu0.icache.overall_mshr_miss_latency::total 5992109500 # number of overall MSHR miss cycles

693system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for ReadReq accesses
694system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013543 # mshr miss rate for ReadReq accesses
695system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for demand accesses
696system.cpu0.icache.demand_mshr_miss_rate::total 0.013543 # mshr miss rate for demand accesses
697system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for overall accesses
698system.cpu0.icache.overall_mshr_miss_rate::total 0.013543 # mshr miss rate for overall accesses

691system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for ReadReq accesses
692system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013543 # mshr miss rate for ReadReq accesses
693system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for demand accesses
694system.cpu0.icache.demand_mshr_miss_rate::total 0.013543 # mshr miss rate for demand accesses
695system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for overall accesses
696system.cpu0.icache.overall_mshr_miss_rate::total 0.013543 # mshr miss rate for overall accesses

699system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average ReadReq mshr miss latency
700system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.942332 # average ReadReq mshr miss latency
701system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency
702system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency
703system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency
704system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency

697system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average ReadReq mshr miss latency
698system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.589497 # average ReadReq mshr miss latency
699system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average overall mshr miss latency
700system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.589497 # average overall mshr miss latency
701system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average overall mshr miss latency
702system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.589497 # average overall mshr miss latency

705system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate

703system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate

706system.cpu0.dcache.replacements 817835 # number of replacements
707system.cpu0.dcache.tagsinuse 479.881432 # Cycle average of tags in use
708system.cpu0.dcache.total_refs 8879650 # Total number of references to valid blocks.
709system.cpu0.dcache.sampled_refs 818347 # Sample count of references to valid blocks.
710system.cpu0.dcache.avg_refs 10.850715 # Average number of references to valid blocks.

704system.cpu0.dcache.replacements 817819 # number of replacements
705system.cpu0.dcache.tagsinuse 479.881496 # Cycle average of tags in use
706system.cpu0.dcache.total_refs 8879648 # Total number of references to valid blocks.
707system.cpu0.dcache.sampled_refs 818331 # Sample count of references to valid blocks.
708system.cpu0.dcache.avg_refs 10.850925 # Average number of references to valid blocks.

711system.cpu0.dcache.warmup_cycle 85697000 # Cycle when the warmup percentage was hit.

709system.cpu0.dcache.warmup_cycle 85697000 # Cycle when the warmup percentage was hit.

712system.cpu0.dcache.occ_blocks::cpu0.data 479.881432 # Average occupied blocks per requestor
713system.cpu0.dcache.occ_percent::cpu0.data 0.937268 # Average percentage of cache occupancy
714system.cpu0.dcache.occ_percent::total 0.937268 # Average percentage of cache occupancy
715system.cpu0.dcache.ReadReq_hits::cpu0.data 5008280 # number of ReadReq hits
716system.cpu0.dcache.ReadReq_hits::total 5008280 # number of ReadReq hits
717system.cpu0.dcache.WriteReq_hits::cpu0.data 3627742 # number of WriteReq hits
718system.cpu0.dcache.WriteReq_hits::total 3627742 # number of WriteReq hits

710system.cpu0.dcache.occ_blocks::cpu0.data 479.881496 # Average occupied blocks per requestor
711system.cpu0.dcache.occ_percent::cpu0.data 0.937269 # Average percentage of cache occupancy
712system.cpu0.dcache.occ_percent::total 0.937269 # Average percentage of cache occupancy
713system.cpu0.dcache.ReadReq_hits::cpu0.data 5008276 # number of ReadReq hits
714system.cpu0.dcache.ReadReq_hits::total 5008276 # number of ReadReq hits
715system.cpu0.dcache.WriteReq_hits::cpu0.data 3627744 # number of WriteReq hits
716system.cpu0.dcache.WriteReq_hits::total 3627744 # number of WriteReq hits

719system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117045 # number of LoadLockedReq hits
720system.cpu0.dcache.LoadLockedReq_hits::total 117045 # number of LoadLockedReq hits
721system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122538 # number of StoreCondReq hits
722system.cpu0.dcache.StoreCondReq_hits::total 122538 # number of StoreCondReq hits

717system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117045 # number of LoadLockedReq hits
718system.cpu0.dcache.LoadLockedReq_hits::total 117045 # number of LoadLockedReq hits
719system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122538 # number of StoreCondReq hits
720system.cpu0.dcache.StoreCondReq_hits::total 122538 # number of StoreCondReq hits

723system.cpu0.dcache.demand_hits::cpu0.data 8636022 # number of demand (read+write) hits
724system.cpu0.dcache.demand_hits::total 8636022 # number of demand (read+write) hits
725system.cpu0.dcache.overall_hits::cpu0.data 8636022 # number of overall hits
726system.cpu0.dcache.overall_hits::total 8636022 # number of overall hits
727system.cpu0.dcache.ReadReq_misses::cpu0.data 610615 # number of ReadReq misses
728system.cpu0.dcache.ReadReq_misses::total 610615 # number of ReadReq misses
729system.cpu0.dcache.WriteReq_misses::cpu0.data 207039 # number of WriteReq misses
730system.cpu0.dcache.WriteReq_misses::total 207039 # number of WriteReq misses

721system.cpu0.dcache.demand_hits::cpu0.data 8636020 # number of demand (read+write) hits
722system.cpu0.dcache.demand_hits::total 8636020 # number of demand (read+write) hits
723system.cpu0.dcache.overall_hits::cpu0.data 8636020 # number of overall hits
724system.cpu0.dcache.overall_hits::total 8636020 # number of overall hits
725system.cpu0.dcache.ReadReq_misses::cpu0.data 610602 # number of ReadReq misses
726system.cpu0.dcache.ReadReq_misses::total 610602 # number of ReadReq misses
727system.cpu0.dcache.WriteReq_misses::cpu0.data 207036 # number of WriteReq misses
728system.cpu0.dcache.WriteReq_misses::total 207036 # number of WriteReq misses

731system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6562 # number of LoadLockedReq misses
732system.cpu0.dcache.LoadLockedReq_misses::total 6562 # number of LoadLockedReq misses
733system.cpu0.dcache.StoreCondReq_misses::cpu0.data 580 # number of StoreCondReq misses
734system.cpu0.dcache.StoreCondReq_misses::total 580 # number of StoreCondReq misses

729system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6562 # number of LoadLockedReq misses
730system.cpu0.dcache.LoadLockedReq_misses::total 6562 # number of LoadLockedReq misses
731system.cpu0.dcache.StoreCondReq_misses::cpu0.data 580 # number of StoreCondReq misses
732system.cpu0.dcache.StoreCondReq_misses::total 580 # number of StoreCondReq misses

735system.cpu0.dcache.demand_misses::cpu0.data 817654 # number of demand (read+write) misses
736system.cpu0.dcache.demand_misses::total 817654 # number of demand (read+write) misses
737system.cpu0.dcache.overall_misses::cpu0.data 817654 # number of overall misses
738system.cpu0.dcache.overall_misses::total 817654 # number of overall misses
739system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19940488000 # number of ReadReq miss cycles
740system.cpu0.dcache.ReadReq_miss_latency::total 19940488000 # number of ReadReq miss cycles
741system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7282919000 # number of WriteReq miss cycles
742system.cpu0.dcache.WriteReq_miss_latency::total 7282919000 # number of WriteReq miss cycles
743system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92852000 # number of LoadLockedReq miss cycles
744system.cpu0.dcache.LoadLockedReq_miss_latency::total 92852000 # number of LoadLockedReq miss cycles
745system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8304000 # number of StoreCondReq miss cycles
746system.cpu0.dcache.StoreCondReq_miss_latency::total 8304000 # number of StoreCondReq miss cycles
747system.cpu0.dcache.demand_miss_latency::cpu0.data 27223407000 # number of demand (read+write) miss cycles
748system.cpu0.dcache.demand_miss_latency::total 27223407000 # number of demand (read+write) miss cycles
749system.cpu0.dcache.overall_miss_latency::cpu0.data 27223407000 # number of overall miss cycles
750system.cpu0.dcache.overall_miss_latency::total 27223407000 # number of overall miss cycles
751system.cpu0.dcache.ReadReq_accesses::cpu0.data 5618895 # number of ReadReq accesses(hits+misses)
752system.cpu0.dcache.ReadReq_accesses::total 5618895 # number of ReadReq accesses(hits+misses)
753system.cpu0.dcache.WriteReq_accesses::cpu0.data 3834781 # number of WriteReq accesses(hits+misses)
754system.cpu0.dcache.WriteReq_accesses::total 3834781 # number of WriteReq accesses(hits+misses)

733system.cpu0.dcache.demand_misses::cpu0.data 817638 # number of demand (read+write) misses
734system.cpu0.dcache.demand_misses::total 817638 # number of demand (read+write) misses
735system.cpu0.dcache.overall_misses::cpu0.data 817638 # number of overall misses
736system.cpu0.dcache.overall_misses::total 817638 # number of overall misses
737system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19940652000 # number of ReadReq miss cycles
738system.cpu0.dcache.ReadReq_miss_latency::total 19940652000 # number of ReadReq miss cycles
739system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7284412000 # number of WriteReq miss cycles
740system.cpu0.dcache.WriteReq_miss_latency::total 7284412000 # number of WriteReq miss cycles
741system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92857000 # number of LoadLockedReq miss cycles
742system.cpu0.dcache.LoadLockedReq_miss_latency::total 92857000 # number of LoadLockedReq miss cycles
743system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8303000 # number of StoreCondReq miss cycles
744system.cpu0.dcache.StoreCondReq_miss_latency::total 8303000 # number of StoreCondReq miss cycles
745system.cpu0.dcache.demand_miss_latency::cpu0.data 27225064000 # number of demand (read+write) miss cycles
746system.cpu0.dcache.demand_miss_latency::total 27225064000 # number of demand (read+write) miss cycles
747system.cpu0.dcache.overall_miss_latency::cpu0.data 27225064000 # number of overall miss cycles
748system.cpu0.dcache.overall_miss_latency::total 27225064000 # number of overall miss cycles
749system.cpu0.dcache.ReadReq_accesses::cpu0.data 5618878 # number of ReadReq accesses(hits+misses)
750system.cpu0.dcache.ReadReq_accesses::total 5618878 # number of ReadReq accesses(hits+misses)
751system.cpu0.dcache.WriteReq_accesses::cpu0.data 3834780 # number of WriteReq accesses(hits+misses)
752system.cpu0.dcache.WriteReq_accesses::total 3834780 # number of WriteReq accesses(hits+misses)

755system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123607 # number of LoadLockedReq accesses(hits+misses)
756system.cpu0.dcache.LoadLockedReq_accesses::total 123607 # number of LoadLockedReq accesses(hits+misses)
757system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123118 # number of StoreCondReq accesses(hits+misses)
758system.cpu0.dcache.StoreCondReq_accesses::total 123118 # number of StoreCondReq accesses(hits+misses)

753system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123607 # number of LoadLockedReq accesses(hits+misses)
754system.cpu0.dcache.LoadLockedReq_accesses::total 123607 # number of LoadLockedReq accesses(hits+misses)
755system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123118 # number of StoreCondReq accesses(hits+misses)
756system.cpu0.dcache.StoreCondReq_accesses::total 123118 # number of StoreCondReq accesses(hits+misses)

759system.cpu0.dcache.demand_accesses::cpu0.data 9453676 # number of demand (read+write) accesses
760system.cpu0.dcache.demand_accesses::total 9453676 # number of demand (read+write) accesses
761system.cpu0.dcache.overall_accesses::cpu0.data 9453676 # number of overall (read+write) accesses
762system.cpu0.dcache.overall_accesses::total 9453676 # number of overall (read+write) accesses
763system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108672 # miss rate for ReadReq accesses
764system.cpu0.dcache.ReadReq_miss_rate::total 0.108672 # miss rate for ReadReq accesses
765system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.053990 # miss rate for WriteReq accesses
766system.cpu0.dcache.WriteReq_miss_rate::total 0.053990 # miss rate for WriteReq accesses

757system.cpu0.dcache.demand_accesses::cpu0.data 9453658 # number of demand (read+write) accesses
758system.cpu0.dcache.demand_accesses::total 9453658 # number of demand (read+write) accesses
759system.cpu0.dcache.overall_accesses::cpu0.data 9453658 # number of overall (read+write) accesses
760system.cpu0.dcache.overall_accesses::total 9453658 # number of overall (read+write) accesses
761system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108670 # miss rate for ReadReq accesses
762system.cpu0.dcache.ReadReq_miss_rate::total 0.108670 # miss rate for ReadReq accesses
763system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.053989 # miss rate for WriteReq accesses
764system.cpu0.dcache.WriteReq_miss_rate::total 0.053989 # miss rate for WriteReq accesses

767system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053088 # miss rate for LoadLockedReq accesses
768system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053088 # miss rate for LoadLockedReq accesses
769system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004711 # miss rate for StoreCondReq accesses
770system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004711 # miss rate for StoreCondReq accesses

765system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053088 # miss rate for LoadLockedReq accesses
766system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053088 # miss rate for LoadLockedReq accesses
767system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004711 # miss rate for StoreCondReq accesses
768system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004711 # miss rate for StoreCondReq accesses

771system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086491 # miss rate for demand accesses
772system.cpu0.dcache.demand_miss_rate::total 0.086491 # miss rate for demand accesses
773system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086491 # miss rate for overall accesses
774system.cpu0.dcache.overall_miss_rate::total 0.086491 # miss rate for overall accesses
775system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32656.400514 # average ReadReq miss latency
776system.cpu0.dcache.ReadReq_avg_miss_latency::total 32656.400514 # average ReadReq miss latency
777system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35176.556108 # average WriteReq miss latency
778system.cpu0.dcache.WriteReq_avg_miss_latency::total 35176.556108 # average WriteReq miss latency
779system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14149.954282 # average LoadLockedReq miss latency
780system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14149.954282 # average LoadLockedReq miss latency
781system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14317.241379 # average StoreCondReq miss latency
782system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14317.241379 # average StoreCondReq miss latency
783system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency
784system.cpu0.dcache.demand_avg_miss_latency::total 33294.531672 # average overall miss latency
785system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency
786system.cpu0.dcache.overall_avg_miss_latency::total 33294.531672 # average overall miss latency

769system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086489 # miss rate for demand accesses
770system.cpu0.dcache.demand_miss_rate::total 0.086489 # miss rate for demand accesses
771system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086489 # miss rate for overall accesses
772system.cpu0.dcache.overall_miss_rate::total 0.086489 # miss rate for overall accesses
773system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32657.364372 # average ReadReq miss latency
774system.cpu0.dcache.ReadReq_avg_miss_latency::total 32657.364372 # average ReadReq miss latency
775system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35184.277131 # average WriteReq miss latency
776system.cpu0.dcache.WriteReq_avg_miss_latency::total 35184.277131 # average WriteReq miss latency
777system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14150.716245 # average LoadLockedReq miss latency
778system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14150.716245 # average LoadLockedReq miss latency
779system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14315.517241 # average StoreCondReq miss latency
780system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14315.517241 # average StoreCondReq miss latency
781system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33297.209768 # average overall miss latency
782system.cpu0.dcache.demand_avg_miss_latency::total 33297.209768 # average overall miss latency
783system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33297.209768 # average overall miss latency
784system.cpu0.dcache.overall_avg_miss_latency::total 33297.209768 # average overall miss latency

787system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
788system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
789system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
790system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
791system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
792system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
793system.cpu0.dcache.fast_writes 0 # number of fast writes performed
794system.cpu0.dcache.cache_copies 0 # number of cache copies performed

785system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
786system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
787system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
788system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
789system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
790system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
791system.cpu0.dcache.fast_writes 0 # number of fast writes performed
792system.cpu0.dcache.cache_copies 0 # number of cache copies performed

795system.cpu0.dcache.writebacks::writebacks 359699 # number of writebacks
796system.cpu0.dcache.writebacks::total 359699 # number of writebacks
797system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 610615 # number of ReadReq MSHR misses
798system.cpu0.dcache.ReadReq_mshr_misses::total 610615 # number of ReadReq MSHR misses
799system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 207039 # number of WriteReq MSHR misses
800system.cpu0.dcache.WriteReq_mshr_misses::total 207039 # number of WriteReq MSHR misses

793system.cpu0.dcache.writebacks::writebacks 359687 # number of writebacks
794system.cpu0.dcache.writebacks::total 359687 # number of writebacks
795system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 610602 # number of ReadReq MSHR misses
796system.cpu0.dcache.ReadReq_mshr_misses::total 610602 # number of ReadReq MSHR misses
797system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 207036 # number of WriteReq MSHR misses
798system.cpu0.dcache.WriteReq_mshr_misses::total 207036 # number of WriteReq MSHR misses

801system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6562 # number of LoadLockedReq MSHR misses
802system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6562 # number of LoadLockedReq MSHR misses
803system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 580 # number of StoreCondReq MSHR misses
804system.cpu0.dcache.StoreCondReq_mshr_misses::total 580 # number of StoreCondReq MSHR misses

799system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6562 # number of LoadLockedReq MSHR misses
800system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6562 # number of LoadLockedReq MSHR misses
801system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 580 # number of StoreCondReq MSHR misses
802system.cpu0.dcache.StoreCondReq_mshr_misses::total 580 # number of StoreCondReq MSHR misses

805system.cpu0.dcache.demand_mshr_misses::cpu0.data 817654 # number of demand (read+write) MSHR misses
806system.cpu0.dcache.demand_mshr_misses::total 817654 # number of demand (read+write) MSHR misses
807system.cpu0.dcache.overall_mshr_misses::cpu0.data 817654 # number of overall MSHR misses
808system.cpu0.dcache.overall_mshr_misses::total 817654 # number of overall MSHR misses
809system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18108577524 # number of ReadReq MSHR miss cycles
810system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18108577524 # number of ReadReq MSHR miss cycles
811system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6661800002 # number of WriteReq MSHR miss cycles
812system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6661800002 # number of WriteReq MSHR miss cycles
813system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73166000 # number of LoadLockedReq MSHR miss cycles
814system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73166000 # number of LoadLockedReq MSHR miss cycles
815system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 6564000 # number of StoreCondReq MSHR miss cycles
816system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 6564000 # number of StoreCondReq MSHR miss cycles
817system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24770377526 # number of demand (read+write) MSHR miss cycles
818system.cpu0.dcache.demand_mshr_miss_latency::total 24770377526 # number of demand (read+write) MSHR miss cycles
819system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24770377526 # number of overall MSHR miss cycles
820system.cpu0.dcache.overall_mshr_miss_latency::total 24770377526 # number of overall MSHR miss cycles
821system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601208500 # number of ReadReq MSHR uncacheable cycles
822system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601208500 # number of ReadReq MSHR uncacheable cycles
823system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014438500 # number of WriteReq MSHR uncacheable cycles
824system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014438500 # number of WriteReq MSHR uncacheable cycles
825system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615647000 # number of overall MSHR uncacheable cycles
826system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615647000 # number of overall MSHR uncacheable cycles
827system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108672 # mshr miss rate for ReadReq accesses
828system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108672 # mshr miss rate for ReadReq accesses
829system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053990 # mshr miss rate for WriteReq accesses
830system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053990 # mshr miss rate for WriteReq accesses

803system.cpu0.dcache.demand_mshr_misses::cpu0.data 817638 # number of demand (read+write) MSHR misses
804system.cpu0.dcache.demand_mshr_misses::total 817638 # number of demand (read+write) MSHR misses
805system.cpu0.dcache.overall_mshr_misses::cpu0.data 817638 # number of overall MSHR misses
806system.cpu0.dcache.overall_mshr_misses::total 817638 # number of overall MSHR misses
807system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18108780524 # number of ReadReq MSHR miss cycles
808system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18108780524 # number of ReadReq MSHR miss cycles
809system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6663302002 # number of WriteReq MSHR miss cycles
810system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6663302002 # number of WriteReq MSHR miss cycles
811system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73171000 # number of LoadLockedReq MSHR miss cycles
812system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73171000 # number of LoadLockedReq MSHR miss cycles
813system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 6563000 # number of StoreCondReq MSHR miss cycles
814system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 6563000 # number of StoreCondReq MSHR miss cycles
815system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24772082526 # number of demand (read+write) MSHR miss cycles
816system.cpu0.dcache.demand_mshr_miss_latency::total 24772082526 # number of demand (read+write) MSHR miss cycles
817system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24772082526 # number of overall MSHR miss cycles
818system.cpu0.dcache.overall_mshr_miss_latency::total 24772082526 # number of overall MSHR miss cycles
819system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601210500 # number of ReadReq MSHR uncacheable cycles
820system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601210500 # number of ReadReq MSHR uncacheable cycles
821system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014423500 # number of WriteReq MSHR uncacheable cycles
822system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014423500 # number of WriteReq MSHR uncacheable cycles
823system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615634000 # number of overall MSHR uncacheable cycles
824system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615634000 # number of overall MSHR uncacheable cycles
825system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108670 # mshr miss rate for ReadReq accesses
826system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108670 # mshr miss rate for ReadReq accesses
827system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053989 # mshr miss rate for WriteReq accesses
828system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053989 # mshr miss rate for WriteReq accesses

831system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053088 # mshr miss rate for LoadLockedReq accesses
832system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053088 # mshr miss rate for LoadLockedReq accesses
833system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004711 # mshr miss rate for StoreCondReq accesses
834system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004711 # mshr miss rate for StoreCondReq accesses

829system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053088 # mshr miss rate for LoadLockedReq accesses
830system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053088 # mshr miss rate for LoadLockedReq accesses
831system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004711 # mshr miss rate for StoreCondReq accesses
832system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004711 # mshr miss rate for StoreCondReq accesses

835system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for demand accesses
836system.cpu0.dcache.demand_mshr_miss_rate::total 0.086491 # mshr miss rate for demand accesses
837system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for overall accesses
838system.cpu0.dcache.overall_mshr_miss_rate::total 0.086491 # mshr miss rate for overall accesses
839system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29656.293285 # average ReadReq mshr miss latency
840system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29656.293285 # average ReadReq mshr miss latency
841system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32176.546457 # average WriteReq mshr miss latency
842system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32176.546457 # average WriteReq mshr miss latency
843system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11149.954282 # average LoadLockedReq mshr miss latency
844system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11149.954282 # average LoadLockedReq mshr miss latency
845system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11317.241379 # average StoreCondReq mshr miss latency
846system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11317.241379 # average StoreCondReq mshr miss latency
847system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency
848system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency
849system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency
850system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency

833system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086489 # mshr miss rate for demand accesses
834system.cpu0.dcache.demand_mshr_miss_rate::total 0.086489 # mshr miss rate for demand accesses
835system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086489 # mshr miss rate for overall accesses
836system.cpu0.dcache.overall_mshr_miss_rate::total 0.086489 # mshr miss rate for overall accesses
837system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29657.257140 # average ReadReq mshr miss latency
838system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29657.257140 # average ReadReq mshr miss latency
839system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32184.267480 # average WriteReq mshr miss latency
840system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32184.267480 # average WriteReq mshr miss latency
841system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11150.716245 # average LoadLockedReq mshr miss latency
842system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11150.716245 # average LoadLockedReq mshr miss latency
843system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11315.517241 # average StoreCondReq mshr miss latency
844system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11315.517241 # average StoreCondReq mshr miss latency
845system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30297.127245 # average overall mshr miss latency
846system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30297.127245 # average overall mshr miss latency
847system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30297.127245 # average overall mshr miss latency
848system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30297.127245 # average overall mshr miss latency

851system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
852system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
853system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
854system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
855system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
856system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
857system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
858system.cpu1.dtb.fetch_hits 0 # ITB hits

--- 23 unchanged lines hidden (view full) ---

882system.cpu1.itb.write_hits 0 # DTB write hits
883system.cpu1.itb.write_misses 0 # DTB write misses
884system.cpu1.itb.write_acv 0 # DTB write access violations
885system.cpu1.itb.write_accesses 0 # DTB write accesses
886system.cpu1.itb.data_hits 0 # DTB hits
887system.cpu1.itb.data_misses 0 # DTB misses
888system.cpu1.itb.data_acv 0 # DTB access violations
889system.cpu1.itb.data_accesses 0 # DTB accesses

849system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
850system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
851system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
852system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
853system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
854system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
855system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
856system.cpu1.dtb.fetch_hits 0 # ITB hits

--- 23 unchanged lines hidden (view full) ---

880system.cpu1.itb.write_hits 0 # DTB write hits
881system.cpu1.itb.write_misses 0 # DTB write misses
882system.cpu1.itb.write_acv 0 # DTB write access violations
883system.cpu1.itb.write_accesses 0 # DTB write accesses
884system.cpu1.itb.data_hits 0 # DTB hits
885system.cpu1.itb.data_misses 0 # DTB misses
886system.cpu1.itb.data_acv 0 # DTB access violations
887system.cpu1.itb.data_accesses 0 # DTB accesses

890system.cpu1.numCycles 3908222380 # number of cpu cycles simulated

888system.cpu1.numCycles 3908222400 # number of cpu cycles simulated

891system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
892system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
893system.cpu1.committedInsts 23256004 # Number of instructions committed
894system.cpu1.committedOps 23256004 # Number of ops (including micro ops) committed
895system.cpu1.num_int_alu_accesses 21401422 # Number of integer alu accesses
896system.cpu1.num_fp_alu_accesses 186242 # Number of float alu accesses
897system.cpu1.num_func_calls 709842 # number of times a function call or return occured
898system.cpu1.num_conditional_control_insts 2519926 # number of instructions that are conditional controls
899system.cpu1.num_int_insts 21401422 # number of integer instructions
900system.cpu1.num_fp_insts 186242 # number of float instructions
901system.cpu1.num_int_register_reads 29248159 # number of times the integer registers were read
902system.cpu1.num_int_register_writes 15707401 # number of times the integer registers were written
903system.cpu1.num_fp_register_reads 95219 # number of times the floating registers were read
904system.cpu1.num_fp_register_writes 97489 # number of times the floating registers were written
905system.cpu1.num_mem_refs 6725970 # number of memory refs
906system.cpu1.num_load_insts 3973767 # Number of load instructions
907system.cpu1.num_store_insts 2752203 # Number of store instructions

889system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
890system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
891system.cpu1.committedInsts 23256004 # Number of instructions committed
892system.cpu1.committedOps 23256004 # Number of ops (including micro ops) committed
893system.cpu1.num_int_alu_accesses 21401422 # Number of integer alu accesses
894system.cpu1.num_fp_alu_accesses 186242 # Number of float alu accesses
895system.cpu1.num_func_calls 709842 # number of times a function call or return occured
896system.cpu1.num_conditional_control_insts 2519926 # number of instructions that are conditional controls
897system.cpu1.num_int_insts 21401422 # number of integer instructions
898system.cpu1.num_fp_insts 186242 # number of float instructions
899system.cpu1.num_int_register_reads 29248159 # number of times the integer registers were read
900system.cpu1.num_int_register_writes 15707401 # number of times the integer registers were written
901system.cpu1.num_fp_register_reads 95219 # number of times the floating registers were read
902system.cpu1.num_fp_register_writes 97489 # number of times the floating registers were written
903system.cpu1.num_mem_refs 6725970 # number of memory refs
904system.cpu1.num_load_insts 3973767 # Number of load instructions
905system.cpu1.num_store_insts 2752203 # Number of store instructions

908system.cpu1.num_idle_cycles 3808684025.637170 # Number of idle cycles
909system.cpu1.num_busy_cycles 99538354.362830 # Number of busy cycles

906system.cpu1.num_idle_cycles 3808683702.691761 # Number of idle cycles
907system.cpu1.num_busy_cycles 99538697.308239 # Number of busy cycles

910system.cpu1.not_idle_fraction 0.025469 # Percentage of non-idle cycles
911system.cpu1.idle_fraction 0.974531 # Percentage of idle cycles
912system.cpu1.kern.inst.arm 0 # number of arm instructions executed
913system.cpu1.kern.inst.quiesce 3849 # number of quiesce instructions executed
914system.cpu1.kern.inst.hwrei 109556 # number of hwrei instructions executed
915system.cpu1.kern.ipl_count::0 40729 40.60% 40.60% # number of times we switched to this ipl
916system.cpu1.kern.ipl_count::22 1966 1.96% 42.56% # number of times we switched to this ipl
917system.cpu1.kern.ipl_count::30 91 0.09% 42.65% # number of times we switched to this ipl
918system.cpu1.kern.ipl_count::31 57540 57.35% 100.00% # number of times we switched to this ipl
919system.cpu1.kern.ipl_count::total 100326 # number of times we switched to this ipl
920system.cpu1.kern.ipl_good::0 39783 48.79% 48.79% # number of times we switched to this ipl from a different ipl
921system.cpu1.kern.ipl_good::22 1966 2.41% 51.21% # number of times we switched to this ipl from a different ipl
922system.cpu1.kern.ipl_good::30 91 0.11% 51.32% # number of times we switched to this ipl from a different ipl
923system.cpu1.kern.ipl_good::31 39692 48.68% 100.00% # number of times we switched to this ipl from a different ipl
924system.cpu1.kern.ipl_good::total 81532 # number of times we switched to this ipl from a different ipl

908system.cpu1.not_idle_fraction 0.025469 # Percentage of non-idle cycles
909system.cpu1.idle_fraction 0.974531 # Percentage of idle cycles
910system.cpu1.kern.inst.arm 0 # number of arm instructions executed
911system.cpu1.kern.inst.quiesce 3849 # number of quiesce instructions executed
912system.cpu1.kern.inst.hwrei 109556 # number of hwrei instructions executed
913system.cpu1.kern.ipl_count::0 40729 40.60% 40.60% # number of times we switched to this ipl
914system.cpu1.kern.ipl_count::22 1966 1.96% 42.56% # number of times we switched to this ipl
915system.cpu1.kern.ipl_count::30 91 0.09% 42.65% # number of times we switched to this ipl
916system.cpu1.kern.ipl_count::31 57540 57.35% 100.00% # number of times we switched to this ipl
917system.cpu1.kern.ipl_count::total 100326 # number of times we switched to this ipl
918system.cpu1.kern.ipl_good::0 39783 48.79% 48.79% # number of times we switched to this ipl from a different ipl
919system.cpu1.kern.ipl_good::22 1966 2.41% 51.21% # number of times we switched to this ipl from a different ipl
920system.cpu1.kern.ipl_good::30 91 0.11% 51.32% # number of times we switched to this ipl from a different ipl
921system.cpu1.kern.ipl_good::31 39692 48.68% 100.00% # number of times we switched to this ipl from a different ipl
922system.cpu1.kern.ipl_good::total 81532 # number of times we switched to this ipl from a different ipl

925system.cpu1.kern.ipl_ticks::0 1901560823500 97.31% 97.31% # number of cycles we spent at this ipl
926system.cpu1.kern.ipl_ticks::22 537428500 0.03% 97.34% # number of cycles we spent at this ipl

923system.cpu1.kern.ipl_ticks::0 1901560916500 97.31% 97.31% # number of cycles we spent at this ipl
924system.cpu1.kern.ipl_ticks::22 537337500 0.03% 97.34% # number of cycles we spent at this ipl

927system.cpu1.kern.ipl_ticks::30 59036000 0.00% 97.34% # number of cycles we spent at this ipl

925system.cpu1.kern.ipl_ticks::30 59036000 0.00% 97.34% # number of cycles we spent at this ipl

928system.cpu1.kern.ipl_ticks::31 51953872000 2.66% 100.00% # number of cycles we spent at this ipl
929system.cpu1.kern.ipl_ticks::total 1954111160000 # number of cycles we spent at this ipl

926system.cpu1.kern.ipl_ticks::31 51953880000 2.66% 100.00% # number of cycles we spent at this ipl
927system.cpu1.kern.ipl_ticks::total 1954111170000 # number of cycles we spent at this ipl

930system.cpu1.kern.ipl_used::0 0.976773 # fraction of swpipl calls that actually changed the ipl
931system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
932system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
933system.cpu1.kern.ipl_used::31 0.689816 # fraction of swpipl calls that actually changed the ipl
934system.cpu1.kern.ipl_used::total 0.812671 # fraction of swpipl calls that actually changed the ipl
935system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed
936system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed
937system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed

--- 39 unchanged lines hidden (view full) ---

977system.cpu1.kern.mode_switch::idle 2038 # number of protection mode switches
978system.cpu1.kern.mode_good::kernel 568
979system.cpu1.kern.mode_good::user 515
980system.cpu1.kern.mode_good::idle 53
981system.cpu1.kern.mode_switch_good::kernel 0.200282 # fraction of useful protection mode switches
982system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
983system.cpu1.kern.mode_switch_good::idle 0.026006 # fraction of useful protection mode switches
984system.cpu1.kern.mode_switch_good::total 0.210800 # fraction of useful protection mode switches

928system.cpu1.kern.ipl_used::0 0.976773 # fraction of swpipl calls that actually changed the ipl
929system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
930system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
931system.cpu1.kern.ipl_used::31 0.689816 # fraction of swpipl calls that actually changed the ipl
932system.cpu1.kern.ipl_used::total 0.812671 # fraction of swpipl calls that actually changed the ipl
933system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed
934system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed
935system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed

--- 39 unchanged lines hidden (view full) ---

975system.cpu1.kern.mode_switch::idle 2038 # number of protection mode switches
976system.cpu1.kern.mode_good::kernel 568
977system.cpu1.kern.mode_good::user 515
978system.cpu1.kern.mode_good::idle 53
979system.cpu1.kern.mode_switch_good::kernel 0.200282 # fraction of useful protection mode switches
980system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
981system.cpu1.kern.mode_switch_good::idle 0.026006 # fraction of useful protection mode switches
982system.cpu1.kern.mode_switch_good::total 0.210800 # fraction of useful protection mode switches

985system.cpu1.kern.mode_ticks::kernel 72316980000 3.70% 3.70% # number of ticks spent at the given mode
986system.cpu1.kern.mode_ticks::user 1607803000 0.08% 3.78% # number of ticks spent at the given mode
987system.cpu1.kern.mode_ticks::idle 1879348629000 96.22% 100.00% # number of ticks spent at the given mode

983system.cpu1.kern.mode_ticks::kernel 72317077000 3.70% 3.70% # number of ticks spent at the given mode
984system.cpu1.kern.mode_ticks::user 1608073000 0.08% 3.78% # number of ticks spent at the given mode
985system.cpu1.kern.mode_ticks::idle 1879348652000 96.22% 100.00% # number of ticks spent at the given mode

988system.cpu1.kern.swap_context 2293 # number of times the context was actually changed

986system.cpu1.kern.swap_context 2293 # number of times the context was actually changed

989system.cpu1.icache.replacements 513695 # number of replacements
990system.cpu1.icache.tagsinuse 501.294136 # Cycle average of tags in use
991system.cpu1.icache.total_refs 22744962 # Total number of references to valid blocks.
992system.cpu1.icache.sampled_refs 514207 # Sample count of references to valid blocks.
993system.cpu1.icache.avg_refs 44.233085 # Average number of references to valid blocks.

987system.cpu1.icache.replacements 513692 # number of replacements
988system.cpu1.icache.tagsinuse 501.294138 # Cycle average of tags in use
989system.cpu1.icache.total_refs 22744965 # Total number of references to valid blocks.
990system.cpu1.icache.sampled_refs 514204 # Sample count of references to valid blocks.
991system.cpu1.icache.avg_refs 44.233349 # Average number of references to valid blocks.

994system.cpu1.icache.warmup_cycle 96225204000 # Cycle when the warmup percentage was hit.

992system.cpu1.icache.warmup_cycle 96225204000 # Cycle when the warmup percentage was hit.

995system.cpu1.icache.occ_blocks::cpu1.inst 501.294136 # Average occupied blocks per requestor

993system.cpu1.icache.occ_blocks::cpu1.inst 501.294138 # Average occupied blocks per requestor

996system.cpu1.icache.occ_percent::cpu1.inst 0.979090 # Average percentage of cache occupancy
997system.cpu1.icache.occ_percent::total 0.979090 # Average percentage of cache occupancy

994system.cpu1.icache.occ_percent::cpu1.inst 0.979090 # Average percentage of cache occupancy
995system.cpu1.icache.occ_percent::total 0.979090 # Average percentage of cache occupancy

998system.cpu1.icache.ReadReq_hits::cpu1.inst 22744962 # number of ReadReq hits
999system.cpu1.icache.ReadReq_hits::total 22744962 # number of ReadReq hits
1000system.cpu1.icache.demand_hits::cpu1.inst 22744962 # number of demand (read+write) hits
1001system.cpu1.icache.demand_hits::total 22744962 # number of demand (read+write) hits
1002system.cpu1.icache.overall_hits::cpu1.inst 22744962 # number of overall hits
1003system.cpu1.icache.overall_hits::total 22744962 # number of overall hits
1004system.cpu1.icache.ReadReq_misses::cpu1.inst 514232 # number of ReadReq misses
1005system.cpu1.icache.ReadReq_misses::total 514232 # number of ReadReq misses
1006system.cpu1.icache.demand_misses::cpu1.inst 514232 # number of demand (read+write) misses
1007system.cpu1.icache.demand_misses::total 514232 # number of demand (read+write) misses
1008system.cpu1.icache.overall_misses::cpu1.inst 514232 # number of overall misses
1009system.cpu1.icache.overall_misses::total 514232 # number of overall misses
1010system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7551962500 # number of ReadReq miss cycles
1011system.cpu1.icache.ReadReq_miss_latency::total 7551962500 # number of ReadReq miss cycles
1012system.cpu1.icache.demand_miss_latency::cpu1.inst 7551962500 # number of demand (read+write) miss cycles
1013system.cpu1.icache.demand_miss_latency::total 7551962500 # number of demand (read+write) miss cycles
1014system.cpu1.icache.overall_miss_latency::cpu1.inst 7551962500 # number of overall miss cycles
1015system.cpu1.icache.overall_miss_latency::total 7551962500 # number of overall miss cycles

996system.cpu1.icache.ReadReq_hits::cpu1.inst 22744965 # number of ReadReq hits
997system.cpu1.icache.ReadReq_hits::total 22744965 # number of ReadReq hits
998system.cpu1.icache.demand_hits::cpu1.inst 22744965 # number of demand (read+write) hits
999system.cpu1.icache.demand_hits::total 22744965 # number of demand (read+write) hits
1000system.cpu1.icache.overall_hits::cpu1.inst 22744965 # number of overall hits
1001system.cpu1.icache.overall_hits::total 22744965 # number of overall hits
1002system.cpu1.icache.ReadReq_misses::cpu1.inst 514229 # number of ReadReq misses
1003system.cpu1.icache.ReadReq_misses::total 514229 # number of ReadReq misses
1004system.cpu1.icache.demand_misses::cpu1.inst 514229 # number of demand (read+write) misses
1005system.cpu1.icache.demand_misses::total 514229 # number of demand (read+write) misses
1006system.cpu1.icache.overall_misses::cpu1.inst 514229 # number of overall misses
1007system.cpu1.icache.overall_misses::total 514229 # number of overall misses
1008system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7551928500 # number of ReadReq miss cycles
1009system.cpu1.icache.ReadReq_miss_latency::total 7551928500 # number of ReadReq miss cycles
1010system.cpu1.icache.demand_miss_latency::cpu1.inst 7551928500 # number of demand (read+write) miss cycles
1011system.cpu1.icache.demand_miss_latency::total 7551928500 # number of demand (read+write) miss cycles
1012system.cpu1.icache.overall_miss_latency::cpu1.inst 7551928500 # number of overall miss cycles
1013system.cpu1.icache.overall_miss_latency::total 7551928500 # number of overall miss cycles

1016system.cpu1.icache.ReadReq_accesses::cpu1.inst 23259194 # number of ReadReq accesses(hits+misses)
1017system.cpu1.icache.ReadReq_accesses::total 23259194 # number of ReadReq accesses(hits+misses)
1018system.cpu1.icache.demand_accesses::cpu1.inst 23259194 # number of demand (read+write) accesses
1019system.cpu1.icache.demand_accesses::total 23259194 # number of demand (read+write) accesses
1020system.cpu1.icache.overall_accesses::cpu1.inst 23259194 # number of overall (read+write) accesses
1021system.cpu1.icache.overall_accesses::total 23259194 # number of overall (read+write) accesses
1022system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022109 # miss rate for ReadReq accesses
1023system.cpu1.icache.ReadReq_miss_rate::total 0.022109 # miss rate for ReadReq accesses
1024system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022109 # miss rate for demand accesses
1025system.cpu1.icache.demand_miss_rate::total 0.022109 # miss rate for demand accesses
1026system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022109 # miss rate for overall accesses
1027system.cpu1.icache.overall_miss_rate::total 0.022109 # miss rate for overall accesses

1014system.cpu1.icache.ReadReq_accesses::cpu1.inst 23259194 # number of ReadReq accesses(hits+misses)
1015system.cpu1.icache.ReadReq_accesses::total 23259194 # number of ReadReq accesses(hits+misses)
1016system.cpu1.icache.demand_accesses::cpu1.inst 23259194 # number of demand (read+write) accesses
1017system.cpu1.icache.demand_accesses::total 23259194 # number of demand (read+write) accesses
1018system.cpu1.icache.overall_accesses::cpu1.inst 23259194 # number of overall (read+write) accesses
1019system.cpu1.icache.overall_accesses::total 23259194 # number of overall (read+write) accesses
1020system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022109 # miss rate for ReadReq accesses
1021system.cpu1.icache.ReadReq_miss_rate::total 0.022109 # miss rate for ReadReq accesses
1022system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022109 # miss rate for demand accesses
1023system.cpu1.icache.demand_miss_rate::total 0.022109 # miss rate for demand accesses
1024system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022109 # miss rate for overall accesses
1025system.cpu1.icache.overall_miss_rate::total 0.022109 # miss rate for overall accesses

1028system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.905389 # average ReadReq miss latency
1029system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.905389 # average ReadReq miss latency
1030system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency
1031system.cpu1.icache.demand_avg_miss_latency::total 14685.905389 # average overall miss latency
1032system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency
1033system.cpu1.icache.overall_avg_miss_latency::total 14685.905389 # average overall miss latency

1026system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.924948 # average ReadReq miss latency
1027system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.924948 # average ReadReq miss latency
1028system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.924948 # average overall miss latency
1029system.cpu1.icache.demand_avg_miss_latency::total 14685.924948 # average overall miss latency
1030system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.924948 # average overall miss latency
1031system.cpu1.icache.overall_avg_miss_latency::total 14685.924948 # average overall miss latency

1034system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1035system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1036system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1037system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1038system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1039system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1040system.cpu1.icache.fast_writes 0 # number of fast writes performed
1041system.cpu1.icache.cache_copies 0 # number of cache copies performed

1032system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1033system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1034system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1035system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1036system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1037system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1038system.cpu1.icache.fast_writes 0 # number of fast writes performed
1039system.cpu1.icache.cache_copies 0 # number of cache copies performed

1042system.cpu1.icache.writebacks::writebacks 11 # number of writebacks
1043system.cpu1.icache.writebacks::total 11 # number of writebacks
1044system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 514232 # number of ReadReq MSHR misses
1045system.cpu1.icache.ReadReq_mshr_misses::total 514232 # number of ReadReq MSHR misses
1046system.cpu1.icache.demand_mshr_misses::cpu1.inst 514232 # number of demand (read+write) MSHR misses
1047system.cpu1.icache.demand_mshr_misses::total 514232 # number of demand (read+write) MSHR misses
1048system.cpu1.icache.overall_mshr_misses::cpu1.inst 514232 # number of overall MSHR misses
1049system.cpu1.icache.overall_mshr_misses::total 514232 # number of overall MSHR misses
1050system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6009201500 # number of ReadReq MSHR miss cycles
1051system.cpu1.icache.ReadReq_mshr_miss_latency::total 6009201500 # number of ReadReq MSHR miss cycles
1052system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6009201500 # number of demand (read+write) MSHR miss cycles
1053system.cpu1.icache.demand_mshr_miss_latency::total 6009201500 # number of demand (read+write) MSHR miss cycles
1054system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6009201500 # number of overall MSHR miss cycles
1055system.cpu1.icache.overall_mshr_miss_latency::total 6009201500 # number of overall MSHR miss cycles

1040system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 514229 # number of ReadReq MSHR misses
1041system.cpu1.icache.ReadReq_mshr_misses::total 514229 # number of ReadReq MSHR misses
1042system.cpu1.icache.demand_mshr_misses::cpu1.inst 514229 # number of demand (read+write) MSHR misses
1043system.cpu1.icache.demand_mshr_misses::total 514229 # number of demand (read+write) MSHR misses
1044system.cpu1.icache.overall_mshr_misses::cpu1.inst 514229 # number of overall MSHR misses
1045system.cpu1.icache.overall_mshr_misses::total 514229 # number of overall MSHR misses
1046system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6009175500 # number of ReadReq MSHR miss cycles
1047system.cpu1.icache.ReadReq_mshr_miss_latency::total 6009175500 # number of ReadReq MSHR miss cycles
1048system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6009175500 # number of demand (read+write) MSHR miss cycles
1049system.cpu1.icache.demand_mshr_miss_latency::total 6009175500 # number of demand (read+write) MSHR miss cycles
1050system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6009175500 # number of overall MSHR miss cycles
1051system.cpu1.icache.overall_mshr_miss_latency::total 6009175500 # number of overall MSHR miss cycles

1056system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for ReadReq accesses
1057system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022109 # mshr miss rate for ReadReq accesses
1058system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for demand accesses
1059system.cpu1.icache.demand_mshr_miss_rate::total 0.022109 # mshr miss rate for demand accesses
1060system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for overall accesses
1061system.cpu1.icache.overall_mshr_miss_rate::total 0.022109 # mshr miss rate for overall accesses

1052system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for ReadReq accesses
1053system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022109 # mshr miss rate for ReadReq accesses
1054system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for demand accesses
1055system.cpu1.icache.demand_mshr_miss_rate::total 0.022109 # mshr miss rate for demand accesses
1056system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for overall accesses
1057system.cpu1.icache.overall_mshr_miss_rate::total 0.022109 # mshr miss rate for overall accesses

1062system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average ReadReq mshr miss latency
1063system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.778987 # average ReadReq mshr miss latency
1064system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average overall mshr miss latency
1065system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.778987 # average overall mshr miss latency
1066system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average overall mshr miss latency
1067system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.778987 # average overall mshr miss latency

1058system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average ReadReq mshr miss latency
1059system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.796600 # average ReadReq mshr miss latency
1060system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average overall mshr miss latency
1061system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.796600 # average overall mshr miss latency
1062system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average overall mshr miss latency
1063system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.796600 # average overall mshr miss latency

1068system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate

1064system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate

1069system.cpu1.dcache.replacements 642543 # number of replacements
1070system.cpu1.dcache.tagsinuse 493.349744 # Cycle average of tags in use
1071system.cpu1.dcache.total_refs 6059288 # Total number of references to valid blocks.
1072system.cpu1.dcache.sampled_refs 642980 # Sample count of references to valid blocks.
1073system.cpu1.dcache.avg_refs 9.423758 # Average number of references to valid blocks.

1065system.cpu1.dcache.replacements 642542 # number of replacements
1066system.cpu1.dcache.tagsinuse 493.349728 # Cycle average of tags in use
1067system.cpu1.dcache.total_refs 6059289 # Total number of references to valid blocks.
1068system.cpu1.dcache.sampled_refs 642979 # Sample count of references to valid blocks.
1069system.cpu1.dcache.avg_refs 9.423774 # Average number of references to valid blocks.

1074system.cpu1.dcache.warmup_cycle 54205321000 # Cycle when the warmup percentage was hit.

1070system.cpu1.dcache.warmup_cycle 54205321000 # Cycle when the warmup percentage was hit.

1075system.cpu1.dcache.occ_blocks::cpu1.data 493.349744 # Average occupied blocks per requestor

1071system.cpu1.dcache.occ_blocks::cpu1.data 493.349728 # Average occupied blocks per requestor

1076system.cpu1.dcache.occ_percent::cpu1.data 0.963574 # Average percentage of cache occupancy
1077system.cpu1.dcache.occ_percent::total 0.963574 # Average percentage of cache occupancy

1072system.cpu1.dcache.occ_percent::cpu1.data 0.963574 # Average percentage of cache occupancy
1073system.cpu1.dcache.occ_percent::total 0.963574 # Average percentage of cache occupancy

1078system.cpu1.dcache.ReadReq_hits::cpu1.data 3370942 # number of ReadReq hits
1079system.cpu1.dcache.ReadReq_hits::total 3370942 # number of ReadReq hits
1080system.cpu1.dcache.WriteReq_hits::cpu1.data 2541026 # number of WriteReq hits
1081system.cpu1.dcache.WriteReq_hits::total 2541026 # number of WriteReq hits

1074system.cpu1.dcache.ReadReq_hits::cpu1.data 3370941 # number of ReadReq hits
1075system.cpu1.dcache.ReadReq_hits::total 3370941 # number of ReadReq hits
1076system.cpu1.dcache.WriteReq_hits::cpu1.data 2541028 # number of WriteReq hits
1077system.cpu1.dcache.WriteReq_hits::total 2541028 # number of WriteReq hits

1082system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71125 # number of LoadLockedReq hits
1083system.cpu1.dcache.LoadLockedReq_hits::total 71125 # number of LoadLockedReq hits
1084system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80221 # number of StoreCondReq hits
1085system.cpu1.dcache.StoreCondReq_hits::total 80221 # number of StoreCondReq hits

1078system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71125 # number of LoadLockedReq hits
1079system.cpu1.dcache.LoadLockedReq_hits::total 71125 # number of LoadLockedReq hits
1080system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80221 # number of StoreCondReq hits
1081system.cpu1.dcache.StoreCondReq_hits::total 80221 # number of StoreCondReq hits

1086system.cpu1.dcache.demand_hits::cpu1.data 5911968 # number of demand (read+write) hits
1087system.cpu1.dcache.demand_hits::total 5911968 # number of demand (read+write) hits
1088system.cpu1.dcache.overall_hits::cpu1.data 5911968 # number of overall hits
1089system.cpu1.dcache.overall_hits::total 5911968 # number of overall hits
1090system.cpu1.dcache.ReadReq_misses::cpu1.data 513440 # number of ReadReq misses
1091system.cpu1.dcache.ReadReq_misses::total 513440 # number of ReadReq misses
1092system.cpu1.dcache.WriteReq_misses::cpu1.data 122215 # number of WriteReq misses
1093system.cpu1.dcache.WriteReq_misses::total 122215 # number of WriteReq misses

1082system.cpu1.dcache.demand_hits::cpu1.data 5911969 # number of demand (read+write) hits
1083system.cpu1.dcache.demand_hits::total 5911969 # number of demand (read+write) hits
1084system.cpu1.dcache.overall_hits::cpu1.data 5911969 # number of overall hits
1085system.cpu1.dcache.overall_hits::total 5911969 # number of overall hits
1086system.cpu1.dcache.ReadReq_misses::cpu1.data 513441 # number of ReadReq misses
1087system.cpu1.dcache.ReadReq_misses::total 513441 # number of ReadReq misses
1088system.cpu1.dcache.WriteReq_misses::cpu1.data 122213 # number of WriteReq misses
1089system.cpu1.dcache.WriteReq_misses::total 122213 # number of WriteReq misses

1094system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13103 # number of LoadLockedReq misses
1095system.cpu1.dcache.LoadLockedReq_misses::total 13103 # number of LoadLockedReq misses
1096system.cpu1.dcache.StoreCondReq_misses::cpu1.data 640 # number of StoreCondReq misses
1097system.cpu1.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses

1090system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13103 # number of LoadLockedReq misses
1091system.cpu1.dcache.LoadLockedReq_misses::total 13103 # number of LoadLockedReq misses
1092system.cpu1.dcache.StoreCondReq_misses::cpu1.data 640 # number of StoreCondReq misses
1093system.cpu1.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses

1098system.cpu1.dcache.demand_misses::cpu1.data 635655 # number of demand (read+write) misses
1099system.cpu1.dcache.demand_misses::total 635655 # number of demand (read+write) misses
1100system.cpu1.dcache.overall_misses::cpu1.data 635655 # number of overall misses
1101system.cpu1.dcache.overall_misses::total 635655 # number of overall misses
1102system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7202447500 # number of ReadReq miss cycles
1103system.cpu1.dcache.ReadReq_miss_latency::total 7202447500 # number of ReadReq miss cycles
1104system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2665469000 # number of WriteReq miss cycles
1105system.cpu1.dcache.WriteReq_miss_latency::total 2665469000 # number of WriteReq miss cycles
1106system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 183740000 # number of LoadLockedReq miss cycles
1107system.cpu1.dcache.LoadLockedReq_miss_latency::total 183740000 # number of LoadLockedReq miss cycles

1094system.cpu1.dcache.demand_misses::cpu1.data 635654 # number of demand (read+write) misses
1095system.cpu1.dcache.demand_misses::total 635654 # number of demand (read+write) misses
1096system.cpu1.dcache.overall_misses::cpu1.data 635654 # number of overall misses
1097system.cpu1.dcache.overall_misses::total 635654 # number of overall misses
1098system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7202554500 # number of ReadReq miss cycles
1099system.cpu1.dcache.ReadReq_miss_latency::total 7202554500 # number of ReadReq miss cycles
1100system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2665634000 # number of WriteReq miss cycles
1101system.cpu1.dcache.WriteReq_miss_latency::total 2665634000 # number of WriteReq miss cycles
1102system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 183727000 # number of LoadLockedReq miss cycles
1103system.cpu1.dcache.LoadLockedReq_miss_latency::total 183727000 # number of LoadLockedReq miss cycles

1108system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8466000 # number of StoreCondReq miss cycles
1109system.cpu1.dcache.StoreCondReq_miss_latency::total 8466000 # number of StoreCondReq miss cycles

1104system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8466000 # number of StoreCondReq miss cycles
1105system.cpu1.dcache.StoreCondReq_miss_latency::total 8466000 # number of StoreCondReq miss cycles

1110system.cpu1.dcache.demand_miss_latency::cpu1.data 9867916500 # number of demand (read+write) miss cycles
1111system.cpu1.dcache.demand_miss_latency::total 9867916500 # number of demand (read+write) miss cycles
1112system.cpu1.dcache.overall_miss_latency::cpu1.data 9867916500 # number of overall miss cycles
1113system.cpu1.dcache.overall_miss_latency::total 9867916500 # number of overall miss cycles

1106system.cpu1.dcache.demand_miss_latency::cpu1.data 9868188500 # number of demand (read+write) miss cycles
1107system.cpu1.dcache.demand_miss_latency::total 9868188500 # number of demand (read+write) miss cycles
1108system.cpu1.dcache.overall_miss_latency::cpu1.data 9868188500 # number of overall miss cycles
1109system.cpu1.dcache.overall_miss_latency::total 9868188500 # number of overall miss cycles

1114system.cpu1.dcache.ReadReq_accesses::cpu1.data 3884382 # number of ReadReq accesses(hits+misses)
1115system.cpu1.dcache.ReadReq_accesses::total 3884382 # number of ReadReq accesses(hits+misses)
1116system.cpu1.dcache.WriteReq_accesses::cpu1.data 2663241 # number of WriteReq accesses(hits+misses)
1117system.cpu1.dcache.WriteReq_accesses::total 2663241 # number of WriteReq accesses(hits+misses)
1118system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 84228 # number of LoadLockedReq accesses(hits+misses)
1119system.cpu1.dcache.LoadLockedReq_accesses::total 84228 # number of LoadLockedReq accesses(hits+misses)
1120system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80861 # number of StoreCondReq accesses(hits+misses)
1121system.cpu1.dcache.StoreCondReq_accesses::total 80861 # number of StoreCondReq accesses(hits+misses)
1122system.cpu1.dcache.demand_accesses::cpu1.data 6547623 # number of demand (read+write) accesses
1123system.cpu1.dcache.demand_accesses::total 6547623 # number of demand (read+write) accesses
1124system.cpu1.dcache.overall_accesses::cpu1.data 6547623 # number of overall (read+write) accesses
1125system.cpu1.dcache.overall_accesses::total 6547623 # number of overall (read+write) accesses
1126system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.132181 # miss rate for ReadReq accesses
1127system.cpu1.dcache.ReadReq_miss_rate::total 0.132181 # miss rate for ReadReq accesses

1110system.cpu1.dcache.ReadReq_accesses::cpu1.data 3884382 # number of ReadReq accesses(hits+misses)
1111system.cpu1.dcache.ReadReq_accesses::total 3884382 # number of ReadReq accesses(hits+misses)
1112system.cpu1.dcache.WriteReq_accesses::cpu1.data 2663241 # number of WriteReq accesses(hits+misses)
1113system.cpu1.dcache.WriteReq_accesses::total 2663241 # number of WriteReq accesses(hits+misses)
1114system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 84228 # number of LoadLockedReq accesses(hits+misses)
1115system.cpu1.dcache.LoadLockedReq_accesses::total 84228 # number of LoadLockedReq accesses(hits+misses)
1116system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80861 # number of StoreCondReq accesses(hits+misses)
1117system.cpu1.dcache.StoreCondReq_accesses::total 80861 # number of StoreCondReq accesses(hits+misses)
1118system.cpu1.dcache.demand_accesses::cpu1.data 6547623 # number of demand (read+write) accesses
1119system.cpu1.dcache.demand_accesses::total 6547623 # number of demand (read+write) accesses
1120system.cpu1.dcache.overall_accesses::cpu1.data 6547623 # number of overall (read+write) accesses
1121system.cpu1.dcache.overall_accesses::total 6547623 # number of overall (read+write) accesses
1122system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.132181 # miss rate for ReadReq accesses
1123system.cpu1.dcache.ReadReq_miss_rate::total 0.132181 # miss rate for ReadReq accesses

1128system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045890 # miss rate for WriteReq accesses
1129system.cpu1.dcache.WriteReq_miss_rate::total 0.045890 # miss rate for WriteReq accesses

1124system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045889 # miss rate for WriteReq accesses
1125system.cpu1.dcache.WriteReq_miss_rate::total 0.045889 # miss rate for WriteReq accesses

1130system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155566 # miss rate for LoadLockedReq accesses
1131system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155566 # miss rate for LoadLockedReq accesses
1132system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007915 # miss rate for StoreCondReq accesses
1133system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007915 # miss rate for StoreCondReq accesses
1134system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097082 # miss rate for demand accesses
1135system.cpu1.dcache.demand_miss_rate::total 0.097082 # miss rate for demand accesses
1136system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097082 # miss rate for overall accesses
1137system.cpu1.dcache.overall_miss_rate::total 0.097082 # miss rate for overall accesses

1126system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155566 # miss rate for LoadLockedReq accesses
1127system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155566 # miss rate for LoadLockedReq accesses
1128system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007915 # miss rate for StoreCondReq accesses
1129system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007915 # miss rate for StoreCondReq accesses
1130system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097082 # miss rate for demand accesses
1131system.cpu1.dcache.demand_miss_rate::total 0.097082 # miss rate for demand accesses
1132system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097082 # miss rate for overall accesses
1133system.cpu1.dcache.overall_miss_rate::total 0.097082 # miss rate for overall accesses

1138system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14027.827010 # average ReadReq miss latency
1139system.cpu1.dcache.ReadReq_avg_miss_latency::total 14027.827010 # average ReadReq miss latency
1140system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21809.671481 # average WriteReq miss latency
1141system.cpu1.dcache.WriteReq_avg_miss_latency::total 21809.671481 # average WriteReq miss latency
1142system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14022.742883 # average LoadLockedReq miss latency
1143system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14022.742883 # average LoadLockedReq miss latency

1134system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14028.008087 # average ReadReq miss latency
1135system.cpu1.dcache.ReadReq_avg_miss_latency::total 14028.008087 # average ReadReq miss latency
1136system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21811.378495 # average WriteReq miss latency
1137system.cpu1.dcache.WriteReq_avg_miss_latency::total 21811.378495 # average WriteReq miss latency
1138system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14021.750744 # average LoadLockedReq miss latency
1139system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14021.750744 # average LoadLockedReq miss latency

1144system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000 # average StoreCondReq miss latency
1145system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000 # average StoreCondReq miss latency

1140system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000 # average StoreCondReq miss latency
1141system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000 # average StoreCondReq miss latency

1146system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency
1147system.cpu1.dcache.demand_avg_miss_latency::total 15524.013026 # average overall miss latency
1148system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency
1149system.cpu1.dcache.overall_avg_miss_latency::total 15524.013026 # average overall miss latency

1142system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.465354 # average overall miss latency
1143system.cpu1.dcache.demand_avg_miss_latency::total 15524.465354 # average overall miss latency
1144system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.465354 # average overall miss latency
1145system.cpu1.dcache.overall_avg_miss_latency::total 15524.465354 # average overall miss latency

1150system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1151system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1152system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1153system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1154system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1155system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1156system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1157system.cpu1.dcache.cache_copies 0 # number of cache copies performed

1146system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1147system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1148system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1149system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1150system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1151system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1152system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1153system.cpu1.dcache.cache_copies 0 # number of cache copies performed

1158system.cpu1.dcache.writebacks::writebacks 498964 # number of writebacks
1159system.cpu1.dcache.writebacks::total 498964 # number of writebacks
1160system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 513440 # number of ReadReq MSHR misses
1161system.cpu1.dcache.ReadReq_mshr_misses::total 513440 # number of ReadReq MSHR misses
1162system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 122215 # number of WriteReq MSHR misses
1163system.cpu1.dcache.WriteReq_mshr_misses::total 122215 # number of WriteReq MSHR misses

1154system.cpu1.dcache.writebacks::writebacks 498963 # number of writebacks
1155system.cpu1.dcache.writebacks::total 498963 # number of writebacks
1156system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 513441 # number of ReadReq MSHR misses
1157system.cpu1.dcache.ReadReq_mshr_misses::total 513441 # number of ReadReq MSHR misses
1158system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 122213 # number of WriteReq MSHR misses
1159system.cpu1.dcache.WriteReq_mshr_misses::total 122213 # number of WriteReq MSHR misses

1164system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13103 # number of LoadLockedReq MSHR misses
1165system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13103 # number of LoadLockedReq MSHR misses
1166system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 640 # number of StoreCondReq MSHR misses
1167system.cpu1.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses

1160system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13103 # number of LoadLockedReq MSHR misses
1161system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13103 # number of LoadLockedReq MSHR misses
1162system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 640 # number of StoreCondReq MSHR misses
1163system.cpu1.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses

1168system.cpu1.dcache.demand_mshr_misses::cpu1.data 635655 # number of demand (read+write) MSHR misses
1169system.cpu1.dcache.demand_mshr_misses::total 635655 # number of demand (read+write) MSHR misses
1170system.cpu1.dcache.overall_mshr_misses::cpu1.data 635655 # number of overall MSHR misses
1171system.cpu1.dcache.overall_mshr_misses::total 635655 # number of overall MSHR misses
1172system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662112010 # number of ReadReq MSHR miss cycles
1173system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662112010 # number of ReadReq MSHR miss cycles
1174system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298824000 # number of WriteReq MSHR miss cycles
1175system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298824000 # number of WriteReq MSHR miss cycles
1176system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144431000 # number of LoadLockedReq MSHR miss cycles
1177system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144431000 # number of LoadLockedReq MSHR miss cycles

1164system.cpu1.dcache.demand_mshr_misses::cpu1.data 635654 # number of demand (read+write) MSHR misses
1165system.cpu1.dcache.demand_mshr_misses::total 635654 # number of demand (read+write) MSHR misses
1166system.cpu1.dcache.overall_mshr_misses::cpu1.data 635654 # number of overall MSHR misses
1167system.cpu1.dcache.overall_mshr_misses::total 635654 # number of overall MSHR misses
1168system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662217009 # number of ReadReq MSHR miss cycles
1169system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662217009 # number of ReadReq MSHR miss cycles
1170system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298995000 # number of WriteReq MSHR miss cycles
1171system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298995000 # number of WriteReq MSHR miss cycles
1172system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144418000 # number of LoadLockedReq MSHR miss cycles
1173system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144418000 # number of LoadLockedReq MSHR miss cycles

1178system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6549000 # number of StoreCondReq MSHR miss cycles
1179system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6549000 # number of StoreCondReq MSHR miss cycles
1180system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5000 # number of StoreCondFailReq MSHR miss cycles
1181system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5000 # number of StoreCondFailReq MSHR miss cycles

1174system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6549000 # number of StoreCondReq MSHR miss cycles
1175system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6549000 # number of StoreCondReq MSHR miss cycles
1176system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5000 # number of StoreCondFailReq MSHR miss cycles
1177system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5000 # number of StoreCondFailReq MSHR miss cycles

1182system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7960936010 # number of demand (read+write) MSHR miss cycles
1183system.cpu1.dcache.demand_mshr_miss_latency::total 7960936010 # number of demand (read+write) MSHR miss cycles
1184system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7960936010 # number of overall MSHR miss cycles
1185system.cpu1.dcache.overall_mshr_miss_latency::total 7960936010 # number of overall MSHR miss cycles

1178system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7961212009 # number of demand (read+write) MSHR miss cycles
1179system.cpu1.dcache.demand_mshr_miss_latency::total 7961212009 # number of demand (read+write) MSHR miss cycles
1180system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7961212009 # number of overall MSHR miss cycles
1181system.cpu1.dcache.overall_mshr_miss_latency::total 7961212009 # number of overall MSHR miss cycles

1186system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295035500 # number of ReadReq MSHR uncacheable cycles
1187system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 295035500 # number of ReadReq MSHR uncacheable cycles

1182system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295035500 # number of ReadReq MSHR uncacheable cycles
1183system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 295035500 # number of ReadReq MSHR uncacheable cycles

1188system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516397500 # number of WriteReq MSHR uncacheable cycles
1189system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516397500 # number of WriteReq MSHR uncacheable cycles
1190system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811433000 # number of overall MSHR uncacheable cycles
1191system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811433000 # number of overall MSHR uncacheable cycles

1184system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516366500 # number of WriteReq MSHR uncacheable cycles
1185system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516366500 # number of WriteReq MSHR uncacheable cycles
1186system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811402000 # number of overall MSHR uncacheable cycles
1187system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811402000 # number of overall MSHR uncacheable cycles

1192system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.132181 # mshr miss rate for ReadReq accesses
1193system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses

1188system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.132181 # mshr miss rate for ReadReq accesses
1189system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses

1194system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045890 # mshr miss rate for WriteReq accesses
1195system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045890 # mshr miss rate for WriteReq accesses

1190system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045889 # mshr miss rate for WriteReq accesses
1191system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses

1196system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155566 # mshr miss rate for LoadLockedReq accesses
1197system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155566 # mshr miss rate for LoadLockedReq accesses
1198system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007915 # mshr miss rate for StoreCondReq accesses
1199system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007915 # mshr miss rate for StoreCondReq accesses
1200system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for demand accesses
1201system.cpu1.dcache.demand_mshr_miss_rate::total 0.097082 # mshr miss rate for demand accesses
1202system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for overall accesses
1203system.cpu1.dcache.overall_mshr_miss_rate::total 0.097082 # mshr miss rate for overall accesses

1192system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155566 # mshr miss rate for LoadLockedReq accesses
1193system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155566 # mshr miss rate for LoadLockedReq accesses
1194system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007915 # mshr miss rate for StoreCondReq accesses
1195system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007915 # mshr miss rate for StoreCondReq accesses
1196system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for demand accesses
1197system.cpu1.dcache.demand_mshr_miss_rate::total 0.097082 # mshr miss rate for demand accesses
1198system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for overall accesses
1199system.cpu1.dcache.overall_mshr_miss_rate::total 0.097082 # mshr miss rate for overall accesses

1204system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.796841 # average ReadReq mshr miss latency
1205system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.796841 # average ReadReq mshr miss latency
1206system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18809.671481 # average WriteReq mshr miss latency
1207system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18809.671481 # average WriteReq mshr miss latency
1208system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11022.742883 # average LoadLockedReq mshr miss latency
1209system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11022.742883 # average LoadLockedReq mshr miss latency

1200system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.979863 # average ReadReq mshr miss latency
1201system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.979863 # average ReadReq mshr miss latency
1202system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18811.378495 # average WriteReq mshr miss latency
1203system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18811.378495 # average WriteReq mshr miss latency
1204system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11021.750744 # average LoadLockedReq mshr miss latency
1205system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11021.750744 # average LoadLockedReq mshr miss latency

1210system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500 # average StoreCondReq mshr miss latency
1211system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500 # average StoreCondReq mshr miss latency
1212system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1213system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency

1206system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500 # average StoreCondReq mshr miss latency
1207system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500 # average StoreCondReq mshr miss latency
1208system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1209system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency

1214system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency
1215system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency
1216system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency
1217system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency

1210system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12524.442557 # average overall mshr miss latency
1211system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12524.442557 # average overall mshr miss latency
1212system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12524.442557 # average overall mshr miss latency
1213system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12524.442557 # average overall mshr miss latency