| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.957578 # Number of seconds simulated 4sim_ticks 1957577582000 # Number of ticks simulated 5final_tick 1957577582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.954209 # Number of seconds simulated 4sim_ticks 1954209106000 # Number of ticks simulated 5final_tick 1954209106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1866861 # Simulator instruction rate (inst/s) 8host_op_rate 1866860 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 61595044213 # Simulator tick rate (ticks/s) 10host_mem_usage 296940 # Number of bytes of host memory used 11host_seconds 31.78 # Real time elapsed on the host 12sim_insts 59331415 # Number of instructions simulated 13sim_ops 59331415 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 825984 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 24749824 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 37440 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 398080 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28662144 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 825984 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 37440 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 863424 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7684736 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7684736 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 12906 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 386716 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 585 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 6220 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 447846 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 120074 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 120074 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 421942 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12643087 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1354131 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 19126 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 203353 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14641639 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 421942 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 19126 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 441068 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3925635 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3925635 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3925635 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 421942 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12643087 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1354131 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 19126 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 203353 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18567274 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 340832 # number of replacements 52system.l2c.tagsinuse 65295.945000 # Cycle average of tags in use 53system.l2c.total_refs 2492123 # Total number of references to valid blocks. 54system.l2c.sampled_refs 405944 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.139081 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 7739998000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 55466.932424 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 4795.907583 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 4852.495880 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 163.850290 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 16.758824 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.846358 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.073180 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.074043 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.002500 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000256 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.996337 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 902441 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 771400 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 86210 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 33732 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1793783 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 821051 # number of Writeback hits 74system.l2c.Writeback_hits::total 821051 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 166 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 34 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 172323 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 12709 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 185032 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 902441 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 943723 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 86210 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 46441 # number of demand (read+write) hits 88system.l2c.demand_hits::total 1978815 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 902441 # number of overall hits 90system.l2c.overall_hits::cpu0.data 943723 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 86210 # number of overall hits 92system.l2c.overall_hits::cpu1.data 46441 # number of overall hits 93system.l2c.overall_hits::total 1978815 # number of overall hits 94system.l2c.ReadReq_misses::cpu0.inst 12906 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 271613 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 596 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 192 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 285307 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2453 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 486 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 2939 # number of UpgradeReq misses 102system.l2c.SCUpgradeReq_misses::cpu0.data 16 # number of SCUpgradeReq misses 103system.l2c.SCUpgradeReq_misses::cpu1.data 72 # number of SCUpgradeReq misses 104system.l2c.SCUpgradeReq_misses::total 88 # number of SCUpgradeReq misses 105system.l2c.ReadExReq_misses::cpu0.data 115483 # number of ReadExReq misses 106system.l2c.ReadExReq_misses::cpu1.data 6047 # number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 121530 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 12906 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 387096 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 596 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 6239 # number of demand (read+write) misses 112system.l2c.demand_misses::total 406837 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 12906 # number of overall misses 114system.l2c.overall_misses::cpu0.data 387096 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 596 # number of overall misses 116system.l2c.overall_misses::cpu1.data 6239 # number of overall misses 117system.l2c.overall_misses::total 406837 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 671157500 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14128859000 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 30971000 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 10024000 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 14841011500 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 2088000 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 624000 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 2712000 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 260000 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 208000 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 468000 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 6005389000 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 314450000 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6319839000 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 671157500 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 20134248000 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 30971000 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 324474000 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 21160850500 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 671157500 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 20134248000 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 30971000 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 324474000 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 21160850500 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 915347 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 1043013 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 86806 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 33924 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2079090 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 821051 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 821051 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 2619 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 540 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 3159 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 30 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 122 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 287806 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 18756 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 306562 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 915347 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 1330819 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 86806 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 52680 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2385652 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 915347 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 1330819 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 86806 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 52680 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2385652 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.014100 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.260412 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.006866 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.005660 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.137227 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.936617 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.900000 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.930358 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.533333 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.782609 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.721311 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.401253 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.322403 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.396429 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.014100 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.290871 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.006866 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.118432 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.170535 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.014100 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.290871 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.006866 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.118432 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.170535 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.525492 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.345955 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51964.765101 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 52208.333333 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52017.691469 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 851.202609 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1283.950617 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 922.762845 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16250 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2888.888889 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 5318.181818 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.363984 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.992228 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 52002.295729 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 52003.525492 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52013.578027 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 51964.765101 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 52007.372976 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52013.092467 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 52003.525492 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52013.578027 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 51964.765101 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 52007.372976 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52013.092467 # average overall miss latency | 7host_inst_rate 1820229 # Simulator instruction rate (inst/s) 8host_op_rate 1820228 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 59866957581 # Simulator tick rate (ticks/s) 10host_mem_usage 296900 # Number of bytes of host memory used 11host_seconds 32.64 # Real time elapsed on the host 12sim_insts 59416827 # Number of instructions simulated 13sim_ops 59416827 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 717056 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 23797184 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 145856 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 1424768 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28734208 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 717056 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 145856 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 862912 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 7745216 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7745216 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 11204 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 371831 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 2279 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 22262 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 448972 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 121019 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 121019 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 366929 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 12177399 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1355712 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 74637 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 729077 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 14703753 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 366929 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 74637 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 441566 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 3963351 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 3963351 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 3963351 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 366929 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 12177399 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1355712 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 74637 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 729077 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 18667104 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 342059 # number of replacements 52system.l2c.tagsinuse 65268.179703 # Cycle average of tags in use 53system.l2c.total_refs 2559285 # Total number of references to valid blocks. 54system.l2c.sampled_refs 407065 # Sample count of references to valid blocks. 55system.l2c.avg_refs 6.287165 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 7752825000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 55637.656104 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 3742.496714 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 4175.529809 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 1176.827938 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 535.669138 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.848963 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.057106 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.063714 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.017957 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.008174 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.995913 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 478629 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu0.data 342574 # number of ReadReq hits 70system.l2c.ReadReq_hits::cpu1.inst 511941 # number of ReadReq hits 71system.l2c.ReadReq_hits::cpu1.data 491320 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1824464 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 858732 # number of Writeback hits 74system.l2c.Writeback_hits::total 858732 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 137 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 95 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 232 # number of UpgradeReq hits 78system.l2c.SCUpgradeReq_hits::cpu0.data 22 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits 81system.l2c.ReadExReq_hits::cpu0.data 101383 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 99295 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits 84system.l2c.demand_hits::cpu0.inst 478629 # number of demand (read+write) hits 85system.l2c.demand_hits::cpu0.data 443957 # number of demand (read+write) hits 86system.l2c.demand_hits::cpu1.inst 511941 # number of demand (read+write) hits 87system.l2c.demand_hits::cpu1.data 590615 # number of demand (read+write) hits 88system.l2c.demand_hits::total 2025142 # number of demand (read+write) hits 89system.l2c.overall_hits::cpu0.inst 478629 # number of overall hits 90system.l2c.overall_hits::cpu0.data 443957 # number of overall hits 91system.l2c.overall_hits::cpu1.inst 511941 # number of overall hits 92system.l2c.overall_hits::cpu1.data 590615 # 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number of ReadExReq misses 107system.l2c.ReadExReq_misses::total 122691 # number of ReadExReq misses 108system.l2c.demand_misses::cpu0.inst 11204 # number of demand (read+write) misses 109system.l2c.demand_misses::cpu0.data 372187 # number of demand (read+write) misses 110system.l2c.demand_misses::cpu1.inst 2290 # number of demand (read+write) misses 111system.l2c.demand_misses::cpu1.data 22304 # number of demand (read+write) misses 112system.l2c.demand_misses::total 407985 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 11204 # number of overall misses 114system.l2c.overall_misses::cpu0.data 372187 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 2290 # number of overall misses 116system.l2c.overall_misses::cpu1.data 22304 # number of overall misses 117system.l2c.overall_misses::total 407985 # number of overall misses 118system.l2c.ReadReq_miss_latency::cpu0.inst 582910000 # number of ReadReq miss cycles 119system.l2c.ReadReq_miss_latency::cpu0.data 14075669000 # number of ReadReq miss cycles 120system.l2c.ReadReq_miss_latency::cpu1.inst 119002000 # number of ReadReq miss cycles 121system.l2c.ReadReq_miss_latency::cpu1.data 63420000 # number of ReadReq miss cycles 122system.l2c.ReadReq_miss_latency::total 14841001000 # number of ReadReq miss cycles 123system.l2c.UpgradeReq_miss_latency::cpu0.data 1144000 # number of UpgradeReq miss cycles 124system.l2c.UpgradeReq_miss_latency::cpu1.data 1924000 # number of UpgradeReq miss cycles 125system.l2c.UpgradeReq_miss_latency::total 3068000 # number of UpgradeReq miss cycles 126system.l2c.SCUpgradeReq_miss_latency::cpu0.data 695000 # number of SCUpgradeReq miss cycles 127system.l2c.SCUpgradeReq_miss_latency::cpu1.data 156000 # number of SCUpgradeReq miss cycles 128system.l2c.SCUpgradeReq_miss_latency::total 851000 # number of SCUpgradeReq miss cycles 129system.l2c.ReadExReq_miss_latency::cpu0.data 5283374000 # number of ReadExReq miss cycles 130system.l2c.ReadExReq_miss_latency::cpu1.data 1096874000 # number of ReadExReq miss cycles 131system.l2c.ReadExReq_miss_latency::total 6380248000 # number of ReadExReq miss cycles 132system.l2c.demand_miss_latency::cpu0.inst 582910000 # number of demand (read+write) miss cycles 133system.l2c.demand_miss_latency::cpu0.data 19359043000 # number of demand (read+write) miss cycles 134system.l2c.demand_miss_latency::cpu1.inst 119002000 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu1.data 1160294000 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::total 21221249000 # number of demand (read+write) miss cycles 137system.l2c.overall_miss_latency::cpu0.inst 582910000 # number of overall miss cycles 138system.l2c.overall_miss_latency::cpu0.data 19359043000 # number of overall miss cycles 139system.l2c.overall_miss_latency::cpu1.inst 119002000 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu1.data 1160294000 # number of overall miss cycles 141system.l2c.overall_miss_latency::total 21221249000 # number of overall miss cycles 142system.l2c.ReadReq_accesses::cpu0.inst 489833 # number of ReadReq accesses(hits+misses) 143system.l2c.ReadReq_accesses::cpu0.data 613163 # number of ReadReq accesses(hits+misses) 144system.l2c.ReadReq_accesses::cpu1.inst 514231 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu1.data 492531 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::total 2109758 # number of ReadReq accesses(hits+misses) 147system.l2c.Writeback_accesses::writebacks 858732 # number of Writeback accesses(hits+misses) 148system.l2c.Writeback_accesses::total 858732 # number of Writeback accesses(hits+misses) 149system.l2c.UpgradeReq_accesses::cpu0.data 2713 # number of UpgradeReq accesses(hits+misses) 150system.l2c.UpgradeReq_accesses::cpu1.data 571 # number of UpgradeReq accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::total 3284 # number of UpgradeReq accesses(hits+misses) 152system.l2c.SCUpgradeReq_accesses::cpu0.data 107 # number of SCUpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu1.data 112 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 219 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu0.data 202981 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::cpu1.data 120388 # number of ReadExReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::total 323369 # number of ReadExReq accesses(hits+misses) 158system.l2c.demand_accesses::cpu0.inst 489833 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu0.data 816144 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu1.inst 514231 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu1.data 612919 # number of demand (read+write) accesses 162system.l2c.demand_accesses::total 2433127 # number of demand (read+write) accesses 163system.l2c.overall_accesses::cpu0.inst 489833 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu0.data 816144 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 514231 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 612919 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2433127 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.022873 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.441300 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.004453 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.002459 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::total 0.135226 # miss rate for ReadReq accesses 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.949502 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.833625 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.929354 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.794393 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.785714 # miss rate for SCUpgradeReq accesses 178system.l2c.SCUpgradeReq_miss_rate::total 0.789954 # miss rate for SCUpgradeReq accesses 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.500530 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.175208 # miss rate for ReadExReq accesses 181system.l2c.ReadExReq_miss_rate::total 0.379415 # miss rate for ReadExReq accesses 182system.l2c.demand_miss_rate::cpu0.inst 0.022873 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.456031 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.004453 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.036390 # miss rate for demand accesses 186system.l2c.demand_miss_rate::total 0.167679 # miss rate for demand accesses 187system.l2c.overall_miss_rate::cpu0.inst 0.022873 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.456031 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.004453 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.036390 # miss rate for overall accesses 191system.l2c.overall_miss_rate::total 0.167679 # miss rate for overall accesses 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52026.954659 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.629730 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51965.938865 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 52369.942197 # average ReadReq miss latency 196system.l2c.ReadReq_avg_miss_latency::total 52020.024957 # average ReadReq miss latency 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 444.099379 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4042.016807 # average UpgradeReq miss latency 199system.l2c.UpgradeReq_avg_miss_latency::total 1005.242464 # average UpgradeReq miss latency 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8176.470588 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1772.727273 # average SCUpgradeReq miss latency 202system.l2c.SCUpgradeReq_avg_miss_latency::total 4919.075145 # average SCUpgradeReq miss latency 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736274 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52001.801546 # average ReadExReq miss latency 205system.l2c.ReadExReq_avg_miss_latency::total 52002.575576 # average ReadExReq miss latency 206system.l2c.demand_avg_miss_latency::cpu0.inst 52026.954659 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52014.291203 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 51965.938865 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 52021.789813 # average overall miss latency 210system.l2c.demand_avg_miss_latency::total 52014.777504 # average overall miss latency 211system.l2c.overall_avg_miss_latency::cpu0.inst 52026.954659 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52014.291203 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 51965.938865 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 52021.789813 # average overall miss latency 215system.l2c.overall_avg_miss_latency::total 52014.777504 # average overall miss latency |
| 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed | 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed |
| 224system.l2c.writebacks::writebacks 78554 # number of writebacks 225system.l2c.writebacks::total 78554 # number of writebacks | 224system.l2c.writebacks::writebacks 79488 # number of writebacks 225system.l2c.writebacks::total 79488 # number of writebacks |
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number of overall MSHR miss cycles 277system.l2c.overall_mshr_miss_latency::cpu1.inst 23400000 # number of overall MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu1.data 249606000 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::total 16278384000 # number of overall MSHR miss cycles 280system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 792098000 # number of ReadReq MSHR uncacheable cycles 281system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 10214500 # number of ReadReq MSHR uncacheable cycles 282system.l2c.ReadReq_mshr_uncacheable_latency::total 802312500 # number of ReadReq MSHR uncacheable cycles 283system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1122098500 # number of WriteReq MSHR uncacheable cycles 284system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 269224500 # number of WriteReq MSHR uncacheable cycles 285system.l2c.WriteReq_mshr_uncacheable_latency::total 1391323000 # number of WriteReq MSHR uncacheable cycles 286system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1914196500 # number of overall MSHR uncacheable cycles 287system.l2c.overall_mshr_uncacheable_latency::cpu1.data 279439000 # number of overall MSHR uncacheable cycles 288system.l2c.overall_mshr_uncacheable_latency::total 2193635500 # number of overall MSHR uncacheable cycles 289system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for ReadReq accesses 290system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.260412 # mshr miss rate for ReadReq accesses 291system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for ReadReq accesses 292system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005660 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::total 0.137222 # mshr miss rate for ReadReq accesses 294system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.936617 # mshr miss rate for UpgradeReq accesses 295system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.900000 # mshr miss rate for UpgradeReq accesses 296system.l2c.UpgradeReq_mshr_miss_rate::total 0.930358 # mshr miss rate for UpgradeReq accesses 297system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.533333 # mshr miss rate for SCUpgradeReq accesses 298system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.782609 # mshr miss rate for SCUpgradeReq accesses 299system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.721311 # mshr miss rate for SCUpgradeReq accesses 300system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401253 # mshr miss rate for ReadExReq accesses 301system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.322403 # mshr miss rate for ReadExReq accesses 302system.l2c.ReadExReq_mshr_miss_rate::total 0.396429 # mshr miss rate for ReadExReq accesses 303system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for demand accesses 304system.l2c.demand_mshr_miss_rate::cpu0.data 0.290871 # mshr miss rate for demand accesses 305system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for demand accesses 306system.l2c.demand_mshr_miss_rate::cpu1.data 0.118432 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::total 0.170530 # mshr miss rate for demand accesses 308system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014100 # mshr miss rate for overall accesses 309system.l2c.overall_mshr_miss_rate::cpu0.data 0.290871 # mshr miss rate for overall accesses 310system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006739 # mshr miss rate for overall accesses 311system.l2c.overall_mshr_miss_rate::cpu1.data 0.118432 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::total 0.170530 # mshr miss rate for overall accesses 313system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average ReadReq mshr miss latency 314system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.345955 # average ReadReq mshr miss latency 315system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40208.333333 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::total 40017.753491 # average ReadReq mshr miss latency 318system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.905830 # average UpgradeReq mshr miss latency 319system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40012.345679 # average UpgradeReq mshr miss latency 320system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40024.498129 # average UpgradeReq mshr miss latency 321system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency | 232system.l2c.ReadReq_mshr_misses::cpu0.inst 11204 # number of ReadReq MSHR misses 233system.l2c.ReadReq_mshr_misses::cpu0.data 270589 # number of ReadReq MSHR misses 234system.l2c.ReadReq_mshr_misses::cpu1.inst 2279 # number of ReadReq MSHR misses 235system.l2c.ReadReq_mshr_misses::cpu1.data 1211 # number of ReadReq MSHR misses 236system.l2c.ReadReq_mshr_misses::total 285283 # number of ReadReq MSHR misses 237system.l2c.UpgradeReq_mshr_misses::cpu0.data 2576 # number of UpgradeReq MSHR misses 238system.l2c.UpgradeReq_mshr_misses::cpu1.data 476 # number of UpgradeReq MSHR misses 239system.l2c.UpgradeReq_mshr_misses::total 3052 # number of UpgradeReq MSHR misses 240system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 85 # number of SCUpgradeReq MSHR misses 241system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 88 # number of SCUpgradeReq MSHR misses 242system.l2c.SCUpgradeReq_mshr_misses::total 173 # number of SCUpgradeReq MSHR misses 243system.l2c.ReadExReq_mshr_misses::cpu0.data 101598 # number of ReadExReq MSHR misses 244system.l2c.ReadExReq_mshr_misses::cpu1.data 21093 # number of ReadExReq MSHR misses 245system.l2c.ReadExReq_mshr_misses::total 122691 # number of ReadExReq MSHR misses 246system.l2c.demand_mshr_misses::cpu0.inst 11204 # number of demand (read+write) MSHR misses 247system.l2c.demand_mshr_misses::cpu0.data 372187 # number of demand (read+write) MSHR misses 248system.l2c.demand_mshr_misses::cpu1.inst 2279 # number of demand (read+write) MSHR misses 249system.l2c.demand_mshr_misses::cpu1.data 22304 # number of demand (read+write) MSHR misses 250system.l2c.demand_mshr_misses::total 407974 # number of demand (read+write) MSHR misses 251system.l2c.overall_mshr_misses::cpu0.inst 11204 # number of overall MSHR misses 252system.l2c.overall_mshr_misses::cpu0.data 372187 # number of overall MSHR misses 253system.l2c.overall_mshr_misses::cpu1.inst 2279 # number of overall MSHR misses 254system.l2c.overall_mshr_misses::cpu1.data 22304 # number of overall MSHR misses 255system.l2c.overall_mshr_misses::total 407974 # number of overall MSHR misses 256system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 448459000 # number of ReadReq MSHR miss cycles 257system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10828601000 # number of ReadReq MSHR miss cycles 258system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 91164000 # number of ReadReq MSHR miss cycles 259system.l2c.ReadReq_mshr_miss_latency::cpu1.data 48888000 # number of ReadReq MSHR miss cycles 260system.l2c.ReadReq_mshr_miss_latency::total 11417112000 # number of ReadReq MSHR miss cycles 261system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 103144000 # number of UpgradeReq MSHR miss cycles 262system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19089000 # number of UpgradeReq MSHR miss cycles 263system.l2c.UpgradeReq_mshr_miss_latency::total 122233000 # number of UpgradeReq MSHR miss cycles 264system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3419000 # number of SCUpgradeReq MSHR miss cycles 265system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 3520000 # number of SCUpgradeReq MSHR miss cycles 266system.l2c.SCUpgradeReq_mshr_miss_latency::total 6939000 # number of SCUpgradeReq MSHR miss cycles 267system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4064198000 # number of ReadExReq MSHR miss cycles 268system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 843758000 # number of ReadExReq MSHR miss cycles 269system.l2c.ReadExReq_mshr_miss_latency::total 4907956000 # number of ReadExReq MSHR miss cycles 270system.l2c.demand_mshr_miss_latency::cpu0.inst 448459000 # number of demand (read+write) MSHR miss cycles 271system.l2c.demand_mshr_miss_latency::cpu0.data 14892799000 # number of demand (read+write) MSHR miss cycles 272system.l2c.demand_mshr_miss_latency::cpu1.inst 91164000 # number of demand (read+write) MSHR miss cycles 273system.l2c.demand_mshr_miss_latency::cpu1.data 892646000 # number of demand (read+write) MSHR miss cycles 274system.l2c.demand_mshr_miss_latency::total 16325068000 # number of demand (read+write) MSHR miss cycles 275system.l2c.overall_mshr_miss_latency::cpu0.inst 448459000 # number of overall MSHR miss cycles 276system.l2c.overall_mshr_miss_latency::cpu0.data 14892799000 # number of overall MSHR miss cycles 277system.l2c.overall_mshr_miss_latency::cpu1.inst 91164000 # number of overall MSHR miss cycles 278system.l2c.overall_mshr_miss_latency::cpu1.data 892646000 # number of overall MSHR miss cycles 279system.l2c.overall_mshr_miss_latency::total 16325068000 # number of overall MSHR miss cycles 280system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 538312030 # number of ReadReq MSHR uncacheable cycles 281system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 264188000 # number of ReadReq MSHR uncacheable cycles 282system.l2c.ReadReq_mshr_uncacheable_latency::total 802500030 # number of ReadReq MSHR uncacheable cycles 283system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 914387000 # number of WriteReq MSHR uncacheable cycles 284system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 465201000 # number of WriteReq MSHR uncacheable cycles 285system.l2c.WriteReq_mshr_uncacheable_latency::total 1379588000 # number of WriteReq MSHR uncacheable cycles 286system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1452699030 # number of overall MSHR uncacheable cycles 287system.l2c.overall_mshr_uncacheable_latency::cpu1.data 729389000 # number of overall MSHR uncacheable cycles 288system.l2c.overall_mshr_uncacheable_latency::total 2182088030 # number of overall MSHR uncacheable cycles 289system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for ReadReq accesses 290system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.441300 # mshr miss rate for ReadReq accesses 291system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for ReadReq accesses 292system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002459 # mshr miss rate for ReadReq accesses 293system.l2c.ReadReq_mshr_miss_rate::total 0.135221 # mshr miss rate for ReadReq accesses 294system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.949502 # mshr miss rate for UpgradeReq accesses 295system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.833625 # mshr miss rate for UpgradeReq accesses 296system.l2c.UpgradeReq_mshr_miss_rate::total 0.929354 # mshr miss rate for UpgradeReq accesses 297system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.794393 # mshr miss rate for SCUpgradeReq accesses 298system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SCUpgradeReq accesses 299system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.789954 # mshr miss rate for SCUpgradeReq accesses 300system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.500530 # mshr miss rate for ReadExReq accesses 301system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.175208 # mshr miss rate for ReadExReq accesses 302system.l2c.ReadExReq_mshr_miss_rate::total 0.379415 # mshr miss rate for ReadExReq accesses 303system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for demand accesses 304system.l2c.demand_mshr_miss_rate::cpu0.data 0.456031 # mshr miss rate for demand accesses 305system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for demand accesses 306system.l2c.demand_mshr_miss_rate::cpu1.data 0.036390 # mshr miss rate for demand accesses 307system.l2c.demand_mshr_miss_rate::total 0.167675 # mshr miss rate for demand accesses 308system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for overall accesses 309system.l2c.overall_mshr_miss_rate::cpu0.data 0.456031 # mshr miss rate for overall accesses 310system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for overall accesses 311system.l2c.overall_mshr_miss_rate::cpu1.data 0.036390 # mshr miss rate for overall accesses 312system.l2c.overall_mshr_miss_rate::total 0.167675 # mshr miss rate for overall accesses 313system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average ReadReq mshr miss latency 314system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.629730 # average ReadReq mshr miss latency 315system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average ReadReq mshr miss latency 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40369.942197 # average ReadReq mshr miss latency 317system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.302647 # average ReadReq mshr miss latency 318system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.372671 # average UpgradeReq mshr miss latency 319system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40102.941176 # average UpgradeReq mshr miss latency 320system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40050.131062 # average UpgradeReq mshr miss latency 321system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40223.529412 # average SCUpgradeReq mshr miss latency |
| 322system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency | 322system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency |
| 323system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 324system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.363984 # average ReadExReq mshr miss latency 325system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.992228 # average ReadExReq mshr miss latency 326system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.295729 # average ReadExReq mshr miss latency 327system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average overall mshr miss latency 328system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency 329system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency 332system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.254300 # average overall mshr miss latency 333system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.578027 # average overall mshr miss latency 334system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.372976 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::total 40013.135837 # average overall mshr miss latency | 323system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40109.826590 # average SCUpgradeReq mshr miss latency 324system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736274 # average ReadExReq mshr miss latency 325system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40001.801546 # average ReadExReq mshr miss latency 326system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575576 # average ReadExReq mshr miss latency 327system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average overall mshr miss latency 328system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291203 # average overall mshr miss latency 329system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average overall mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency 331system.l2c.demand_avg_mshr_miss_latency::total 40014.971542 # average overall mshr miss latency 332system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average overall mshr miss latency 333system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291203 # average overall mshr miss latency 334system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency 336system.l2c.overall_avg_mshr_miss_latency::total 40014.971542 # average overall mshr miss latency |
| 337system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 338system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 339system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 340system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 341system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 342system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 343system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 344system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 345system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 346system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 337system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 338system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 339system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 340system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 341system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 342system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 343system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 344system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 345system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 346system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 347system.iocache.replacements 41694 # number of replacements 348system.iocache.tagsinuse 0.563379 # Cycle average of tags in use | 347system.iocache.replacements 41707 # number of replacements 348system.iocache.tagsinuse 1.261560 # Cycle average of tags in use |
| 349system.iocache.total_refs 0 # Total number of references to valid blocks. | 349system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 350system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. | 350system.iocache.sampled_refs 41723 # Sample count of references to valid blocks. |
| 351system.iocache.avg_refs 0 # Average number of references to valid blocks. | 351system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 352system.iocache.warmup_cycle 1750565168000 # Cycle when the warmup percentage was hit. 353system.iocache.occ_blocks::tsunami.ide 0.563379 # Average occupied blocks per requestor 354system.iocache.occ_percent::tsunami.ide 0.035211 # Average percentage of cache occupancy 355system.iocache.occ_percent::total 0.035211 # Average percentage of cache occupancy 356system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 357system.iocache.ReadReq_misses::total 174 # number of ReadReq misses | 352system.iocache.warmup_cycle 1747651126000 # Cycle when the warmup percentage was hit. 353system.iocache.occ_blocks::tsunami.ide 1.261560 # Average occupied blocks per requestor 354system.iocache.occ_percent::tsunami.ide 0.078847 # Average percentage of cache occupancy 355system.iocache.occ_percent::total 0.078847 # Average percentage of cache occupancy 356system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 357system.iocache.ReadReq_misses::total 176 # number of ReadReq misses |
| 358system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 359system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses | 358system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 359system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses |
| 360system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 361system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 362system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 363system.iocache.overall_misses::total 41726 # number of overall misses 364system.iocache.ReadReq_miss_latency::tsunami.ide 20052998 # number of ReadReq miss cycles 365system.iocache.ReadReq_miss_latency::total 20052998 # number of ReadReq miss cycles 366system.iocache.WriteReq_miss_latency::tsunami.ide 5719883806 # number of WriteReq miss cycles 367system.iocache.WriteReq_miss_latency::total 5719883806 # number of WriteReq miss cycles 368system.iocache.demand_miss_latency::tsunami.ide 5739936804 # number of demand (read+write) miss cycles 369system.iocache.demand_miss_latency::total 5739936804 # number of demand (read+write) miss cycles 370system.iocache.overall_miss_latency::tsunami.ide 5739936804 # number of overall miss cycles 371system.iocache.overall_miss_latency::total 5739936804 # number of overall miss cycles 372system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 373system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) | 360system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 361system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 362system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 363system.iocache.overall_misses::total 41728 # number of overall misses 364system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles 365system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles 366system.iocache.WriteReq_miss_latency::tsunami.ide 7626020806 # number of WriteReq miss cycles 367system.iocache.WriteReq_miss_latency::total 7626020806 # number of WriteReq miss cycles 368system.iocache.demand_miss_latency::tsunami.ide 7647034804 # number of demand (read+write) miss cycles 369system.iocache.demand_miss_latency::total 7647034804 # number of demand (read+write) miss cycles 370system.iocache.overall_miss_latency::tsunami.ide 7647034804 # number of overall miss cycles 371system.iocache.overall_miss_latency::total 7647034804 # number of overall miss cycles 372system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 373system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) |
| 374system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 375system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) | 374system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 375system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) |
| 376system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 377system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 378system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 379system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses | 376system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 377system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 378system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 379system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses |
| 380system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 381system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 382system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 383system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 384system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 385system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 386system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 387system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 380system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 381system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 382system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 383system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 384system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 385system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 386system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 387system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 388system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency 389system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency 390system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137656.040768 # average WriteReq miss latency 391system.iocache.WriteReq_avg_miss_latency::total 137656.040768 # average WriteReq miss latency 392system.iocache.demand_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency 393system.iocache.demand_avg_miss_latency::total 137562.594162 # average overall miss latency 394system.iocache.overall_avg_miss_latency::tsunami.ide 137562.594162 # average overall miss latency 395system.iocache.overall_avg_miss_latency::total 137562.594162 # average overall miss latency 396system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked | 388system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency 389system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency 390system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183529.572728 # average WriteReq miss latency 391system.iocache.WriteReq_avg_miss_latency::total 183529.572728 # average WriteReq miss latency 392system.iocache.demand_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency 393system.iocache.demand_avg_miss_latency::total 183259.077933 # average overall miss latency 394system.iocache.overall_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency 395system.iocache.overall_avg_miss_latency::total 183259.077933 # average overall miss latency 396system.iocache.blocked_cycles::no_mshrs 7245000 # number of cycles access was blocked |
| 397system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 397system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 398system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked | 398system.iocache.blocked::no_mshrs 7076 # number of cycles access was blocked |
| 399system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 399system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 400system.iocache.avg_blocked_cycles::no_mshrs 6179.373554 # average number of cycles each access was blocked | 400system.iocache.avg_blocked_cycles::no_mshrs 1023.883550 # average number of cycles each access was blocked |
| 401system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.iocache.fast_writes 0 # number of fast writes performed 403system.iocache.cache_copies 0 # number of cache copies performed | 401system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.iocache.fast_writes 0 # number of fast writes performed 403system.iocache.cache_copies 0 # number of cache copies performed |
| 404system.iocache.writebacks::writebacks 41520 # number of writebacks 405system.iocache.writebacks::total 41520 # number of writebacks 406system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 407system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses | 404system.iocache.writebacks::writebacks 41531 # number of writebacks 405system.iocache.writebacks::total 41531 # number of writebacks 406system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 407system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses |
| 408system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 409system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses | 408system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 409system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses |
| 410system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses 411system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses 412system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses 413system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses 414system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles 415system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles 416system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3559028000 # number of WriteReq MSHR miss cycles 417system.iocache.WriteReq_mshr_miss_latency::total 3559028000 # number of WriteReq MSHR miss cycles 418system.iocache.demand_mshr_miss_latency::tsunami.ide 3570032998 # number of demand (read+write) MSHR miss cycles 419system.iocache.demand_mshr_miss_latency::total 3570032998 # number of demand (read+write) MSHR miss cycles 420system.iocache.overall_mshr_miss_latency::tsunami.ide 3570032998 # number of overall MSHR miss cycles 421system.iocache.overall_mshr_miss_latency::total 3570032998 # number of overall MSHR miss cycles | 410system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 411system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 412system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 413system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 414system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861000 # number of ReadReq MSHR miss cycles 415system.iocache.ReadReq_mshr_miss_latency::total 11861000 # number of ReadReq MSHR miss cycles 416system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465163000 # number of WriteReq MSHR miss cycles 417system.iocache.WriteReq_mshr_miss_latency::total 5465163000 # number of WriteReq MSHR miss cycles 418system.iocache.demand_mshr_miss_latency::tsunami.ide 5477024000 # number of demand (read+write) MSHR miss cycles 419system.iocache.demand_mshr_miss_latency::total 5477024000 # number of demand (read+write) MSHR miss cycles 420system.iocache.overall_mshr_miss_latency::tsunami.ide 5477024000 # number of overall MSHR miss cycles 421system.iocache.overall_mshr_miss_latency::total 5477024000 # number of overall MSHR miss cycles |
| 422system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 424system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 425system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 422system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 424system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 425system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency 431system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency 432system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85652.387370 # average WriteReq mshr miss latency 433system.iocache.WriteReq_avg_mshr_miss_latency::total 85652.387370 # average WriteReq mshr miss latency 434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency 435system.iocache.demand_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency 436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85558.955999 # average overall mshr miss latency 437system.iocache.overall_avg_mshr_miss_latency::total 85558.955999 # average overall mshr miss latency | 430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455 # average ReadReq mshr miss latency 431system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455 # average ReadReq mshr miss latency 432system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131525.871198 # average WriteReq mshr miss latency 433system.iocache.WriteReq_avg_mshr_miss_latency::total 131525.871198 # average WriteReq mshr miss latency 434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency 435system.iocache.demand_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency 436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency 437system.iocache.overall_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency |
| 438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 442system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 443system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 444system.disk0.dma_write_txs 395 # Number of DMA write transactions. 445system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 446system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 447system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 448system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 449system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 450system.disk2.dma_write_txs 1 # Number of DMA write transactions. 451system.cpu0.dtb.fetch_hits 0 # ITB hits 452system.cpu0.dtb.fetch_misses 0 # ITB misses 453system.cpu0.dtb.fetch_acv 0 # ITB acv 454system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 442system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 443system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 444system.disk0.dma_write_txs 395 # Number of DMA write transactions. 445system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 446system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 447system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 448system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 449system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 450system.disk2.dma_write_txs 1 # Number of DMA write transactions. 451system.cpu0.dtb.fetch_hits 0 # ITB hits 452system.cpu0.dtb.fetch_misses 0 # ITB misses 453system.cpu0.dtb.fetch_acv 0 # ITB acv 454system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 455system.cpu0.dtb.read_hits 8630502 # DTB read hits 456system.cpu0.dtb.read_misses 7443 # DTB read misses 457system.cpu0.dtb.read_acv 210 # DTB read access violations 458system.cpu0.dtb.read_accesses 490673 # DTB read accesses 459system.cpu0.dtb.write_hits 6043026 # DTB write hits 460system.cpu0.dtb.write_misses 813 # DTB write misses 461system.cpu0.dtb.write_acv 134 # DTB write access violations 462system.cpu0.dtb.write_accesses 187452 # DTB write accesses 463system.cpu0.dtb.data_hits 14673528 # DTB hits 464system.cpu0.dtb.data_misses 8256 # DTB misses 465system.cpu0.dtb.data_acv 344 # DTB access violations 466system.cpu0.dtb.data_accesses 678125 # DTB accesses 467system.cpu0.itb.fetch_hits 3852973 # ITB hits 468system.cpu0.itb.fetch_misses 3871 # ITB misses 469system.cpu0.itb.fetch_acv 184 # ITB acv 470system.cpu0.itb.fetch_accesses 3856844 # ITB accesses | 455system.cpu0.dtb.read_hits 5733478 # DTB read hits 456system.cpu0.dtb.read_misses 7687 # DTB read misses 457system.cpu0.dtb.read_acv 174 # DTB read access violations 458system.cpu0.dtb.read_accesses 524201 # DTB read accesses 459system.cpu0.dtb.write_hits 3961950 # DTB write hits 460system.cpu0.dtb.write_misses 798 # DTB write misses 461system.cpu0.dtb.write_acv 115 # DTB write access violations 462system.cpu0.dtb.write_accesses 195659 # DTB write accesses 463system.cpu0.dtb.data_hits 9695428 # DTB hits 464system.cpu0.dtb.data_misses 8485 # DTB misses 465system.cpu0.dtb.data_acv 289 # DTB access violations 466system.cpu0.dtb.data_accesses 719860 # DTB accesses 467system.cpu0.itb.fetch_hits 3214168 # ITB hits 468system.cpu0.itb.fetch_misses 3841 # ITB misses 469system.cpu0.itb.fetch_acv 143 # ITB acv 470system.cpu0.itb.fetch_accesses 3218009 # ITB accesses |
| 471system.cpu0.itb.read_hits 0 # DTB read hits 472system.cpu0.itb.read_misses 0 # DTB read misses 473system.cpu0.itb.read_acv 0 # DTB read access violations 474system.cpu0.itb.read_accesses 0 # DTB read accesses 475system.cpu0.itb.write_hits 0 # DTB write hits 476system.cpu0.itb.write_misses 0 # DTB write misses 477system.cpu0.itb.write_acv 0 # DTB write access violations 478system.cpu0.itb.write_accesses 0 # DTB write accesses 479system.cpu0.itb.data_hits 0 # DTB hits 480system.cpu0.itb.data_misses 0 # DTB misses 481system.cpu0.itb.data_acv 0 # DTB access violations 482system.cpu0.itb.data_accesses 0 # DTB accesses | 471system.cpu0.itb.read_hits 0 # DTB read hits 472system.cpu0.itb.read_misses 0 # DTB read misses 473system.cpu0.itb.read_acv 0 # DTB read access violations 474system.cpu0.itb.read_accesses 0 # DTB read accesses 475system.cpu0.itb.write_hits 0 # DTB write hits 476system.cpu0.itb.write_misses 0 # DTB write misses 477system.cpu0.itb.write_acv 0 # DTB write access violations 478system.cpu0.itb.write_accesses 0 # DTB write accesses 479system.cpu0.itb.data_hits 0 # DTB hits 480system.cpu0.itb.data_misses 0 # DTB misses 481system.cpu0.itb.data_acv 0 # DTB access violations 482system.cpu0.itb.data_accesses 0 # DTB accesses |
| 483system.cpu0.numCycles 3914070794 # number of cpu cycles simulated | 483system.cpu0.numCycles 3908418212 # number of cpu cycles simulated |
| 484system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 485system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 484system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 485system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 486system.cpu0.committedInsts 54051547 # Number of instructions committed 487system.cpu0.committedOps 54051547 # Number of ops (including micro ops) committed 488system.cpu0.num_int_alu_accesses 50023130 # Number of integer alu accesses 489system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses 490system.cpu0.num_func_calls 1426247 # number of times a function call or return occured 491system.cpu0.num_conditional_control_insts 6235141 # number of instructions that are conditional controls 492system.cpu0.num_int_insts 50023130 # number of integer instructions 493system.cpu0.num_fp_insts 293967 # number of float instructions 494system.cpu0.num_int_register_reads 68498295 # number of times the integer registers were read 495system.cpu0.num_int_register_writes 37064173 # number of times the integer registers were written 496system.cpu0.num_fp_register_reads 143353 # number of times the floating registers were read 497system.cpu0.num_fp_register_writes 146452 # number of times the floating registers were written 498system.cpu0.num_mem_refs 14719518 # number of memory refs 499system.cpu0.num_load_insts 8661793 # Number of load instructions 500system.cpu0.num_store_insts 6057725 # Number of store instructions 501system.cpu0.num_idle_cycles 3679914036.735006 # Number of idle cycles 502system.cpu0.num_busy_cycles 234156757.264994 # Number of busy cycles 503system.cpu0.not_idle_fraction 0.059824 # Percentage of non-idle cycles 504system.cpu0.idle_fraction 0.940176 # Percentage of idle cycles | 486system.cpu0.committedInsts 36160823 # Number of instructions committed 487system.cpu0.committedOps 36160823 # Number of ops (including micro ops) committed 488system.cpu0.num_int_alu_accesses 33648358 # Number of integer alu accesses 489system.cpu0.num_fp_alu_accesses 143029 # Number of float alu accesses 490system.cpu0.num_func_calls 874754 # number of times a function call or return occured 491system.cpu0.num_conditional_control_insts 4239281 # number of instructions that are conditional controls 492system.cpu0.num_int_insts 33648358 # number of integer instructions 493system.cpu0.num_fp_insts 143029 # number of float instructions 494system.cpu0.num_int_register_reads 46246578 # number of times the integer registers were read 495system.cpu0.num_int_register_writes 25142775 # number of times the integer registers were written 496system.cpu0.num_fp_register_reads 70823 # number of times the floating registers were read 497system.cpu0.num_fp_register_writes 71471 # number of times the floating registers were written 498system.cpu0.num_mem_refs 9726012 # number of memory refs 499system.cpu0.num_load_insts 5755191 # Number of load instructions 500system.cpu0.num_store_insts 3970821 # Number of store instructions 501system.cpu0.num_idle_cycles 3741416410.998085 # Number of idle cycles 502system.cpu0.num_busy_cycles 167001801.001915 # Number of busy cycles 503system.cpu0.not_idle_fraction 0.042729 # Percentage of non-idle cycles 504system.cpu0.idle_fraction 0.957271 # Percentage of idle cycles |
| 505system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 505system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 506system.cpu0.kern.inst.quiesce 6362 # number of quiesce instructions executed 507system.cpu0.kern.inst.hwrei 202969 # number of hwrei instructions executed 508system.cpu0.kern.ipl_count::0 72743 40.62% 40.62% # number of times we switched to this ipl 509system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl 510system.cpu0.kern.ipl_count::22 1974 1.10% 41.80% # number of times we switched to this ipl 511system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl 512system.cpu0.kern.ipl_count::31 104206 58.20% 100.00% # number of times we switched to this ipl 513system.cpu0.kern.ipl_count::total 179060 # number of times we switched to this ipl 514system.cpu0.kern.ipl_good::0 71376 49.27% 49.27% # number of times we switched to this ipl from a different ipl 515system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl 516system.cpu0.kern.ipl_good::22 1974 1.36% 50.73% # number of times we switched to this ipl from a different ipl 517system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl 518system.cpu0.kern.ipl_good::31 71370 49.27% 100.00% # number of times we switched to this ipl from a different ipl 519system.cpu0.kern.ipl_good::total 144857 # number of times we switched to this ipl from a different ipl 520system.cpu0.kern.ipl_ticks::0 1898820258500 97.03% 97.03% # number of cycles we spent at this ipl 521system.cpu0.kern.ipl_ticks::21 78970000 0.00% 97.03% # number of cycles we spent at this ipl 522system.cpu0.kern.ipl_ticks::22 565865000 0.03% 97.06% # number of cycles we spent at this ipl 523system.cpu0.kern.ipl_ticks::30 4687500 0.00% 97.06% # number of cycles we spent at this ipl 524system.cpu0.kern.ipl_ticks::31 57565586000 2.94% 100.00% # number of cycles we spent at this ipl 525system.cpu0.kern.ipl_ticks::total 1957035367000 # number of cycles we spent at this ipl 526system.cpu0.kern.ipl_used::0 0.981208 # fraction of swpipl calls that actually changed the ipl | 506system.cpu0.kern.inst.quiesce 4839 # number of quiesce instructions executed 507system.cpu0.kern.inst.hwrei 129052 # number of hwrei instructions executed 508system.cpu0.kern.ipl_count::0 41012 38.31% 38.31% # number of times we switched to this ipl 509system.cpu0.kern.ipl_count::21 131 0.12% 38.43% # number of times we switched to this ipl 510system.cpu0.kern.ipl_count::22 1971 1.84% 40.28% # number of times we switched to this ipl 511system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl 512system.cpu0.kern.ipl_count::31 63918 59.71% 100.00% # number of times we switched to this ipl 513system.cpu0.kern.ipl_count::total 107049 # number of times we switched to this ipl 514system.cpu0.kern.ipl_good::0 40581 48.74% 48.74% # number of times we switched to this ipl from a different ipl 515system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl 516system.cpu0.kern.ipl_good::22 1971 2.37% 51.26% # number of times we switched to this ipl from a different ipl 517system.cpu0.kern.ipl_good::30 17 0.02% 51.28% # number of times we switched to this ipl from a different ipl 518system.cpu0.kern.ipl_good::31 40564 48.72% 100.00% # number of times we switched to this ipl from a different ipl 519system.cpu0.kern.ipl_good::total 83264 # number of times we switched to this ipl from a different ipl 520system.cpu0.kern.ipl_ticks::0 1905787793000 97.52% 97.52% # number of cycles we spent at this ipl 521system.cpu0.kern.ipl_ticks::21 88207500 0.00% 97.53% # number of cycles we spent at this ipl 522system.cpu0.kern.ipl_ticks::22 590484500 0.03% 97.56% # number of cycles we spent at this ipl 523system.cpu0.kern.ipl_ticks::30 12827000 0.00% 97.56% # number of cycles we spent at this ipl 524system.cpu0.kern.ipl_ticks::31 47728938000 2.44% 100.00% # number of cycles we spent at this ipl 525system.cpu0.kern.ipl_ticks::total 1954208250000 # number of cycles we spent at this ipl 526system.cpu0.kern.ipl_used::0 0.989491 # fraction of swpipl calls that actually changed the ipl |
| 527system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 528system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 529system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 527system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 528system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 529system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 530system.cpu0.kern.ipl_used::31 0.684893 # fraction of swpipl calls that actually changed the ipl 531system.cpu0.kern.ipl_used::total 0.808986 # fraction of swpipl calls that actually changed the ipl 532system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 533system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 534system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 535system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 536system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 537system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 538system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 539system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 540system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 541system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 542system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 543system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 544system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 545system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 546system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 547system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 548system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 549system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 550system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 551system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 552system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 553system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 554system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 555system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 556system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 557system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 558system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 559system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 560system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 561system.cpu0.kern.syscall::total 222 # number of syscalls executed | 530system.cpu0.kern.ipl_used::31 0.634626 # fraction of swpipl calls that actually changed the ipl 531system.cpu0.kern.ipl_used::total 0.777812 # fraction of swpipl calls that actually changed the ipl 532system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed 533system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed 534system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed 535system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed 536system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed 537system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed 538system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed 539system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed 540system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed 541system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed 542system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed 543system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed 544system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed 545system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed 546system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed 547system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed 548system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed 549system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed 550system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed 551system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed 552system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed 553system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed 554system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed 555system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed 556system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed 557system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed 558system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed 559system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed 560system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed 561system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed 562system.cpu0.kern.syscall::total 224 # number of syscalls executed |
| 562system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 563system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 563system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed 564system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed 565system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed 566system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed 567system.cpu0.kern.callpal::swpctx 3894 2.07% 2.12% # number of callpals executed 568system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed 569system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed 570system.cpu0.kern.callpal::swpipl 172198 91.50% 93.65% # number of callpals executed 571system.cpu0.kern.callpal::rdps 6677 3.55% 97.19% # number of callpals executed 572system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed 573system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed 574system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed 575system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed 576system.cpu0.kern.callpal::rti 4750 2.52% 99.73% # number of callpals executed 577system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed 578system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed 579system.cpu0.kern.callpal::total 188201 # number of callpals executed 580system.cpu0.kern.mode_switch::kernel 7301 # number of protection mode switches 581system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches | 564system.cpu0.kern.callpal::wripir 91 0.08% 0.08% # number of callpals executed 565system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed 566system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed 567system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed 568system.cpu0.kern.callpal::swpctx 1959 1.72% 1.80% # number of callpals executed 569system.cpu0.kern.callpal::tbi 44 0.04% 1.84% # number of callpals executed 570system.cpu0.kern.callpal::wrent 7 0.01% 1.84% # number of callpals executed 571system.cpu0.kern.callpal::swpipl 101151 88.59% 90.44% # number of callpals executed 572system.cpu0.kern.callpal::rdps 6620 5.80% 96.24% # number of callpals executed 573system.cpu0.kern.callpal::wrkgp 1 0.00% 96.24% # number of callpals executed 574system.cpu0.kern.callpal::wrusp 4 0.00% 96.24% # number of callpals executed 575system.cpu0.kern.callpal::rdusp 7 0.01% 96.25% # number of callpals executed 576system.cpu0.kern.callpal::whami 2 0.00% 96.25% # number of callpals executed 577system.cpu0.kern.callpal::rti 3778 3.31% 99.56% # number of callpals executed 578system.cpu0.kern.callpal::callsys 356 0.31% 99.87% # number of callpals executed 579system.cpu0.kern.callpal::imb 149 0.13% 100.00% # number of callpals executed 580system.cpu0.kern.callpal::total 114173 # number of callpals executed 581system.cpu0.kern.mode_switch::kernel 5323 # number of protection mode switches 582system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches |
| 582system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 583system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 583system.cpu0.kern.mode_good::kernel 1283 584system.cpu0.kern.mode_good::user 1283 | 584system.cpu0.kern.mode_good::kernel 1229 585system.cpu0.kern.mode_good::user 1230 |
| 585system.cpu0.kern.mode_good::idle 0 | 586system.cpu0.kern.mode_good::idle 0 |
| 586system.cpu0.kern.mode_switch_good::kernel 0.175729 # fraction of useful protection mode switches | 587system.cpu0.kern.mode_switch_good::kernel 0.230885 # fraction of useful protection mode switches |
| 587system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 588system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 588system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 589system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 589system.cpu0.kern.mode_switch_good::total 0.298928 # fraction of useful protection mode switches 590system.cpu0.kern.mode_ticks::kernel 1953310949000 99.83% 99.83% # number of ticks spent at the given mode 591system.cpu0.kern.mode_ticks::user 3370111000 0.17% 100.00% # number of ticks spent at the given mode | 590system.cpu0.kern.mode_switch_good::total 0.375248 # fraction of useful protection mode switches 591system.cpu0.kern.mode_ticks::kernel 1950524029000 99.81% 99.81% # number of ticks spent at the given mode 592system.cpu0.kern.mode_ticks::user 3684214000 0.19% 100.00% # number of ticks spent at the given mode |
| 592system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 593system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 593system.cpu0.kern.swap_context 3895 # number of times the context was actually changed | 594system.cpu0.kern.swap_context 1960 # number of times the context was actually changed |
| 594system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 595system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 596system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 597system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 598system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 599system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 600system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 601system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 617system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 618system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 619system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 620system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 621system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 622system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 623system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 624system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 595system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 596system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 597system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 598system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 599system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 600system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 601system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 602system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 618system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 619system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 620system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 621system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 622system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 623system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 624system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 625system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 625system.cpu0.icache.replacements 914734 # number of replacements 626system.cpu0.icache.tagsinuse 508.814250 # Cycle average of tags in use 627system.cpu0.icache.total_refs 53144779 # Total number of references to valid blocks. 628system.cpu0.icache.sampled_refs 915246 # Sample count of references to valid blocks. 629system.cpu0.icache.avg_refs 58.066114 # Average number of references to valid blocks. 630system.cpu0.icache.warmup_cycle 35914239000 # Cycle when the warmup percentage was hit. 631system.cpu0.icache.occ_blocks::cpu0.inst 508.814250 # Average occupied blocks per requestor 632system.cpu0.icache.occ_percent::cpu0.inst 0.993778 # Average percentage of cache occupancy 633system.cpu0.icache.occ_percent::total 0.993778 # Average percentage of cache occupancy 634system.cpu0.icache.ReadReq_hits::cpu0.inst 53144779 # number of ReadReq hits 635system.cpu0.icache.ReadReq_hits::total 53144779 # number of ReadReq hits 636system.cpu0.icache.demand_hits::cpu0.inst 53144779 # number of demand (read+write) hits 637system.cpu0.icache.demand_hits::total 53144779 # number of demand (read+write) hits 638system.cpu0.icache.overall_hits::cpu0.inst 53144779 # number of overall hits 639system.cpu0.icache.overall_hits::total 53144779 # number of overall hits 640system.cpu0.icache.ReadReq_misses::cpu0.inst 915368 # number of ReadReq misses 641system.cpu0.icache.ReadReq_misses::total 915368 # number of ReadReq misses 642system.cpu0.icache.demand_misses::cpu0.inst 915368 # number of demand (read+write) misses 643system.cpu0.icache.demand_misses::total 915368 # number of demand (read+write) misses 644system.cpu0.icache.overall_misses::cpu0.inst 915368 # number of overall misses 645system.cpu0.icache.overall_misses::total 915368 # number of overall misses 646system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13361799000 # number of ReadReq miss cycles 647system.cpu0.icache.ReadReq_miss_latency::total 13361799000 # number of ReadReq miss cycles 648system.cpu0.icache.demand_miss_latency::cpu0.inst 13361799000 # number of demand (read+write) miss cycles 649system.cpu0.icache.demand_miss_latency::total 13361799000 # number of demand (read+write) miss cycles 650system.cpu0.icache.overall_miss_latency::cpu0.inst 13361799000 # number of overall miss cycles 651system.cpu0.icache.overall_miss_latency::total 13361799000 # number of overall miss cycles 652system.cpu0.icache.ReadReq_accesses::cpu0.inst 54060147 # number of ReadReq accesses(hits+misses) 653system.cpu0.icache.ReadReq_accesses::total 54060147 # number of ReadReq accesses(hits+misses) 654system.cpu0.icache.demand_accesses::cpu0.inst 54060147 # number of demand (read+write) accesses 655system.cpu0.icache.demand_accesses::total 54060147 # number of demand (read+write) accesses 656system.cpu0.icache.overall_accesses::cpu0.inst 54060147 # number of overall (read+write) accesses 657system.cpu0.icache.overall_accesses::total 54060147 # number of overall (read+write) accesses 658system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016932 # miss rate for ReadReq accesses 659system.cpu0.icache.ReadReq_miss_rate::total 0.016932 # miss rate for ReadReq accesses 660system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016932 # miss rate for demand accesses 661system.cpu0.icache.demand_miss_rate::total 0.016932 # miss rate for demand accesses 662system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016932 # miss rate for overall accesses 663system.cpu0.icache.overall_miss_rate::total 0.016932 # miss rate for overall accesses 664system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14597.188235 # average ReadReq miss latency 665system.cpu0.icache.ReadReq_avg_miss_latency::total 14597.188235 # average ReadReq miss latency 666system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency 667system.cpu0.icache.demand_avg_miss_latency::total 14597.188235 # average overall miss latency 668system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14597.188235 # average overall miss latency 669system.cpu0.icache.overall_avg_miss_latency::total 14597.188235 # average overall miss latency | 626system.cpu0.icache.replacements 489211 # number of replacements 627system.cpu0.icache.tagsinuse 508.795621 # Cycle average of tags in use 628system.cpu0.icache.total_refs 35679745 # Total number of references to valid blocks. 629system.cpu0.icache.sampled_refs 489723 # Sample count of references to valid blocks. 630system.cpu0.icache.avg_refs 72.856993 # Average number of references to valid blocks. 631system.cpu0.icache.warmup_cycle 36113258000 # Cycle when the warmup percentage was hit. 632system.cpu0.icache.occ_blocks::cpu0.inst 508.795621 # Average occupied blocks per requestor 633system.cpu0.icache.occ_percent::cpu0.inst 0.993741 # Average percentage of cache occupancy 634system.cpu0.icache.occ_percent::total 0.993741 # Average percentage of cache occupancy 635system.cpu0.icache.ReadReq_hits::cpu0.inst 35679745 # number of ReadReq hits 636system.cpu0.icache.ReadReq_hits::total 35679745 # number of ReadReq hits 637system.cpu0.icache.demand_hits::cpu0.inst 35679745 # number of demand (read+write) hits 638system.cpu0.icache.demand_hits::total 35679745 # number of demand (read+write) hits 639system.cpu0.icache.overall_hits::cpu0.inst 35679745 # number of overall hits 640system.cpu0.icache.overall_hits::total 35679745 # number of overall hits 641system.cpu0.icache.ReadReq_misses::cpu0.inst 489853 # number of ReadReq misses 642system.cpu0.icache.ReadReq_misses::total 489853 # number of ReadReq misses 643system.cpu0.icache.demand_misses::cpu0.inst 489853 # number of demand (read+write) misses 644system.cpu0.icache.demand_misses::total 489853 # number of demand (read+write) misses 645system.cpu0.icache.overall_misses::cpu0.inst 489853 # number of overall misses 646system.cpu0.icache.overall_misses::total 489853 # number of overall misses 647system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462564000 # number of ReadReq miss cycles 648system.cpu0.icache.ReadReq_miss_latency::total 7462564000 # number of ReadReq miss cycles 649system.cpu0.icache.demand_miss_latency::cpu0.inst 7462564000 # number of demand (read+write) miss cycles 650system.cpu0.icache.demand_miss_latency::total 7462564000 # number of demand (read+write) miss cycles 651system.cpu0.icache.overall_miss_latency::cpu0.inst 7462564000 # number of overall miss cycles 652system.cpu0.icache.overall_miss_latency::total 7462564000 # number of overall miss cycles 653system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169598 # number of ReadReq accesses(hits+misses) 654system.cpu0.icache.ReadReq_accesses::total 36169598 # number of ReadReq accesses(hits+misses) 655system.cpu0.icache.demand_accesses::cpu0.inst 36169598 # number of demand (read+write) accesses 656system.cpu0.icache.demand_accesses::total 36169598 # number of demand (read+write) accesses 657system.cpu0.icache.overall_accesses::cpu0.inst 36169598 # number of overall (read+write) accesses 658system.cpu0.icache.overall_accesses::total 36169598 # number of overall (read+write) accesses 659system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013543 # miss rate for ReadReq accesses 660system.cpu0.icache.ReadReq_miss_rate::total 0.013543 # miss rate for ReadReq accesses 661system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013543 # miss rate for demand accesses 662system.cpu0.icache.demand_miss_rate::total 0.013543 # miss rate for demand accesses 663system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013543 # miss rate for overall accesses 664system.cpu0.icache.overall_miss_rate::total 0.013543 # miss rate for overall accesses 665system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15234.292737 # average ReadReq miss latency 666system.cpu0.icache.ReadReq_avg_miss_latency::total 15234.292737 # average ReadReq miss latency 667system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency 668system.cpu0.icache.demand_avg_miss_latency::total 15234.292737 # average overall miss latency 669system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency 670system.cpu0.icache.overall_avg_miss_latency::total 15234.292737 # average overall miss latency |
| 670system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 671system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 672system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 673system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 674system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 675system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 676system.cpu0.icache.fast_writes 0 # number of fast writes performed 677system.cpu0.icache.cache_copies 0 # number of cache copies performed | 671system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 672system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 673system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 674system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 675system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 676system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 677system.cpu0.icache.fast_writes 0 # number of fast writes performed 678system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 678system.cpu0.icache.writebacks::writebacks 55 # number of writebacks 679system.cpu0.icache.writebacks::total 55 # number of writebacks 680system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915368 # number of ReadReq MSHR misses 681system.cpu0.icache.ReadReq_mshr_misses::total 915368 # number of ReadReq MSHR misses 682system.cpu0.icache.demand_mshr_misses::cpu0.inst 915368 # number of demand (read+write) MSHR misses 683system.cpu0.icache.demand_mshr_misses::total 915368 # number of demand (read+write) MSHR misses 684system.cpu0.icache.overall_mshr_misses::cpu0.inst 915368 # number of overall MSHR misses 685system.cpu0.icache.overall_mshr_misses::total 915368 # number of overall MSHR misses 686system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10614998000 # number of ReadReq MSHR miss cycles 687system.cpu0.icache.ReadReq_mshr_miss_latency::total 10614998000 # number of ReadReq MSHR miss cycles 688system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10614998000 # number of demand (read+write) MSHR miss cycles 689system.cpu0.icache.demand_mshr_miss_latency::total 10614998000 # number of demand (read+write) MSHR miss cycles 690system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10614998000 # number of overall MSHR miss cycles 691system.cpu0.icache.overall_mshr_miss_latency::total 10614998000 # number of overall MSHR miss cycles 692system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for ReadReq accesses 693system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016932 # mshr miss rate for ReadReq accesses 694system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for demand accesses 695system.cpu0.icache.demand_mshr_miss_rate::total 0.016932 # mshr miss rate for demand accesses 696system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016932 # mshr miss rate for overall accesses 697system.cpu0.icache.overall_mshr_miss_rate::total 0.016932 # mshr miss rate for overall accesses 698system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average ReadReq mshr miss latency 699system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11596.426792 # average ReadReq mshr miss latency 700system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency 701system.cpu0.icache.demand_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency 702system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.426792 # average overall mshr miss latency 703system.cpu0.icache.overall_avg_mshr_miss_latency::total 11596.426792 # average overall mshr miss latency | 679system.cpu0.icache.writebacks::writebacks 58 # number of writebacks 680system.cpu0.icache.writebacks::total 58 # number of writebacks 681system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489853 # number of ReadReq MSHR misses 682system.cpu0.icache.ReadReq_mshr_misses::total 489853 # number of ReadReq MSHR misses 683system.cpu0.icache.demand_mshr_misses::cpu0.inst 489853 # number of demand (read+write) MSHR misses 684system.cpu0.icache.demand_mshr_misses::total 489853 # number of demand (read+write) MSHR misses 685system.cpu0.icache.overall_mshr_misses::cpu0.inst 489853 # number of overall MSHR misses 686system.cpu0.icache.overall_mshr_misses::total 489853 # number of overall MSHR misses 687system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992343500 # number of ReadReq MSHR miss cycles 688system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992343500 # number of ReadReq MSHR miss cycles 689system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992343500 # number of demand (read+write) MSHR miss cycles 690system.cpu0.icache.demand_mshr_miss_latency::total 5992343500 # number of demand (read+write) MSHR miss cycles 691system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992343500 # number of overall MSHR miss cycles 692system.cpu0.icache.overall_mshr_miss_latency::total 5992343500 # number of overall MSHR miss cycles 693system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for ReadReq accesses 694system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013543 # mshr miss rate for ReadReq accesses 695system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for demand accesses 696system.cpu0.icache.demand_mshr_miss_rate::total 0.013543 # mshr miss rate for demand accesses 697system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for overall accesses 698system.cpu0.icache.overall_mshr_miss_rate::total 0.013543 # mshr miss rate for overall accesses 699system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average ReadReq mshr miss latency 700system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.942332 # average ReadReq mshr miss latency 701system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency 702system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency 703system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency 704system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency |
| 704system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 705system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 705system.cpu0.dcache.replacements 1337419 # number of replacements 706system.cpu0.dcache.tagsinuse 506.341163 # Cycle average of tags in use 707system.cpu0.dcache.total_refs 13344261 # Total number of references to valid blocks. 708system.cpu0.dcache.sampled_refs 1337832 # Sample count of references to valid blocks. 709system.cpu0.dcache.avg_refs 9.974542 # Average number of references to valid blocks. 710system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. 711system.cpu0.dcache.occ_blocks::cpu0.data 506.341163 # Average occupied blocks per requestor 712system.cpu0.dcache.occ_percent::cpu0.data 0.988948 # Average percentage of cache occupancy 713system.cpu0.dcache.occ_percent::total 0.988948 # Average percentage of cache occupancy 714system.cpu0.dcache.ReadReq_hits::cpu0.data 7419012 # number of ReadReq hits 715system.cpu0.dcache.ReadReq_hits::total 7419012 # number of ReadReq hits 716system.cpu0.dcache.WriteReq_hits::cpu0.data 5558431 # number of WriteReq hits 717system.cpu0.dcache.WriteReq_hits::total 5558431 # number of WriteReq hits 718system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176349 # number of LoadLockedReq hits 719system.cpu0.dcache.LoadLockedReq_hits::total 176349 # number of LoadLockedReq hits 720system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191666 # number of StoreCondReq hits 721system.cpu0.dcache.StoreCondReq_hits::total 191666 # number of StoreCondReq hits 722system.cpu0.dcache.demand_hits::cpu0.data 12977443 # number of demand (read+write) hits 723system.cpu0.dcache.demand_hits::total 12977443 # number of demand (read+write) hits 724system.cpu0.dcache.overall_hits::cpu0.data 12977443 # number of overall hits 725system.cpu0.dcache.overall_hits::total 12977443 # number of overall hits 726system.cpu0.dcache.ReadReq_misses::cpu0.data 1034980 # number of ReadReq misses 727system.cpu0.dcache.ReadReq_misses::total 1034980 # number of ReadReq misses 728system.cpu0.dcache.WriteReq_misses::cpu0.data 291529 # number of WriteReq misses 729system.cpu0.dcache.WriteReq_misses::total 291529 # number of WriteReq misses 730system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16694 # number of LoadLockedReq misses 731system.cpu0.dcache.LoadLockedReq_misses::total 16694 # number of LoadLockedReq misses 732system.cpu0.dcache.StoreCondReq_misses::cpu0.data 411 # number of StoreCondReq misses 733system.cpu0.dcache.StoreCondReq_misses::total 411 # number of StoreCondReq misses 734system.cpu0.dcache.demand_misses::cpu0.data 1326509 # number of demand (read+write) misses 735system.cpu0.dcache.demand_misses::total 1326509 # number of demand (read+write) misses 736system.cpu0.dcache.overall_misses::cpu0.data 1326509 # number of overall misses 737system.cpu0.dcache.overall_misses::total 1326509 # number of overall misses 738system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 25827814500 # number of ReadReq miss cycles 739system.cpu0.dcache.ReadReq_miss_latency::total 25827814500 # number of ReadReq miss cycles 740system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9022984000 # number of WriteReq miss cycles 741system.cpu0.dcache.WriteReq_miss_latency::total 9022984000 # number of WriteReq miss cycles 742system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234039000 # number of LoadLockedReq miss cycles 743system.cpu0.dcache.LoadLockedReq_miss_latency::total 234039000 # number of LoadLockedReq miss cycles 744system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2995000 # number of StoreCondReq miss cycles 745system.cpu0.dcache.StoreCondReq_miss_latency::total 2995000 # number of StoreCondReq miss cycles 746system.cpu0.dcache.demand_miss_latency::cpu0.data 34850798500 # number of demand (read+write) miss cycles 747system.cpu0.dcache.demand_miss_latency::total 34850798500 # number of demand (read+write) miss cycles 748system.cpu0.dcache.overall_miss_latency::cpu0.data 34850798500 # number of overall miss cycles 749system.cpu0.dcache.overall_miss_latency::total 34850798500 # number of overall miss cycles 750system.cpu0.dcache.ReadReq_accesses::cpu0.data 8453992 # number of ReadReq accesses(hits+misses) 751system.cpu0.dcache.ReadReq_accesses::total 8453992 # number of ReadReq accesses(hits+misses) 752system.cpu0.dcache.WriteReq_accesses::cpu0.data 5849960 # number of WriteReq accesses(hits+misses) 753system.cpu0.dcache.WriteReq_accesses::total 5849960 # number of WriteReq accesses(hits+misses) 754system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193043 # number of LoadLockedReq accesses(hits+misses) 755system.cpu0.dcache.LoadLockedReq_accesses::total 193043 # number of LoadLockedReq accesses(hits+misses) 756system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192077 # number of StoreCondReq accesses(hits+misses) 757system.cpu0.dcache.StoreCondReq_accesses::total 192077 # number of StoreCondReq accesses(hits+misses) 758system.cpu0.dcache.demand_accesses::cpu0.data 14303952 # number of demand (read+write) accesses 759system.cpu0.dcache.demand_accesses::total 14303952 # number of demand (read+write) accesses 760system.cpu0.dcache.overall_accesses::cpu0.data 14303952 # number of overall (read+write) accesses 761system.cpu0.dcache.overall_accesses::total 14303952 # number of overall (read+write) accesses 762system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122425 # miss rate for ReadReq accesses 763system.cpu0.dcache.ReadReq_miss_rate::total 0.122425 # miss rate for ReadReq accesses 764system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049834 # miss rate for WriteReq accesses 765system.cpu0.dcache.WriteReq_miss_rate::total 0.049834 # miss rate for WriteReq accesses 766system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086478 # miss rate for LoadLockedReq accesses 767system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086478 # miss rate for LoadLockedReq accesses 768system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002140 # miss rate for StoreCondReq accesses 769system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002140 # miss rate for StoreCondReq accesses 770system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092737 # miss rate for demand accesses 771system.cpu0.dcache.demand_miss_rate::total 0.092737 # miss rate for demand accesses 772system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092737 # miss rate for overall accesses 773system.cpu0.dcache.overall_miss_rate::total 0.092737 # miss rate for overall accesses 774system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24954.892365 # average ReadReq miss latency 775system.cpu0.dcache.ReadReq_avg_miss_latency::total 24954.892365 # average ReadReq miss latency 776system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30950.553804 # average WriteReq miss latency 777system.cpu0.dcache.WriteReq_avg_miss_latency::total 30950.553804 # average WriteReq miss latency 778system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14019.348269 # average LoadLockedReq miss latency 779system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14019.348269 # average LoadLockedReq miss latency 780system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7287.104623 # average StoreCondReq miss latency 781system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7287.104623 # average StoreCondReq miss latency 782system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency 783system.cpu0.dcache.demand_avg_miss_latency::total 26272.568448 # average overall miss latency 784system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26272.568448 # average overall miss latency 785system.cpu0.dcache.overall_avg_miss_latency::total 26272.568448 # average overall miss latency | 706system.cpu0.dcache.replacements 817835 # number of replacements 707system.cpu0.dcache.tagsinuse 479.881432 # Cycle average of tags in use 708system.cpu0.dcache.total_refs 8879650 # Total number of references to valid blocks. 709system.cpu0.dcache.sampled_refs 818347 # Sample count of references to valid blocks. 710system.cpu0.dcache.avg_refs 10.850715 # Average number of references to valid blocks. 711system.cpu0.dcache.warmup_cycle 85697000 # Cycle when the warmup percentage was hit. 712system.cpu0.dcache.occ_blocks::cpu0.data 479.881432 # Average occupied blocks per requestor 713system.cpu0.dcache.occ_percent::cpu0.data 0.937268 # Average percentage of cache occupancy 714system.cpu0.dcache.occ_percent::total 0.937268 # Average percentage of cache occupancy 715system.cpu0.dcache.ReadReq_hits::cpu0.data 5008280 # number of ReadReq hits 716system.cpu0.dcache.ReadReq_hits::total 5008280 # number of ReadReq hits 717system.cpu0.dcache.WriteReq_hits::cpu0.data 3627742 # number of WriteReq hits 718system.cpu0.dcache.WriteReq_hits::total 3627742 # number of WriteReq hits 719system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117045 # number of LoadLockedReq hits 720system.cpu0.dcache.LoadLockedReq_hits::total 117045 # number of LoadLockedReq hits 721system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122538 # number of StoreCondReq hits 722system.cpu0.dcache.StoreCondReq_hits::total 122538 # number of StoreCondReq hits 723system.cpu0.dcache.demand_hits::cpu0.data 8636022 # number of demand (read+write) hits 724system.cpu0.dcache.demand_hits::total 8636022 # number of demand (read+write) hits 725system.cpu0.dcache.overall_hits::cpu0.data 8636022 # number of overall hits 726system.cpu0.dcache.overall_hits::total 8636022 # number of overall hits 727system.cpu0.dcache.ReadReq_misses::cpu0.data 610615 # number of ReadReq misses 728system.cpu0.dcache.ReadReq_misses::total 610615 # number of ReadReq misses 729system.cpu0.dcache.WriteReq_misses::cpu0.data 207039 # number of WriteReq misses 730system.cpu0.dcache.WriteReq_misses::total 207039 # number of WriteReq misses 731system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6562 # number of LoadLockedReq misses 732system.cpu0.dcache.LoadLockedReq_misses::total 6562 # number of LoadLockedReq misses 733system.cpu0.dcache.StoreCondReq_misses::cpu0.data 580 # number of StoreCondReq misses 734system.cpu0.dcache.StoreCondReq_misses::total 580 # number of StoreCondReq misses 735system.cpu0.dcache.demand_misses::cpu0.data 817654 # number of demand (read+write) misses 736system.cpu0.dcache.demand_misses::total 817654 # number of demand (read+write) misses 737system.cpu0.dcache.overall_misses::cpu0.data 817654 # number of overall misses 738system.cpu0.dcache.overall_misses::total 817654 # number of overall misses 739system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19940488000 # number of ReadReq miss cycles 740system.cpu0.dcache.ReadReq_miss_latency::total 19940488000 # number of ReadReq miss cycles 741system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7282919000 # number of WriteReq miss cycles 742system.cpu0.dcache.WriteReq_miss_latency::total 7282919000 # number of WriteReq miss cycles 743system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92852000 # number of LoadLockedReq miss cycles 744system.cpu0.dcache.LoadLockedReq_miss_latency::total 92852000 # number of LoadLockedReq miss cycles 745system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8304000 # number of StoreCondReq miss cycles 746system.cpu0.dcache.StoreCondReq_miss_latency::total 8304000 # number of StoreCondReq miss cycles 747system.cpu0.dcache.demand_miss_latency::cpu0.data 27223407000 # number of demand (read+write) miss cycles 748system.cpu0.dcache.demand_miss_latency::total 27223407000 # number of demand (read+write) miss cycles 749system.cpu0.dcache.overall_miss_latency::cpu0.data 27223407000 # number of overall miss cycles 750system.cpu0.dcache.overall_miss_latency::total 27223407000 # number of overall miss cycles 751system.cpu0.dcache.ReadReq_accesses::cpu0.data 5618895 # number of ReadReq accesses(hits+misses) 752system.cpu0.dcache.ReadReq_accesses::total 5618895 # number of ReadReq accesses(hits+misses) 753system.cpu0.dcache.WriteReq_accesses::cpu0.data 3834781 # number of WriteReq accesses(hits+misses) 754system.cpu0.dcache.WriteReq_accesses::total 3834781 # number of WriteReq accesses(hits+misses) 755system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123607 # number of LoadLockedReq accesses(hits+misses) 756system.cpu0.dcache.LoadLockedReq_accesses::total 123607 # number of LoadLockedReq accesses(hits+misses) 757system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123118 # number of StoreCondReq accesses(hits+misses) 758system.cpu0.dcache.StoreCondReq_accesses::total 123118 # number of StoreCondReq accesses(hits+misses) 759system.cpu0.dcache.demand_accesses::cpu0.data 9453676 # number of demand (read+write) accesses 760system.cpu0.dcache.demand_accesses::total 9453676 # number of demand (read+write) accesses 761system.cpu0.dcache.overall_accesses::cpu0.data 9453676 # number of overall (read+write) accesses 762system.cpu0.dcache.overall_accesses::total 9453676 # number of overall (read+write) accesses 763system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108672 # miss rate for ReadReq accesses 764system.cpu0.dcache.ReadReq_miss_rate::total 0.108672 # miss rate for ReadReq accesses 765system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.053990 # miss rate for WriteReq accesses 766system.cpu0.dcache.WriteReq_miss_rate::total 0.053990 # miss rate for WriteReq accesses 767system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053088 # miss rate for LoadLockedReq accesses 768system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053088 # miss rate for LoadLockedReq accesses 769system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004711 # miss rate for StoreCondReq accesses 770system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004711 # miss rate for StoreCondReq accesses 771system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086491 # miss rate for demand accesses 772system.cpu0.dcache.demand_miss_rate::total 0.086491 # miss rate for demand accesses 773system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086491 # miss rate for overall accesses 774system.cpu0.dcache.overall_miss_rate::total 0.086491 # miss rate for overall accesses 775system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32656.400514 # average ReadReq miss latency 776system.cpu0.dcache.ReadReq_avg_miss_latency::total 32656.400514 # average ReadReq miss latency 777system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35176.556108 # average WriteReq miss latency 778system.cpu0.dcache.WriteReq_avg_miss_latency::total 35176.556108 # average WriteReq miss latency 779system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14149.954282 # average LoadLockedReq miss latency 780system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14149.954282 # average LoadLockedReq miss latency 781system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14317.241379 # average StoreCondReq miss latency 782system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14317.241379 # average StoreCondReq miss latency 783system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency 784system.cpu0.dcache.demand_avg_miss_latency::total 33294.531672 # average overall miss latency 785system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency 786system.cpu0.dcache.overall_avg_miss_latency::total 33294.531672 # average overall miss latency |
| 786system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 787system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 788system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 789system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 790system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 791system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 792system.cpu0.dcache.fast_writes 0 # number of fast writes performed 793system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 787system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 793system.cpu0.dcache.fast_writes 0 # number of fast writes performed 794system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 794system.cpu0.dcache.writebacks::writebacks 790358 # number of writebacks 795system.cpu0.dcache.writebacks::total 790358 # number of writebacks 796system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1034980 # number of ReadReq MSHR misses 797system.cpu0.dcache.ReadReq_mshr_misses::total 1034980 # number of ReadReq MSHR misses 798system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291529 # number of WriteReq MSHR misses 799system.cpu0.dcache.WriteReq_mshr_misses::total 291529 # number of WriteReq MSHR misses 800system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16694 # number of LoadLockedReq MSHR misses 801system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16694 # number of LoadLockedReq MSHR misses 802system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 411 # number of StoreCondReq MSHR misses 803system.cpu0.dcache.StoreCondReq_mshr_misses::total 411 # number of StoreCondReq MSHR misses 804system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326509 # number of demand (read+write) MSHR misses 805system.cpu0.dcache.demand_mshr_misses::total 1326509 # number of demand (read+write) MSHR misses 806system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326509 # number of overall MSHR misses 807system.cpu0.dcache.overall_mshr_misses::total 1326509 # number of overall MSHR misses 808system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 22722836500 # number of ReadReq MSHR miss cycles 809system.cpu0.dcache.ReadReq_mshr_miss_latency::total 22722836500 # number of ReadReq MSHR miss cycles 810system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8148397000 # number of WriteReq MSHR miss cycles 811system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8148397000 # number of WriteReq MSHR miss cycles 812system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 183957000 # number of LoadLockedReq MSHR miss cycles 813system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 183957000 # number of LoadLockedReq MSHR miss cycles 814system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1762000 # number of StoreCondReq MSHR miss cycles 815system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1762000 # number of StoreCondReq MSHR miss cycles 816system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30871233500 # number of demand (read+write) MSHR miss cycles 817system.cpu0.dcache.demand_mshr_miss_latency::total 30871233500 # number of demand (read+write) MSHR miss cycles 818system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30871233500 # number of overall MSHR miss cycles 819system.cpu0.dcache.overall_mshr_miss_latency::total 30871233500 # number of overall MSHR miss cycles 820system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles 821system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles 822system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1241998500 # number of WriteReq MSHR uncacheable cycles 823system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1241998500 # number of WriteReq MSHR uncacheable cycles 824system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126468500 # number of overall MSHR uncacheable cycles 825system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126468500 # number of overall MSHR uncacheable cycles 826system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122425 # mshr miss rate for ReadReq accesses 827system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122425 # mshr miss rate for ReadReq accesses 828system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049834 # mshr miss rate for WriteReq accesses 829system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049834 # mshr miss rate for WriteReq accesses 830system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086478 # mshr miss rate for LoadLockedReq accesses 831system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086478 # mshr miss rate for LoadLockedReq accesses 832system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002140 # mshr miss rate for StoreCondReq accesses 833system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002140 # mshr miss rate for StoreCondReq accesses 834system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for demand accesses 835system.cpu0.dcache.demand_mshr_miss_rate::total 0.092737 # mshr miss rate for demand accesses 836system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092737 # mshr miss rate for overall accesses 837system.cpu0.dcache.overall_mshr_miss_rate::total 0.092737 # mshr miss rate for overall accesses 838system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21954.855649 # average ReadReq mshr miss latency 839system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21954.855649 # average ReadReq mshr miss latency 840system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27950.553804 # average WriteReq mshr miss latency 841system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27950.553804 # average WriteReq mshr miss latency 842system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11019.348269 # average LoadLockedReq mshr miss latency 843system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11019.348269 # average LoadLockedReq mshr miss latency 844system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4287.104623 # average StoreCondReq mshr miss latency 845system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4287.104623 # average StoreCondReq mshr miss latency 846system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency 847system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency 848system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23272.539802 # average overall mshr miss latency 849system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23272.539802 # average overall mshr miss latency | 795system.cpu0.dcache.writebacks::writebacks 359699 # number of writebacks 796system.cpu0.dcache.writebacks::total 359699 # number of writebacks 797system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 610615 # number of ReadReq MSHR misses 798system.cpu0.dcache.ReadReq_mshr_misses::total 610615 # number of ReadReq MSHR misses 799system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 207039 # number of WriteReq MSHR misses 800system.cpu0.dcache.WriteReq_mshr_misses::total 207039 # number of WriteReq MSHR misses 801system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6562 # number of LoadLockedReq MSHR misses 802system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6562 # number of LoadLockedReq MSHR misses 803system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 580 # number of StoreCondReq MSHR misses 804system.cpu0.dcache.StoreCondReq_mshr_misses::total 580 # number of StoreCondReq MSHR misses 805system.cpu0.dcache.demand_mshr_misses::cpu0.data 817654 # number of demand (read+write) MSHR misses 806system.cpu0.dcache.demand_mshr_misses::total 817654 # number of demand (read+write) MSHR misses 807system.cpu0.dcache.overall_mshr_misses::cpu0.data 817654 # number of overall MSHR misses 808system.cpu0.dcache.overall_mshr_misses::total 817654 # number of overall MSHR misses 809system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18108577524 # number of ReadReq MSHR miss cycles 810system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18108577524 # number of ReadReq MSHR miss cycles 811system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6661800002 # number of WriteReq MSHR miss cycles 812system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6661800002 # number of WriteReq MSHR miss cycles 813system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73166000 # number of LoadLockedReq MSHR miss cycles 814system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73166000 # number of LoadLockedReq MSHR miss cycles 815system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 6564000 # number of StoreCondReq MSHR miss cycles 816system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 6564000 # number of StoreCondReq MSHR miss cycles 817system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24770377526 # number of demand (read+write) MSHR miss cycles 818system.cpu0.dcache.demand_mshr_miss_latency::total 24770377526 # number of demand (read+write) MSHR miss cycles 819system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24770377526 # number of overall MSHR miss cycles 820system.cpu0.dcache.overall_mshr_miss_latency::total 24770377526 # number of overall MSHR miss cycles 821system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601208500 # number of ReadReq MSHR uncacheable cycles 822system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601208500 # number of ReadReq MSHR uncacheable cycles 823system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014438500 # number of WriteReq MSHR uncacheable cycles 824system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014438500 # number of WriteReq MSHR uncacheable cycles 825system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615647000 # number of overall MSHR uncacheable cycles 826system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615647000 # number of overall MSHR uncacheable cycles 827system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108672 # mshr miss rate for ReadReq accesses 828system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108672 # mshr miss rate for ReadReq accesses 829system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053990 # mshr miss rate for WriteReq accesses 830system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053990 # mshr miss rate for WriteReq accesses 831system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053088 # mshr miss rate for LoadLockedReq accesses 832system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053088 # mshr miss rate for LoadLockedReq accesses 833system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004711 # mshr miss rate for StoreCondReq accesses 834system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004711 # mshr miss rate for StoreCondReq accesses 835system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for demand accesses 836system.cpu0.dcache.demand_mshr_miss_rate::total 0.086491 # mshr miss rate for demand accesses 837system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for overall accesses 838system.cpu0.dcache.overall_mshr_miss_rate::total 0.086491 # mshr miss rate for overall accesses 839system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29656.293285 # average ReadReq mshr miss latency 840system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29656.293285 # average ReadReq mshr miss latency 841system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32176.546457 # average WriteReq mshr miss latency 842system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32176.546457 # average WriteReq mshr miss latency 843system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11149.954282 # average LoadLockedReq mshr miss latency 844system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11149.954282 # average LoadLockedReq mshr miss latency 845system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11317.241379 # average StoreCondReq mshr miss latency 846system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11317.241379 # average StoreCondReq mshr miss latency 847system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency 848system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency 849system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency 850system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency |
| 850system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 851system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 852system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 853system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 854system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 855system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 856system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 857system.cpu1.dtb.fetch_hits 0 # ITB hits 858system.cpu1.dtb.fetch_misses 0 # ITB misses 859system.cpu1.dtb.fetch_acv 0 # ITB acv 860system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 851system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 852system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 853system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 854system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 855system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 856system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 857system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 858system.cpu1.dtb.fetch_hits 0 # ITB hits 859system.cpu1.dtb.fetch_misses 0 # ITB misses 860system.cpu1.dtb.fetch_acv 0 # ITB acv 861system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 861system.cpu1.dtb.read_hits 1049963 # DTB read hits 862system.cpu1.dtb.read_misses 2992 # DTB read misses 863system.cpu1.dtb.read_acv 0 # DTB read access violations 864system.cpu1.dtb.read_accesses 239363 # DTB read accesses 865system.cpu1.dtb.write_hits 651106 # DTB write hits 866system.cpu1.dtb.write_misses 341 # DTB write misses 867system.cpu1.dtb.write_acv 29 # DTB write access violations 868system.cpu1.dtb.write_accesses 105247 # DTB write accesses 869system.cpu1.dtb.data_hits 1701069 # DTB hits 870system.cpu1.dtb.data_misses 3333 # DTB misses 871system.cpu1.dtb.data_acv 29 # DTB access violations 872system.cpu1.dtb.data_accesses 344610 # DTB accesses 873system.cpu1.itb.fetch_hits 1493400 # ITB hits 874system.cpu1.itb.fetch_misses 1216 # ITB misses 875system.cpu1.itb.fetch_acv 0 # ITB acv 876system.cpu1.itb.fetch_accesses 1494616 # ITB accesses | 862system.cpu1.dtb.read_hits 3958078 # DTB read hits 863system.cpu1.dtb.read_misses 2750 # DTB read misses 864system.cpu1.dtb.read_acv 36 # DTB read access violations 865system.cpu1.dtb.read_accesses 205838 # DTB read accesses 866system.cpu1.dtb.write_hits 2742847 # DTB write hits 867system.cpu1.dtb.write_misses 356 # DTB write misses 868system.cpu1.dtb.write_acv 48 # DTB write access violations 869system.cpu1.dtb.write_accesses 97040 # DTB write accesses 870system.cpu1.dtb.data_hits 6700925 # DTB hits 871system.cpu1.dtb.data_misses 3106 # DTB misses 872system.cpu1.dtb.data_acv 84 # DTB access violations 873system.cpu1.dtb.data_accesses 302878 # DTB accesses 874system.cpu1.itb.fetch_hits 2128502 # ITB hits 875system.cpu1.itb.fetch_misses 1246 # ITB misses 876system.cpu1.itb.fetch_acv 41 # ITB acv 877system.cpu1.itb.fetch_accesses 2129748 # ITB accesses |
| 877system.cpu1.itb.read_hits 0 # DTB read hits 878system.cpu1.itb.read_misses 0 # DTB read misses 879system.cpu1.itb.read_acv 0 # DTB read access violations 880system.cpu1.itb.read_accesses 0 # DTB read accesses 881system.cpu1.itb.write_hits 0 # DTB write hits 882system.cpu1.itb.write_misses 0 # DTB write misses 883system.cpu1.itb.write_acv 0 # DTB write access violations 884system.cpu1.itb.write_accesses 0 # DTB write accesses 885system.cpu1.itb.data_hits 0 # DTB hits 886system.cpu1.itb.data_misses 0 # DTB misses 887system.cpu1.itb.data_acv 0 # DTB access violations 888system.cpu1.itb.data_accesses 0 # DTB accesses | 878system.cpu1.itb.read_hits 0 # DTB read hits 879system.cpu1.itb.read_misses 0 # DTB read misses 880system.cpu1.itb.read_acv 0 # DTB read access violations 881system.cpu1.itb.read_accesses 0 # DTB read accesses 882system.cpu1.itb.write_hits 0 # DTB write hits 883system.cpu1.itb.write_misses 0 # DTB write misses 884system.cpu1.itb.write_acv 0 # DTB write access violations 885system.cpu1.itb.write_accesses 0 # DTB write accesses 886system.cpu1.itb.data_hits 0 # DTB hits 887system.cpu1.itb.data_misses 0 # DTB misses 888system.cpu1.itb.data_acv 0 # DTB access violations 889system.cpu1.itb.data_accesses 0 # DTB accesses |
| 889system.cpu1.numCycles 3915155164 # number of cpu cycles simulated | 890system.cpu1.numCycles 3908222380 # number of cpu cycles simulated |
| 890system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 891system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 891system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 892system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 892system.cpu1.committedInsts 5279868 # Number of instructions committed 893system.cpu1.committedOps 5279868 # Number of ops (including micro ops) committed 894system.cpu1.num_int_alu_accesses 4945263 # Number of integer alu accesses 895system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses 896system.cpu1.num_func_calls 157997 # number of times a function call or return occured 897system.cpu1.num_conditional_control_insts 510441 # number of instructions that are conditional controls 898system.cpu1.num_int_insts 4945263 # number of integer instructions 899system.cpu1.num_fp_insts 34031 # number of float instructions 900system.cpu1.num_int_register_reads 6880916 # number of times the integer registers were read 901system.cpu1.num_int_register_writes 3730475 # number of times the integer registers were written 902system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read 903system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written 904system.cpu1.num_mem_refs 1710522 # number of memory refs 905system.cpu1.num_load_insts 1055970 # Number of load instructions 906system.cpu1.num_store_insts 654552 # Number of store instructions 907system.cpu1.num_idle_cycles 3896226886.998010 # Number of idle cycles 908system.cpu1.num_busy_cycles 18928277.001990 # Number of busy cycles 909system.cpu1.not_idle_fraction 0.004835 # Percentage of non-idle cycles 910system.cpu1.idle_fraction 0.995165 # Percentage of idle cycles | 893system.cpu1.committedInsts 23256004 # Number of instructions committed 894system.cpu1.committedOps 23256004 # Number of ops (including micro ops) committed 895system.cpu1.num_int_alu_accesses 21401422 # Number of integer alu accesses 896system.cpu1.num_fp_alu_accesses 186242 # Number of float alu accesses 897system.cpu1.num_func_calls 709842 # number of times a function call or return occured 898system.cpu1.num_conditional_control_insts 2519926 # number of instructions that are conditional controls 899system.cpu1.num_int_insts 21401422 # number of integer instructions 900system.cpu1.num_fp_insts 186242 # number of float instructions 901system.cpu1.num_int_register_reads 29248159 # number of times the integer registers were read 902system.cpu1.num_int_register_writes 15707401 # number of times the integer registers were written 903system.cpu1.num_fp_register_reads 95219 # number of times the floating registers were read 904system.cpu1.num_fp_register_writes 97489 # number of times the floating registers were written 905system.cpu1.num_mem_refs 6725970 # number of memory refs 906system.cpu1.num_load_insts 3973767 # Number of load instructions 907system.cpu1.num_store_insts 2752203 # Number of store instructions 908system.cpu1.num_idle_cycles 3808684025.637170 # Number of idle cycles 909system.cpu1.num_busy_cycles 99538354.362830 # Number of busy cycles 910system.cpu1.not_idle_fraction 0.025469 # Percentage of non-idle cycles 911system.cpu1.idle_fraction 0.974531 # Percentage of idle cycles |
| 911system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 912system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 912system.cpu1.kern.inst.quiesce 2314 # number of quiesce instructions executed 913system.cpu1.kern.inst.hwrei 36187 # number of hwrei instructions executed 914system.cpu1.kern.ipl_count::0 9288 32.15% 32.15% # number of times we switched to this ipl 915system.cpu1.kern.ipl_count::22 1969 6.81% 38.96% # number of times we switched to this ipl 916system.cpu1.kern.ipl_count::30 88 0.30% 39.27% # number of times we switched to this ipl 917system.cpu1.kern.ipl_count::31 17548 60.73% 100.00% # number of times we switched to this ipl 918system.cpu1.kern.ipl_count::total 28893 # number of times we switched to this ipl 919system.cpu1.kern.ipl_good::0 9278 45.20% 45.20% # number of times we switched to this ipl from a different ipl 920system.cpu1.kern.ipl_good::22 1969 9.59% 54.80% # number of times we switched to this ipl from a different ipl 921system.cpu1.kern.ipl_good::30 88 0.43% 55.23% # number of times we switched to this ipl from a different ipl 922system.cpu1.kern.ipl_good::31 9190 44.77% 100.00% # number of times we switched to this ipl from a different ipl 923system.cpu1.kern.ipl_good::total 20525 # number of times we switched to this ipl from a different ipl 924system.cpu1.kern.ipl_ticks::0 1917614123000 97.96% 97.96% # number of cycles we spent at this ipl 925system.cpu1.kern.ipl_ticks::22 507941000 0.03% 97.98% # number of cycles we spent at this ipl 926system.cpu1.kern.ipl_ticks::30 53691000 0.00% 97.99% # number of cycles we spent at this ipl 927system.cpu1.kern.ipl_ticks::31 39401069000 2.01% 100.00% # number of cycles we spent at this ipl 928system.cpu1.kern.ipl_ticks::total 1957576824000 # number of cycles we spent at this ipl 929system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl | 913system.cpu1.kern.inst.quiesce 3849 # number of quiesce instructions executed 914system.cpu1.kern.inst.hwrei 109556 # number of hwrei instructions executed 915system.cpu1.kern.ipl_count::0 40729 40.60% 40.60% # number of times we switched to this ipl 916system.cpu1.kern.ipl_count::22 1966 1.96% 42.56% # number of times we switched to this ipl 917system.cpu1.kern.ipl_count::30 91 0.09% 42.65% # number of times we switched to this ipl 918system.cpu1.kern.ipl_count::31 57540 57.35% 100.00% # number of times we switched to this ipl 919system.cpu1.kern.ipl_count::total 100326 # number of times we switched to this ipl 920system.cpu1.kern.ipl_good::0 39783 48.79% 48.79% # number of times we switched to this ipl from a different ipl 921system.cpu1.kern.ipl_good::22 1966 2.41% 51.21% # number of times we switched to this ipl from a different ipl 922system.cpu1.kern.ipl_good::30 91 0.11% 51.32% # number of times we switched to this ipl from a different ipl 923system.cpu1.kern.ipl_good::31 39692 48.68% 100.00% # number of times we switched to this ipl from a different ipl 924system.cpu1.kern.ipl_good::total 81532 # number of times we switched to this ipl from a different ipl 925system.cpu1.kern.ipl_ticks::0 1901560823500 97.31% 97.31% # number of cycles we spent at this ipl 926system.cpu1.kern.ipl_ticks::22 537428500 0.03% 97.34% # number of cycles we spent at this ipl 927system.cpu1.kern.ipl_ticks::30 59036000 0.00% 97.34% # number of cycles we spent at this ipl 928system.cpu1.kern.ipl_ticks::31 51953872000 2.66% 100.00% # number of cycles we spent at this ipl 929system.cpu1.kern.ipl_ticks::total 1954111160000 # number of cycles we spent at this ipl 930system.cpu1.kern.ipl_used::0 0.976773 # fraction of swpipl calls that actually changed the ipl |
| 930system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 931system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 931system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 932system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 932system.cpu1.kern.ipl_used::31 0.523706 # fraction of swpipl calls that actually changed the ipl 933system.cpu1.kern.ipl_used::total 0.710380 # fraction of swpipl calls that actually changed the ipl 934system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 935system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 936system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 937system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 938system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 939system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 940system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 941system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 942system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 943system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 944system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 945system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 946system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 947system.cpu1.kern.syscall::total 104 # number of syscalls executed | 933system.cpu1.kern.ipl_used::31 0.689816 # fraction of swpipl calls that actually changed the ipl 934system.cpu1.kern.ipl_used::total 0.812671 # fraction of swpipl calls that actually changed the ipl 935system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed 936system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed 937system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed 938system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed 939system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed 940system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed 941system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed 942system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed 943system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed 944system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed 945system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed 946system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed 947system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed 948system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed 949system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed 950system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed 951system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed 952system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed 953system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed 954system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed 955system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed 956system.cpu1.kern.syscall::total 102 # number of syscalls executed |
| 948system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 957system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 949system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed 950system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed 951system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed 952system.cpu1.kern.callpal::swpctx 337 1.14% 1.17% # number of callpals executed 953system.cpu1.kern.callpal::tbi 3 0.01% 1.18% # number of callpals executed 954system.cpu1.kern.callpal::wrent 7 0.02% 1.20% # number of callpals executed 955system.cpu1.kern.callpal::swpipl 24305 82.25% 83.46% # number of callpals executed 956system.cpu1.kern.callpal::rdps 2170 7.34% 90.80% # number of callpals executed 957system.cpu1.kern.callpal::wrkgp 1 0.00% 90.80% # number of callpals executed 958system.cpu1.kern.callpal::wrusp 4 0.01% 90.82% # number of callpals executed 959system.cpu1.kern.callpal::whami 3 0.01% 90.83% # number of callpals executed 960system.cpu1.kern.callpal::rti 2530 8.56% 99.39% # number of callpals executed 961system.cpu1.kern.callpal::callsys 136 0.46% 99.85% # number of callpals executed 962system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed | 958system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed 959system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed 960system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed 961system.cpu1.kern.callpal::swpctx 2292 2.22% 2.24% # number of callpals executed 962system.cpu1.kern.callpal::tbi 10 0.01% 2.25% # number of callpals executed 963system.cpu1.kern.callpal::wrent 7 0.01% 2.26% # number of callpals executed 964system.cpu1.kern.callpal::swpipl 94758 91.98% 94.24% # number of callpals executed 965system.cpu1.kern.callpal::rdps 2221 2.16% 96.40% # number of callpals executed 966system.cpu1.kern.callpal::wrkgp 1 0.00% 96.40% # number of callpals executed 967system.cpu1.kern.callpal::wrusp 3 0.00% 96.40% # number of callpals executed 968system.cpu1.kern.callpal::rdusp 2 0.00% 96.40% # number of callpals executed 969system.cpu1.kern.callpal::whami 3 0.00% 96.41% # number of callpals executed 970system.cpu1.kern.callpal::rti 3510 3.41% 99.81% # number of callpals executed 971system.cpu1.kern.callpal::callsys 161 0.16% 99.97% # number of callpals executed 972system.cpu1.kern.callpal::imb 31 0.03% 100.00% # number of callpals executed |
| 963system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 973system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 964system.cpu1.kern.callpal::total 29550 # number of callpals executed 965system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches 966system.cpu1.kern.mode_switch::user 463 # number of protection mode switches 967system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches 968system.cpu1.kern.mode_good::kernel 476 969system.cpu1.kern.mode_good::user 463 970system.cpu1.kern.mode_good::idle 13 971system.cpu1.kern.mode_switch_good::kernel 0.592777 # fraction of useful protection mode switches | 974system.cpu1.kern.callpal::total 103020 # number of callpals executed 975system.cpu1.kern.mode_switch::kernel 2836 # number of protection mode switches 976system.cpu1.kern.mode_switch::user 515 # number of protection mode switches 977system.cpu1.kern.mode_switch::idle 2038 # number of protection mode switches 978system.cpu1.kern.mode_good::kernel 568 979system.cpu1.kern.mode_good::user 515 980system.cpu1.kern.mode_good::idle 53 981system.cpu1.kern.mode_switch_good::kernel 0.200282 # fraction of useful protection mode switches |
| 972system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 982system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 973system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches 974system.cpu1.kern.mode_switch_good::total 0.285800 # fraction of useful protection mode switches 975system.cpu1.kern.mode_ticks::kernel 3531821000 0.18% 0.18% # number of ticks spent at the given mode 976system.cpu1.kern.mode_ticks::user 1727088000 0.09% 0.27% # number of ticks spent at the given mode 977system.cpu1.kern.mode_ticks::idle 1952317913000 99.73% 100.00% # number of ticks spent at the given mode 978system.cpu1.kern.swap_context 338 # number of times the context was actually changed 979system.cpu1.icache.replacements 86261 # number of replacements 980system.cpu1.icache.tagsinuse 419.419440 # Cycle average of tags in use 981system.cpu1.icache.total_refs 5196422 # Total number of references to valid blocks. 982system.cpu1.icache.sampled_refs 86773 # Sample count of references to valid blocks. 983system.cpu1.icache.avg_refs 59.885241 # Average number of references to valid blocks. 984system.cpu1.icache.warmup_cycle 1941709468000 # Cycle when the warmup percentage was hit. 985system.cpu1.icache.occ_blocks::cpu1.inst 419.419440 # Average occupied blocks per requestor 986system.cpu1.icache.occ_percent::cpu1.inst 0.819179 # Average percentage of cache occupancy 987system.cpu1.icache.occ_percent::total 0.819179 # Average percentage of cache occupancy 988system.cpu1.icache.ReadReq_hits::cpu1.inst 5196422 # number of ReadReq hits 989system.cpu1.icache.ReadReq_hits::total 5196422 # number of ReadReq hits 990system.cpu1.icache.demand_hits::cpu1.inst 5196422 # number of demand (read+write) hits 991system.cpu1.icache.demand_hits::total 5196422 # number of demand (read+write) hits 992system.cpu1.icache.overall_hits::cpu1.inst 5196422 # number of overall hits 993system.cpu1.icache.overall_hits::total 5196422 # number of overall hits 994system.cpu1.icache.ReadReq_misses::cpu1.inst 86809 # number of ReadReq misses 995system.cpu1.icache.ReadReq_misses::total 86809 # number of ReadReq misses 996system.cpu1.icache.demand_misses::cpu1.inst 86809 # number of demand (read+write) misses 997system.cpu1.icache.demand_misses::total 86809 # number of demand (read+write) misses 998system.cpu1.icache.overall_misses::cpu1.inst 86809 # number of overall misses 999system.cpu1.icache.overall_misses::total 86809 # number of overall misses 1000system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1248608500 # number of ReadReq miss cycles 1001system.cpu1.icache.ReadReq_miss_latency::total 1248608500 # number of ReadReq miss cycles 1002system.cpu1.icache.demand_miss_latency::cpu1.inst 1248608500 # number of demand (read+write) miss cycles 1003system.cpu1.icache.demand_miss_latency::total 1248608500 # number of demand (read+write) miss cycles 1004system.cpu1.icache.overall_miss_latency::cpu1.inst 1248608500 # number of overall miss cycles 1005system.cpu1.icache.overall_miss_latency::total 1248608500 # number of overall miss cycles 1006system.cpu1.icache.ReadReq_accesses::cpu1.inst 5283231 # number of ReadReq accesses(hits+misses) 1007system.cpu1.icache.ReadReq_accesses::total 5283231 # number of ReadReq accesses(hits+misses) 1008system.cpu1.icache.demand_accesses::cpu1.inst 5283231 # number of demand (read+write) accesses 1009system.cpu1.icache.demand_accesses::total 5283231 # number of demand (read+write) accesses 1010system.cpu1.icache.overall_accesses::cpu1.inst 5283231 # number of overall (read+write) accesses 1011system.cpu1.icache.overall_accesses::total 5283231 # number of overall (read+write) accesses 1012system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016431 # miss rate for ReadReq accesses 1013system.cpu1.icache.ReadReq_miss_rate::total 0.016431 # miss rate for ReadReq accesses 1014system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016431 # miss rate for demand accesses 1015system.cpu1.icache.demand_miss_rate::total 0.016431 # miss rate for demand accesses 1016system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016431 # miss rate for overall accesses 1017system.cpu1.icache.overall_miss_rate::total 0.016431 # miss rate for overall accesses 1018system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14383.399187 # average ReadReq miss latency 1019system.cpu1.icache.ReadReq_avg_miss_latency::total 14383.399187 # average ReadReq miss latency 1020system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency 1021system.cpu1.icache.demand_avg_miss_latency::total 14383.399187 # average overall miss latency 1022system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14383.399187 # average overall miss latency 1023system.cpu1.icache.overall_avg_miss_latency::total 14383.399187 # average overall miss latency | 983system.cpu1.kern.mode_switch_good::idle 0.026006 # fraction of useful protection mode switches 984system.cpu1.kern.mode_switch_good::total 0.210800 # fraction of useful protection mode switches 985system.cpu1.kern.mode_ticks::kernel 72316980000 3.70% 3.70% # number of ticks spent at the given mode 986system.cpu1.kern.mode_ticks::user 1607803000 0.08% 3.78% # number of ticks spent at the given mode 987system.cpu1.kern.mode_ticks::idle 1879348629000 96.22% 100.00% # number of ticks spent at the given mode 988system.cpu1.kern.swap_context 2293 # number of times the context was actually changed 989system.cpu1.icache.replacements 513695 # number of replacements 990system.cpu1.icache.tagsinuse 501.294136 # Cycle average of tags in use 991system.cpu1.icache.total_refs 22744962 # Total number of references to valid blocks. 992system.cpu1.icache.sampled_refs 514207 # Sample count of references to valid blocks. 993system.cpu1.icache.avg_refs 44.233085 # Average number of references to valid blocks. 994system.cpu1.icache.warmup_cycle 96225204000 # Cycle when the warmup percentage was hit. 995system.cpu1.icache.occ_blocks::cpu1.inst 501.294136 # Average occupied blocks per requestor 996system.cpu1.icache.occ_percent::cpu1.inst 0.979090 # Average percentage of cache occupancy 997system.cpu1.icache.occ_percent::total 0.979090 # Average percentage of cache occupancy 998system.cpu1.icache.ReadReq_hits::cpu1.inst 22744962 # number of ReadReq hits 999system.cpu1.icache.ReadReq_hits::total 22744962 # number of ReadReq hits 1000system.cpu1.icache.demand_hits::cpu1.inst 22744962 # number of demand (read+write) hits 1001system.cpu1.icache.demand_hits::total 22744962 # number of demand (read+write) hits 1002system.cpu1.icache.overall_hits::cpu1.inst 22744962 # number of overall hits 1003system.cpu1.icache.overall_hits::total 22744962 # number of overall hits 1004system.cpu1.icache.ReadReq_misses::cpu1.inst 514232 # number of ReadReq misses 1005system.cpu1.icache.ReadReq_misses::total 514232 # number of ReadReq misses 1006system.cpu1.icache.demand_misses::cpu1.inst 514232 # number of demand (read+write) misses 1007system.cpu1.icache.demand_misses::total 514232 # number of demand (read+write) misses 1008system.cpu1.icache.overall_misses::cpu1.inst 514232 # number of overall misses 1009system.cpu1.icache.overall_misses::total 514232 # number of overall misses 1010system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7551962500 # number of ReadReq miss cycles 1011system.cpu1.icache.ReadReq_miss_latency::total 7551962500 # number of ReadReq miss cycles 1012system.cpu1.icache.demand_miss_latency::cpu1.inst 7551962500 # number of demand (read+write) miss cycles 1013system.cpu1.icache.demand_miss_latency::total 7551962500 # number of demand (read+write) miss cycles 1014system.cpu1.icache.overall_miss_latency::cpu1.inst 7551962500 # number of overall miss cycles 1015system.cpu1.icache.overall_miss_latency::total 7551962500 # number of overall miss cycles 1016system.cpu1.icache.ReadReq_accesses::cpu1.inst 23259194 # number of ReadReq accesses(hits+misses) 1017system.cpu1.icache.ReadReq_accesses::total 23259194 # number of ReadReq accesses(hits+misses) 1018system.cpu1.icache.demand_accesses::cpu1.inst 23259194 # number of demand (read+write) accesses 1019system.cpu1.icache.demand_accesses::total 23259194 # number of demand (read+write) accesses 1020system.cpu1.icache.overall_accesses::cpu1.inst 23259194 # number of overall (read+write) accesses 1021system.cpu1.icache.overall_accesses::total 23259194 # number of overall (read+write) accesses 1022system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022109 # miss rate for ReadReq accesses 1023system.cpu1.icache.ReadReq_miss_rate::total 0.022109 # miss rate for ReadReq accesses 1024system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022109 # miss rate for demand accesses 1025system.cpu1.icache.demand_miss_rate::total 0.022109 # miss rate for demand accesses 1026system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022109 # miss rate for overall accesses 1027system.cpu1.icache.overall_miss_rate::total 0.022109 # miss rate for overall accesses 1028system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.905389 # average ReadReq miss latency 1029system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.905389 # average ReadReq miss latency 1030system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency 1031system.cpu1.icache.demand_avg_miss_latency::total 14685.905389 # average overall miss latency 1032system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency 1033system.cpu1.icache.overall_avg_miss_latency::total 14685.905389 # average overall miss latency |
| 1024system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1025system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1026system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1027system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1028system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1029system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1030system.cpu1.icache.fast_writes 0 # number of fast writes performed 1031system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1034system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1035system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1036system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1037system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1038system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1039system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1040system.cpu1.icache.fast_writes 0 # number of fast writes performed 1041system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1032system.cpu1.icache.writebacks::writebacks 14 # number of writebacks 1033system.cpu1.icache.writebacks::total 14 # number of writebacks 1034system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86809 # number of ReadReq MSHR misses 1035system.cpu1.icache.ReadReq_mshr_misses::total 86809 # number of ReadReq MSHR misses 1036system.cpu1.icache.demand_mshr_misses::cpu1.inst 86809 # number of demand (read+write) MSHR misses 1037system.cpu1.icache.demand_mshr_misses::total 86809 # number of demand (read+write) MSHR misses 1038system.cpu1.icache.overall_mshr_misses::cpu1.inst 86809 # number of overall MSHR misses 1039system.cpu1.icache.overall_mshr_misses::total 86809 # number of overall MSHR misses 1040system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 988145500 # number of ReadReq MSHR miss cycles 1041system.cpu1.icache.ReadReq_mshr_miss_latency::total 988145500 # number of ReadReq MSHR miss cycles 1042system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 988145500 # number of demand (read+write) MSHR miss cycles 1043system.cpu1.icache.demand_mshr_miss_latency::total 988145500 # number of demand (read+write) MSHR miss cycles 1044system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 988145500 # number of overall MSHR miss cycles 1045system.cpu1.icache.overall_mshr_miss_latency::total 988145500 # number of overall MSHR miss cycles 1046system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for ReadReq accesses 1047system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016431 # mshr miss rate for ReadReq accesses 1048system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for demand accesses 1049system.cpu1.icache.demand_mshr_miss_rate::total 0.016431 # mshr miss rate for demand accesses 1050system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016431 # mshr miss rate for overall accesses 1051system.cpu1.icache.overall_mshr_miss_rate::total 0.016431 # mshr miss rate for overall accesses 1052system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average ReadReq mshr miss latency 1053system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11382.984483 # average ReadReq mshr miss latency 1054system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average overall mshr miss latency 1055system.cpu1.icache.demand_avg_mshr_miss_latency::total 11382.984483 # average overall mshr miss latency 1056system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11382.984483 # average overall mshr miss latency 1057system.cpu1.icache.overall_avg_mshr_miss_latency::total 11382.984483 # average overall mshr miss latency | 1042system.cpu1.icache.writebacks::writebacks 11 # number of writebacks 1043system.cpu1.icache.writebacks::total 11 # number of writebacks 1044system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 514232 # number of ReadReq MSHR misses 1045system.cpu1.icache.ReadReq_mshr_misses::total 514232 # number of ReadReq MSHR misses 1046system.cpu1.icache.demand_mshr_misses::cpu1.inst 514232 # number of demand (read+write) MSHR misses 1047system.cpu1.icache.demand_mshr_misses::total 514232 # number of demand (read+write) MSHR misses 1048system.cpu1.icache.overall_mshr_misses::cpu1.inst 514232 # number of overall MSHR misses 1049system.cpu1.icache.overall_mshr_misses::total 514232 # number of overall MSHR misses 1050system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6009201500 # number of ReadReq MSHR miss cycles 1051system.cpu1.icache.ReadReq_mshr_miss_latency::total 6009201500 # number of ReadReq MSHR miss cycles 1052system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6009201500 # number of demand (read+write) MSHR miss cycles 1053system.cpu1.icache.demand_mshr_miss_latency::total 6009201500 # number of demand (read+write) MSHR miss cycles 1054system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6009201500 # number of overall MSHR miss cycles 1055system.cpu1.icache.overall_mshr_miss_latency::total 6009201500 # number of overall MSHR miss cycles 1056system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for ReadReq accesses 1057system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022109 # mshr miss rate for ReadReq accesses 1058system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for demand accesses 1059system.cpu1.icache.demand_mshr_miss_rate::total 0.022109 # mshr miss rate for demand accesses 1060system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for overall accesses 1061system.cpu1.icache.overall_mshr_miss_rate::total 0.022109 # mshr miss rate for overall accesses 1062system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average ReadReq mshr miss latency 1063system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.778987 # average ReadReq mshr miss latency 1064system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average overall mshr miss latency 1065system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.778987 # average overall mshr miss latency 1066system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average overall mshr miss latency 1067system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.778987 # average overall mshr miss latency |
| 1058system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1068system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1059system.cpu1.dcache.replacements 52782 # number of replacements 1060system.cpu1.dcache.tagsinuse 416.168626 # Cycle average of tags in use 1061system.cpu1.dcache.total_refs 1644833 # Total number of references to valid blocks. 1062system.cpu1.dcache.sampled_refs 53294 # Sample count of references to valid blocks. 1063system.cpu1.dcache.avg_refs 30.863380 # Average number of references to valid blocks. 1064system.cpu1.dcache.warmup_cycle 1922770151000 # Cycle when the warmup percentage was hit. 1065system.cpu1.dcache.occ_blocks::cpu1.data 416.168626 # Average occupied blocks per requestor 1066system.cpu1.dcache.occ_percent::cpu1.data 0.812829 # Average percentage of cache occupancy 1067system.cpu1.dcache.occ_percent::total 0.812829 # Average percentage of cache occupancy 1068system.cpu1.dcache.ReadReq_hits::cpu1.data 1003125 # number of ReadReq hits 1069system.cpu1.dcache.ReadReq_hits::total 1003125 # number of ReadReq hits 1070system.cpu1.dcache.WriteReq_hits::cpu1.data 616808 # number of WriteReq hits 1071system.cpu1.dcache.WriteReq_hits::total 616808 # number of WriteReq hits 1072system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11818 # number of LoadLockedReq hits 1073system.cpu1.dcache.LoadLockedReq_hits::total 11818 # number of LoadLockedReq hits 1074system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11519 # number of StoreCondReq hits 1075system.cpu1.dcache.StoreCondReq_hits::total 11519 # number of StoreCondReq hits 1076system.cpu1.dcache.demand_hits::cpu1.data 1619933 # number of demand (read+write) hits 1077system.cpu1.dcache.demand_hits::total 1619933 # number of demand (read+write) hits 1078system.cpu1.dcache.overall_hits::cpu1.data 1619933 # number of overall hits 1079system.cpu1.dcache.overall_hits::total 1619933 # number of overall hits 1080system.cpu1.dcache.ReadReq_misses::cpu1.data 36999 # number of ReadReq misses 1081system.cpu1.dcache.ReadReq_misses::total 36999 # number of ReadReq misses 1082system.cpu1.dcache.WriteReq_misses::cpu1.data 20414 # number of WriteReq misses 1083system.cpu1.dcache.WriteReq_misses::total 20414 # number of WriteReq misses 1084system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 944 # number of LoadLockedReq misses 1085system.cpu1.dcache.LoadLockedReq_misses::total 944 # number of LoadLockedReq misses 1086system.cpu1.dcache.StoreCondReq_misses::cpu1.data 507 # number of StoreCondReq misses 1087system.cpu1.dcache.StoreCondReq_misses::total 507 # number of StoreCondReq misses 1088system.cpu1.dcache.demand_misses::cpu1.data 57413 # number of demand (read+write) misses 1089system.cpu1.dcache.demand_misses::total 57413 # number of demand (read+write) misses 1090system.cpu1.dcache.overall_misses::cpu1.data 57413 # number of overall misses 1091system.cpu1.dcache.overall_misses::total 57413 # number of overall misses 1092system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 492506000 # number of ReadReq miss cycles 1093system.cpu1.dcache.ReadReq_miss_latency::total 492506000 # number of ReadReq miss cycles 1094system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 549958000 # number of WriteReq miss cycles 1095system.cpu1.dcache.WriteReq_miss_latency::total 549958000 # number of WriteReq miss cycles 1096system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 11305000 # number of LoadLockedReq miss cycles 1097system.cpu1.dcache.LoadLockedReq_miss_latency::total 11305000 # number of LoadLockedReq miss cycles 1098system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6352000 # number of StoreCondReq miss cycles 1099system.cpu1.dcache.StoreCondReq_miss_latency::total 6352000 # number of StoreCondReq miss cycles 1100system.cpu1.dcache.demand_miss_latency::cpu1.data 1042464000 # number of demand (read+write) miss cycles 1101system.cpu1.dcache.demand_miss_latency::total 1042464000 # number of demand (read+write) miss cycles 1102system.cpu1.dcache.overall_miss_latency::cpu1.data 1042464000 # number of overall miss cycles 1103system.cpu1.dcache.overall_miss_latency::total 1042464000 # number of overall miss cycles 1104system.cpu1.dcache.ReadReq_accesses::cpu1.data 1040124 # number of ReadReq accesses(hits+misses) 1105system.cpu1.dcache.ReadReq_accesses::total 1040124 # number of ReadReq accesses(hits+misses) 1106system.cpu1.dcache.WriteReq_accesses::cpu1.data 637222 # number of WriteReq accesses(hits+misses) 1107system.cpu1.dcache.WriteReq_accesses::total 637222 # number of WriteReq accesses(hits+misses) 1108system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12762 # number of LoadLockedReq accesses(hits+misses) 1109system.cpu1.dcache.LoadLockedReq_accesses::total 12762 # number of LoadLockedReq accesses(hits+misses) 1110system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12026 # number of StoreCondReq accesses(hits+misses) 1111system.cpu1.dcache.StoreCondReq_accesses::total 12026 # number of StoreCondReq accesses(hits+misses) 1112system.cpu1.dcache.demand_accesses::cpu1.data 1677346 # number of demand (read+write) accesses 1113system.cpu1.dcache.demand_accesses::total 1677346 # number of demand (read+write) accesses 1114system.cpu1.dcache.overall_accesses::cpu1.data 1677346 # number of overall (read+write) accesses 1115system.cpu1.dcache.overall_accesses::total 1677346 # number of overall (read+write) accesses 1116system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035572 # miss rate for ReadReq accesses 1117system.cpu1.dcache.ReadReq_miss_rate::total 0.035572 # miss rate for ReadReq accesses 1118system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses 1119system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses 1120system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.073970 # miss rate for LoadLockedReq accesses 1121system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.073970 # miss rate for LoadLockedReq accesses 1122system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042159 # miss rate for StoreCondReq accesses 1123system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042159 # miss rate for StoreCondReq accesses 1124system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034228 # miss rate for demand accesses 1125system.cpu1.dcache.demand_miss_rate::total 0.034228 # miss rate for demand accesses 1126system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034228 # miss rate for overall accesses 1127system.cpu1.dcache.overall_miss_rate::total 0.034228 # miss rate for overall accesses 1128system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13311.332739 # average ReadReq miss latency 1129system.cpu1.dcache.ReadReq_avg_miss_latency::total 13311.332739 # average ReadReq miss latency 1130system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26940.237092 # average WriteReq miss latency 1131system.cpu1.dcache.WriteReq_avg_miss_latency::total 26940.237092 # average WriteReq miss latency 1132system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11975.635593 # average LoadLockedReq miss latency 1133system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11975.635593 # average LoadLockedReq miss latency 1134system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12528.599606 # average StoreCondReq miss latency 1135system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12528.599606 # average StoreCondReq miss latency 1136system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18157.281452 # average overall miss latency 1137system.cpu1.dcache.demand_avg_miss_latency::total 18157.281452 # average overall miss latency 1138system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18157.281452 # average overall miss latency 1139system.cpu1.dcache.overall_avg_miss_latency::total 18157.281452 # average overall miss latency | 1069system.cpu1.dcache.replacements 642543 # number of replacements 1070system.cpu1.dcache.tagsinuse 493.349744 # Cycle average of tags in use 1071system.cpu1.dcache.total_refs 6059288 # Total number of references to valid blocks. 1072system.cpu1.dcache.sampled_refs 642980 # Sample count of references to valid blocks. 1073system.cpu1.dcache.avg_refs 9.423758 # Average number of references to valid blocks. 1074system.cpu1.dcache.warmup_cycle 54205321000 # Cycle when the warmup percentage was hit. 1075system.cpu1.dcache.occ_blocks::cpu1.data 493.349744 # Average occupied blocks per requestor 1076system.cpu1.dcache.occ_percent::cpu1.data 0.963574 # Average percentage of cache occupancy 1077system.cpu1.dcache.occ_percent::total 0.963574 # Average percentage of cache occupancy 1078system.cpu1.dcache.ReadReq_hits::cpu1.data 3370942 # number of ReadReq hits 1079system.cpu1.dcache.ReadReq_hits::total 3370942 # number of ReadReq hits 1080system.cpu1.dcache.WriteReq_hits::cpu1.data 2541026 # number of WriteReq hits 1081system.cpu1.dcache.WriteReq_hits::total 2541026 # number of WriteReq hits 1082system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71125 # number of LoadLockedReq hits 1083system.cpu1.dcache.LoadLockedReq_hits::total 71125 # number of LoadLockedReq hits 1084system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80221 # number of StoreCondReq hits 1085system.cpu1.dcache.StoreCondReq_hits::total 80221 # number of StoreCondReq hits 1086system.cpu1.dcache.demand_hits::cpu1.data 5911968 # number of demand (read+write) hits 1087system.cpu1.dcache.demand_hits::total 5911968 # number of demand (read+write) hits 1088system.cpu1.dcache.overall_hits::cpu1.data 5911968 # number of overall hits 1089system.cpu1.dcache.overall_hits::total 5911968 # number of overall hits 1090system.cpu1.dcache.ReadReq_misses::cpu1.data 513440 # number of ReadReq misses 1091system.cpu1.dcache.ReadReq_misses::total 513440 # number of ReadReq misses 1092system.cpu1.dcache.WriteReq_misses::cpu1.data 122215 # number of WriteReq misses 1093system.cpu1.dcache.WriteReq_misses::total 122215 # number of WriteReq misses 1094system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13103 # number of LoadLockedReq misses 1095system.cpu1.dcache.LoadLockedReq_misses::total 13103 # number of LoadLockedReq misses 1096system.cpu1.dcache.StoreCondReq_misses::cpu1.data 640 # number of StoreCondReq misses 1097system.cpu1.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses 1098system.cpu1.dcache.demand_misses::cpu1.data 635655 # number of demand (read+write) misses 1099system.cpu1.dcache.demand_misses::total 635655 # number of demand (read+write) misses 1100system.cpu1.dcache.overall_misses::cpu1.data 635655 # number of overall misses 1101system.cpu1.dcache.overall_misses::total 635655 # number of overall misses 1102system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7202447500 # number of ReadReq miss cycles 1103system.cpu1.dcache.ReadReq_miss_latency::total 7202447500 # number of ReadReq miss cycles 1104system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2665469000 # number of WriteReq miss cycles 1105system.cpu1.dcache.WriteReq_miss_latency::total 2665469000 # number of WriteReq miss cycles 1106system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 183740000 # number of LoadLockedReq miss cycles 1107system.cpu1.dcache.LoadLockedReq_miss_latency::total 183740000 # number of LoadLockedReq miss cycles 1108system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8466000 # number of StoreCondReq miss cycles 1109system.cpu1.dcache.StoreCondReq_miss_latency::total 8466000 # number of StoreCondReq miss cycles 1110system.cpu1.dcache.demand_miss_latency::cpu1.data 9867916500 # number of demand (read+write) miss cycles 1111system.cpu1.dcache.demand_miss_latency::total 9867916500 # number of demand (read+write) miss cycles 1112system.cpu1.dcache.overall_miss_latency::cpu1.data 9867916500 # number of overall miss cycles 1113system.cpu1.dcache.overall_miss_latency::total 9867916500 # number of overall miss cycles 1114system.cpu1.dcache.ReadReq_accesses::cpu1.data 3884382 # number of ReadReq accesses(hits+misses) 1115system.cpu1.dcache.ReadReq_accesses::total 3884382 # number of ReadReq accesses(hits+misses) 1116system.cpu1.dcache.WriteReq_accesses::cpu1.data 2663241 # number of WriteReq accesses(hits+misses) 1117system.cpu1.dcache.WriteReq_accesses::total 2663241 # number of WriteReq accesses(hits+misses) 1118system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 84228 # number of LoadLockedReq accesses(hits+misses) 1119system.cpu1.dcache.LoadLockedReq_accesses::total 84228 # number of LoadLockedReq accesses(hits+misses) 1120system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80861 # number of StoreCondReq accesses(hits+misses) 1121system.cpu1.dcache.StoreCondReq_accesses::total 80861 # number of StoreCondReq accesses(hits+misses) 1122system.cpu1.dcache.demand_accesses::cpu1.data 6547623 # number of demand (read+write) accesses 1123system.cpu1.dcache.demand_accesses::total 6547623 # number of demand (read+write) accesses 1124system.cpu1.dcache.overall_accesses::cpu1.data 6547623 # number of overall (read+write) accesses 1125system.cpu1.dcache.overall_accesses::total 6547623 # number of overall (read+write) accesses 1126system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.132181 # miss rate for ReadReq accesses 1127system.cpu1.dcache.ReadReq_miss_rate::total 0.132181 # miss rate for ReadReq accesses 1128system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045890 # miss rate for WriteReq accesses 1129system.cpu1.dcache.WriteReq_miss_rate::total 0.045890 # miss rate for WriteReq accesses 1130system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155566 # miss rate for LoadLockedReq accesses 1131system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155566 # miss rate for LoadLockedReq accesses 1132system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007915 # miss rate for StoreCondReq accesses 1133system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007915 # miss rate for StoreCondReq accesses 1134system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097082 # miss rate for demand accesses 1135system.cpu1.dcache.demand_miss_rate::total 0.097082 # miss rate for demand accesses 1136system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097082 # miss rate for overall accesses 1137system.cpu1.dcache.overall_miss_rate::total 0.097082 # miss rate for overall accesses 1138system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14027.827010 # average ReadReq miss latency 1139system.cpu1.dcache.ReadReq_avg_miss_latency::total 14027.827010 # average ReadReq miss latency 1140system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21809.671481 # average WriteReq miss latency 1141system.cpu1.dcache.WriteReq_avg_miss_latency::total 21809.671481 # average WriteReq miss latency 1142system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14022.742883 # average LoadLockedReq miss latency 1143system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14022.742883 # average LoadLockedReq miss latency 1144system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000 # average StoreCondReq miss latency 1145system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000 # average StoreCondReq miss latency 1146system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency 1147system.cpu1.dcache.demand_avg_miss_latency::total 15524.013026 # average overall miss latency 1148system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency 1149system.cpu1.dcache.overall_avg_miss_latency::total 15524.013026 # average overall miss latency |
| 1140system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1141system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1142system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1143system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1144system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1145system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1146system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1147system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1150system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1151system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1152system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1153system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1154system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1155system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1156system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1157system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1148system.cpu1.dcache.writebacks::writebacks 30624 # number of writebacks 1149system.cpu1.dcache.writebacks::total 30624 # number of writebacks 1150system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 36999 # number of ReadReq MSHR misses 1151system.cpu1.dcache.ReadReq_mshr_misses::total 36999 # number of ReadReq MSHR misses 1152system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20414 # number of WriteReq MSHR misses 1153system.cpu1.dcache.WriteReq_mshr_misses::total 20414 # number of WriteReq MSHR misses 1154system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 944 # number of LoadLockedReq MSHR misses 1155system.cpu1.dcache.LoadLockedReq_mshr_misses::total 944 # number of LoadLockedReq MSHR misses 1156system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 507 # number of StoreCondReq MSHR misses 1157system.cpu1.dcache.StoreCondReq_mshr_misses::total 507 # number of StoreCondReq MSHR misses 1158system.cpu1.dcache.demand_mshr_misses::cpu1.data 57413 # number of demand (read+write) MSHR misses 1159system.cpu1.dcache.demand_mshr_misses::total 57413 # number of demand (read+write) MSHR misses 1160system.cpu1.dcache.overall_mshr_misses::cpu1.data 57413 # number of overall MSHR misses 1161system.cpu1.dcache.overall_mshr_misses::total 57413 # number of overall MSHR misses 1162system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 381507000 # number of ReadReq MSHR miss cycles 1163system.cpu1.dcache.ReadReq_mshr_miss_latency::total 381507000 # number of ReadReq MSHR miss cycles 1164system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 488716000 # number of WriteReq MSHR miss cycles 1165system.cpu1.dcache.WriteReq_mshr_miss_latency::total 488716000 # number of WriteReq MSHR miss cycles 1166system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8473000 # number of LoadLockedReq MSHR miss cycles 1167system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8473000 # number of LoadLockedReq MSHR miss cycles 1168system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4831000 # number of StoreCondReq MSHR miss cycles 1169system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4831000 # number of StoreCondReq MSHR miss cycles 1170system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 870223000 # number of demand (read+write) MSHR miss cycles 1171system.cpu1.dcache.demand_mshr_miss_latency::total 870223000 # number of demand (read+write) MSHR miss cycles 1172system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 870223000 # number of overall MSHR miss cycles 1173system.cpu1.dcache.overall_mshr_miss_latency::total 870223000 # number of overall MSHR miss cycles 1174system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11412500 # number of ReadReq MSHR uncacheable cycles 1175system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11412500 # number of ReadReq MSHR uncacheable cycles 1176system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298066500 # number of WriteReq MSHR uncacheable cycles 1177system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298066500 # number of WriteReq MSHR uncacheable cycles 1178system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309479000 # number of overall MSHR uncacheable cycles 1179system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309479000 # number of overall MSHR uncacheable cycles 1180system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035572 # mshr miss rate for ReadReq accesses 1181system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035572 # mshr miss rate for ReadReq accesses 1182system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032036 # mshr miss rate for WriteReq accesses 1183system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032036 # mshr miss rate for WriteReq accesses 1184system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.073970 # mshr miss rate for LoadLockedReq accesses 1185system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.073970 # mshr miss rate for LoadLockedReq accesses 1186system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042159 # mshr miss rate for StoreCondReq accesses 1187system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042159 # mshr miss rate for StoreCondReq accesses 1188system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for demand accesses 1189system.cpu1.dcache.demand_mshr_miss_rate::total 0.034228 # mshr miss rate for demand accesses 1190system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034228 # mshr miss rate for overall accesses 1191system.cpu1.dcache.overall_mshr_miss_rate::total 0.034228 # mshr miss rate for overall accesses 1192system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10311.278683 # average ReadReq mshr miss latency 1193system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10311.278683 # average ReadReq mshr miss latency 1194system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23940.237092 # average WriteReq mshr miss latency 1195system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23940.237092 # average WriteReq mshr miss latency 1196system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8975.635593 # average LoadLockedReq mshr miss latency 1197system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8975.635593 # average LoadLockedReq mshr miss latency 1198system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9528.599606 # average StoreCondReq mshr miss latency 1199system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9528.599606 # average StoreCondReq mshr miss latency 1200system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency 1201system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency 1202system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15157.246617 # average overall mshr miss latency 1203system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15157.246617 # average overall mshr miss latency | 1158system.cpu1.dcache.writebacks::writebacks 498964 # number of writebacks 1159system.cpu1.dcache.writebacks::total 498964 # number of writebacks 1160system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 513440 # number of ReadReq MSHR misses 1161system.cpu1.dcache.ReadReq_mshr_misses::total 513440 # number of ReadReq MSHR misses 1162system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 122215 # number of WriteReq MSHR misses 1163system.cpu1.dcache.WriteReq_mshr_misses::total 122215 # number of WriteReq MSHR misses 1164system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13103 # number of LoadLockedReq MSHR misses 1165system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13103 # number of LoadLockedReq MSHR misses 1166system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 640 # number of StoreCondReq MSHR misses 1167system.cpu1.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses 1168system.cpu1.dcache.demand_mshr_misses::cpu1.data 635655 # number of demand (read+write) MSHR misses 1169system.cpu1.dcache.demand_mshr_misses::total 635655 # number of demand (read+write) MSHR misses 1170system.cpu1.dcache.overall_mshr_misses::cpu1.data 635655 # number of overall MSHR misses 1171system.cpu1.dcache.overall_mshr_misses::total 635655 # number of overall MSHR misses 1172system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662112010 # number of ReadReq MSHR miss cycles 1173system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662112010 # number of ReadReq MSHR miss cycles 1174system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298824000 # number of WriteReq MSHR miss cycles 1175system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298824000 # number of WriteReq MSHR miss cycles 1176system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144431000 # number of LoadLockedReq MSHR miss cycles 1177system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144431000 # number of LoadLockedReq MSHR miss cycles 1178system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6549000 # number of StoreCondReq MSHR miss cycles 1179system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6549000 # number of StoreCondReq MSHR miss cycles 1180system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5000 # number of StoreCondFailReq MSHR miss cycles 1181system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5000 # number of StoreCondFailReq MSHR miss cycles 1182system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7960936010 # number of demand (read+write) MSHR miss cycles 1183system.cpu1.dcache.demand_mshr_miss_latency::total 7960936010 # number of demand (read+write) MSHR miss cycles 1184system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7960936010 # number of overall MSHR miss cycles 1185system.cpu1.dcache.overall_mshr_miss_latency::total 7960936010 # number of overall MSHR miss cycles 1186system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295035500 # number of ReadReq MSHR uncacheable cycles 1187system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 295035500 # number of ReadReq MSHR uncacheable cycles 1188system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516397500 # number of WriteReq MSHR uncacheable cycles 1189system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516397500 # number of WriteReq MSHR uncacheable cycles 1190system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811433000 # number of overall MSHR uncacheable cycles 1191system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811433000 # number of overall MSHR uncacheable cycles 1192system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.132181 # mshr miss rate for ReadReq accesses 1193system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses 1194system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045890 # mshr miss rate for WriteReq accesses 1195system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045890 # mshr miss rate for WriteReq accesses 1196system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155566 # mshr miss rate for LoadLockedReq accesses 1197system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155566 # mshr miss rate for LoadLockedReq accesses 1198system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007915 # mshr miss rate for StoreCondReq accesses 1199system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007915 # mshr miss rate for StoreCondReq accesses 1200system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for demand accesses 1201system.cpu1.dcache.demand_mshr_miss_rate::total 0.097082 # mshr miss rate for demand accesses 1202system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for overall accesses 1203system.cpu1.dcache.overall_mshr_miss_rate::total 0.097082 # mshr miss rate for overall accesses 1204system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.796841 # average ReadReq mshr miss latency 1205system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.796841 # average ReadReq mshr miss latency 1206system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18809.671481 # average WriteReq mshr miss latency 1207system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18809.671481 # average WriteReq mshr miss latency 1208system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11022.742883 # average LoadLockedReq mshr miss latency 1209system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11022.742883 # average LoadLockedReq mshr miss latency 1210system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500 # average StoreCondReq mshr miss latency 1211system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500 # average StoreCondReq mshr miss latency 1212system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1213system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1214system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency 1215system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency 1216system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency 1217system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency |
| 1204system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1205system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1206system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1207system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1208system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1209system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1210system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1211 1212---------- End Simulation Statistics ---------- | 1218system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1219system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1220system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1221system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1222system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1223system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1224system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1225 1226---------- End Simulation Statistics ---------- |