| stats.txt (8983:8800b05e1cb3) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.958647 # Number of seconds simulated 4sim_ticks 1958647095000 # Number of ticks simulated 5final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.958647 # Number of seconds simulated 4sim_ticks 1958647095000 # Number of ticks simulated 5final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 669282 # Simulator instruction rate (inst/s) 8host_op_rate 669282 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22085281308 # Simulator tick rate (ticks/s) 10host_mem_usage 295084 # Number of bytes of host memory used 11host_seconds 88.69 # Real time elapsed on the host | 7host_inst_rate 1245422 # Simulator instruction rate (inst/s) 8host_op_rate 1245421 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41097010927 # Simulator tick rate (ticks/s) 10host_mem_usage 295412 # Number of bytes of host memory used 11host_seconds 47.66 # Real time elapsed on the host |
| 12sim_insts 59355643 # Number of instructions simulated 13sim_ops 59355643 # Number of ops (including micro ops) simulated | 12sim_insts 59355643 # Number of instructions simulated 13sim_ops 59355643 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 30050624 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10333120 # Number of bytes written to this memory 17system.physmem.num_reads 469541 # Number of read requests responded to by this memory 18system.physmem.num_writes 161455 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 15342541 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 495852 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 5275642 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 20618183 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu0.inst 919744 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 25960192 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 51456 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 468416 # Number of bytes read from this memory 19system.physmem.bytes_read::total 30050624 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 919744 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 51456 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 971200 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 10333120 # Number of bytes written to this memory 24system.physmem.bytes_written::total 10333120 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 14371 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 405628 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 804 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 7319 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 469541 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 161455 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 161455 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 469581 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 13254145 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1353391 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 26271 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 239153 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 15342541 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 469581 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 26271 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 495852 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 5275642 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 5275642 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 5275642 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 469581 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 13254145 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1353391 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 26271 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 239153 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 20618183 # Total bandwidth to/from this memory (bytes/s) |
| 24system.l2c.replacements 393576 # number of replacements 25system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use 26system.l2c.total_refs 2371449 # Total number of references to valid blocks. 27system.l2c.sampled_refs 427769 # Sample count of references to valid blocks. 28system.l2c.avg_refs 5.543761 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 23419.887612 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu0.inst 3728.336055 # Average occupied blocks per requestor --- 105 unchanged lines hidden (view full) --- 137system.l2c.overall_accesses::cpu0.data 1334296 # number of overall (read+write) accesses 138system.l2c.overall_accesses::cpu1.inst 87002 # number of overall (read+write) accesses 139system.l2c.overall_accesses::cpu1.data 52907 # number of overall (read+write) accesses 140system.l2c.overall_accesses::total 2389965 # number of overall (read+write) accesses 141system.l2c.ReadReq_miss_rate::cpu0.inst 0.015693 # miss rate for ReadReq accesses 142system.l2c.ReadReq_miss_rate::cpu0.data 0.275649 # miss rate for ReadReq accesses 143system.l2c.ReadReq_miss_rate::cpu1.inst 0.009368 # miss rate for ReadReq accesses 144system.l2c.ReadReq_miss_rate::cpu1.data 0.033331 # miss rate for ReadReq accesses | 51system.l2c.replacements 393576 # number of replacements 52system.l2c.tagsinuse 34487.800710 # Cycle average of tags in use 53system.l2c.total_refs 2371449 # Total number of references to valid blocks. 54system.l2c.sampled_refs 427769 # Sample count of references to valid blocks. 55system.l2c.avg_refs 5.543761 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 23419.887612 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 3728.336055 # Average occupied blocks per requestor --- 105 unchanged lines hidden (view full) --- 164system.l2c.overall_accesses::cpu0.data 1334296 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu1.inst 87002 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu1.data 52907 # number of overall (read+write) accesses 167system.l2c.overall_accesses::total 2389965 # number of overall (read+write) accesses 168system.l2c.ReadReq_miss_rate::cpu0.inst 0.015693 # miss rate for ReadReq accesses 169system.l2c.ReadReq_miss_rate::cpu0.data 0.275649 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu1.inst 0.009368 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu1.data 0.033331 # miss rate for ReadReq accesses |
| 172system.l2c.ReadReq_miss_rate::total 0.146292 # miss rate for ReadReq accesses |
|
| 145system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934476 # miss rate for UpgradeReq accesses 146system.l2c.UpgradeReq_miss_rate::cpu1.data 0.903285 # miss rate for UpgradeReq accesses | 173system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934476 # miss rate for UpgradeReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu1.data 0.903285 # miss rate for UpgradeReq accesses |
| 175system.l2c.UpgradeReq_miss_rate::total 0.929089 # miss rate for UpgradeReq accesses |
|
| 147system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.454545 # miss rate for SCUpgradeReq accesses 148system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.795699 # miss rate for SCUpgradeReq accesses | 176system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.454545 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.795699 # miss rate for SCUpgradeReq accesses |
| 178system.l2c.SCUpgradeReq_miss_rate::total 0.706349 # miss rate for SCUpgradeReq accesses |
|
| 149system.l2c.ReadExReq_miss_rate::cpu0.data 0.408381 # miss rate for ReadExReq accesses 150system.l2c.ReadExReq_miss_rate::cpu1.data 0.330189 # miss rate for ReadExReq accesses | 179system.l2c.ReadExReq_miss_rate::cpu0.data 0.408381 # miss rate for ReadExReq accesses 180system.l2c.ReadExReq_miss_rate::cpu1.data 0.330189 # miss rate for ReadExReq accesses |
| 181system.l2c.ReadExReq_miss_rate::total 0.403596 # miss rate for ReadExReq accesses |
|
| 151system.l2c.demand_miss_rate::cpu0.inst 0.015693 # miss rate for demand accesses 152system.l2c.demand_miss_rate::cpu0.data 0.304282 # miss rate for demand accesses 153system.l2c.demand_miss_rate::cpu1.inst 0.009368 # miss rate for demand accesses 154system.l2c.demand_miss_rate::cpu1.data 0.138621 # miss rate for demand accesses | 182system.l2c.demand_miss_rate::cpu0.inst 0.015693 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu0.data 0.304282 # miss rate for demand accesses 184system.l2c.demand_miss_rate::cpu1.inst 0.009368 # miss rate for demand accesses 185system.l2c.demand_miss_rate::cpu1.data 0.138621 # miss rate for demand accesses |
| 186system.l2c.demand_miss_rate::total 0.179301 # miss rate for demand accesses |
|
| 155system.l2c.overall_miss_rate::cpu0.inst 0.015693 # miss rate for overall accesses 156system.l2c.overall_miss_rate::cpu0.data 0.304282 # miss rate for overall accesses 157system.l2c.overall_miss_rate::cpu1.inst 0.009368 # miss rate for overall accesses 158system.l2c.overall_miss_rate::cpu1.data 0.138621 # miss rate for overall accesses | 187system.l2c.overall_miss_rate::cpu0.inst 0.015693 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu0.data 0.304282 # miss rate for overall accesses 189system.l2c.overall_miss_rate::cpu1.inst 0.009368 # miss rate for overall accesses 190system.l2c.overall_miss_rate::cpu1.data 0.138621 # miss rate for overall accesses |
| 191system.l2c.overall_miss_rate::total 0.179301 # miss rate for overall accesses |
|
| 159system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190 # average ReadReq miss latency 160system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332 # average ReadReq miss latency 161system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595 # average ReadReq miss latency 162system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262 # average ReadReq miss latency | 192system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595 # average ReadReq miss latency 195system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262 # average ReadReq miss latency |
| 196system.l2c.ReadReq_avg_miss_latency::total 52016.667760 # average ReadReq miss latency |
|
| 163system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 914.798206 # average UpgradeReq miss latency 164system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1575.757576 # average UpgradeReq miss latency | 197system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 914.798206 # average UpgradeReq miss latency 198system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1575.757576 # average UpgradeReq miss latency |
| 199system.l2c.UpgradeReq_avg_miss_latency::total 1025.780190 # average UpgradeReq miss latency |
|
| 165system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6933.333333 # average SCUpgradeReq miss latency 166system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4216.216216 # average SCUpgradeReq miss latency | 200system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6933.333333 # average SCUpgradeReq miss latency 201system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4216.216216 # average SCUpgradeReq miss latency |
| 202system.l2c.SCUpgradeReq_avg_miss_latency::total 4674.157303 # average SCUpgradeReq miss latency |
|
| 167system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612 # average ReadExReq miss latency 168system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972 # average ReadExReq miss latency | 203system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612 # average ReadExReq miss latency 204system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972 # average ReadExReq miss latency |
| 205system.l2c.ReadExReq_avg_miss_latency::total 52002.375911 # average ReadExReq miss latency |
|
| 169system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency 170system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency 171system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency 172system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency | 206system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency 207system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency 208system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency 209system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency |
| 210system.l2c.demand_avg_miss_latency::total 52012.540780 # average overall miss latency |
|
| 173system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency 174system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency 175system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency 176system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency | 211system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency 212system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency 213system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency 214system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency |
| 215system.l2c.overall_avg_miss_latency::total 52012.540780 # average overall miss latency |
|
| 177system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 179system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 180system.l2c.blocked::no_targets 0 # number of cycles access was blocked 181system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 182system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 183system.l2c.fast_writes 0 # number of fast writes performed 184system.l2c.cache_copies 0 # number of cache copies performed --- 61 unchanged lines hidden (view full) --- 246system.l2c.WriteReq_mshr_uncacheable_latency::total 1391411500 # number of WriteReq MSHR uncacheable cycles 247system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1914300000 # number of overall MSHR uncacheable cycles 248system.l2c.overall_mshr_uncacheable_latency::cpu1.data 279426000 # number of overall MSHR uncacheable cycles 249system.l2c.overall_mshr_uncacheable_latency::total 2193726000 # number of overall MSHR uncacheable cycles 250system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for ReadReq accesses 251system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275649 # mshr miss rate for ReadReq accesses 252system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for ReadReq accesses 253system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.033331 # mshr miss rate for ReadReq accesses | 216system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 219system.l2c.blocked::no_targets 0 # number of cycles access was blocked 220system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.l2c.fast_writes 0 # number of fast writes performed 223system.l2c.cache_copies 0 # number of cache copies performed --- 61 unchanged lines hidden (view full) --- 285system.l2c.WriteReq_mshr_uncacheable_latency::total 1391411500 # number of WriteReq MSHR uncacheable cycles 286system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1914300000 # number of overall MSHR uncacheable cycles 287system.l2c.overall_mshr_uncacheable_latency::cpu1.data 279426000 # number of overall MSHR uncacheable cycles 288system.l2c.overall_mshr_uncacheable_latency::total 2193726000 # number of overall MSHR uncacheable cycles 289system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for ReadReq accesses 290system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275649 # mshr miss rate for ReadReq accesses 291system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for ReadReq accesses 292system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.033331 # mshr miss rate for ReadReq accesses |
| 293system.l2c.ReadReq_mshr_miss_rate::total 0.146287 # mshr miss rate for ReadReq accesses |
|
| 254system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934476 # mshr miss rate for UpgradeReq accesses 255system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses | 294system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934476 # mshr miss rate for UpgradeReq accesses 295system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses |
| 296system.l2c.UpgradeReq_mshr_miss_rate::total 0.929089 # mshr miss rate for UpgradeReq accesses |
|
| 256system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses 257system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses | 297system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses 298system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses |
| 299system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706349 # mshr miss rate for SCUpgradeReq accesses |
|
| 258system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses 259system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses | 300system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses 301system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses |
| 302system.l2c.ReadExReq_mshr_miss_rate::total 0.403596 # mshr miss rate for ReadExReq accesses |
|
| 260system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses 261system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses 262system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses 263system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses | 303system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses 304system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses 305system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses 306system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses |
| 307system.l2c.demand_mshr_miss_rate::total 0.179296 # mshr miss rate for demand accesses |
|
| 264system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses 265system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses 266system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses 267system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses | 308system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses 309system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses 310system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses 311system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses |
| 312system.l2c.overall_mshr_miss_rate::total 0.179296 # mshr miss rate for overall accesses |
|
| 268system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency 269system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency 270system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency 271system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency | 313system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency 314system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency 315system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency 316system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency |
| 317system.l2c.ReadReq_avg_mshr_miss_latency::total 40016.717580 # average ReadReq mshr miss latency |
|
| 272system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency 273system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency | 318system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency 319system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency |
| 320system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.691995 # average UpgradeReq mshr miss latency |
|
| 274system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency 275system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency | 321system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency 322system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency |
| 323system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency |
|
| 276system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency 277system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency | 324system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency 325system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency |
| 326system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.375911 # average ReadExReq mshr miss latency |
|
| 278system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency 279system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency 280system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency 281system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency | 327system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency 328system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency 329system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency 330system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency |
| 331system.l2c.demand_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency |
|
| 282system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency 283system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency 284system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency 285system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency | 332system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency 333system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency 334system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency 335system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency |
| 336system.l2c.overall_avg_mshr_miss_latency::total 40012.576107 # average overall mshr miss latency |
|
| 286system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 287system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency | 337system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 338system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency |
| 339system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 288system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 289system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency | 340system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 341system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |
| 342system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 290system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 291system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency | 343system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 344system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency |
| 345system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 292system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 293system.iocache.replacements 41694 # number of replacements 294system.iocache.tagsinuse 0.563721 # Cycle average of tags in use 295system.iocache.total_refs 0 # Total number of references to valid blocks. 296system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. 297system.iocache.avg_refs 0 # Average number of references to valid blocks. 298system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit. 299system.iocache.occ_blocks::tsunami.ide 0.563721 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 319system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 320system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 321system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 322system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 323system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 324system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 325system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 326system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses | 346system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 347system.iocache.replacements 41694 # number of replacements 348system.iocache.tagsinuse 0.563721 # Cycle average of tags in use 349system.iocache.total_refs 0 # Total number of references to valid blocks. 350system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. 351system.iocache.avg_refs 0 # Average number of references to valid blocks. 352system.iocache.warmup_cycle 1751545158000 # Cycle when the warmup percentage was hit. 353system.iocache.occ_blocks::tsunami.ide 0.563721 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 373system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 374system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 375system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 376system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 377system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 378system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 379system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 380system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses |
| 381system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
|
| 327system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses | 382system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses |
| 383system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses |
|
| 328system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses | 384system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses |
| 385system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses |
|
| 329system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses | 386system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses |
| 387system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
|
| 330system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency | 388system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency |
| 389system.iocache.ReadReq_avg_miss_latency::total 115247.114943 # average ReadReq miss latency |
|
| 331system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency | 390system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency |
| 391system.iocache.WriteReq_avg_miss_latency::total 137701.766606 # average WriteReq miss latency |
|
| 332system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency | 392system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency |
| 393system.iocache.demand_avg_miss_latency::total 137608.129320 # average overall miss latency |
|
| 333system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency | 394system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency |
| 395system.iocache.overall_avg_miss_latency::total 137608.129320 # average overall miss latency |
|
| 334system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked 335system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 336system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked 337system.iocache.blocked::no_targets 0 # number of cycles access was blocked 338system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked 339system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 340system.iocache.fast_writes 0 # number of fast writes performed 341system.iocache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 353system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles 354system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560928000 # number of WriteReq MSHR miss cycles 355system.iocache.WriteReq_mshr_miss_latency::total 3560928000 # number of WriteReq MSHR miss cycles 356system.iocache.demand_mshr_miss_latency::tsunami.ide 3571932998 # number of demand (read+write) MSHR miss cycles 357system.iocache.demand_mshr_miss_latency::total 3571932998 # number of demand (read+write) MSHR miss cycles 358system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles 359system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles 360system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses | 396system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked 397system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked 399system.iocache.blocked::no_targets 0 # number of cycles access was blocked 400system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked 401system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.iocache.fast_writes 0 # number of fast writes performed 403system.iocache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 415system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles 416system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560928000 # number of WriteReq MSHR miss cycles 417system.iocache.WriteReq_mshr_miss_latency::total 3560928000 # number of WriteReq MSHR miss cycles 418system.iocache.demand_mshr_miss_latency::tsunami.ide 3571932998 # number of demand (read+write) MSHR miss cycles 419system.iocache.demand_mshr_miss_latency::total 3571932998 # number of demand (read+write) MSHR miss cycles 420system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles 421system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles 422system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses |
| 423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
|
| 361system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses | 424system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses |
| 425system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses |
|
| 362system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses | 426system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses |
| 427system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses |
|
| 363system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses | 428system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses |
| 429system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
|
| 364system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency | 430system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency |
| 431system.iocache.ReadReq_avg_mshr_miss_latency::total 63247.114943 # average ReadReq mshr miss latency |
|
| 365system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency | 432system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency |
| 433system.iocache.WriteReq_avg_mshr_miss_latency::total 85698.113208 # average WriteReq mshr miss latency |
|
| 366system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency | 434system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency |
| 435system.iocache.demand_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency |
|
| 367system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency | 436system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency |
| 437system.iocache.overall_avg_mshr_miss_latency::total 85604.491157 # average overall mshr miss latency |
|
| 368system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 369system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 370system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 371system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 372system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 373system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 374system.disk0.dma_write_txs 395 # Number of DMA write transactions. 375system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 77 unchanged lines hidden (view full) --- 453system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl 454system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl 455system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl 456system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl 457system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 458system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 459system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 460system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl | 438system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 439system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 440system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 441system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 442system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 443system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 444system.disk0.dma_write_txs 395 # Number of DMA write transactions. 445system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). --- 77 unchanged lines hidden (view full) --- 523system.cpu0.kern.ipl_ticks::30 4729500 0.00% 97.05% # number of cycles we spent at this ipl 524system.cpu0.kern.ipl_ticks::31 57694185000 2.95% 100.00% # number of cycles we spent at this ipl 525system.cpu0.kern.ipl_ticks::total 1958011857000 # number of cycles we spent at this ipl 526system.cpu0.kern.ipl_used::0 0.981207 # fraction of swpipl calls that actually changed the ipl 527system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 528system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 529system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 530system.cpu0.kern.ipl_used::31 0.684822 # fraction of swpipl calls that actually changed the ipl |
| 531system.cpu0.kern.ipl_used::total 0.808938 # fraction of swpipl calls that actually changed the ipl |
|
| 461system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 462system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 463system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 464system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 465system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 466system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 467system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 468system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed --- 41 unchanged lines hidden (view full) --- 510system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 511system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 512system.cpu0.kern.mode_good::kernel 1283 513system.cpu0.kern.mode_good::user 1283 514system.cpu0.kern.mode_good::idle 0 515system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches 516system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 517system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 532system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 533system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 534system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 535system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 536system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 537system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 538system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 539system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed --- 41 unchanged lines hidden (view full) --- 581system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 582system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 583system.cpu0.kern.mode_good::kernel 1283 584system.cpu0.kern.mode_good::user 1283 585system.cpu0.kern.mode_good::idle 0 586system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches 587system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 588system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 518system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches | 589system.cpu0.kern.mode_switch_good::total 0.298893 # fraction of useful protection mode switches |
| 519system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode 520system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode 521system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 522system.cpu0.kern.swap_context 3895 # number of times the context was actually changed 523system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 524system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 525system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 526system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA --- 53 unchanged lines hidden (view full) --- 580system.cpu0.icache.overall_miss_latency::total 13429132500 # number of overall miss cycles 581system.cpu0.icache.ReadReq_accesses::cpu0.inst 54081252 # number of ReadReq accesses(hits+misses) 582system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses) 583system.cpu0.icache.demand_accesses::cpu0.inst 54081252 # number of demand (read+write) accesses 584system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses 585system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses 586system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses 587system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses | 590system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode 591system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode 592system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 593system.cpu0.kern.swap_context 3895 # number of times the context was actually changed 594system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 595system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 596system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 597system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA --- 53 unchanged lines hidden (view full) --- 651system.cpu0.icache.overall_miss_latency::total 13429132500 # number of overall miss cycles 652system.cpu0.icache.ReadReq_accesses::cpu0.inst 54081252 # number of ReadReq accesses(hits+misses) 653system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses) 654system.cpu0.icache.demand_accesses::cpu0.inst 54081252 # number of demand (read+write) accesses 655system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses 656system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses 657system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses 658system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses |
| 659system.cpu0.icache.ReadReq_miss_rate::total 0.016933 # miss rate for ReadReq accesses |
|
| 588system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses | 660system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses |
| 661system.cpu0.icache.demand_miss_rate::total 0.016933 # miss rate for demand accesses |
|
| 589system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses | 662system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses |
| 663system.cpu0.icache.overall_miss_rate::total 0.016933 # miss rate for overall accesses |
|
| 590system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency | 664system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency |
| 665system.cpu0.icache.ReadReq_avg_miss_latency::total 14664.130944 # average ReadReq miss latency |
|
| 591system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency | 666system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency |
| 667system.cpu0.icache.demand_avg_miss_latency::total 14664.130944 # average overall miss latency |
|
| 592system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency | 668system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency |
| 669system.cpu0.icache.overall_avg_miss_latency::total 14664.130944 # average overall miss latency |
|
| 593system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 594system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 595system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 596system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 597system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 598system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 599system.cpu0.icache.fast_writes 0 # number of fast writes performed 600system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 608system.cpu0.icache.overall_mshr_misses::total 915781 # number of overall MSHR misses 609system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10681093500 # number of ReadReq MSHR miss cycles 610system.cpu0.icache.ReadReq_mshr_miss_latency::total 10681093500 # number of ReadReq MSHR miss cycles 611system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10681093500 # number of demand (read+write) MSHR miss cycles 612system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 # number of demand (read+write) MSHR miss cycles 613system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles 614system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles 615system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses | 670system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 671system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 672system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 673system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 674system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 675system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 676system.cpu0.icache.fast_writes 0 # number of fast writes performed 677system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 685system.cpu0.icache.overall_mshr_misses::total 915781 # number of overall MSHR misses 686system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10681093500 # number of ReadReq MSHR miss cycles 687system.cpu0.icache.ReadReq_mshr_miss_latency::total 10681093500 # number of ReadReq MSHR miss cycles 688system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10681093500 # number of demand (read+write) MSHR miss cycles 689system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 # number of demand (read+write) MSHR miss cycles 690system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles 691system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles 692system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses |
| 693system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016933 # mshr miss rate for ReadReq accesses |
|
| 616system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses | 694system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses |
| 695system.cpu0.icache.demand_mshr_miss_rate::total 0.016933 # mshr miss rate for demand accesses |
|
| 617system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses | 696system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses |
| 697system.cpu0.icache.overall_mshr_miss_rate::total 0.016933 # mshr miss rate for overall accesses |
|
| 618system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency | 698system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency |
| 699system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11663.370937 # average ReadReq mshr miss latency |
|
| 619system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency | 700system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency |
| 701system.cpu0.icache.demand_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency |
|
| 620system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency | 702system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency |
| 703system.cpu0.icache.overall_avg_mshr_miss_latency::total 11663.370937 # average overall mshr miss latency |
|
| 621system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 622system.cpu0.dcache.replacements 1338438 # number of replacements 623system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use 624system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks. 625system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks. 626system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks. 627system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. 628system.cpu0.dcache.occ_blocks::cpu0.data 503.524900 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 672system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses) 673system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192084 # number of StoreCondReq accesses(hits+misses) 674system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses) 675system.cpu0.dcache.demand_accesses::cpu0.data 14308776 # number of demand (read+write) accesses 676system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses 677system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses 678system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses 679system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses | 704system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 705system.cpu0.dcache.replacements 1338438 # number of replacements 706system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use 707system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks. 708system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks. 709system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks. 710system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. 711system.cpu0.dcache.occ_blocks::cpu0.data 503.524900 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 755system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses) 756system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192084 # number of StoreCondReq accesses(hits+misses) 757system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses) 758system.cpu0.dcache.demand_accesses::cpu0.data 14308776 # number of demand (read+write) accesses 759system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses 760system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses 761system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses 762system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses |
| 763system.cpu0.dcache.ReadReq_miss_rate::total 0.122512 # miss rate for ReadReq accesses |
|
| 680system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses | 764system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses |
| 765system.cpu0.dcache.WriteReq_miss_rate::total 0.049821 # miss rate for WriteReq accesses |
|
| 681system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses | 766system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses |
| 767system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085698 # miss rate for LoadLockedReq accesses |
|
| 682system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses | 768system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses |
| 769system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002134 # miss rate for StoreCondReq accesses |
|
| 683system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses | 770system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses |
| 771system.cpu0.dcache.demand_miss_rate::total 0.092785 # miss rate for demand accesses |
|
| 684system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses | 772system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses |
| 773system.cpu0.dcache.overall_miss_rate::total 0.092785 # miss rate for overall accesses |
|
| 685system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency | 774system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency |
| 775system.cpu0.dcache.ReadReq_avg_miss_latency::total 25644.487844 # average ReadReq miss latency |
|
| 686system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency | 776system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency |
| 777system.cpu0.dcache.WriteReq_avg_miss_latency::total 31248.127161 # average WriteReq miss latency |
|
| 687system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency | 778system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency |
| 779system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14201.462766 # average LoadLockedReq miss latency |
|
| 688system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency | 780system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency |
| 781system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7251.219512 # average StoreCondReq miss latency |
|
| 689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency | 782system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency |
| 783system.cpu0.dcache.demand_avg_miss_latency::total 26874.991809 # average overall miss latency |
|
| 690system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency | 784system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency |
| 785system.cpu0.dcache.overall_avg_miss_latency::total 26874.991809 # average overall miss latency |
|
| 691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 697system.cpu0.dcache.fast_writes 0 # number of fast writes performed 698system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 25 unchanged lines hidden (view full) --- 724system.cpu0.dcache.overall_mshr_miss_latency::total 31697284500 # number of overall MSHR miss cycles 725system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles 726system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles 727system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1242107000 # number of WriteReq MSHR uncacheable cycles 728system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 # number of WriteReq MSHR uncacheable cycles 729system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles 730system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles 731system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses | 786system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 787system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 788system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 789system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 790system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 791system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 792system.cpu0.dcache.fast_writes 0 # number of fast writes performed 793system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 25 unchanged lines hidden (view full) --- 819system.cpu0.dcache.overall_mshr_miss_latency::total 31697284500 # number of overall MSHR miss cycles 820system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles 821system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles 822system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1242107000 # number of WriteReq MSHR uncacheable cycles 823system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 # number of WriteReq MSHR uncacheable cycles 824system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles 825system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles 826system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses |
| 827system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122512 # mshr miss rate for ReadReq accesses |
|
| 732system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses | 828system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses |
| 829system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049821 # mshr miss rate for WriteReq accesses |
|
| 733system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses | 830system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses |
| 831system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085698 # mshr miss rate for LoadLockedReq accesses |
|
| 734system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses | 832system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses |
| 833system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002134 # mshr miss rate for StoreCondReq accesses |
|
| 735system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses | 834system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses |
| 835system.cpu0.dcache.demand_mshr_miss_rate::total 0.092785 # mshr miss rate for demand accesses |
|
| 736system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses | 836system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses |
| 837system.cpu0.dcache.overall_mshr_miss_rate::total 0.092785 # mshr miss rate for overall accesses |
|
| 737system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency | 838system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency |
| 839system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22644.451168 # average ReadReq mshr miss latency |
|
| 738system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency | 840system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency |
| 841system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28248.127161 # average WriteReq mshr miss latency |
|
| 739system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency | 842system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency |
| 843system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11201.462766 # average LoadLockedReq mshr miss latency |
|
| 740system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency | 844system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency |
| 845system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4251.219512 # average StoreCondReq mshr miss latency |
|
| 741system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency | 846system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency |
| 847system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency |
|
| 742system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency | 848system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency |
| 849system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23874.963186 # average overall mshr miss latency |
|
| 743system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency | 850system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency |
| 851system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 744system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency | 852system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency |
| 853system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 745system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency | 854system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency |
| 855system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 746system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 747system.cpu1.dtb.fetch_hits 0 # ITB hits 748system.cpu1.dtb.fetch_misses 0 # ITB misses 749system.cpu1.dtb.fetch_acv 0 # ITB acv 750system.cpu1.dtb.fetch_accesses 0 # ITB accesses 751system.cpu1.dtb.read_hits 1050117 # DTB read hits 752system.cpu1.dtb.read_misses 2992 # DTB read misses 753system.cpu1.dtb.read_acv 0 # DTB read access violations --- 61 unchanged lines hidden (view full) --- 815system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl 816system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl 817system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl 818system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl 819system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl 820system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 821system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 822system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl | 856system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 857system.cpu1.dtb.fetch_hits 0 # ITB hits 858system.cpu1.dtb.fetch_misses 0 # ITB misses 859system.cpu1.dtb.fetch_acv 0 # ITB acv 860system.cpu1.dtb.fetch_accesses 0 # ITB accesses 861system.cpu1.dtb.read_hits 1050117 # DTB read hits 862system.cpu1.dtb.read_misses 2992 # DTB read misses 863system.cpu1.dtb.read_acv 0 # DTB read access violations --- 61 unchanged lines hidden (view full) --- 925system.cpu1.kern.ipl_ticks::22 507844000 0.03% 97.94% # number of cycles we spent at this ipl 926system.cpu1.kern.ipl_ticks::30 54239000 0.00% 97.95% # number of cycles we spent at this ipl 927system.cpu1.kern.ipl_ticks::31 40205672000 2.05% 100.00% # number of cycles we spent at this ipl 928system.cpu1.kern.ipl_ticks::total 1958646337000 # number of cycles we spent at this ipl 929system.cpu1.kern.ipl_used::0 0.998923 # fraction of swpipl calls that actually changed the ipl 930system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 931system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 932system.cpu1.kern.ipl_used::31 0.523674 # fraction of swpipl calls that actually changed the ipl |
| 933system.cpu1.kern.ipl_used::total 0.710351 # fraction of swpipl calls that actually changed the ipl |
|
| 823system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 824system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 825system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 826system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 827system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 828system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 829system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 830system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed --- 24 unchanged lines hidden (view full) --- 855system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 856system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches 857system.cpu1.kern.mode_good::kernel 477 858system.cpu1.kern.mode_good::user 464 859system.cpu1.kern.mode_good::idle 13 860system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches 861system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 862system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches | 934system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 935system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 936system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 937system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 938system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 939system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 940system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 941system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed --- 24 unchanged lines hidden (view full) --- 966system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 967system.cpu1.kern.mode_switch::idle 2064 # number of protection mode switches 968system.cpu1.kern.mode_good::kernel 477 969system.cpu1.kern.mode_good::user 464 970system.cpu1.kern.mode_good::idle 13 971system.cpu1.kern.mode_switch_good::kernel 0.593284 # fraction of useful protection mode switches 972system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 973system.cpu1.kern.mode_switch_good::idle 0.006298 # fraction of useful protection mode switches |
| 863system.cpu1.kern.mode_switch_good::total 1.599582 # fraction of useful protection mode switches | 974system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches |
| 864system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode 865system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode 866system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode 867system.cpu1.kern.swap_context 338 # number of times the context was actually changed 868system.cpu1.icache.replacements 86457 # number of replacements 869system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use 870system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks. 871system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks. --- 22 unchanged lines hidden (view full) --- 894system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles 895system.cpu1.icache.ReadReq_accesses::cpu1.inst 5286354 # number of ReadReq accesses(hits+misses) 896system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses) 897system.cpu1.icache.demand_accesses::cpu1.inst 5286354 # number of demand (read+write) accesses 898system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses 899system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses 900system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses 901system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses | 975system.cpu1.kern.mode_ticks::kernel 3571416000 0.18% 0.18% # number of ticks spent at the given mode 976system.cpu1.kern.mode_ticks::user 1745054000 0.09% 0.27% # number of ticks spent at the given mode 977system.cpu1.kern.mode_ticks::idle 1953329865000 99.73% 100.00% # number of ticks spent at the given mode 978system.cpu1.kern.swap_context 338 # number of times the context was actually changed 979system.cpu1.icache.replacements 86457 # number of replacements 980system.cpu1.icache.tagsinuse 419.807616 # Cycle average of tags in use 981system.cpu1.icache.total_refs 5199349 # Total number of references to valid blocks. 982system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks. --- 22 unchanged lines hidden (view full) --- 1005system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles 1006system.cpu1.icache.ReadReq_accesses::cpu1.inst 5286354 # number of ReadReq accesses(hits+misses) 1007system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses) 1008system.cpu1.icache.demand_accesses::cpu1.inst 5286354 # number of demand (read+write) accesses 1009system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses 1010system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses 1011system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses 1012system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses |
| 1013system.cpu1.icache.ReadReq_miss_rate::total 0.016458 # miss rate for ReadReq accesses |
|
| 902system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses | 1014system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses |
| 1015system.cpu1.icache.demand_miss_rate::total 0.016458 # miss rate for demand accesses |
|
| 903system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses | 1016system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses |
| 1017system.cpu1.icache.overall_miss_rate::total 0.016458 # miss rate for overall accesses |
|
| 904system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency | 1018system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency |
| 1019system.cpu1.icache.ReadReq_avg_miss_latency::total 14488.908683 # average ReadReq miss latency |
|
| 905system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency | 1020system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency |
| 1021system.cpu1.icache.demand_avg_miss_latency::total 14488.908683 # average overall miss latency |
|
| 906system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency | 1022system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency |
| 1023system.cpu1.icache.overall_avg_miss_latency::total 14488.908683 # average overall miss latency |
|
| 907system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 908system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 909system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 910system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 911system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 912system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 913system.cpu1.icache.fast_writes 0 # number of fast writes performed 914system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 922system.cpu1.icache.overall_mshr_misses::total 87005 # number of overall MSHR misses 923system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 999558500 # number of ReadReq MSHR miss cycles 924system.cpu1.icache.ReadReq_mshr_miss_latency::total 999558500 # number of ReadReq MSHR miss cycles 925system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 999558500 # number of demand (read+write) MSHR miss cycles 926system.cpu1.icache.demand_mshr_miss_latency::total 999558500 # number of demand (read+write) MSHR miss cycles 927system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles 928system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles 929system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses | 1024system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1025system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1026system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1027system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1028system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1029system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1030system.cpu1.icache.fast_writes 0 # number of fast writes performed 1031system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 7 unchanged lines hidden (view full) --- 1039system.cpu1.icache.overall_mshr_misses::total 87005 # number of overall MSHR misses 1040system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 999558500 # number of ReadReq MSHR miss cycles 1041system.cpu1.icache.ReadReq_mshr_miss_latency::total 999558500 # number of ReadReq MSHR miss cycles 1042system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 999558500 # number of demand (read+write) MSHR miss cycles 1043system.cpu1.icache.demand_mshr_miss_latency::total 999558500 # number of demand (read+write) MSHR miss cycles 1044system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles 1045system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles 1046system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses |
| 1047system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016458 # mshr miss rate for ReadReq accesses |
|
| 930system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses | 1048system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses |
| 1049system.cpu1.icache.demand_mshr_miss_rate::total 0.016458 # mshr miss rate for demand accesses |
|
| 931system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses | 1050system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses |
| 1051system.cpu1.icache.overall_mshr_miss_rate::total 0.016458 # mshr miss rate for overall accesses |
|
| 932system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency | 1052system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency |
| 1053system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11488.517901 # average ReadReq mshr miss latency |
|
| 933system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency | 1054system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency |
| 1055system.cpu1.icache.demand_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency |
|
| 934system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency | 1056system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency |
| 1057system.cpu1.icache.overall_avg_mshr_miss_latency::total 11488.517901 # average overall mshr miss latency |
|
| 935system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 936system.cpu1.dcache.replacements 52960 # number of replacements 937system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use 938system.cpu1.dcache.total_refs 1644934 # Total number of references to valid blocks. 939system.cpu1.dcache.sampled_refs 53472 # Sample count of references to valid blocks. 940system.cpu1.dcache.avg_refs 30.762530 # Average number of references to valid blocks. 941system.cpu1.dcache.warmup_cycle 1942411783000 # Cycle when the warmup percentage was hit. 942system.cpu1.dcache.occ_blocks::cpu1.data 389.521271 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 986system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses) 987system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12031 # number of StoreCondReq accesses(hits+misses) 988system.cpu1.dcache.StoreCondReq_accesses::total 12031 # number of StoreCondReq accesses(hits+misses) 989system.cpu1.dcache.demand_accesses::cpu1.data 1677594 # number of demand (read+write) accesses 990system.cpu1.dcache.demand_accesses::total 1677594 # number of demand (read+write) accesses 991system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses 992system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses 993system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses | 1058system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1059system.cpu1.dcache.replacements 52960 # number of replacements 1060system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use 1061system.cpu1.dcache.total_refs 1644934 # Total number of references to valid blocks. 1062system.cpu1.dcache.sampled_refs 53472 # Sample count of references to valid blocks. 1063system.cpu1.dcache.avg_refs 30.762530 # Average number of references to valid blocks. 1064system.cpu1.dcache.warmup_cycle 1942411783000 # Cycle when the warmup percentage was hit. 1065system.cpu1.dcache.occ_blocks::cpu1.data 389.521271 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 1109system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses) 1110system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12031 # number of StoreCondReq accesses(hits+misses) 1111system.cpu1.dcache.StoreCondReq_accesses::total 12031 # number of StoreCondReq accesses(hits+misses) 1112system.cpu1.dcache.demand_accesses::cpu1.data 1677594 # number of demand (read+write) accesses 1113system.cpu1.dcache.demand_accesses::total 1677594 # number of demand (read+write) accesses 1114system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses 1115system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses 1116system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses |
| 1117system.cpu1.dcache.ReadReq_miss_rate::total 0.035676 # miss rate for ReadReq accesses |
|
| 994system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses | 1118system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses |
| 1119system.cpu1.dcache.WriteReq_miss_rate::total 0.032042 # miss rate for WriteReq accesses |
|
| 995system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses | 1120system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses |
| 1121system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.076923 # miss rate for LoadLockedReq accesses |
|
| 996system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses | 1122system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses |
| 1123system.cpu1.dcache.StoreCondReq_miss_rate::total 0.041975 # miss rate for StoreCondReq accesses |
|
| 997system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses | 1124system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses |
| 1125system.cpu1.dcache.demand_miss_rate::total 0.034296 # miss rate for demand accesses |
|
| 998system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses | 1126system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses |
| 1127system.cpu1.dcache.overall_miss_rate::total 0.034296 # miss rate for overall accesses |
|
| 999system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency | 1128system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency |
| 1129system.cpu1.dcache.ReadReq_avg_miss_latency::total 14368.630938 # average ReadReq miss latency |
|
| 1000system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency | 1130system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency |
| 1131system.cpu1.dcache.WriteReq_avg_miss_latency::total 27265.853778 # average WriteReq miss latency |
|
| 1001system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency | 1132system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency |
| 1133system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13318.737271 # average LoadLockedReq miss latency |
|
| 1002system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency | 1134system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency |
| 1135system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 12704.950495 # average StoreCondReq miss latency |
|
| 1003system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency | 1136system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency |
| 1137system.cpu1.dcache.demand_avg_miss_latency::total 18946.344770 # average overall miss latency |
|
| 1004system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency | 1138system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency |
| 1139system.cpu1.dcache.overall_avg_miss_latency::total 18946.344770 # average overall miss latency |
|
| 1005system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1006system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1007system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1008system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1009system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1010system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1011system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1012system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 25 unchanged lines hidden (view full) --- 1038system.cpu1.dcache.overall_mshr_miss_latency::total 917455000 # number of overall MSHR miss cycles 1039system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11413500 # number of ReadReq MSHR uncacheable cycles 1040system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11413500 # number of ReadReq MSHR uncacheable cycles 1041system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles 1042system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles 1043system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles 1044system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles 1045system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses | 1140system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1141system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1142system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1143system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1144system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1145system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1146system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1147system.cpu1.dcache.cache_copies 0 # number of cache copies performed --- 25 unchanged lines hidden (view full) --- 1173system.cpu1.dcache.overall_mshr_miss_latency::total 917455000 # number of overall MSHR miss cycles 1174system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11413500 # number of ReadReq MSHR uncacheable cycles 1175system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11413500 # number of ReadReq MSHR uncacheable cycles 1176system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles 1177system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles 1178system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles 1179system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles 1180system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses |
| 1181system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035676 # mshr miss rate for ReadReq accesses |
|
| 1046system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses | 1182system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses |
| 1183system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032042 # mshr miss rate for WriteReq accesses |
|
| 1047system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses | 1184system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses |
| 1185system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.076923 # mshr miss rate for LoadLockedReq accesses |
|
| 1048system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses | 1186system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses |
| 1187system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.041975 # mshr miss rate for StoreCondReq accesses |
|
| 1049system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses | 1188system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses |
| 1189system.cpu1.dcache.demand_mshr_miss_rate::total 0.034296 # mshr miss rate for demand accesses |
|
| 1050system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses | 1190system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses |
| 1191system.cpu1.dcache.overall_mshr_miss_rate::total 0.034296 # mshr miss rate for overall accesses |
|
| 1051system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency | 1192system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency |
| 1193system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11368.577048 # average ReadReq mshr miss latency |
|
| 1052system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency | 1194system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency |
| 1195system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24265.853778 # average WriteReq mshr miss latency |
|
| 1053system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency | 1196system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency |
| 1197system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10318.737271 # average LoadLockedReq mshr miss latency |
|
| 1054system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency | 1198system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency |
| 1199system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9704.950495 # average StoreCondReq mshr miss latency |
|
| 1055system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency | 1200system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency |
| 1201system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency |
|
| 1056system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency | 1202system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency |
| 1203system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15946.310008 # average overall mshr miss latency |
|
| 1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency | 1204system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency |
| 1205system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 1058system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency | 1206system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency |
| 1207system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 1059system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency | 1208system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency |
| 1209system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 1060system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1061 1062---------- End Simulation Statistics ---------- | 1210system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1211 1212---------- End Simulation Statistics ---------- |