| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.958647 # Number of seconds simulated 4sim_ticks 1958647095000 # Number of ticks simulated 5final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.958647 # Number of seconds simulated 4sim_ticks 1958647095000 # Number of ticks simulated 5final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1989502 # Simulator instruction rate (inst/s) 8host_op_rate 1989500 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 65650485361 # Simulator tick rate (ticks/s) 10host_mem_usage 290388 # Number of bytes of host memory used 11host_seconds 29.83 # Real time elapsed on the host | 7host_inst_rate 669282 # Simulator instruction rate (inst/s) 8host_op_rate 669282 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22085281308 # Simulator tick rate (ticks/s) 10host_mem_usage 295084 # Number of bytes of host memory used 11host_seconds 88.69 # Real time elapsed on the host |
| 12sim_insts 59355643 # Number of instructions simulated 13sim_ops 59355643 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30050624 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10333120 # Number of bytes written to this memory 17system.physmem.num_reads 469541 # Number of read requests responded to by this memory 18system.physmem.num_writes 161455 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 153 unchanged lines hidden (view full) --- 173system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency 174system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency 175system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency 176system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency 177system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 179system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 180system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 59355643 # Number of instructions simulated 13sim_ops 59355643 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30050624 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10333120 # Number of bytes written to this memory 17system.physmem.num_reads 469541 # Number of read requests responded to by this memory 18system.physmem.num_writes 161455 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 153 unchanged lines hidden (view full) --- 173system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency 174system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency 175system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency 176system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency 177system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 179system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 180system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 181system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 182system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 181system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 182system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 183system.l2c.fast_writes 0 # number of fast writes performed 184system.l2c.cache_copies 0 # number of cache copies performed 185system.l2c.writebacks::writebacks 119935 # number of writebacks 186system.l2c.writebacks::total 119935 # number of writebacks 187system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 188system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 189system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 190system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits --- 140 unchanged lines hidden (view full) --- 331system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency 332system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency 333system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency 334system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked 335system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 336system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked 337system.iocache.blocked::no_targets 0 # number of cycles access was blocked 338system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked | 183system.l2c.fast_writes 0 # number of fast writes performed 184system.l2c.cache_copies 0 # number of cache copies performed 185system.l2c.writebacks::writebacks 119935 # number of writebacks 186system.l2c.writebacks::total 119935 # number of writebacks 187system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits 188system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 189system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 190system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits --- 140 unchanged lines hidden (view full) --- 331system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency 332system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency 333system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency 334system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked 335system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 336system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked 337system.iocache.blocked::no_targets 0 # number of cycles access was blocked 338system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # average number of cycles each access was blocked |
| 339system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 339system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 340system.iocache.fast_writes 0 # number of fast writes performed 341system.iocache.cache_copies 0 # number of cache copies performed 342system.iocache.writebacks::writebacks 41520 # number of writebacks 343system.iocache.writebacks::total 41520 # number of writebacks 344system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 345system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 346system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 347system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses --- 161 unchanged lines hidden (view full) --- 509system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches 510system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 511system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 512system.cpu0.kern.mode_good::kernel 1283 513system.cpu0.kern.mode_good::user 1283 514system.cpu0.kern.mode_good::idle 0 515system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches 516system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 340system.iocache.fast_writes 0 # number of fast writes performed 341system.iocache.cache_copies 0 # number of cache copies performed 342system.iocache.writebacks::writebacks 41520 # number of writebacks 343system.iocache.writebacks::total 41520 # number of writebacks 344system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 345system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 346system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 347system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses --- 161 unchanged lines hidden (view full) --- 509system.cpu0.kern.mode_switch::kernel 7302 # number of protection mode switches 510system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 511system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 512system.cpu0.kern.mode_good::kernel 1283 513system.cpu0.kern.mode_good::user 1283 514system.cpu0.kern.mode_good::idle 0 515system.cpu0.kern.mode_switch_good::kernel 0.175705 # fraction of useful protection mode switches 516system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 517system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches 518system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches | 517system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 518system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches |
| 519system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode 520system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode 521system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 522system.cpu0.kern.swap_context 3895 # number of times the context was actually changed 523system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 524system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 525system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 526system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 527system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU | 519system.cpu0.kern.mode_ticks::kernel 1954355762000 99.83% 99.83% # number of ticks spent at the given mode 520system.cpu0.kern.mode_ticks::user 3390072000 0.17% 100.00% # number of ticks spent at the given mode 521system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 522system.cpu0.kern.swap_context 3895 # number of times the context was actually changed 523system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 524system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 525system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 526system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 527system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| 528system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post | 528system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post |
| 529system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 530system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU | 529system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 530system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| 531system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post | 531system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post |
| 532system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 533system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU | 532system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 533system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| 534system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post | 534system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post |
| 535system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 536system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU | 535system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 536system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| 537system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post | 537system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post |
| 538system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 539system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU | 538system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 539system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| 540system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post | 540system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post |
| 541system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 542system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU | 541system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 542system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| 543system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post | 543system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post |
| 544system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 545system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU | 544system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 545system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| 546system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post | 546system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post |
| 547system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 548system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU | 547system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 548system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| 549system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post | 549system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post |
| 550system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR | 550system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| 551system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post | 551system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post |
| 552system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 553system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 554system.cpu0.icache.replacements 915147 # number of replacements 555system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use 556system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks. 557system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks. 558system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks. 559system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit. --- 29 unchanged lines hidden (view full) --- 589system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses 590system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency 591system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency 592system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency 593system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 594system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 595system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 596system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 552system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 553system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 554system.cpu0.icache.replacements 915147 # number of replacements 555system.cpu0.icache.tagsinuse 508.800486 # Cycle average of tags in use 556system.cpu0.icache.total_refs 53165471 # Total number of references to valid blocks. 557system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks. 558system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks. 559system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit. --- 29 unchanged lines hidden (view full) --- 589system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses 590system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency 591system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency 592system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency 593system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 594system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 595system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 596system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 597system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 598system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 597system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 598system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 599system.cpu0.icache.fast_writes 0 # number of fast writes performed 600system.cpu0.icache.cache_copies 0 # number of cache copies performed 601system.cpu0.icache.writebacks::writebacks 55 # number of writebacks 602system.cpu0.icache.writebacks::total 55 # number of writebacks 603system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915781 # number of ReadReq MSHR misses 604system.cpu0.icache.ReadReq_mshr_misses::total 915781 # number of ReadReq MSHR misses 605system.cpu0.icache.demand_mshr_misses::cpu0.inst 915781 # number of demand (read+write) MSHR misses 606system.cpu0.icache.demand_mshr_misses::total 915781 # number of demand (read+write) MSHR misses --- 80 unchanged lines hidden (view full) --- 687system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency 688system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency 689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency 690system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency 691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 599system.cpu0.icache.fast_writes 0 # number of fast writes performed 600system.cpu0.icache.cache_copies 0 # number of cache copies performed 601system.cpu0.icache.writebacks::writebacks 55 # number of writebacks 602system.cpu0.icache.writebacks::total 55 # number of writebacks 603system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915781 # number of ReadReq MSHR misses 604system.cpu0.icache.ReadReq_mshr_misses::total 915781 # number of ReadReq MSHR misses 605system.cpu0.icache.demand_mshr_misses::cpu0.inst 915781 # number of demand (read+write) MSHR misses 606system.cpu0.icache.demand_mshr_misses::total 915781 # number of demand (read+write) MSHR misses --- 80 unchanged lines hidden (view full) --- 687system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency 688system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency 689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency 690system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency 691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 695system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 696system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 697system.cpu0.dcache.fast_writes 0 # number of fast writes performed 698system.cpu0.dcache.cache_copies 0 # number of cache copies performed 699system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks 700system.cpu0.dcache.writebacks::total 786441 # number of writebacks 701system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036101 # number of ReadReq MSHR misses 702system.cpu0.dcache.ReadReq_mshr_misses::total 1036101 # number of ReadReq MSHR misses 703system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291536 # number of WriteReq MSHR misses 704system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses --- 198 unchanged lines hidden (view full) --- 903system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses 904system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency 905system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency 906system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency 907system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 908system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 909system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 910system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 697system.cpu0.dcache.fast_writes 0 # number of fast writes performed 698system.cpu0.dcache.cache_copies 0 # number of cache copies performed 699system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks 700system.cpu0.dcache.writebacks::total 786441 # number of writebacks 701system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036101 # number of ReadReq MSHR misses 702system.cpu0.dcache.ReadReq_mshr_misses::total 1036101 # number of ReadReq MSHR misses 703system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291536 # number of WriteReq MSHR misses 704system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses --- 198 unchanged lines hidden (view full) --- 903system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses 904system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency 905system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency 906system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency 907system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 908system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 909system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 910system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 911system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 912system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 911system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 912system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 913system.cpu1.icache.fast_writes 0 # number of fast writes performed 914system.cpu1.icache.cache_copies 0 # number of cache copies performed 915system.cpu1.icache.writebacks::writebacks 14 # number of writebacks 916system.cpu1.icache.writebacks::total 14 # number of writebacks 917system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87005 # number of ReadReq MSHR misses 918system.cpu1.icache.ReadReq_mshr_misses::total 87005 # number of ReadReq MSHR misses 919system.cpu1.icache.demand_mshr_misses::cpu1.inst 87005 # number of demand (read+write) MSHR misses 920system.cpu1.icache.demand_mshr_misses::total 87005 # number of demand (read+write) MSHR misses --- 80 unchanged lines hidden (view full) --- 1001system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency 1002system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency 1003system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency 1004system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency 1005system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1006system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1007system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1008system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 913system.cpu1.icache.fast_writes 0 # number of fast writes performed 914system.cpu1.icache.cache_copies 0 # number of cache copies performed 915system.cpu1.icache.writebacks::writebacks 14 # number of writebacks 916system.cpu1.icache.writebacks::total 14 # number of writebacks 917system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87005 # number of ReadReq MSHR misses 918system.cpu1.icache.ReadReq_mshr_misses::total 87005 # number of ReadReq MSHR misses 919system.cpu1.icache.demand_mshr_misses::cpu1.inst 87005 # number of demand (read+write) MSHR misses 920system.cpu1.icache.demand_mshr_misses::total 87005 # number of demand (read+write) MSHR misses --- 80 unchanged lines hidden (view full) --- 1001system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency 1002system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency 1003system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency 1004system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency 1005system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1006system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1007system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1008system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1009system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1010system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 1009system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1010system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1011system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1012system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1013system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks 1014system.cpu1.dcache.writebacks::total 29784 # number of writebacks 1015system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses 1016system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses 1017system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses 1018system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses --- 44 unchanged lines hidden --- | 1011system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1012system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1013system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks 1014system.cpu1.dcache.writebacks::total 29784 # number of writebacks 1015system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses 1016system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses 1017system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses 1018system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses --- 44 unchanged lines hidden --- |