Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.966742 # Number of seconds simulated

4sim_ticks 1966741627000 # Number of ticks simulated
5final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 1966742176000 # Number of ticks simulated
5final_tick 1966742176000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1661877 # Simulator instruction rate (inst/s)
8host_op_rate 1661877 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 53617278530 # Simulator tick rate (ticks/s)
10host_mem_usage 335968 # Number of bytes of host memory used
11host_seconds 36.68 # Real time elapsed on the host
12sim_insts 60959478 # Number of instructions simulated
13sim_ops 60959478 # Number of ops (including micro ops) simulated

7host_inst_rate 1742915 # Simulator instruction rate (inst/s)
8host_op_rate 1742915 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 56229643103 # Simulator tick rate (ticks/s)
10host_mem_usage 335876 # Number of bytes of host memory used
11host_seconds 34.98 # Real time elapsed on the host
12sim_insts 60961842 # Number of instructions simulated
13sim_ops 60961842 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.inst 796800 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 24828736 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 62272 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 430784 # Number of bytes read from this memory

21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory

22system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory
26system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory
27system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory
28system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory

22system.physmem.bytes_read::total 26119552 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 796800 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 62272 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::total 859072 # Number of instructions bytes read from this memory
26system.physmem.bytes_written::writebacks 7774400 # Number of bytes written to this memory
27system.physmem.bytes_written::total 7774400 # Number of bytes written to this memory
28system.physmem.num_reads::cpu0.inst 12450 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 387949 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 973 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 6731 # Number of read requests responded to by this memory

32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory

33system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s)

33system.physmem.num_reads::total 408118 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 121475 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 121475 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu0.inst 405137 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu0.data 12624296 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.inst 31663 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.data 219034 # Total read bandwidth from this memory (bytes/s)

40system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s)

41system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s)

41system.physmem.bw_read::total 13280618 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu0.inst 405137 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu1.inst 31663 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 436800 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_write::writebacks 3952933 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 3952933 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 3952933 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.inst 405137 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu0.data 12624296 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.inst 31663 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu1.data 219034 # Total bandwidth to/from this memory (bytes/s)

52system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s)

53system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 408131 # Number of read requests accepted
55system.physmem.writeReqs 121489 # Number of write requests accepted
56system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM

53system.physmem.bw_total::total 17233551 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 408118 # Number of read requests accepted
55system.physmem.writeReqs 121475 # Number of write requests accepted
56system.physmem.readBursts 408118 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 121475 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 26112384 # Total number of bytes read from DRAM

59system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue

60system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side

60system.physmem.bytesWritten 7772672 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 26119552 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 7774400 # Total written bytes from the system interface side

63system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 25299 # Per bank write bursts
67system.physmem.perBankRdBursts::1 25599 # Per bank write bursts
68system.physmem.perBankRdBursts::2 25910 # Per bank write bursts
69system.physmem.perBankRdBursts::3 25657 # Per bank write bursts
70system.physmem.perBankRdBursts::4 25586 # Per bank write bursts
71system.physmem.perBankRdBursts::5 25177 # Per bank write bursts
72system.physmem.perBankRdBursts::6 26012 # Per bank write bursts
73system.physmem.perBankRdBursts::7 25110 # Per bank write bursts
74system.physmem.perBankRdBursts::8 25002 # Per bank write bursts
75system.physmem.perBankRdBursts::9 25326 # Per bank write bursts

76system.physmem.perBankRdBursts::10 25348 # Per bank write bursts

76system.physmem.perBankRdBursts::10 25349 # Per bank write bursts

77system.physmem.perBankRdBursts::11 25350 # Per bank write bursts

78system.physmem.perBankRdBursts::12 25736 # Per bank write bursts
79system.physmem.perBankRdBursts::13 25396 # Per bank write bursts

78system.physmem.perBankRdBursts::12 25737 # Per bank write bursts
79system.physmem.perBankRdBursts::13 25386 # Per bank write bursts

80system.physmem.perBankRdBursts::14 25673 # Per bank write bursts

81system.physmem.perBankRdBursts::15 25838 # Per bank write bursts

81system.physmem.perBankRdBursts::15 25833 # Per bank write bursts

82system.physmem.perBankWrBursts::0 7888 # Per bank write bursts
83system.physmem.perBankWrBursts::1 7973 # Per bank write bursts
84system.physmem.perBankWrBursts::2 7891 # Per bank write bursts
85system.physmem.perBankWrBursts::3 7697 # Per bank write bursts
86system.physmem.perBankWrBursts::4 7528 # Per bank write bursts
87system.physmem.perBankWrBursts::5 7375 # Per bank write bursts
88system.physmem.perBankWrBursts::6 8079 # Per bank write bursts
89system.physmem.perBankWrBursts::7 7030 # Per bank write bursts
90system.physmem.perBankWrBursts::8 7056 # Per bank write bursts
91system.physmem.perBankWrBursts::9 7058 # Per bank write bursts

92system.physmem.perBankWrBursts::10 7243 # Per bank write bursts

92system.physmem.perBankWrBursts::10 7244 # Per bank write bursts

93system.physmem.perBankWrBursts::11 7671 # Per bank write bursts
94system.physmem.perBankWrBursts::12 7657 # Per bank write bursts

95system.physmem.perBankWrBursts::13 7555 # Per bank write bursts

95system.physmem.perBankWrBursts::13 7545 # Per bank write bursts

96system.physmem.perBankWrBursts::14 7813 # Per bank write bursts

97system.physmem.perBankWrBursts::15 7948 # Per bank write bursts

97system.physmem.perBankWrBursts::15 7943 # Per bank write bursts

98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 71 # Number of times write queue was full causing retry

100system.physmem.totGap 1966734334500 # Total gap between requests

100system.physmem.totGap 1966734882500 # Total gap between requests

101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 0 # Read request sizes (log2)
104system.physmem.readPktSize::3 0 # Read request sizes (log2)
105system.physmem.readPktSize::4 0 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)

107system.physmem.readPktSize::6 408131 # Read request sizes (log2)

107system.physmem.readPktSize::6 408118 # Read request sizes (log2)

108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 0 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)

114system.physmem.writePktSize::6 121489 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see

114system.physmem.writePktSize::6 121475 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 407913 # What read queue length does an incoming req see

116system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see

--- 30 unchanged lines hidden (view full) ---

154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see

162system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see

162system.physmem.wrQLenPdf::15 1645 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 2764 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 5834 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 6413 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 7349 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 8420 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 6966 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 7388 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 8059 # What write queue length does an incoming req see

173system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see

174system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see

174system.physmem.wrQLenPdf::27 6925 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 7056 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 6260 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 6183 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 5977 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 5774 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 413 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 397 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 235 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 266 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 267 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 294 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 293 # What write queue length does an incoming req see

190system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see

191system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see

191system.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 316 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 305 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 291 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see

198system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see

199system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see

199system.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 236 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 336 # What write queue length does an incoming req see

204system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see

205system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes

205system.physmem.wrQLenPdf::58 197 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 197 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 123 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 65997 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 513.433277 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 309.806046 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 413.661980 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 15519 23.51% 23.51% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 12333 18.69% 42.20% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 4691 7.11% 49.31% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3281 4.97% 54.28% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 3296 4.99% 59.28% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 1531 2.32% 61.60% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1650 2.50% 64.10% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1071 1.62% 65.72% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 22625 34.28% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 65997 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 5403 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 75.512863 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 2871.806103 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-8191 5400 99.94% 99.94% # Reads before turning the bus around for writes

229system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes

232system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes
233system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads

232system.physmem.rdPerTurnAround::total 5403 # Reads before turning the bus around for writes
233system.physmem.wrPerTurnAround::samples 5403 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::mean 22.477883 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::gmean 18.790649 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::stdev 24.259878 # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::16-23 4886 90.43% 90.43% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::24-31 27 0.50% 90.93% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-39 174 3.22% 94.15% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::40-47 7 0.13% 94.28% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::48-55 5 0.09% 94.37% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::56-63 18 0.33% 94.71% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::64-71 10 0.19% 94.89% # Writes before turning the bus around for reads

244system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads

245system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads

245system.physmem.wrPerTurnAround::80-87 26 0.48% 95.41% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::88-95 6 0.11% 95.52% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::96-103 152 2.81% 98.33% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::104-111 23 0.43% 98.76% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::112-119 4 0.07% 98.83% # Writes before turning the bus around for reads

250system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads

256system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads

256system.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::176-183 7 0.13% 99.35% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::184-191 10 0.19% 99.54% # Writes before turning the bus around for reads

259system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads

260system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads

260system.physmem.wrPerTurnAround::200-207 3 0.06% 99.72% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::216-223 6 0.11% 99.85% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::224-231 4 0.07% 99.93% # Writes before turning the bus around for reads

264system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads

267system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads
268system.physmem.totQLat 6252046750 # Total ticks spent queuing
269system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM
270system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers
271system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst

267system.physmem.wrPerTurnAround::total 5403 # Writes before turning the bus around for reads
268system.physmem.totQLat 6253232750 # Total ticks spent queuing
269system.physmem.totMemAccLat 13903345250 # Total ticks spent from burst creation until serviced by the DRAM
270system.physmem.totBusLat 2040030000 # Total ticks spent in databus transfers
271system.physmem.avgQLat 15326.33 # Average queueing delay per DRAM burst

272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

273system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst

273system.physmem.avgMemAccLat 34076.33 # Average memory access latency per DRAM burst

274system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s
275system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s
276system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s
277system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s
278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
279system.physmem.busUtil 0.13 # Data bus utilization in percentage
280system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
282system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing

283system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing
284system.physmem.readRowHits 365911 # Number of row buffer hits during reads

283system.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing
284system.physmem.readRowHits 365871 # Number of row buffer hits during reads

285system.physmem.writeRowHits 97586 # Number of row buffer hits during writes

286system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads
287system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes
288system.physmem.avgGap 3713482.00 # Average gap between requests

286system.physmem.readRowHitRate 89.67 # Row buffer hit rate for reads
287system.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes
288system.physmem.avgGap 3713672.35 # Average gap between requests

289system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined

290system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ)
291system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ)

290system.physmem_0.actEnergy 236455380 # Energy for activate commands per rank (pJ)
291system.physmem_0.preEnergy 125679015 # Energy for precharge commands per rank (pJ)

292system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ)
293system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ)

294system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ)
295system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ)
296system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ)
297system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ)
298system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ)
299system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ)
300system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ)
301system.physmem_0.averagePower 250.237247 # Core power per rank (mW)
302system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank
303system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states
304system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states
305system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states
306system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states
307system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states
308system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states
309system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ)
310system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ)
311system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ)
312system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ)
313system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ)
314system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ)
315system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ)
316system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ)
317system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ)
318system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ)
319system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ)
320system.physmem_1.averagePower 250.444709 # Core power per rank (mW)
321system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank
322system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states
323system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states
324system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states
325system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states
326system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states
327system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states
328system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
329system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states

294system.physmem_0.refreshEnergy 5647926960.000001 # Energy for refresh commands per rank (pJ)
295system.physmem_0.actBackEnergy 5154923820 # Energy for active background per rank (pJ)
296system.physmem_0.preBackEnergy 376838880 # Energy for precharge background per rank (pJ)
297system.physmem_0.actPowerDownEnergy 13418648160 # Energy for active power-down per rank (pJ)
298system.physmem_0.prePowerDownEnergy 6443555040 # Energy for precharge power-down per rank (pJ)
299system.physmem_0.selfRefreshEnergy 458974810065 # Energy for self refresh per rank (pJ)
300system.physmem_0.totalEnergy 492161345970 # Total energy per rank (pJ)
301system.physmem_0.averagePower 250.241923 # Core power per rank (mW)
302system.physmem_0.totalIdleTime 1954449369000 # Total Idle time Per DRAM Rank
303system.physmem_0.memoryStateTime::IDLE 631981750 # Time in different power states
304system.physmem_0.memoryStateTime::REF 2402382000 # Time in different power states
305system.physmem_0.memoryStateTime::SREF 1908243357500 # Time in different power states
306system.physmem_0.memoryStateTime::PRE_PDN 16780134250 # Time in different power states
307system.physmem_0.memoryStateTime::ACT 9257305750 # Time in different power states
308system.physmem_0.memoryStateTime::ACT_PDN 29427014750 # Time in different power states
309system.physmem_1.actEnergy 234763200 # Energy for activate commands per rank (pJ)
310system.physmem_1.preEnergy 124779600 # Energy for precharge commands per rank (pJ)
311system.physmem_1.readEnergy 1454103840 # Energy for read commands per rank (pJ)
312system.physmem_1.writeEnergy 313132140 # Energy for write commands per rank (pJ)
313system.physmem_1.refreshEnergy 5778230640.000001 # Energy for refresh commands per rank (pJ)
314system.physmem_1.actBackEnergy 5151828720 # Energy for active background per rank (pJ)
315system.physmem_1.preBackEnergy 364649760 # Energy for precharge background per rank (pJ)
316system.physmem_1.actPowerDownEnergy 13829543490 # Energy for active power-down per rank (pJ)
317system.physmem_1.prePowerDownEnergy 6726228480 # Energy for precharge power-down per rank (pJ)
318system.physmem_1.selfRefreshEnergy 458595076560 # Energy for self refresh per rank (pJ)
319system.physmem_1.totalEnergy 492575015880 # Total energy per rank (pJ)
320system.physmem_1.averagePower 250.452256 # Core power per rank (mW)
321system.physmem_1.totalIdleTime 1954420956750 # Total Idle time Per DRAM Rank
322system.physmem_1.memoryStateTime::IDLE 598934250 # Time in different power states
323system.physmem_1.memoryStateTime::REF 2457676000 # Time in different power states
324system.physmem_1.memoryStateTime::SREF 1906644575500 # Time in different power states
325system.physmem_1.memoryStateTime::PRE_PDN 17516296750 # Time in different power states
326system.physmem_1.memoryStateTime::ACT 9196775500 # Time in different power states
327system.physmem_1.memoryStateTime::ACT_PDN 30327918000 # Time in different power states
328system.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
329system.bridge.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states

330system.cpu_clk_domain.clock 500 # Clock period in ticks
331system.cpu0.dtb.fetch_hits 0 # ITB hits
332system.cpu0.dtb.fetch_misses 0 # ITB misses
333system.cpu0.dtb.fetch_acv 0 # ITB acv
334system.cpu0.dtb.fetch_accesses 0 # ITB accesses

335system.cpu0.dtb.read_hits 7479115 # DTB read hits

335system.cpu0.dtb.read_hits 7479524 # DTB read hits

336system.cpu0.dtb.read_misses 7764 # DTB read misses
337system.cpu0.dtb.read_acv 210 # DTB read access violations
338system.cpu0.dtb.read_accesses 524068 # DTB read accesses

339system.cpu0.dtb.write_hits 5079820 # DTB write hits

339system.cpu0.dtb.write_hits 5079926 # DTB write hits

340system.cpu0.dtb.write_misses 909 # DTB write misses
341system.cpu0.dtb.write_acv 133 # DTB write access violations
342system.cpu0.dtb.write_accesses 202594 # DTB write accesses

343system.cpu0.dtb.data_hits 12558935 # DTB hits

343system.cpu0.dtb.data_hits 12559450 # DTB hits

344system.cpu0.dtb.data_misses 8673 # DTB misses
345system.cpu0.dtb.data_acv 343 # DTB access violations
346system.cpu0.dtb.data_accesses 726662 # DTB accesses

347system.cpu0.itb.fetch_hits 3638634 # ITB hits

347system.cpu0.itb.fetch_hits 3638587 # ITB hits

348system.cpu0.itb.fetch_misses 3984 # ITB misses
349system.cpu0.itb.fetch_acv 184 # ITB acv

350system.cpu0.itb.fetch_accesses 3642618 # ITB accesses

350system.cpu0.itb.fetch_accesses 3642571 # ITB accesses

351system.cpu0.itb.read_hits 0 # DTB read hits
352system.cpu0.itb.read_misses 0 # DTB read misses
353system.cpu0.itb.read_acv 0 # DTB read access violations
354system.cpu0.itb.read_accesses 0 # DTB read accesses
355system.cpu0.itb.write_hits 0 # DTB write hits
356system.cpu0.itb.write_misses 0 # DTB write misses
357system.cpu0.itb.write_acv 0 # DTB write access violations
358system.cpu0.itb.write_accesses 0 # DTB write accesses
359system.cpu0.itb.data_hits 0 # DTB hits
360system.cpu0.itb.data_misses 0 # DTB misses
361system.cpu0.itb.data_acv 0 # DTB access violations
362system.cpu0.itb.data_accesses 0 # DTB accesses

363system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions
364system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state
365system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state
366system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state
367system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state
368system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state

363system.cpu0.numPwrStateTransitions 13586 # Number of power state transitions
364system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state
365system.cpu0.pwrStateClkGateDist::mean 272328046.518475 # Distribution of time spent in the clock gated state
366system.cpu0.pwrStateClkGateDist::stdev 432907003.390448 # Distribution of time spent in the clock gated state
367system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state
368system.cpu0.pwrStateClkGateDist::min_value 169000 # Distribution of time spent in the clock gated state

369system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state

370system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state
371system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states
372system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states
373system.cpu0.numCycles 3933483254 # number of cpu cycles simulated

370system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state
371system.cpu0.pwrStateResidencyTicks::ON 116817756000 # Cumulative time (in ticks) in various power states
372system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849924420000 # Cumulative time (in ticks) in various power states
373system.cpu0.numCycles 3933484352 # number of cpu cycles simulated

374system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
375system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
376system.cpu0.kern.inst.arm 0 # number of arm instructions executed

377system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
378system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed
379system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl

377system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed
378system.cpu0.kern.inst.hwrei 163848 # number of hwrei instructions executed
379system.cpu0.kern.ipl_count::0 56217 40.17% 40.17% # number of times we switched to this ipl

380system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl
381system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl
382system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl
383system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl

384system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl
385system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl

384system.cpu0.kern.ipl_count::total 139951 # number of times we switched to this ipl
385system.cpu0.kern.ipl_good::0 55705 49.07% 49.07% # number of times we switched to this ipl from a different ipl

386system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
387system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl
388system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl

389system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl
390system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl
391system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl
392system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl
393system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl
394system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl
395system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl
396system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl
397system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl

389system.cpu0.kern.ipl_good::31 55272 48.69% 100.00% # number of times we switched to this ipl from a different ipl
390system.cpu0.kern.ipl_good::total 113516 # number of times we switched to this ipl from a different ipl
391system.cpu0.kern.ipl_ticks::0 1903162232500 96.77% 96.77% # number of cycles we spent at this ipl
392system.cpu0.kern.ipl_ticks::21 93267000 0.00% 96.77% # number of cycles we spent at this ipl
393system.cpu0.kern.ipl_ticks::22 789745000 0.04% 96.81% # number of cycles we spent at this ipl
394system.cpu0.kern.ipl_ticks::30 321096500 0.02% 96.83% # number of cycles we spent at this ipl
395system.cpu0.kern.ipl_ticks::31 62375109000 3.17% 100.00% # number of cycles we spent at this ipl
396system.cpu0.kern.ipl_ticks::total 1966741450000 # number of cycles we spent at this ipl
397system.cpu0.kern.ipl_used::0 0.990892 # fraction of swpipl calls that actually changed the ipl

398system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
399system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
400system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl

401system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl
402system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl

401system.cpu0.kern.ipl_used::31 0.680732 # fraction of swpipl calls that actually changed the ipl
402system.cpu0.kern.ipl_used::total 0.811112 # fraction of swpipl calls that actually changed the ipl

403system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
404system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed
405system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed
406system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed
407system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed

408system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed

408system.cpu0.kern.callpal::swpctx 3063 2.07% 2.43% # number of callpals executed

409system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed
410system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed

411system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed

411system.cpu0.kern.callpal::swpipl 132999 89.79% 92.25% # number of callpals executed

412system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed
413system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed
414system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed
415system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed
416system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed
417system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed
418system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed
419system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed

420system.cpu0.kern.callpal::total 148125 # number of callpals executed
421system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches
422system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches

420system.cpu0.kern.callpal::total 148123 # number of callpals executed
421system.cpu0.kern.mode_switch::kernel 6987 # number of protection mode switches
422system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches

423system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches

424system.cpu0.kern.mode_good::kernel 1368
425system.cpu0.kern.mode_good::user 1369

424system.cpu0.kern.mode_good::kernel 1369
425system.cpu0.kern.mode_good::user 1370

426system.cpu0.kern.mode_good::idle 0

427system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches

427system.cpu0.kern.mode_switch_good::kernel 0.195935 # fraction of useful protection mode switches

428system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
429system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches

430system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches
431system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode
432system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode

430system.cpu0.kern.mode_switch_good::total 0.327749 # fraction of useful protection mode switches
431system.cpu0.kern.mode_ticks::kernel 1962822047500 99.80% 99.80% # number of ticks spent at the given mode
432system.cpu0.kern.mode_ticks::user 3919400500 0.20% 100.00% # number of ticks spent at the given mode

433system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode

434system.cpu0.kern.swap_context 3065 # number of times the context was actually changed
435system.cpu0.committedInsts 47690735 # Number of instructions committed
436system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed
437system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses
438system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses
439system.cpu0.num_func_calls 1190980 # number of times a function call or return occured
440system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls
441system.cpu0.num_int_insts 44243506 # number of integer instructions
442system.cpu0.num_fp_insts 210072 # number of float instructions
443system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read
444system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written
445system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read
446system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written
447system.cpu0.num_mem_refs 12599733 # number of memory refs
448system.cpu0.num_load_insts 7506744 # Number of load instructions
449system.cpu0.num_store_insts 5092989 # Number of store instructions
450system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles
451system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles
452system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles
453system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles
454system.cpu0.Branches 7182999 # Number of branches fetched
455system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction
456system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction
457system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction

434system.cpu0.kern.swap_context 3064 # number of times the context was actually changed
435system.cpu0.committedInsts 47693300 # Number of instructions committed
436system.cpu0.committedOps 47693300 # Number of ops (including micro ops) committed
437system.cpu0.num_int_alu_accesses 44245928 # Number of integer alu accesses
438system.cpu0.num_fp_alu_accesses 210005 # Number of float alu accesses
439system.cpu0.num_func_calls 1191022 # number of times a function call or return occured
440system.cpu0.num_conditional_control_insts 5607802 # number of instructions that are conditional controls
441system.cpu0.num_int_insts 44245928 # number of integer instructions
442system.cpu0.num_fp_insts 210005 # number of float instructions
443system.cpu0.num_int_register_reads 60860766 # number of times the integer registers were read
444system.cpu0.num_int_register_writes 32957591 # number of times the integer registers were written
445system.cpu0.num_fp_register_reads 102620 # number of times the floating registers were read
446system.cpu0.num_fp_register_writes 104398 # number of times the floating registers were written
447system.cpu0.num_mem_refs 12600240 # number of memory refs
448system.cpu0.num_load_insts 7507148 # Number of load instructions
449system.cpu0.num_store_insts 5093092 # Number of store instructions
450system.cpu0.num_idle_cycles 3699848839.998118 # Number of idle cycles
451system.cpu0.num_busy_cycles 233635512.001881 # Number of busy cycles
452system.cpu0.not_idle_fraction 0.059397 # Percentage of non-idle cycles
453system.cpu0.idle_fraction 0.940603 # Percentage of idle cycles
454system.cpu0.Branches 7183589 # Number of branches fetched
455system.cpu0.op_class::No_OpClass 2715591 5.69% 5.69% # Class of executed instruction
456system.cpu0.op_class::IntAlu 31389831 65.80% 71.50% # Class of executed instruction
457system.cpu0.op_class::IntMult 52060 0.11% 71.61% # Class of executed instruction

458system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction

459system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction

459system.cpu0.op_class::FloatAdd 26674 0.06% 71.66% # Class of executed instruction

460system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction
461system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction
462system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction
463system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction

464system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction
465system.cpu0.op_class::FloatMisc 0 0.00% 71.66% # Class of executed instruction
466system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction
467system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction
468system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction
469system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction
470system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction
471system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction
472system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction
473system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction
474system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction
475system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction
476system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction
477system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction
478system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction
479system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction
480system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction
481system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction
482system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction
483system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction
484system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction
485system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction
486system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction
487system.cpu0.op_class::MemRead 7588274 15.91% 87.57% # Class of executed instruction
488system.cpu0.op_class::MemWrite 5010180 10.50% 98.08% # Class of executed instruction
489system.cpu0.op_class::FloatMemRead 92589 0.19% 98.27% # Class of executed instruction
490system.cpu0.op_class::FloatMemWrite 88924 0.19% 98.46% # Class of executed instruction
491system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction

464system.cpu0.op_class::FloatDiv 1883 0.00% 71.67% # Class of executed instruction
465system.cpu0.op_class::FloatMisc 0 0.00% 71.67% # Class of executed instruction
466system.cpu0.op_class::FloatSqrt 0 0.00% 71.67% # Class of executed instruction
467system.cpu0.op_class::SimdAdd 0 0.00% 71.67% # Class of executed instruction
468system.cpu0.op_class::SimdAddAcc 0 0.00% 71.67% # Class of executed instruction
469system.cpu0.op_class::SimdAlu 0 0.00% 71.67% # Class of executed instruction
470system.cpu0.op_class::SimdCmp 0 0.00% 71.67% # Class of executed instruction
471system.cpu0.op_class::SimdCvt 0 0.00% 71.67% # Class of executed instruction
472system.cpu0.op_class::SimdMisc 0 0.00% 71.67% # Class of executed instruction
473system.cpu0.op_class::SimdMult 0 0.00% 71.67% # Class of executed instruction
474system.cpu0.op_class::SimdMultAcc 0 0.00% 71.67% # Class of executed instruction
475system.cpu0.op_class::SimdShift 0 0.00% 71.67% # Class of executed instruction
476system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.67% # Class of executed instruction
477system.cpu0.op_class::SimdSqrt 0 0.00% 71.67% # Class of executed instruction
478system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.67% # Class of executed instruction
479system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.67% # Class of executed instruction
480system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.67% # Class of executed instruction
481system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.67% # Class of executed instruction
482system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.67% # Class of executed instruction
483system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.67% # Class of executed instruction
484system.cpu0.op_class::SimdFloatMult 0 0.00% 71.67% # Class of executed instruction
485system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.67% # Class of executed instruction
486system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.67% # Class of executed instruction
487system.cpu0.op_class::MemRead 7588720 15.91% 87.57% # Class of executed instruction
488system.cpu0.op_class::MemWrite 5010315 10.50% 98.08% # Class of executed instruction
489system.cpu0.op_class::FloatMemRead 92556 0.19% 98.27% # Class of executed instruction
490system.cpu0.op_class::FloatMemWrite 88892 0.19% 98.46% # Class of executed instruction
491system.cpu0.op_class::IprAccess 735794 1.54% 100.00% # Class of executed instruction

492system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction

493system.cpu0.op_class::total 47699751 # Class of executed instruction
494system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
495system.cpu0.dcache.tags.replacements 1183172 # number of replacements
496system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use
497system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks.
498system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks.
499system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks.

493system.cpu0.op_class::total 47702316 # Class of executed instruction
494system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
495system.cpu0.dcache.tags.replacements 1183155 # number of replacements
496system.cpu0.dcache.tags.tagsinuse 505.237754 # Cycle average of tags in use
497system.cpu0.dcache.tags.total_refs 11370167 # Total number of references to valid blocks.
498system.cpu0.dcache.tags.sampled_refs 1183667 # Sample count of references to valid blocks.
499system.cpu0.dcache.tags.avg_refs 9.605883 # Average number of references to valid blocks.

500system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit.

501system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor
502system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy
503system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy

501system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.237754 # Average occupied blocks per requestor
502system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986792 # Average percentage of cache occupancy
503system.cpu0.dcache.tags.occ_percent::total 0.986792 # Average percentage of cache occupancy

504system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
505system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
506system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
507system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
508system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

509system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses
510system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses
511system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
512system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits
513system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits
514system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits
515system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits

509system.cpu0.dcache.tags.tag_accesses 51474763 # Number of tag accesses
510system.cpu0.dcache.tags.data_accesses 51474763 # Number of data accesses
511system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
512system.cpu0.dcache.ReadReq_hits::cpu0.data 6401125 # number of ReadReq hits
513system.cpu0.dcache.ReadReq_hits::total 6401125 # number of ReadReq hits
514system.cpu0.dcache.WriteReq_hits::cpu0.data 4669512 # number of WriteReq hits
515system.cpu0.dcache.WriteReq_hits::total 4669512 # number of WriteReq hits

516system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits
517system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits

518system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits
519system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits
520system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits
521system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits
522system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits
523system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits
524system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses
525system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses
526system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses
527system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses
528system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses
529system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses

518system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146310 # number of StoreCondReq hits
519system.cpu0.dcache.StoreCondReq_hits::total 146310 # number of StoreCondReq hits
520system.cpu0.dcache.demand_hits::cpu0.data 11070637 # number of demand (read+write) hits
521system.cpu0.dcache.demand_hits::total 11070637 # number of demand (read+write) hits
522system.cpu0.dcache.overall_hits::cpu0.data 11070637 # number of overall hits
523system.cpu0.dcache.overall_hits::total 11070637 # number of overall hits
524system.cpu0.dcache.ReadReq_misses::cpu0.data 938392 # number of ReadReq misses
525system.cpu0.dcache.ReadReq_misses::total 938392 # number of ReadReq misses
526system.cpu0.dcache.WriteReq_misses::cpu0.data 255335 # number of WriteReq misses
527system.cpu0.dcache.WriteReq_misses::total 255335 # number of WriteReq misses
528system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13590 # number of LoadLockedReq misses
529system.cpu0.dcache.LoadLockedReq_misses::total 13590 # number of LoadLockedReq misses

530system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses
531system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses

532system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses
533system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses
534system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses
535system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses
536system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles
537system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles
538system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles
539system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles
540system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles
541system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles
542system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles
543system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles
544system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles
545system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles
546system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles
547system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles
548system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses)
549system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses)
550system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses)
551system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses)
552system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses)
553system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses)
554system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses)
555system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses)
556system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses
557system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses
558system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses
559system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses
560system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses
561system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses
562system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses
563system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses
564system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses
565system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses

532system.cpu0.dcache.demand_misses::cpu0.data 1193727 # number of demand (read+write) misses
533system.cpu0.dcache.demand_misses::total 1193727 # number of demand (read+write) misses
534system.cpu0.dcache.overall_misses::cpu0.data 1193727 # number of overall misses
535system.cpu0.dcache.overall_misses::total 1193727 # number of overall misses
536system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31214419000 # number of ReadReq miss cycles
537system.cpu0.dcache.ReadReq_miss_latency::total 31214419000 # number of ReadReq miss cycles
538system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12662507500 # number of WriteReq miss cycles
539system.cpu0.dcache.WriteReq_miss_latency::total 12662507500 # number of WriteReq miss cycles
540system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles
541system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles
542system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31952500 # number of StoreCondReq miss cycles
543system.cpu0.dcache.StoreCondReq_miss_latency::total 31952500 # number of StoreCondReq miss cycles
544system.cpu0.dcache.demand_miss_latency::cpu0.data 43876926500 # number of demand (read+write) miss cycles
545system.cpu0.dcache.demand_miss_latency::total 43876926500 # number of demand (read+write) miss cycles
546system.cpu0.dcache.overall_miss_latency::cpu0.data 43876926500 # number of overall miss cycles
547system.cpu0.dcache.overall_miss_latency::total 43876926500 # number of overall miss cycles
548system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339517 # number of ReadReq accesses(hits+misses)
549system.cpu0.dcache.ReadReq_accesses::total 7339517 # number of ReadReq accesses(hits+misses)
550system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924847 # number of WriteReq accesses(hits+misses)
551system.cpu0.dcache.WriteReq_accesses::total 4924847 # number of WriteReq accesses(hits+misses)
552system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152584 # number of LoadLockedReq accesses(hits+misses)
553system.cpu0.dcache.LoadLockedReq_accesses::total 152584 # number of LoadLockedReq accesses(hits+misses)
554system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152038 # number of StoreCondReq accesses(hits+misses)
555system.cpu0.dcache.StoreCondReq_accesses::total 152038 # number of StoreCondReq accesses(hits+misses)
556system.cpu0.dcache.demand_accesses::cpu0.data 12264364 # number of demand (read+write) accesses
557system.cpu0.dcache.demand_accesses::total 12264364 # number of demand (read+write) accesses
558system.cpu0.dcache.overall_accesses::cpu0.data 12264364 # number of overall (read+write) accesses
559system.cpu0.dcache.overall_accesses::total 12264364 # number of overall (read+write) accesses
560system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127855 # miss rate for ReadReq accesses
561system.cpu0.dcache.ReadReq_miss_rate::total 0.127855 # miss rate for ReadReq accesses
562system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051846 # miss rate for WriteReq accesses
563system.cpu0.dcache.WriteReq_miss_rate::total 0.051846 # miss rate for WriteReq accesses
564system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089066 # miss rate for LoadLockedReq accesses
565system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089066 # miss rate for LoadLockedReq accesses

566system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses
567system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses

568system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses
569system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses
570system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses
571system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses
572system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency
573system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency
574system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency
575system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency
576system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency
577system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency
578system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency
579system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency
580system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency
581system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency
582system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency
583system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency

568system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097333 # miss rate for demand accesses
569system.cpu0.dcache.demand_miss_rate::total 0.097333 # miss rate for demand accesses
570system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097333 # miss rate for overall accesses
571system.cpu0.dcache.overall_miss_rate::total 0.097333 # miss rate for overall accesses
572system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.730935 # average ReadReq miss latency
573system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.730935 # average ReadReq miss latency
574system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49591.742221 # average WriteReq miss latency
575system.cpu0.dcache.WriteReq_avg_miss_latency::total 49591.742221 # average WriteReq miss latency
576system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11064.606328 # average LoadLockedReq miss latency
577system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11064.606328 # average LoadLockedReq miss latency
578system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.299581 # average StoreCondReq miss latency
579system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.299581 # average StoreCondReq miss latency
580system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency
581system.cpu0.dcache.demand_avg_miss_latency::total 36756.248707 # average overall miss latency
582system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency
583system.cpu0.dcache.overall_avg_miss_latency::total 36756.248707 # average overall miss latency

584system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
585system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
586system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
587system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
588system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
589system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

590system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks
591system.cpu0.dcache.writebacks::total 681271 # number of writebacks
592system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses
593system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses
594system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses
595system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses
596system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses
597system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses

590system.cpu0.dcache.writebacks::writebacks 681263 # number of writebacks
591system.cpu0.dcache.writebacks::total 681263 # number of writebacks
592system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938392 # number of ReadReq MSHR misses
593system.cpu0.dcache.ReadReq_mshr_misses::total 938392 # number of ReadReq MSHR misses
594system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255335 # number of WriteReq MSHR misses
595system.cpu0.dcache.WriteReq_mshr_misses::total 255335 # number of WriteReq MSHR misses
596system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13590 # number of LoadLockedReq MSHR misses
597system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13590 # number of LoadLockedReq MSHR misses

598system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses
599system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses

600system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses
601system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses
602system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses
603system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses

600system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193727 # number of demand (read+write) MSHR misses
601system.cpu0.dcache.demand_mshr_misses::total 1193727 # number of demand (read+write) MSHR misses
602system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193727 # number of overall MSHR misses
603system.cpu0.dcache.overall_mshr_misses::total 1193727 # number of overall MSHR misses

604system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable
605system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable
606system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable
607system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable
608system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses
609system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses

610system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles
611system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles
612system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles
613system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles
614system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles
615system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles
616system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles
617system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles
618system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles
619system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles
620system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles
621system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles
622system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles
623system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles
624system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles
625system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles
626system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses
627system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses
628system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses
629system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses
630system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses
631system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses

610system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30276027000 # number of ReadReq MSHR miss cycles
611system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30276027000 # number of ReadReq MSHR miss cycles
612system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12407172500 # number of WriteReq MSHR miss cycles
613system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12407172500 # number of WriteReq MSHR miss cycles
614system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136778000 # number of LoadLockedReq MSHR miss cycles
615system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136778000 # number of LoadLockedReq MSHR miss cycles
616system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26224500 # number of StoreCondReq MSHR miss cycles
617system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26224500 # number of StoreCondReq MSHR miss cycles
618system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42683199500 # number of demand (read+write) MSHR miss cycles
619system.cpu0.dcache.demand_mshr_miss_latency::total 42683199500 # number of demand (read+write) MSHR miss cycles
620system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42683199500 # number of overall MSHR miss cycles
621system.cpu0.dcache.overall_mshr_miss_latency::total 42683199500 # number of overall MSHR miss cycles
622system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572134500 # number of ReadReq MSHR uncacheable cycles
623system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572134500 # number of ReadReq MSHR uncacheable cycles
624system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572134500 # number of overall MSHR uncacheable cycles
625system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572134500 # number of overall MSHR uncacheable cycles
626system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127855 # mshr miss rate for ReadReq accesses
627system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127855 # mshr miss rate for ReadReq accesses
628system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051846 # mshr miss rate for WriteReq accesses
629system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051846 # mshr miss rate for WriteReq accesses
630system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089066 # mshr miss rate for LoadLockedReq accesses
631system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089066 # mshr miss rate for LoadLockedReq accesses

632system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses
633system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses

634system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses
635system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses
636system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses
637system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses
638system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency
639system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency
640system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency
641system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency
642system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency
643system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency
644system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency
645system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency
646system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency
647system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency
648system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency
649system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency
650system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency
651system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency
652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency
653system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency
654system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
655system.cpu0.icache.tags.replacements 692001 # number of replacements

634system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for demand accesses
635system.cpu0.dcache.demand_mshr_miss_rate::total 0.097333 # mshr miss rate for demand accesses
636system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for overall accesses
637system.cpu0.dcache.overall_mshr_miss_rate::total 0.097333 # mshr miss rate for overall accesses
638system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.730935 # average ReadReq mshr miss latency
639system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.730935 # average ReadReq mshr miss latency
640system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48591.742221 # average WriteReq mshr miss latency
641system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48591.742221 # average WriteReq mshr miss latency
642system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10064.606328 # average LoadLockedReq mshr miss latency
643system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10064.606328 # average LoadLockedReq mshr miss latency
644system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.299581 # average StoreCondReq mshr miss latency
645system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.299581 # average StoreCondReq mshr miss latency
646system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency
647system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency
648system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency
649system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency
650system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.656581 # average ReadReq mshr uncacheable latency
651system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.656581 # average ReadReq mshr uncacheable latency
652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.288920 # average overall mshr uncacheable latency
653system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.288920 # average overall mshr uncacheable latency
654system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
655system.cpu0.icache.tags.replacements 692168 # number of replacements

656system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use

657system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks.
658system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks.
659system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks.
660system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit.

657system.cpu0.icache.tags.total_refs 47009511 # Total number of references to valid blocks.
658system.cpu0.icache.tags.sampled_refs 692680 # Sample count of references to valid blocks.
659system.cpu0.icache.tags.avg_refs 67.866130 # Average number of references to valid blocks.
660system.cpu0.icache.tags.warmup_cycle 44813247500 # Cycle when the warmup percentage was hit.

661system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor
662system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy
663system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy
664system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
665system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
666system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
667system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id
668system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id
669system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

670system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses
671system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses
672system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
673system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits
674system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits
675system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits
676system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits
677system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits
678system.cpu0.icache.overall_hits::total 47007113 # number of overall hits
679system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses
680system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses
681system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses
682system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses
683system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses
684system.cpu0.icache.overall_misses::total 692639 # number of overall misses
685system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles
686system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles
687system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles
688system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles
689system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles
690system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles
691system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses)
692system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses)
693system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses
694system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses
695system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses
696system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses
697system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses
698system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses
699system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses
700system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses
701system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses
702system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses
703system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency
704system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency
705system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency
706system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency
707system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency
708system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency

670system.cpu0.icache.tags.tag_accesses 48395123 # Number of tag accesses
671system.cpu0.icache.tags.data_accesses 48395123 # Number of data accesses
672system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
673system.cpu0.icache.ReadReq_hits::cpu0.inst 47009511 # number of ReadReq hits
674system.cpu0.icache.ReadReq_hits::total 47009511 # number of ReadReq hits
675system.cpu0.icache.demand_hits::cpu0.inst 47009511 # number of demand (read+write) hits
676system.cpu0.icache.demand_hits::total 47009511 # number of demand (read+write) hits
677system.cpu0.icache.overall_hits::cpu0.inst 47009511 # number of overall hits
678system.cpu0.icache.overall_hits::total 47009511 # number of overall hits
679system.cpu0.icache.ReadReq_misses::cpu0.inst 692806 # number of ReadReq misses
680system.cpu0.icache.ReadReq_misses::total 692806 # number of ReadReq misses
681system.cpu0.icache.demand_misses::cpu0.inst 692806 # number of demand (read+write) misses
682system.cpu0.icache.demand_misses::total 692806 # number of demand (read+write) misses
683system.cpu0.icache.overall_misses::cpu0.inst 692806 # number of overall misses
684system.cpu0.icache.overall_misses::total 692806 # number of overall misses
685system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10342349000 # number of ReadReq miss cycles
686system.cpu0.icache.ReadReq_miss_latency::total 10342349000 # number of ReadReq miss cycles
687system.cpu0.icache.demand_miss_latency::cpu0.inst 10342349000 # number of demand (read+write) miss cycles
688system.cpu0.icache.demand_miss_latency::total 10342349000 # number of demand (read+write) miss cycles
689system.cpu0.icache.overall_miss_latency::cpu0.inst 10342349000 # number of overall miss cycles
690system.cpu0.icache.overall_miss_latency::total 10342349000 # number of overall miss cycles
691system.cpu0.icache.ReadReq_accesses::cpu0.inst 47702317 # number of ReadReq accesses(hits+misses)
692system.cpu0.icache.ReadReq_accesses::total 47702317 # number of ReadReq accesses(hits+misses)
693system.cpu0.icache.demand_accesses::cpu0.inst 47702317 # number of demand (read+write) accesses
694system.cpu0.icache.demand_accesses::total 47702317 # number of demand (read+write) accesses
695system.cpu0.icache.overall_accesses::cpu0.inst 47702317 # number of overall (read+write) accesses
696system.cpu0.icache.overall_accesses::total 47702317 # number of overall (read+write) accesses
697system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses
698system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses
699system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses
700system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses
701system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses
702system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses
703system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.203566 # average ReadReq miss latency
704system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.203566 # average ReadReq miss latency
705system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency
706system.cpu0.icache.demand_avg_miss_latency::total 14928.203566 # average overall miss latency
707system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency
708system.cpu0.icache.overall_avg_miss_latency::total 14928.203566 # average overall miss latency

709system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
710system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
711system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
712system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
713system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
714system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

715system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks
716system.cpu0.icache.writebacks::total 692001 # number of writebacks
717system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses
718system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses
719system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses
720system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses
721system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses
722system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses
723system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles
724system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles
725system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles
726system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles
727system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles
728system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles
729system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses
730system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses
731system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses
732system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses
733system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses
734system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses
735system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency
736system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency
737system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency
738system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency
739system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency
740system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency

715system.cpu0.icache.writebacks::writebacks 692168 # number of writebacks
716system.cpu0.icache.writebacks::total 692168 # number of writebacks
717system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692806 # number of ReadReq MSHR misses
718system.cpu0.icache.ReadReq_mshr_misses::total 692806 # number of ReadReq MSHR misses
719system.cpu0.icache.demand_mshr_misses::cpu0.inst 692806 # number of demand (read+write) MSHR misses
720system.cpu0.icache.demand_mshr_misses::total 692806 # number of demand (read+write) MSHR misses
721system.cpu0.icache.overall_mshr_misses::cpu0.inst 692806 # number of overall MSHR misses
722system.cpu0.icache.overall_mshr_misses::total 692806 # number of overall MSHR misses
723system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9649543000 # number of ReadReq MSHR miss cycles
724system.cpu0.icache.ReadReq_mshr_miss_latency::total 9649543000 # number of ReadReq MSHR miss cycles
725system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9649543000 # number of demand (read+write) MSHR miss cycles
726system.cpu0.icache.demand_mshr_miss_latency::total 9649543000 # number of demand (read+write) MSHR miss cycles
727system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9649543000 # number of overall MSHR miss cycles
728system.cpu0.icache.overall_mshr_miss_latency::total 9649543000 # number of overall MSHR miss cycles
729system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses
730system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses
731system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses
732system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses
733system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses
734system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses
735system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average ReadReq mshr miss latency
736system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.203566 # average ReadReq mshr miss latency
737system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency
738system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency
739system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency
740system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency

741system.cpu1.dtb.fetch_hits 0 # ITB hits
742system.cpu1.dtb.fetch_misses 0 # ITB misses
743system.cpu1.dtb.fetch_acv 0 # ITB acv
744system.cpu1.dtb.fetch_accesses 0 # ITB accesses

745system.cpu1.dtb.read_hits 2442522 # DTB read hits

745system.cpu1.dtb.read_hits 2442461 # DTB read hits

746system.cpu1.dtb.read_misses 2621 # DTB read misses
747system.cpu1.dtb.read_acv 0 # DTB read access violations
748system.cpu1.dtb.read_accesses 205338 # DTB read accesses

749system.cpu1.dtb.write_hits 1749235 # DTB write hits

749system.cpu1.dtb.write_hits 1749247 # DTB write hits

750system.cpu1.dtb.write_misses 236 # DTB write misses
751system.cpu1.dtb.write_acv 24 # DTB write access violations
752system.cpu1.dtb.write_accesses 89740 # DTB write accesses

753system.cpu1.dtb.data_hits 4191757 # DTB hits

753system.cpu1.dtb.data_hits 4191708 # DTB hits

754system.cpu1.dtb.data_misses 2857 # DTB misses
755system.cpu1.dtb.data_acv 24 # DTB access violations
756system.cpu1.dtb.data_accesses 295078 # DTB accesses

757system.cpu1.itb.fetch_hits 1826928 # ITB hits

757system.cpu1.itb.fetch_hits 1826964 # ITB hits

758system.cpu1.itb.fetch_misses 1064 # ITB misses
759system.cpu1.itb.fetch_acv 0 # ITB acv

760system.cpu1.itb.fetch_accesses 1827992 # ITB accesses

760system.cpu1.itb.fetch_accesses 1828028 # ITB accesses

761system.cpu1.itb.read_hits 0 # DTB read hits
762system.cpu1.itb.read_misses 0 # DTB read misses
763system.cpu1.itb.read_acv 0 # DTB read access violations
764system.cpu1.itb.read_accesses 0 # DTB read accesses
765system.cpu1.itb.write_hits 0 # DTB write hits
766system.cpu1.itb.write_misses 0 # DTB write misses
767system.cpu1.itb.write_acv 0 # DTB write access violations
768system.cpu1.itb.write_accesses 0 # DTB write accesses
769system.cpu1.itb.data_hits 0 # DTB hits
770system.cpu1.itb.data_misses 0 # DTB misses
771system.cpu1.itb.data_acv 0 # DTB access violations
772system.cpu1.itb.data_accesses 0 # DTB accesses
773system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions
774system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state

775system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state
776system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state

775system.cpu1.pwrStateClkGateDist::mean 692201198.395722 # Distribution of time spent in the clock gated state
776system.cpu1.pwrStateClkGateDist::stdev 417085998.942743 # Distribution of time spent in the clock gated state

777system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state

778system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state
779system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state

778system.cpu1.pwrStateClkGateDist::min_value 61500 # Distribution of time spent in the clock gated state
779system.cpu1.pwrStateClkGateDist::max_value 974672500 # Distribution of time spent in the clock gated state

780system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state

781system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states
782system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states
783system.cpu1.numCycles 3931646339 # number of cpu cycles simulated

781system.cpu1.pwrStateResidencyTicks::ON 25117814500 # Cumulative time (in ticks) in various power states
782system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941624361500 # Cumulative time (in ticks) in various power states
783system.cpu1.numCycles 3931646343 # number of cpu cycles simulated

784system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
785system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
786system.cpu1.kern.inst.arm 0 # number of arm instructions executed
787system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed

788system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed
789system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl

788system.cpu1.kern.inst.hwrei 79704 # number of hwrei instructions executed
789system.cpu1.kern.ipl_count::0 27198 38.42% 38.42% # number of times we switched to this ipl

790system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl
791system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl

792system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl
793system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl
794system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl

792system.cpu1.kern.ipl_count::31 41099 58.06% 100.00% # number of times we switched to this ipl
793system.cpu1.kern.ipl_count::total 70791 # number of times we switched to this ipl
794system.cpu1.kern.ipl_good::0 26333 48.20% 48.20% # number of times we switched to this ipl from a different ipl

795system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl
796system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl

797system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl
798system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl
799system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl
800system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl
801system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl
802system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl
803system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl
804system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl

797system.cpu1.kern.ipl_good::31 25808 47.24% 100.00% # number of times we switched to this ipl from a different ipl
798system.cpu1.kern.ipl_good::total 54635 # number of times we switched to this ipl from a different ipl
799system.cpu1.kern.ipl_ticks::0 1909855455500 97.15% 97.15% # number of cycles we spent at this ipl
800system.cpu1.kern.ipl_ticks::22 731138500 0.04% 97.19% # number of cycles we spent at this ipl
801system.cpu1.kern.ipl_ticks::30 371933000 0.02% 97.21% # number of cycles we spent at this ipl
802system.cpu1.kern.ipl_ticks::31 54864614500 2.79% 100.00% # number of cycles we spent at this ipl
803system.cpu1.kern.ipl_ticks::total 1965823141500 # number of cycles we spent at this ipl
804system.cpu1.kern.ipl_used::0 0.968196 # fraction of swpipl calls that actually changed the ipl

805system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
806system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl

807system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl
808system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl

807system.cpu1.kern.ipl_used::31 0.627947 # fraction of swpipl calls that actually changed the ipl
808system.cpu1.kern.ipl_used::total 0.771779 # fraction of swpipl calls that actually changed the ipl

809system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
810system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed
811system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
812system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
813system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed
814system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed
815system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed

816system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed

816system.cpu1.kern.callpal::swpipl 64571 88.14% 91.50% # number of callpals executed

817system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed
818system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed
819system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed
820system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed
821system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed
822system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
823system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
824system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed

825system.cpu1.kern.callpal::total 73259 # number of callpals executed

825system.cpu1.kern.callpal::total 73263 # number of callpals executed

826system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches
827system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
828system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches
829system.cpu1.kern.mode_good::kernel 816
830system.cpu1.kern.mode_good::user 367
831system.cpu1.kern.mode_good::idle 449
832system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches
833system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
834system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches
835system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches

836system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode
837system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode
838system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode

836system.cpu1.kern.mode_ticks::kernel 18379231500 0.94% 0.94% # number of ticks spent at the given mode
837system.cpu1.kern.mode_ticks::user 1492112000 0.08% 1.01% # number of ticks spent at the given mode
838system.cpu1.kern.mode_ticks::idle 1945079443000 98.99% 100.00% # number of ticks spent at the given mode

839system.cpu1.kern.swap_context 2017 # number of times the context was actually changed

840system.cpu1.committedInsts 13268743 # Number of instructions committed
841system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed
842system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses

840system.cpu1.committedInsts 13268542 # Number of instructions committed
841system.cpu1.committedOps 13268542 # Number of ops (including micro ops) committed
842system.cpu1.num_int_alu_accesses 12224320 # Number of integer alu accesses

843system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses

844system.cpu1.num_func_calls 423393 # number of times a function call or return occured
845system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls
846system.cpu1.num_int_insts 12224543 # number of integer instructions

844system.cpu1.num_func_calls 423403 # number of times a function call or return occured
845system.cpu1.num_conditional_control_insts 1315333 # number of instructions that are conditional controls
846system.cpu1.num_int_insts 12224320 # number of integer instructions

847system.cpu1.num_fp_insts 175144 # number of float instructions

848system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read
849system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written

848system.cpu1.num_int_register_reads 16795598 # number of times the integer registers were read
849system.cpu1.num_int_register_writes 8988647 # number of times the integer registers were written

850system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read
851system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written

852system.cpu1.num_mem_refs 4214824 # number of memory refs
853system.cpu1.num_load_insts 2456352 # Number of load instructions
854system.cpu1.num_store_insts 1758472 # Number of store instructions
855system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles
856system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles
857system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles
858system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles
859system.cpu1.Branches 1899015 # Number of branches fetched
860system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction
861system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction
862system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction

852system.cpu1.num_mem_refs 4214775 # number of memory refs
853system.cpu1.num_load_insts 2456291 # Number of load instructions
854system.cpu1.num_store_insts 1758484 # Number of store instructions
855system.cpu1.num_idle_cycles 3881434187.727123 # Number of idle cycles
856system.cpu1.num_busy_cycles 50212155.272877 # Number of busy cycles
857system.cpu1.not_idle_fraction 0.012771 # Percentage of non-idle cycles
858system.cpu1.idle_fraction 0.987229 # Percentage of idle cycles
859system.cpu1.Branches 1898911 # Number of branches fetched
860system.cpu1.op_class::No_OpClass 719210 5.42% 5.42% # Class of executed instruction
861system.cpu1.op_class::IntAlu 7860972 59.23% 64.65% # Class of executed instruction
862system.cpu1.op_class::IntMult 22603 0.17% 64.82% # Class of executed instruction

863system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction
864system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction
865system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction
866system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction
867system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction
868system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction

869system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction
870system.cpu1.op_class::FloatMisc 0 0.00% 64.94% # Class of executed instruction
871system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction
872system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction
873system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction
874system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction
875system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction
876system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction
877system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction
878system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction
879system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction
880system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction
881system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction
882system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction
883system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction
884system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction
885system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction
886system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction
887system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction
888system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction
889system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction
890system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction
891system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction
892system.cpu1.op_class::MemRead 2447876 18.44% 83.38% # Class of executed instruction
893system.cpu1.op_class::MemWrite 1681278 12.67% 96.05% # Class of executed instruction

869system.cpu1.op_class::FloatDiv 1759 0.01% 64.93% # Class of executed instruction
870system.cpu1.op_class::FloatMisc 0 0.00% 64.93% # Class of executed instruction
871system.cpu1.op_class::FloatSqrt 0 0.00% 64.93% # Class of executed instruction
872system.cpu1.op_class::SimdAdd 0 0.00% 64.93% # Class of executed instruction
873system.cpu1.op_class::SimdAddAcc 0 0.00% 64.93% # Class of executed instruction
874system.cpu1.op_class::SimdAlu 0 0.00% 64.93% # Class of executed instruction
875system.cpu1.op_class::SimdCmp 0 0.00% 64.93% # Class of executed instruction
876system.cpu1.op_class::SimdCvt 0 0.00% 64.93% # Class of executed instruction
877system.cpu1.op_class::SimdMisc 0 0.00% 64.93% # Class of executed instruction
878system.cpu1.op_class::SimdMult 0 0.00% 64.93% # Class of executed instruction
879system.cpu1.op_class::SimdMultAcc 0 0.00% 64.93% # Class of executed instruction
880system.cpu1.op_class::SimdShift 0 0.00% 64.93% # Class of executed instruction
881system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.93% # Class of executed instruction
882system.cpu1.op_class::SimdSqrt 0 0.00% 64.93% # Class of executed instruction
883system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.93% # Class of executed instruction
884system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.93% # Class of executed instruction
885system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.93% # Class of executed instruction
886system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.93% # Class of executed instruction
887system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.93% # Class of executed instruction
888system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.93% # Class of executed instruction
889system.cpu1.op_class::SimdFloatMult 0 0.00% 64.93% # Class of executed instruction
890system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.93% # Class of executed instruction
891system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.93% # Class of executed instruction
892system.cpu1.op_class::MemRead 2447819 18.44% 83.38% # Class of executed instruction
893system.cpu1.op_class::MemWrite 1681290 12.67% 96.05% # Class of executed instruction

894system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction
895system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction

896system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction

896system.cpu1.op_class::IprAccess 364385 2.75% 100.00% # Class of executed instruction

897system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction

898system.cpu1.op_class::total 13271624 # Class of executed instruction
899system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
900system.cpu1.dcache.tags.replacements 162095 # number of replacements
901system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use
902system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks.
903system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks.
904system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks.
905system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit.
906system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor

898system.cpu1.op_class::total 13271423 # Class of executed instruction
899system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
900system.cpu1.dcache.tags.replacements 162127 # number of replacements
901system.cpu1.dcache.tags.tagsinuse 484.320008 # Cycle average of tags in use
902system.cpu1.dcache.tags.total_refs 4015090 # Total number of references to valid blocks.
903system.cpu1.dcache.tags.sampled_refs 162456 # Sample count of references to valid blocks.
904system.cpu1.dcache.tags.avg_refs 24.714938 # Average number of references to valid blocks.
905system.cpu1.dcache.tags.warmup_cycle 72636345500 # Cycle when the warmup percentage was hit.
906system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320008 # Average occupied blocks per requestor

907system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy
908system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy
909system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id
910system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
911system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id
912system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id

913system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses
914system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses
915system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
916system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits
917system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits
918system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits
919system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits
920system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits
921system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits
922system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits
923system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits
924system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits
925system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits
926system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits
927system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits
928system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses
929system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses
930system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses
931system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses
932system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses
933system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses
934system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses
935system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses
936system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses
937system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses
938system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses
939system.cpu1.dcache.overall_misses::total 177419 # number of overall misses
940system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles
941system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles
942system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles
943system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles
944system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles
945system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles
946system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles
947system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles
948system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles
949system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles
950system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles
951system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles
952system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses)
953system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses)
954system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses)
955system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses)
956system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses)
957system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses)
958system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses)
959system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses)
960system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses
961system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses
962system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses
963system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses
964system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses
965system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses
966system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses
967system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses
968system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses
969system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses
970system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses
971system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses
972system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses
973system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses
974system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses
975system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses
976system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency
977system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency
978system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency
979system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency
980system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency
981system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency
982system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency
983system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency
984system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency
985system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency
986system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency
987system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency

913system.cpu1.dcache.tags.tag_accesses 16996743 # Number of tag accesses
914system.cpu1.dcache.tags.data_accesses 16996743 # Number of data accesses
915system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
916system.cpu1.dcache.ReadReq_hits::cpu1.data 2273788 # number of ReadReq hits
917system.cpu1.dcache.ReadReq_hits::total 2273788 # number of ReadReq hits
918system.cpu1.dcache.WriteReq_hits::cpu1.data 1634135 # number of WriteReq hits
919system.cpu1.dcache.WriteReq_hits::total 1634135 # number of WriteReq hits
920system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51915 # number of LoadLockedReq hits
921system.cpu1.dcache.LoadLockedReq_hits::total 51915 # number of LoadLockedReq hits
922system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52085 # number of StoreCondReq hits
923system.cpu1.dcache.StoreCondReq_hits::total 52085 # number of StoreCondReq hits
924system.cpu1.dcache.demand_hits::cpu1.data 3907923 # number of demand (read+write) hits
925system.cpu1.dcache.demand_hits::total 3907923 # number of demand (read+write) hits
926system.cpu1.dcache.overall_hits::cpu1.data 3907923 # number of overall hits
927system.cpu1.dcache.overall_hits::total 3907923 # number of overall hits
928system.cpu1.dcache.ReadReq_misses::cpu1.data 118690 # number of ReadReq misses
929system.cpu1.dcache.ReadReq_misses::total 118690 # number of ReadReq misses
930system.cpu1.dcache.WriteReq_misses::cpu1.data 58791 # number of WriteReq misses
931system.cpu1.dcache.WriteReq_misses::total 58791 # number of WriteReq misses
932system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9152 # number of LoadLockedReq misses
933system.cpu1.dcache.LoadLockedReq_misses::total 9152 # number of LoadLockedReq misses
934system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6117 # number of StoreCondReq misses
935system.cpu1.dcache.StoreCondReq_misses::total 6117 # number of StoreCondReq misses
936system.cpu1.dcache.demand_misses::cpu1.data 177481 # number of demand (read+write) misses
937system.cpu1.dcache.demand_misses::total 177481 # number of demand (read+write) misses
938system.cpu1.dcache.overall_misses::cpu1.data 177481 # number of overall misses
939system.cpu1.dcache.overall_misses::total 177481 # number of overall misses
940system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1467443500 # number of ReadReq miss cycles
941system.cpu1.dcache.ReadReq_miss_latency::total 1467443500 # number of ReadReq miss cycles
942system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1300528500 # number of WriteReq miss cycles
943system.cpu1.dcache.WriteReq_miss_latency::total 1300528500 # number of WriteReq miss cycles
944system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84062000 # number of LoadLockedReq miss cycles
945system.cpu1.dcache.LoadLockedReq_miss_latency::total 84062000 # number of LoadLockedReq miss cycles
946system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34151000 # number of StoreCondReq miss cycles
947system.cpu1.dcache.StoreCondReq_miss_latency::total 34151000 # number of StoreCondReq miss cycles
948system.cpu1.dcache.demand_miss_latency::cpu1.data 2767972000 # number of demand (read+write) miss cycles
949system.cpu1.dcache.demand_miss_latency::total 2767972000 # number of demand (read+write) miss cycles
950system.cpu1.dcache.overall_miss_latency::cpu1.data 2767972000 # number of overall miss cycles
951system.cpu1.dcache.overall_miss_latency::total 2767972000 # number of overall miss cycles
952system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392478 # number of ReadReq accesses(hits+misses)
953system.cpu1.dcache.ReadReq_accesses::total 2392478 # number of ReadReq accesses(hits+misses)
954system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692926 # number of WriteReq accesses(hits+misses)
955system.cpu1.dcache.WriteReq_accesses::total 1692926 # number of WriteReq accesses(hits+misses)
956system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61067 # number of LoadLockedReq accesses(hits+misses)
957system.cpu1.dcache.LoadLockedReq_accesses::total 61067 # number of LoadLockedReq accesses(hits+misses)
958system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58202 # number of StoreCondReq accesses(hits+misses)
959system.cpu1.dcache.StoreCondReq_accesses::total 58202 # number of StoreCondReq accesses(hits+misses)
960system.cpu1.dcache.demand_accesses::cpu1.data 4085404 # number of demand (read+write) accesses
961system.cpu1.dcache.demand_accesses::total 4085404 # number of demand (read+write) accesses
962system.cpu1.dcache.overall_accesses::cpu1.data 4085404 # number of overall (read+write) accesses
963system.cpu1.dcache.overall_accesses::total 4085404 # number of overall (read+write) accesses
964system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049610 # miss rate for ReadReq accesses
965system.cpu1.dcache.ReadReq_miss_rate::total 0.049610 # miss rate for ReadReq accesses
966system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034727 # miss rate for WriteReq accesses
967system.cpu1.dcache.WriteReq_miss_rate::total 0.034727 # miss rate for WriteReq accesses
968system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149868 # miss rate for LoadLockedReq accesses
969system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149868 # miss rate for LoadLockedReq accesses
970system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105099 # miss rate for StoreCondReq accesses
971system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105099 # miss rate for StoreCondReq accesses
972system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043443 # miss rate for demand accesses
973system.cpu1.dcache.demand_miss_rate::total 0.043443 # miss rate for demand accesses
974system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043443 # miss rate for overall accesses
975system.cpu1.dcache.overall_miss_rate::total 0.043443 # miss rate for overall accesses
976system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12363.665852 # average ReadReq miss latency
977system.cpu1.dcache.ReadReq_avg_miss_latency::total 12363.665852 # average ReadReq miss latency
978system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22121.217533 # average WriteReq miss latency
979system.cpu1.dcache.WriteReq_avg_miss_latency::total 22121.217533 # average WriteReq miss latency
980system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.096154 # average LoadLockedReq miss latency
981system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.096154 # average LoadLockedReq miss latency
982system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5582.965506 # average StoreCondReq miss latency
983system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5582.965506 # average StoreCondReq miss latency
984system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency
985system.cpu1.dcache.demand_avg_miss_latency::total 15595.877869 # average overall miss latency
986system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency
987system.cpu1.dcache.overall_avg_miss_latency::total 15595.877869 # average overall miss latency

988system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
989system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
990system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
991system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
992system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
993system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

994system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks
995system.cpu1.dcache.writebacks::total 111600 # number of writebacks
996system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses
997system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses
998system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses
999system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses
1000system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses
1001system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses
1002system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6116 # number of StoreCondReq MSHR misses
1003system.cpu1.dcache.StoreCondReq_mshr_misses::total 6116 # number of StoreCondReq MSHR misses
1004system.cpu1.dcache.demand_mshr_misses::cpu1.data 177419 # number of demand (read+write) MSHR misses
1005system.cpu1.dcache.demand_mshr_misses::total 177419 # number of demand (read+write) MSHR misses
1006system.cpu1.dcache.overall_mshr_misses::cpu1.data 177419 # number of overall MSHR misses
1007system.cpu1.dcache.overall_mshr_misses::total 177419 # number of overall MSHR misses

994system.cpu1.dcache.writebacks::writebacks 111642 # number of writebacks
995system.cpu1.dcache.writebacks::total 111642 # number of writebacks
996system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118690 # number of ReadReq MSHR misses
997system.cpu1.dcache.ReadReq_mshr_misses::total 118690 # number of ReadReq MSHR misses
998system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58791 # number of WriteReq MSHR misses
999system.cpu1.dcache.WriteReq_mshr_misses::total 58791 # number of WriteReq MSHR misses
1000system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9152 # number of LoadLockedReq MSHR misses
1001system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9152 # number of LoadLockedReq MSHR misses
1002system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6117 # number of StoreCondReq MSHR misses
1003system.cpu1.dcache.StoreCondReq_mshr_misses::total 6117 # number of StoreCondReq MSHR misses
1004system.cpu1.dcache.demand_mshr_misses::cpu1.data 177481 # number of demand (read+write) MSHR misses
1005system.cpu1.dcache.demand_mshr_misses::total 177481 # number of demand (read+write) MSHR misses
1006system.cpu1.dcache.overall_mshr_misses::cpu1.data 177481 # number of overall MSHR misses
1007system.cpu1.dcache.overall_mshr_misses::total 177481 # number of overall MSHR misses

1008system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable
1009system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable
1010system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable
1011system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable
1012system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses
1013system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses

1014system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles
1015system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles
1016system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles
1017system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles
1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles
1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles
1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # number of StoreCondReq MSHR miss cycles
1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28056000 # number of StoreCondReq MSHR miss cycles
1022system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2585528000 # number of demand (read+write) MSHR miss cycles
1023system.cpu1.dcache.demand_mshr_miss_latency::total 2585528000 # number of demand (read+write) MSHR miss cycles
1024system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2585528000 # number of overall MSHR miss cycles
1025system.cpu1.dcache.overall_mshr_miss_latency::total 2585528000 # number of overall MSHR miss cycles

1014system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1348753500 # number of ReadReq MSHR miss cycles
1015system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1348753500 # number of ReadReq MSHR miss cycles
1016system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1241737500 # number of WriteReq MSHR miss cycles
1017system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1241737500 # number of WriteReq MSHR miss cycles
1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74910000 # number of LoadLockedReq MSHR miss cycles
1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74910000 # number of LoadLockedReq MSHR miss cycles
1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28034000 # number of StoreCondReq MSHR miss cycles
1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28034000 # number of StoreCondReq MSHR miss cycles
1022system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2590491000 # number of demand (read+write) MSHR miss cycles
1023system.cpu1.dcache.demand_mshr_miss_latency::total 2590491000 # number of demand (read+write) MSHR miss cycles
1024system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2590491000 # number of overall MSHR miss cycles
1025system.cpu1.dcache.overall_mshr_miss_latency::total 2590491000 # number of overall MSHR miss cycles

1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles
1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles
1028system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles
1029system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles

1030system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses
1031system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses
1032system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses
1033system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses
1034system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses
1035system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses
1036system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses
1037system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses
1038system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses
1039system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses
1040system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses
1041system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses
1042system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency
1043system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency
1044system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency
1045system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency
1046system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency
1047system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency
1048system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency
1049system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency
1050system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency
1051system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency
1052system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency
1053system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency

1030system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049610 # mshr miss rate for ReadReq accesses
1031system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049610 # mshr miss rate for ReadReq accesses
1032system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034727 # mshr miss rate for WriteReq accesses
1033system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034727 # mshr miss rate for WriteReq accesses
1034system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149868 # mshr miss rate for LoadLockedReq accesses
1035system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149868 # mshr miss rate for LoadLockedReq accesses
1036system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105099 # mshr miss rate for StoreCondReq accesses
1037system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105099 # mshr miss rate for StoreCondReq accesses
1038system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for demand accesses
1039system.cpu1.dcache.demand_mshr_miss_rate::total 0.043443 # mshr miss rate for demand accesses
1040system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for overall accesses
1041system.cpu1.dcache.overall_mshr_miss_rate::total 0.043443 # mshr miss rate for overall accesses
1042system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11363.665852 # average ReadReq mshr miss latency
1043system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11363.665852 # average ReadReq mshr miss latency
1044system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21121.217533 # average WriteReq mshr miss latency
1045system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21121.217533 # average WriteReq mshr miss latency
1046system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.096154 # average LoadLockedReq mshr miss latency
1047system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.096154 # average LoadLockedReq mshr miss latency
1048system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4582.965506 # average StoreCondReq mshr miss latency
1049system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4582.965506 # average StoreCondReq mshr miss latency
1050system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency
1051system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency
1052system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency
1053system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency

1054system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency
1055system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency
1056system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency
1057system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency

1058system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1059system.cpu1.icache.tags.replacements 326538 # number of replacements
1060system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use
1061system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks.
1062system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks.
1063system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks.
1064system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit.
1065system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor

1058system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1059system.cpu1.icache.tags.replacements 326560 # number of replacements
1060system.cpu1.icache.tags.tagsinuse 445.783409 # Cycle average of tags in use
1061system.cpu1.icache.tags.total_refs 12944312 # Total number of references to valid blocks.
1062system.cpu1.icache.tags.sampled_refs 327071 # Sample count of references to valid blocks.
1063system.cpu1.icache.tags.avg_refs 39.576459 # Average number of references to valid blocks.
1064system.cpu1.icache.tags.warmup_cycle 1960887860500 # Cycle when the warmup percentage was hit.
1065system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783409 # Average occupied blocks per requestor

1066system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy
1067system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy
1068system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1069system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
1070system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id
1071system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
1072system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id

1073system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses
1074system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses
1075system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1076system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits
1077system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits
1078system.cpu1.icache.demand_hits::cpu1.inst 12944535 # number of demand (read+write) hits
1079system.cpu1.icache.demand_hits::total 12944535 # number of demand (read+write) hits
1080system.cpu1.icache.overall_hits::cpu1.inst 12944535 # number of overall hits
1081system.cpu1.icache.overall_hits::total 12944535 # number of overall hits
1082system.cpu1.icache.ReadReq_misses::cpu1.inst 327089 # number of ReadReq misses
1083system.cpu1.icache.ReadReq_misses::total 327089 # number of ReadReq misses
1084system.cpu1.icache.demand_misses::cpu1.inst 327089 # number of demand (read+write) misses
1085system.cpu1.icache.demand_misses::total 327089 # number of demand (read+write) misses
1086system.cpu1.icache.overall_misses::cpu1.inst 327089 # number of overall misses
1087system.cpu1.icache.overall_misses::total 327089 # number of overall misses
1088system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4450039000 # number of ReadReq miss cycles
1089system.cpu1.icache.ReadReq_miss_latency::total 4450039000 # number of ReadReq miss cycles
1090system.cpu1.icache.demand_miss_latency::cpu1.inst 4450039000 # number of demand (read+write) miss cycles
1091system.cpu1.icache.demand_miss_latency::total 4450039000 # number of demand (read+write) miss cycles
1092system.cpu1.icache.overall_miss_latency::cpu1.inst 4450039000 # number of overall miss cycles
1093system.cpu1.icache.overall_miss_latency::total 4450039000 # number of overall miss cycles
1094system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271624 # number of ReadReq accesses(hits+misses)
1095system.cpu1.icache.ReadReq_accesses::total 13271624 # number of ReadReq accesses(hits+misses)
1096system.cpu1.icache.demand_accesses::cpu1.inst 13271624 # number of demand (read+write) accesses
1097system.cpu1.icache.demand_accesses::total 13271624 # number of demand (read+write) accesses
1098system.cpu1.icache.overall_accesses::cpu1.inst 13271624 # number of overall (read+write) accesses
1099system.cpu1.icache.overall_accesses::total 13271624 # number of overall (read+write) accesses
1100system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024646 # miss rate for ReadReq accesses
1101system.cpu1.icache.ReadReq_miss_rate::total 0.024646 # miss rate for ReadReq accesses
1102system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses
1103system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses
1104system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses
1105system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses
1106system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency
1107system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency
1108system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency
1109system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency
1110system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency
1111system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency

1073system.cpu1.icache.tags.tag_accesses 13598534 # Number of tag accesses
1074system.cpu1.icache.tags.data_accesses 13598534 # Number of data accesses
1075system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1076system.cpu1.icache.ReadReq_hits::cpu1.inst 12944312 # number of ReadReq hits
1077system.cpu1.icache.ReadReq_hits::total 12944312 # number of ReadReq hits
1078system.cpu1.icache.demand_hits::cpu1.inst 12944312 # number of demand (read+write) hits
1079system.cpu1.icache.demand_hits::total 12944312 # number of demand (read+write) hits
1080system.cpu1.icache.overall_hits::cpu1.inst 12944312 # number of overall hits
1081system.cpu1.icache.overall_hits::total 12944312 # number of overall hits
1082system.cpu1.icache.ReadReq_misses::cpu1.inst 327111 # number of ReadReq misses
1083system.cpu1.icache.ReadReq_misses::total 327111 # number of ReadReq misses
1084system.cpu1.icache.demand_misses::cpu1.inst 327111 # number of demand (read+write) misses
1085system.cpu1.icache.demand_misses::total 327111 # number of demand (read+write) misses
1086system.cpu1.icache.overall_misses::cpu1.inst 327111 # number of overall misses
1087system.cpu1.icache.overall_misses::total 327111 # number of overall misses
1088system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4448984500 # number of ReadReq miss cycles
1089system.cpu1.icache.ReadReq_miss_latency::total 4448984500 # number of ReadReq miss cycles
1090system.cpu1.icache.demand_miss_latency::cpu1.inst 4448984500 # number of demand (read+write) miss cycles
1091system.cpu1.icache.demand_miss_latency::total 4448984500 # number of demand (read+write) miss cycles
1092system.cpu1.icache.overall_miss_latency::cpu1.inst 4448984500 # number of overall miss cycles
1093system.cpu1.icache.overall_miss_latency::total 4448984500 # number of overall miss cycles
1094system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271423 # number of ReadReq accesses(hits+misses)
1095system.cpu1.icache.ReadReq_accesses::total 13271423 # number of ReadReq accesses(hits+misses)
1096system.cpu1.icache.demand_accesses::cpu1.inst 13271423 # number of demand (read+write) accesses
1097system.cpu1.icache.demand_accesses::total 13271423 # number of demand (read+write) accesses
1098system.cpu1.icache.overall_accesses::cpu1.inst 13271423 # number of overall (read+write) accesses
1099system.cpu1.icache.overall_accesses::total 13271423 # number of overall (read+write) accesses
1100system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024648 # miss rate for ReadReq accesses
1101system.cpu1.icache.ReadReq_miss_rate::total 0.024648 # miss rate for ReadReq accesses
1102system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024648 # miss rate for demand accesses
1103system.cpu1.icache.demand_miss_rate::total 0.024648 # miss rate for demand accesses
1104system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024648 # miss rate for overall accesses
1105system.cpu1.icache.overall_miss_rate::total 0.024648 # miss rate for overall accesses
1106system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.840388 # average ReadReq miss latency
1107system.cpu1.icache.ReadReq_avg_miss_latency::total 13600.840388 # average ReadReq miss latency
1108system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency
1109system.cpu1.icache.demand_avg_miss_latency::total 13600.840388 # average overall miss latency
1110system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency
1111system.cpu1.icache.overall_avg_miss_latency::total 13600.840388 # average overall miss latency

1112system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1113system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1114system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1115system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1116system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1117system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1118system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks
1119system.cpu1.icache.writebacks::total 326538 # number of writebacks
1120system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses
1121system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses
1122system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses
1123system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses
1124system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses
1125system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses
1126system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles
1127system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles
1128system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles
1129system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles
1130system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles
1131system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles
1132system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses
1133system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses
1134system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses
1135system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses
1136system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses
1137system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses
1138system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency
1139system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency
1140system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency
1141system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency
1142system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency
1143system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency

1118system.cpu1.icache.writebacks::writebacks 326560 # number of writebacks
1119system.cpu1.icache.writebacks::total 326560 # number of writebacks
1120system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327111 # number of ReadReq MSHR misses
1121system.cpu1.icache.ReadReq_mshr_misses::total 327111 # number of ReadReq MSHR misses
1122system.cpu1.icache.demand_mshr_misses::cpu1.inst 327111 # number of demand (read+write) MSHR misses
1123system.cpu1.icache.demand_mshr_misses::total 327111 # number of demand (read+write) MSHR misses
1124system.cpu1.icache.overall_mshr_misses::cpu1.inst 327111 # number of overall MSHR misses
1125system.cpu1.icache.overall_mshr_misses::total 327111 # number of overall MSHR misses
1126system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4121873500 # number of ReadReq MSHR miss cycles
1127system.cpu1.icache.ReadReq_mshr_miss_latency::total 4121873500 # number of ReadReq MSHR miss cycles
1128system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4121873500 # number of demand (read+write) MSHR miss cycles
1129system.cpu1.icache.demand_mshr_miss_latency::total 4121873500 # number of demand (read+write) MSHR miss cycles
1130system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4121873500 # number of overall MSHR miss cycles
1131system.cpu1.icache.overall_mshr_miss_latency::total 4121873500 # number of overall MSHR miss cycles
1132system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for ReadReq accesses
1133system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024648 # mshr miss rate for ReadReq accesses
1134system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for demand accesses
1135system.cpu1.icache.demand_mshr_miss_rate::total 0.024648 # mshr miss rate for demand accesses
1136system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for overall accesses
1137system.cpu1.icache.overall_mshr_miss_rate::total 0.024648 # mshr miss rate for overall accesses
1138system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average ReadReq mshr miss latency
1139system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12600.840388 # average ReadReq mshr miss latency
1140system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency
1141system.cpu1.icache.demand_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency
1142system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency
1143system.cpu1.icache.overall_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency

1144system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1145system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1146system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1147system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1148system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1149system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1150system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1151system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1152system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1153system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1154system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1155system.disk2.dma_write_txs 1 # Number of DMA write transactions.

1156system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states

1156system.iobus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states

1157system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
1158system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
1159system.iobus.trans_dist::WriteReq 55675 # Transaction distribution
1160system.iobus.trans_dist::WriteResp 55675 # Transaction distribution
1161system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes)
1162system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
1163system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1164system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)

--- 16 unchanged lines hidden (view full) ---

1181system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1182system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1183system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes)
1184system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
1185system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
1186system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes)
1187system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks)
1188system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)

1189system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks)

1189system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks)

1190system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1191system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
1192system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1193system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
1194system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1195system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks)
1196system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1197system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks)
1198system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1199system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks)
1200system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1201system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks)
1202system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1203system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
1204system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)

1205system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks)

1205system.iobus.reqLayer27.occupancy 216236013 # Layer occupancy (ticks)

1206system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1207system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks)
1208system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1209system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks)
1210system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)

1211system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states

1211system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states

1212system.iocache.tags.replacements 41698 # number of replacements

1213system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use

1213system.iocache.tags.tagsinuse 0.568425 # Cycle average of tags in use

1214system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1215system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
1216system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.

1217system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit.
1218system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor
1219system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy
1220system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy

1217system.iocache.tags.warmup_cycle 1760410358000 # Cycle when the warmup percentage was hit.
1218system.iocache.tags.occ_blocks::tsunami.ide 0.568425 # Average occupied blocks per requestor
1219system.iocache.tags.occ_percent::tsunami.ide 0.035527 # Average percentage of cache occupancy
1220system.iocache.tags.occ_percent::total 0.035527 # Average percentage of cache occupancy

1221system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1222system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1223system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1224system.iocache.tags.tag_accesses 375570 # Number of tag accesses
1225system.iocache.tags.data_accesses 375570 # Number of data accesses

1226system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states

1226system.iocache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states

1227system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
1228system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
1229system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1230system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1231system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses
1232system.iocache.demand_misses::total 41730 # number of demand (read+write) misses
1233system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses
1234system.iocache.overall_misses::total 41730 # number of overall misses
1235system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles
1236system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles

1237system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles
1238system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles
1239system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles
1240system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles
1241system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles
1242system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles

1237system.iocache.WriteLineReq_miss_latency::tsunami.ide 4955951130 # number of WriteLineReq miss cycles
1238system.iocache.WriteLineReq_miss_latency::total 4955951130 # number of WriteLineReq miss cycles
1239system.iocache.demand_miss_latency::tsunami.ide 4978364013 # number of demand (read+write) miss cycles
1240system.iocache.demand_miss_latency::total 4978364013 # number of demand (read+write) miss cycles
1241system.iocache.overall_miss_latency::tsunami.ide 4978364013 # number of overall miss cycles
1242system.iocache.overall_miss_latency::total 4978364013 # number of overall miss cycles

1243system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
1244system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
1245system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1246system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1247system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses
1248system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses
1249system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses
1250system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses
1251system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1252system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1253system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1254system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1255system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1256system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1257system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1258system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1259system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency
1260system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency

1261system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency
1262system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency
1263system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency
1264system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency
1265system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency
1266system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency

1261system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119271.061080 # average WriteLineReq miss latency
1262system.iocache.WriteLineReq_avg_miss_latency::total 119271.061080 # average WriteLineReq miss latency
1263system.iocache.demand_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency
1264system.iocache.demand_avg_miss_latency::total 119299.401222 # average overall miss latency
1265system.iocache.overall_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency
1266system.iocache.overall_avg_miss_latency::total 119299.401222 # average overall miss latency

1267system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked
1268system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1269system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked
1270system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1271system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked
1272system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1273system.iocache.writebacks::writebacks 41520 # number of writebacks
1274system.iocache.writebacks::total 41520 # number of writebacks
1275system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
1276system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
1277system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1278system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1279system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses
1280system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses
1281system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses
1282system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses
1283system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles
1284system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles

1285system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles
1286system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles
1287system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles
1288system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles
1289system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles
1290system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles

1285system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2875898127 # number of WriteLineReq MSHR miss cycles
1286system.iocache.WriteLineReq_mshr_miss_latency::total 2875898127 # number of WriteLineReq MSHR miss cycles
1287system.iocache.demand_mshr_miss_latency::tsunami.ide 2889411010 # number of demand (read+write) MSHR miss cycles
1288system.iocache.demand_mshr_miss_latency::total 2889411010 # number of demand (read+write) MSHR miss cycles
1289system.iocache.overall_mshr_miss_latency::tsunami.ide 2889411010 # number of overall MSHR miss cycles
1290system.iocache.overall_mshr_miss_latency::total 2889411010 # number of overall MSHR miss cycles

1291system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1292system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1293system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1294system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1295system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1296system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1297system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1298system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1299system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency
1300system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency

1301system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency
1302system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency
1303system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency
1304system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency
1305system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency
1306system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency
1307system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1308system.l2c.tags.replacements 342937 # number of replacements
1309system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use
1310system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks.
1311system.l2c.tags.sampled_refs 408458 # Sample count of references to valid blocks.
1312system.l2c.tags.avg_refs 9.766355 # Average number of references to valid blocks.
1313system.l2c.tags.warmup_cycle 7750506000 # Cycle when the warmup percentage was hit.
1314system.l2c.tags.occ_blocks::writebacks 285.827023 # Average occupied blocks per requestor
1315system.l2c.tags.occ_blocks::cpu0.inst 4791.190703 # Average occupied blocks per requestor
1316system.l2c.tags.occ_blocks::cpu0.data 59306.187710 # Average occupied blocks per requestor
1317system.l2c.tags.occ_blocks::cpu1.inst 166.825599 # Average occupied blocks per requestor
1318system.l2c.tags.occ_blocks::cpu1.data 839.923352 # Average occupied blocks per requestor

1301system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69212.026545 # average WriteLineReq mshr miss latency
1302system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69212.026545 # average WriteLineReq mshr miss latency
1303system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency
1304system.iocache.demand_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency
1305system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency
1306system.iocache.overall_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency
1307system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1308system.l2c.tags.replacements 342924 # number of replacements
1309system.l2c.tags.tagsinuse 65389.954347 # Cycle average of tags in use
1310system.l2c.tags.total_refs 3989934 # Total number of references to valid blocks.
1311system.l2c.tags.sampled_refs 408445 # Sample count of references to valid blocks.
1312system.l2c.tags.avg_refs 9.768596 # Average number of references to valid blocks.
1313system.l2c.tags.warmup_cycle 7750508000 # Cycle when the warmup percentage was hit.
1314system.l2c.tags.occ_blocks::writebacks 285.827021 # Average occupied blocks per requestor
1315system.l2c.tags.occ_blocks::cpu0.inst 4794.067634 # Average occupied blocks per requestor
1316system.l2c.tags.occ_blocks::cpu0.data 59305.224879 # Average occupied blocks per requestor
1317system.l2c.tags.occ_blocks::cpu1.inst 165.844219 # Average occupied blocks per requestor
1318system.l2c.tags.occ_blocks::cpu1.data 838.990595 # Average occupied blocks per requestor

1319system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy

1320system.l2c.tags.occ_percent::cpu0.inst 0.073108 # Average percentage of cache occupancy
1321system.l2c.tags.occ_percent::cpu0.data 0.904941 # Average percentage of cache occupancy
1322system.l2c.tags.occ_percent::cpu1.inst 0.002546 # Average percentage of cache occupancy
1323system.l2c.tags.occ_percent::cpu1.data 0.012816 # Average percentage of cache occupancy

1320system.l2c.tags.occ_percent::cpu0.inst 0.073152 # Average percentage of cache occupancy
1321system.l2c.tags.occ_percent::cpu0.data 0.904926 # Average percentage of cache occupancy
1322system.l2c.tags.occ_percent::cpu1.inst 0.002531 # Average percentage of cache occupancy
1323system.l2c.tags.occ_percent::cpu1.data 0.012802 # Average percentage of cache occupancy

1324system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy
1325system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id
1326system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
1327system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id
1328system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id
1329system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id
1330system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id
1331system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id

1332system.l2c.tags.tag_accesses 35591920 # Number of tag accesses
1333system.l2c.tags.data_accesses 35591920 # Number of data accesses
1334system.l2c.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1335system.l2c.WritebackDirty_hits::writebacks 792871 # number of WritebackDirty hits
1336system.l2c.WritebackDirty_hits::total 792871 # number of WritebackDirty hits
1337system.l2c.WritebackClean_hits::writebacks 746791 # number of WritebackClean hits
1338system.l2c.WritebackClean_hits::total 746791 # number of WritebackClean hits
1339system.l2c.UpgradeReq_hits::cpu0.data 3150 # number of UpgradeReq hits
1340system.l2c.UpgradeReq_hits::cpu1.data 2355 # number of UpgradeReq hits
1341system.l2c.UpgradeReq_hits::total 5505 # number of UpgradeReq hits
1342system.l2c.SCUpgradeReq_hits::cpu0.data 947 # number of SCUpgradeReq hits
1343system.l2c.SCUpgradeReq_hits::cpu1.data 959 # number of SCUpgradeReq hits
1344system.l2c.SCUpgradeReq_hits::total 1906 # number of SCUpgradeReq hits
1345system.l2c.ReadExReq_hits::cpu0.data 128503 # number of ReadExReq hits
1346system.l2c.ReadExReq_hits::cpu1.data 43274 # number of ReadExReq hits
1347system.l2c.ReadExReq_hits::total 171777 # number of ReadExReq hits
1348system.l2c.ReadCleanReq_hits::cpu0.inst 680173 # number of ReadCleanReq hits
1349system.l2c.ReadCleanReq_hits::cpu1.inst 326101 # number of ReadCleanReq hits
1350system.l2c.ReadCleanReq_hits::total 1006274 # number of ReadCleanReq hits
1351system.l2c.ReadSharedReq_hits::cpu0.data 663284 # number of ReadSharedReq hits
1352system.l2c.ReadSharedReq_hits::cpu1.data 108416 # number of ReadSharedReq hits
1353system.l2c.ReadSharedReq_hits::total 771700 # number of ReadSharedReq hits
1354system.l2c.demand_hits::cpu0.inst 680173 # number of demand (read+write) hits
1355system.l2c.demand_hits::cpu0.data 791787 # number of demand (read+write) hits
1356system.l2c.demand_hits::cpu1.inst 326101 # number of demand (read+write) hits
1357system.l2c.demand_hits::cpu1.data 151690 # number of demand (read+write) hits
1358system.l2c.demand_hits::total 1949751 # number of demand (read+write) hits
1359system.l2c.overall_hits::cpu0.inst 680173 # number of overall hits
1360system.l2c.overall_hits::cpu0.data 791787 # number of overall hits
1361system.l2c.overall_hits::cpu1.inst 326101 # number of overall hits
1362system.l2c.overall_hits::cpu1.data 151690 # number of overall hits
1363system.l2c.overall_hits::total 1949751 # number of overall hits

1332system.l2c.tags.tag_accesses 35598107 # Number of tag accesses
1333system.l2c.tags.data_accesses 35598107 # Number of data accesses
1334system.l2c.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1335system.l2c.WritebackDirty_hits::writebacks 792905 # number of WritebackDirty hits
1336system.l2c.WritebackDirty_hits::total 792905 # number of WritebackDirty hits
1337system.l2c.WritebackClean_hits::writebacks 747283 # number of WritebackClean hits
1338system.l2c.WritebackClean_hits::total 747283 # number of WritebackClean hits
1339system.l2c.UpgradeReq_hits::cpu0.data 3151 # number of UpgradeReq hits
1340system.l2c.UpgradeReq_hits::cpu1.data 2387 # number of UpgradeReq hits
1341system.l2c.UpgradeReq_hits::total 5538 # number of UpgradeReq hits
1342system.l2c.SCUpgradeReq_hits::cpu0.data 946 # number of SCUpgradeReq hits
1343system.l2c.SCUpgradeReq_hits::cpu1.data 957 # number of SCUpgradeReq hits
1344system.l2c.SCUpgradeReq_hits::total 1903 # number of SCUpgradeReq hits
1345system.l2c.ReadExReq_hits::cpu0.data 128511 # number of ReadExReq hits
1346system.l2c.ReadExReq_hits::cpu1.data 43286 # number of ReadExReq hits
1347system.l2c.ReadExReq_hits::total 171797 # number of ReadExReq hits
1348system.l2c.ReadCleanReq_hits::cpu0.inst 680335 # number of ReadCleanReq hits
1349system.l2c.ReadCleanReq_hits::cpu1.inst 326126 # number of ReadCleanReq hits
1350system.l2c.ReadCleanReq_hits::total 1006461 # number of ReadCleanReq hits
1351system.l2c.ReadSharedReq_hits::cpu0.data 663262 # number of ReadSharedReq hits
1352system.l2c.ReadSharedReq_hits::cpu1.data 108452 # number of ReadSharedReq hits
1353system.l2c.ReadSharedReq_hits::total 771714 # number of ReadSharedReq hits
1354system.l2c.demand_hits::cpu0.inst 680335 # number of demand (read+write) hits
1355system.l2c.demand_hits::cpu0.data 791773 # number of demand (read+write) hits
1356system.l2c.demand_hits::cpu1.inst 326126 # number of demand (read+write) hits
1357system.l2c.demand_hits::cpu1.data 151738 # number of demand (read+write) hits
1358system.l2c.demand_hits::total 1949972 # number of demand (read+write) hits
1359system.l2c.overall_hits::cpu0.inst 680335 # number of overall hits
1360system.l2c.overall_hits::cpu0.data 791773 # number of overall hits
1361system.l2c.overall_hits::cpu1.inst 326126 # number of overall hits
1362system.l2c.overall_hits::cpu1.data 151738 # number of overall hits
1363system.l2c.overall_hits::total 1949972 # number of overall hits

1364system.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses
1365system.l2c.UpgradeReq_misses::cpu1.data 1 # number of UpgradeReq misses
1366system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses

1367system.l2c.ReadExReq_misses::cpu0.data 116830 # number of ReadExReq misses

1367system.l2c.ReadExReq_misses::cpu0.data 116816 # number of ReadExReq misses

1368system.l2c.ReadExReq_misses::cpu1.data 6419 # number of ReadExReq misses

1369system.l2c.ReadExReq_misses::total 123249 # number of ReadExReq misses
1370system.l2c.ReadCleanReq_misses::cpu0.inst 12445 # number of ReadCleanReq misses
1371system.l2c.ReadCleanReq_misses::cpu1.inst 987 # number of ReadCleanReq misses
1372system.l2c.ReadCleanReq_misses::total 13432 # number of ReadCleanReq misses

1369system.l2c.ReadExReq_misses::total 123235 # number of ReadExReq misses
1370system.l2c.ReadCleanReq_misses::cpu0.inst 12450 # number of ReadCleanReq misses
1371system.l2c.ReadCleanReq_misses::cpu1.inst 984 # number of ReadCleanReq misses
1372system.l2c.ReadCleanReq_misses::total 13434 # number of ReadCleanReq misses

1373system.l2c.ReadSharedReq_misses::cpu0.data 271517 # number of ReadSharedReq misses

1374system.l2c.ReadSharedReq_misses::cpu1.data 340 # number of ReadSharedReq misses
1375system.l2c.ReadSharedReq_misses::total 271857 # number of ReadSharedReq misses
1376system.l2c.demand_misses::cpu0.inst 12445 # number of demand (read+write) misses
1377system.l2c.demand_misses::cpu0.data 388347 # number of demand (read+write) misses
1378system.l2c.demand_misses::cpu1.inst 987 # number of demand (read+write) misses
1379system.l2c.demand_misses::cpu1.data 6759 # number of demand (read+write) misses
1380system.l2c.demand_misses::total 408538 # number of demand (read+write) misses
1381system.l2c.overall_misses::cpu0.inst 12445 # number of overall misses
1382system.l2c.overall_misses::cpu0.data 388347 # number of overall misses
1383system.l2c.overall_misses::cpu1.inst 987 # number of overall misses
1384system.l2c.overall_misses::cpu1.data 6759 # number of overall misses
1385system.l2c.overall_misses::total 408538 # number of overall misses

1374system.l2c.ReadSharedReq_misses::cpu1.data 339 # number of ReadSharedReq misses
1375system.l2c.ReadSharedReq_misses::total 271856 # number of ReadSharedReq misses
1376system.l2c.demand_misses::cpu0.inst 12450 # number of demand (read+write) misses
1377system.l2c.demand_misses::cpu0.data 388333 # number of demand (read+write) misses
1378system.l2c.demand_misses::cpu1.inst 984 # number of demand (read+write) misses
1379system.l2c.demand_misses::cpu1.data 6758 # number of demand (read+write) misses
1380system.l2c.demand_misses::total 408525 # number of demand (read+write) misses
1381system.l2c.overall_misses::cpu0.inst 12450 # number of overall misses
1382system.l2c.overall_misses::cpu0.data 388333 # number of overall misses
1383system.l2c.overall_misses::cpu1.inst 984 # number of overall misses
1384system.l2c.overall_misses::cpu1.data 6758 # number of overall misses
1385system.l2c.overall_misses::total 408525 # number of overall misses

1386system.l2c.UpgradeReq_miss_latency::cpu0.data 300000 # number of UpgradeReq miss cycles
1387system.l2c.UpgradeReq_miss_latency::cpu1.data 28500 # number of UpgradeReq miss cycles
1388system.l2c.UpgradeReq_miss_latency::total 328500 # number of UpgradeReq miss cycles

1389system.l2c.ReadExReq_miss_latency::cpu0.data 10622495500 # number of ReadExReq miss cycles
1390system.l2c.ReadExReq_miss_latency::cpu1.data 657559500 # number of ReadExReq miss cycles
1391system.l2c.ReadExReq_miss_latency::total 11280055000 # number of ReadExReq miss cycles
1392system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281839000 # number of ReadCleanReq miss cycles
1393system.l2c.ReadCleanReq_miss_latency::cpu1.inst 101239000 # number of ReadCleanReq miss cycles
1394system.l2c.ReadCleanReq_miss_latency::total 1383078000 # number of ReadCleanReq miss cycles
1395system.l2c.ReadSharedReq_miss_latency::cpu0.data 21946509000 # number of ReadSharedReq miss cycles
1396system.l2c.ReadSharedReq_miss_latency::cpu1.data 42090000 # number of ReadSharedReq miss cycles
1397system.l2c.ReadSharedReq_miss_latency::total 21988599000 # number of ReadSharedReq miss cycles
1398system.l2c.demand_miss_latency::cpu0.inst 1281839000 # number of demand (read+write) miss cycles
1399system.l2c.demand_miss_latency::cpu0.data 32569004500 # number of demand (read+write) miss cycles
1400system.l2c.demand_miss_latency::cpu1.inst 101239000 # number of demand (read+write) miss cycles
1401system.l2c.demand_miss_latency::cpu1.data 699649500 # number of demand (read+write) miss cycles
1402system.l2c.demand_miss_latency::total 34651732000 # number of demand (read+write) miss cycles
1403system.l2c.overall_miss_latency::cpu0.inst 1281839000 # number of overall miss cycles
1404system.l2c.overall_miss_latency::cpu0.data 32569004500 # number of overall miss cycles
1405system.l2c.overall_miss_latency::cpu1.inst 101239000 # number of overall miss cycles
1406system.l2c.overall_miss_latency::cpu1.data 699649500 # number of overall miss cycles
1407system.l2c.overall_miss_latency::total 34651732000 # number of overall miss cycles
1408system.l2c.WritebackDirty_accesses::writebacks 792871 # number of WritebackDirty accesses(hits+misses)
1409system.l2c.WritebackDirty_accesses::total 792871 # number of WritebackDirty accesses(hits+misses)
1410system.l2c.WritebackClean_accesses::writebacks 746791 # number of WritebackClean accesses(hits+misses)
1411system.l2c.WritebackClean_accesses::total 746791 # number of WritebackClean accesses(hits+misses)
1412system.l2c.UpgradeReq_accesses::cpu0.data 3155 # number of UpgradeReq accesses(hits+misses)
1413system.l2c.UpgradeReq_accesses::cpu1.data 2356 # number of UpgradeReq accesses(hits+misses)
1414system.l2c.UpgradeReq_accesses::total 5511 # number of UpgradeReq accesses(hits+misses)
1415system.l2c.SCUpgradeReq_accesses::cpu0.data 947 # number of SCUpgradeReq accesses(hits+misses)
1416system.l2c.SCUpgradeReq_accesses::cpu1.data 959 # number of SCUpgradeReq accesses(hits+misses)
1417system.l2c.SCUpgradeReq_accesses::total 1906 # number of SCUpgradeReq accesses(hits+misses)
1418system.l2c.ReadExReq_accesses::cpu0.data 245333 # number of ReadExReq accesses(hits+misses)
1419system.l2c.ReadExReq_accesses::cpu1.data 49693 # number of ReadExReq accesses(hits+misses)
1420system.l2c.ReadExReq_accesses::total 295026 # number of ReadExReq accesses(hits+misses)
1421system.l2c.ReadCleanReq_accesses::cpu0.inst 692618 # number of ReadCleanReq accesses(hits+misses)
1422system.l2c.ReadCleanReq_accesses::cpu1.inst 327088 # number of ReadCleanReq accesses(hits+misses)
1423system.l2c.ReadCleanReq_accesses::total 1019706 # number of ReadCleanReq accesses(hits+misses)
1424system.l2c.ReadSharedReq_accesses::cpu0.data 934801 # number of ReadSharedReq accesses(hits+misses)
1425system.l2c.ReadSharedReq_accesses::cpu1.data 108756 # number of ReadSharedReq accesses(hits+misses)
1426system.l2c.ReadSharedReq_accesses::total 1043557 # number of ReadSharedReq accesses(hits+misses)
1427system.l2c.demand_accesses::cpu0.inst 692618 # number of demand (read+write) accesses
1428system.l2c.demand_accesses::cpu0.data 1180134 # number of demand (read+write) accesses
1429system.l2c.demand_accesses::cpu1.inst 327088 # number of demand (read+write) accesses
1430system.l2c.demand_accesses::cpu1.data 158449 # number of demand (read+write) accesses
1431system.l2c.demand_accesses::total 2358289 # number of demand (read+write) accesses
1432system.l2c.overall_accesses::cpu0.inst 692618 # number of overall (read+write) accesses
1433system.l2c.overall_accesses::cpu0.data 1180134 # number of overall (read+write) accesses
1434system.l2c.overall_accesses::cpu1.inst 327088 # number of overall (read+write) accesses
1435system.l2c.overall_accesses::cpu1.data 158449 # number of overall (read+write) accesses
1436system.l2c.overall_accesses::total 2358289 # number of overall (read+write) accesses
1437system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001585 # miss rate for UpgradeReq accesses
1438system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000424 # miss rate for UpgradeReq accesses
1439system.l2c.UpgradeReq_miss_rate::total 0.001089 # miss rate for UpgradeReq accesses
1440system.l2c.ReadExReq_miss_rate::cpu0.data 0.476210 # miss rate for ReadExReq accesses
1441system.l2c.ReadExReq_miss_rate::cpu1.data 0.129173 # miss rate for ReadExReq accesses
1442system.l2c.ReadExReq_miss_rate::total 0.417756 # miss rate for ReadExReq accesses
1443system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.017968 # miss rate for ReadCleanReq accesses
1444system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.003018 # miss rate for ReadCleanReq accesses

1389system.l2c.ReadExReq_miss_latency::cpu0.data 10623244500 # number of ReadExReq miss cycles
1390system.l2c.ReadExReq_miss_latency::cpu1.data 659466000 # number of ReadExReq miss cycles
1391system.l2c.ReadExReq_miss_latency::total 11282710500 # number of ReadExReq miss cycles
1392system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281529500 # number of ReadCleanReq miss cycles
1393system.l2c.ReadCleanReq_miss_latency::cpu1.inst 100368000 # number of ReadCleanReq miss cycles
1394system.l2c.ReadCleanReq_miss_latency::total 1381897500 # number of ReadCleanReq miss cycles
1395system.l2c.ReadSharedReq_miss_latency::cpu0.data 21945590000 # number of ReadSharedReq miss cycles
1396system.l2c.ReadSharedReq_miss_latency::cpu1.data 41766500 # number of ReadSharedReq miss cycles
1397system.l2c.ReadSharedReq_miss_latency::total 21987356500 # number of ReadSharedReq miss cycles
1398system.l2c.demand_miss_latency::cpu0.inst 1281529500 # number of demand (read+write) miss cycles
1399system.l2c.demand_miss_latency::cpu0.data 32568834500 # number of demand (read+write) miss cycles
1400system.l2c.demand_miss_latency::cpu1.inst 100368000 # number of demand (read+write) miss cycles
1401system.l2c.demand_miss_latency::cpu1.data 701232500 # number of demand (read+write) miss cycles
1402system.l2c.demand_miss_latency::total 34651964500 # number of demand (read+write) miss cycles
1403system.l2c.overall_miss_latency::cpu0.inst 1281529500 # number of overall miss cycles
1404system.l2c.overall_miss_latency::cpu0.data 32568834500 # number of overall miss cycles
1405system.l2c.overall_miss_latency::cpu1.inst 100368000 # number of overall miss cycles
1406system.l2c.overall_miss_latency::cpu1.data 701232500 # number of overall miss cycles
1407system.l2c.overall_miss_latency::total 34651964500 # number of overall miss cycles
1408system.l2c.WritebackDirty_accesses::writebacks 792905 # number of WritebackDirty accesses(hits+misses)
1409system.l2c.WritebackDirty_accesses::total 792905 # number of WritebackDirty accesses(hits+misses)
1410system.l2c.WritebackClean_accesses::writebacks 747283 # number of WritebackClean accesses(hits+misses)
1411system.l2c.WritebackClean_accesses::total 747283 # number of WritebackClean accesses(hits+misses)
1412system.l2c.UpgradeReq_accesses::cpu0.data 3156 # number of UpgradeReq accesses(hits+misses)
1413system.l2c.UpgradeReq_accesses::cpu1.data 2388 # number of UpgradeReq accesses(hits+misses)
1414system.l2c.UpgradeReq_accesses::total 5544 # number of UpgradeReq accesses(hits+misses)
1415system.l2c.SCUpgradeReq_accesses::cpu0.data 946 # number of SCUpgradeReq accesses(hits+misses)
1416system.l2c.SCUpgradeReq_accesses::cpu1.data 957 # number of SCUpgradeReq accesses(hits+misses)
1417system.l2c.SCUpgradeReq_accesses::total 1903 # number of SCUpgradeReq accesses(hits+misses)
1418system.l2c.ReadExReq_accesses::cpu0.data 245327 # number of ReadExReq accesses(hits+misses)
1419system.l2c.ReadExReq_accesses::cpu1.data 49705 # number of ReadExReq accesses(hits+misses)
1420system.l2c.ReadExReq_accesses::total 295032 # number of ReadExReq accesses(hits+misses)
1421system.l2c.ReadCleanReq_accesses::cpu0.inst 692785 # number of ReadCleanReq accesses(hits+misses)
1422system.l2c.ReadCleanReq_accesses::cpu1.inst 327110 # number of ReadCleanReq accesses(hits+misses)
1423system.l2c.ReadCleanReq_accesses::total 1019895 # number of ReadCleanReq accesses(hits+misses)
1424system.l2c.ReadSharedReq_accesses::cpu0.data 934779 # number of ReadSharedReq accesses(hits+misses)
1425system.l2c.ReadSharedReq_accesses::cpu1.data 108791 # number of ReadSharedReq accesses(hits+misses)
1426system.l2c.ReadSharedReq_accesses::total 1043570 # number of ReadSharedReq accesses(hits+misses)
1427system.l2c.demand_accesses::cpu0.inst 692785 # number of demand (read+write) accesses
1428system.l2c.demand_accesses::cpu0.data 1180106 # number of demand (read+write) accesses
1429system.l2c.demand_accesses::cpu1.inst 327110 # number of demand (read+write) accesses
1430system.l2c.demand_accesses::cpu1.data 158496 # number of demand (read+write) accesses
1431system.l2c.demand_accesses::total 2358497 # number of demand (read+write) accesses
1432system.l2c.overall_accesses::cpu0.inst 692785 # number of overall (read+write) accesses
1433system.l2c.overall_accesses::cpu0.data 1180106 # number of overall (read+write) accesses
1434system.l2c.overall_accesses::cpu1.inst 327110 # number of overall (read+write) accesses
1435system.l2c.overall_accesses::cpu1.data 158496 # number of overall (read+write) accesses
1436system.l2c.overall_accesses::total 2358497 # number of overall (read+write) accesses
1437system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001584 # miss rate for UpgradeReq accesses
1438system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000419 # miss rate for UpgradeReq accesses
1439system.l2c.UpgradeReq_miss_rate::total 0.001082 # miss rate for UpgradeReq accesses
1440system.l2c.ReadExReq_miss_rate::cpu0.data 0.476164 # miss rate for ReadExReq accesses
1441system.l2c.ReadExReq_miss_rate::cpu1.data 0.129142 # miss rate for ReadExReq accesses
1442system.l2c.ReadExReq_miss_rate::total 0.417700 # miss rate for ReadExReq accesses
1443system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.017971 # miss rate for ReadCleanReq accesses
1444system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.003008 # miss rate for ReadCleanReq accesses

1445system.l2c.ReadCleanReq_miss_rate::total 0.013172 # miss rate for ReadCleanReq accesses

1446system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290454 # miss rate for ReadSharedReq accesses
1447system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.003126 # miss rate for ReadSharedReq accesses
1448system.l2c.ReadSharedReq_miss_rate::total 0.260510 # miss rate for ReadSharedReq accesses
1449system.l2c.demand_miss_rate::cpu0.inst 0.017968 # miss rate for demand accesses
1450system.l2c.demand_miss_rate::cpu0.data 0.329070 # miss rate for demand accesses
1451system.l2c.demand_miss_rate::cpu1.inst 0.003018 # miss rate for demand accesses
1452system.l2c.demand_miss_rate::cpu1.data 0.042657 # miss rate for demand accesses
1453system.l2c.demand_miss_rate::total 0.173235 # miss rate for demand accesses
1454system.l2c.overall_miss_rate::cpu0.inst 0.017968 # miss rate for overall accesses
1455system.l2c.overall_miss_rate::cpu0.data 0.329070 # miss rate for overall accesses
1456system.l2c.overall_miss_rate::cpu1.inst 0.003018 # miss rate for overall accesses
1457system.l2c.overall_miss_rate::cpu1.data 0.042657 # miss rate for overall accesses
1458system.l2c.overall_miss_rate::total 0.173235 # miss rate for overall accesses

1446system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290461 # miss rate for ReadSharedReq accesses
1447system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.003116 # miss rate for ReadSharedReq accesses
1448system.l2c.ReadSharedReq_miss_rate::total 0.260506 # miss rate for ReadSharedReq accesses
1449system.l2c.demand_miss_rate::cpu0.inst 0.017971 # miss rate for demand accesses
1450system.l2c.demand_miss_rate::cpu0.data 0.329066 # miss rate for demand accesses
1451system.l2c.demand_miss_rate::cpu1.inst 0.003008 # miss rate for demand accesses
1452system.l2c.demand_miss_rate::cpu1.data 0.042638 # miss rate for demand accesses
1453system.l2c.demand_miss_rate::total 0.173214 # miss rate for demand accesses
1454system.l2c.overall_miss_rate::cpu0.inst 0.017971 # miss rate for overall accesses
1455system.l2c.overall_miss_rate::cpu0.data 0.329066 # miss rate for overall accesses
1456system.l2c.overall_miss_rate::cpu1.inst 0.003008 # miss rate for overall accesses
1457system.l2c.overall_miss_rate::cpu1.data 0.042638 # miss rate for overall accesses
1458system.l2c.overall_miss_rate::total 0.173214 # miss rate for overall accesses

1459system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 60000 # average UpgradeReq miss latency
1460system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 28500 # average UpgradeReq miss latency
1461system.l2c.UpgradeReq_avg_miss_latency::total 54750 # average UpgradeReq miss latency

1462system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90922.669691 # average ReadExReq miss latency
1463system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102439.554448 # average ReadExReq miss latency
1464system.l2c.ReadExReq_avg_miss_latency::total 91522.486998 # average ReadExReq miss latency
1465system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 103000.321414 # average ReadCleanReq miss latency
1466system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 102572.441743 # average ReadCleanReq miss latency
1467system.l2c.ReadCleanReq_avg_miss_latency::total 102968.880286 # average ReadCleanReq miss latency
1468system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80829.226163 # average ReadSharedReq miss latency
1469system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123794.117647 # average ReadSharedReq miss latency
1470system.l2c.ReadSharedReq_avg_miss_latency::total 80882.960527 # average ReadSharedReq miss latency
1471system.l2c.demand_avg_miss_latency::cpu0.inst 103000.321414 # average overall miss latency
1472system.l2c.demand_avg_miss_latency::cpu0.data 83865.729618 # average overall miss latency
1473system.l2c.demand_avg_miss_latency::cpu1.inst 102572.441743 # average overall miss latency
1474system.l2c.demand_avg_miss_latency::cpu1.data 103513.759432 # average overall miss latency
1475system.l2c.demand_avg_miss_latency::total 84818.871194 # average overall miss latency
1476system.l2c.overall_avg_miss_latency::cpu0.inst 103000.321414 # average overall miss latency
1477system.l2c.overall_avg_miss_latency::cpu0.data 83865.729618 # average overall miss latency
1478system.l2c.overall_avg_miss_latency::cpu1.inst 102572.441743 # average overall miss latency
1479system.l2c.overall_avg_miss_latency::cpu1.data 103513.759432 # average overall miss latency
1480system.l2c.overall_avg_miss_latency::total 84818.871194 # average overall miss latency

1462system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90939.978256 # average ReadExReq miss latency
1463system.l2c.ReadExReq_avg_miss_latency::cpu1.data 102736.563328 # average ReadExReq miss latency
1464system.l2c.ReadExReq_avg_miss_latency::total 91554.432588 # average ReadExReq miss latency
1465system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 102934.096386 # average ReadCleanReq miss latency
1466system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 102000 # average ReadCleanReq miss latency
1467system.l2c.ReadCleanReq_avg_miss_latency::total 102865.676641 # average ReadCleanReq miss latency
1468system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 80825.841476 # average ReadSharedReq miss latency
1469system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 123205.014749 # average ReadSharedReq miss latency
1470system.l2c.ReadSharedReq_avg_miss_latency::total 80878.687614 # average ReadSharedReq miss latency
1471system.l2c.demand_avg_miss_latency::cpu0.inst 102934.096386 # average overall miss latency
1472system.l2c.demand_avg_miss_latency::cpu0.data 83868.315338 # average overall miss latency
1473system.l2c.demand_avg_miss_latency::cpu1.inst 102000 # average overall miss latency
1474system.l2c.demand_avg_miss_latency::cpu1.data 103763.317550 # average overall miss latency
1475system.l2c.demand_avg_miss_latency::total 84822.139404 # average overall miss latency
1476system.l2c.overall_avg_miss_latency::cpu0.inst 102934.096386 # average overall miss latency
1477system.l2c.overall_avg_miss_latency::cpu0.data 83868.315338 # average overall miss latency
1478system.l2c.overall_avg_miss_latency::cpu1.inst 102000 # average overall miss latency
1479system.l2c.overall_avg_miss_latency::cpu1.data 103763.317550 # average overall miss latency
1480system.l2c.overall_avg_miss_latency::total 84822.139404 # average overall miss latency

1481system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1482system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1483system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1484system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1485system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1486system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

1487system.l2c.writebacks::writebacks 79969 # number of writebacks
1488system.l2c.writebacks::total 79969 # number of writebacks

1487system.l2c.writebacks::writebacks 79955 # number of writebacks
1488system.l2c.writebacks::total 79955 # number of writebacks

1489system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
1490system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1491system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
1492system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
1493system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
1494system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
1495system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
1496system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
1497system.l2c.UpgradeReq_mshr_misses::cpu0.data 5 # number of UpgradeReq MSHR misses
1498system.l2c.UpgradeReq_mshr_misses::cpu1.data 1 # number of UpgradeReq MSHR misses
1499system.l2c.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses

1500system.l2c.ReadExReq_mshr_misses::cpu0.data 116830 # number of ReadExReq MSHR misses

1500system.l2c.ReadExReq_mshr_misses::cpu0.data 116816 # number of ReadExReq MSHR misses

1501system.l2c.ReadExReq_mshr_misses::cpu1.data 6419 # number of ReadExReq MSHR misses

1502system.l2c.ReadExReq_mshr_misses::total 123249 # number of ReadExReq MSHR misses
1503system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12445 # number of ReadCleanReq MSHR misses
1504system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 976 # number of ReadCleanReq MSHR misses
1505system.l2c.ReadCleanReq_mshr_misses::total 13421 # number of ReadCleanReq MSHR misses

1502system.l2c.ReadExReq_mshr_misses::total 123235 # number of ReadExReq MSHR misses
1503system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12450 # number of ReadCleanReq MSHR misses
1504system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 973 # number of ReadCleanReq MSHR misses
1505system.l2c.ReadCleanReq_mshr_misses::total 13423 # number of ReadCleanReq MSHR misses

1506system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271517 # number of ReadSharedReq MSHR misses

1507system.l2c.ReadSharedReq_mshr_misses::cpu1.data 340 # number of ReadSharedReq MSHR misses
1508system.l2c.ReadSharedReq_mshr_misses::total 271857 # number of ReadSharedReq MSHR misses
1509system.l2c.demand_mshr_misses::cpu0.inst 12445 # number of demand (read+write) MSHR misses
1510system.l2c.demand_mshr_misses::cpu0.data 388347 # number of demand (read+write) MSHR misses
1511system.l2c.demand_mshr_misses::cpu1.inst 976 # number of demand (read+write) MSHR misses
1512system.l2c.demand_mshr_misses::cpu1.data 6759 # number of demand (read+write) MSHR misses
1513system.l2c.demand_mshr_misses::total 408527 # number of demand (read+write) MSHR misses
1514system.l2c.overall_mshr_misses::cpu0.inst 12445 # number of overall MSHR misses
1515system.l2c.overall_mshr_misses::cpu0.data 388347 # number of overall MSHR misses
1516system.l2c.overall_mshr_misses::cpu1.inst 976 # number of overall MSHR misses
1517system.l2c.overall_mshr_misses::cpu1.data 6759 # number of overall MSHR misses
1518system.l2c.overall_mshr_misses::total 408527 # number of overall MSHR misses

1507system.l2c.ReadSharedReq_mshr_misses::cpu1.data 339 # number of ReadSharedReq MSHR misses
1508system.l2c.ReadSharedReq_mshr_misses::total 271856 # number of ReadSharedReq MSHR misses
1509system.l2c.demand_mshr_misses::cpu0.inst 12450 # number of demand (read+write) MSHR misses
1510system.l2c.demand_mshr_misses::cpu0.data 388333 # number of demand (read+write) MSHR misses
1511system.l2c.demand_mshr_misses::cpu1.inst 973 # number of demand (read+write) MSHR misses
1512system.l2c.demand_mshr_misses::cpu1.data 6758 # number of demand (read+write) MSHR misses
1513system.l2c.demand_mshr_misses::total 408514 # number of demand (read+write) MSHR misses
1514system.l2c.overall_mshr_misses::cpu0.inst 12450 # number of overall MSHR misses
1515system.l2c.overall_mshr_misses::cpu0.data 388333 # number of overall MSHR misses
1516system.l2c.overall_mshr_misses::cpu1.inst 973 # number of overall MSHR misses
1517system.l2c.overall_mshr_misses::cpu1.data 6758 # number of overall MSHR misses
1518system.l2c.overall_mshr_misses::total 408514 # number of overall MSHR misses

1519system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable
1520system.l2c.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable
1521system.l2c.ReadReq_mshr_uncacheable::total 7198 # number of ReadReq MSHR uncacheable
1522system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable
1523system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable
1524system.l2c.WriteReq_mshr_uncacheable::total 14123 # number of WriteReq MSHR uncacheable
1525system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses
1526system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses
1527system.l2c.overall_mshr_uncacheable_misses::total 21321 # number of overall MSHR uncacheable misses
1528system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 250000 # number of UpgradeReq MSHR miss cycles
1529system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of UpgradeReq MSHR miss cycles
1530system.l2c.UpgradeReq_mshr_miss_latency::total 268500 # number of UpgradeReq MSHR miss cycles

1531system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9454195500 # number of ReadExReq MSHR miss cycles
1532system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 593369500 # number of ReadExReq MSHR miss cycles
1533system.l2c.ReadExReq_mshr_miss_latency::total 10047565000 # number of ReadExReq MSHR miss cycles
1534system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1157389000 # number of ReadCleanReq MSHR miss cycles
1535system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 90609000 # number of ReadCleanReq MSHR miss cycles
1536system.l2c.ReadCleanReq_mshr_miss_latency::total 1247998000 # number of ReadCleanReq MSHR miss cycles
1537system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19231339000 # number of ReadSharedReq MSHR miss cycles
1538system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 38690000 # number of ReadSharedReq MSHR miss cycles
1539system.l2c.ReadSharedReq_mshr_miss_latency::total 19270029000 # number of ReadSharedReq MSHR miss cycles
1540system.l2c.demand_mshr_miss_latency::cpu0.inst 1157389000 # number of demand (read+write) MSHR miss cycles
1541system.l2c.demand_mshr_miss_latency::cpu0.data 28685534500 # number of demand (read+write) MSHR miss cycles
1542system.l2c.demand_mshr_miss_latency::cpu1.inst 90609000 # number of demand (read+write) MSHR miss cycles
1543system.l2c.demand_mshr_miss_latency::cpu1.data 632059500 # number of demand (read+write) MSHR miss cycles
1544system.l2c.demand_mshr_miss_latency::total 30565592000 # number of demand (read+write) MSHR miss cycles
1545system.l2c.overall_mshr_miss_latency::cpu0.inst 1157389000 # number of overall MSHR miss cycles
1546system.l2c.overall_mshr_miss_latency::cpu0.data 28685534500 # number of overall MSHR miss cycles
1547system.l2c.overall_mshr_miss_latency::cpu1.inst 90609000 # number of overall MSHR miss cycles
1548system.l2c.overall_mshr_miss_latency::cpu1.data 632059500 # number of overall MSHR miss cycles
1549system.l2c.overall_mshr_miss_latency::total 30565592000 # number of overall MSHR miss cycles

1531system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9455084500 # number of ReadExReq MSHR miss cycles
1532system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 595276000 # number of ReadExReq MSHR miss cycles
1533system.l2c.ReadExReq_mshr_miss_latency::total 10050360500 # number of ReadExReq MSHR miss cycles
1534system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1157029500 # number of ReadCleanReq MSHR miss cycles
1535system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 89768000 # number of ReadCleanReq MSHR miss cycles
1536system.l2c.ReadCleanReq_mshr_miss_latency::total 1246797500 # number of ReadCleanReq MSHR miss cycles
1537system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19230420000 # number of ReadSharedReq MSHR miss cycles
1538system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 38376500 # number of ReadSharedReq MSHR miss cycles
1539system.l2c.ReadSharedReq_mshr_miss_latency::total 19268796500 # number of ReadSharedReq MSHR miss cycles
1540system.l2c.demand_mshr_miss_latency::cpu0.inst 1157029500 # number of demand (read+write) MSHR miss cycles
1541system.l2c.demand_mshr_miss_latency::cpu0.data 28685504500 # number of demand (read+write) MSHR miss cycles
1542system.l2c.demand_mshr_miss_latency::cpu1.inst 89768000 # number of demand (read+write) MSHR miss cycles
1543system.l2c.demand_mshr_miss_latency::cpu1.data 633652500 # number of demand (read+write) MSHR miss cycles
1544system.l2c.demand_mshr_miss_latency::total 30565954500 # number of demand (read+write) MSHR miss cycles
1545system.l2c.overall_mshr_miss_latency::cpu0.inst 1157029500 # number of overall MSHR miss cycles
1546system.l2c.overall_mshr_miss_latency::cpu0.data 28685504500 # number of overall MSHR miss cycles
1547system.l2c.overall_mshr_miss_latency::cpu1.inst 89768000 # number of overall MSHR miss cycles
1548system.l2c.overall_mshr_miss_latency::cpu1.data 633652500 # number of overall MSHR miss cycles
1549system.l2c.overall_mshr_miss_latency::total 30565954500 # number of overall MSHR miss cycles

1550system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1483681000 # number of ReadReq MSHR uncacheable cycles
1551system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24728000 # number of ReadReq MSHR uncacheable cycles
1552system.l2c.ReadReq_mshr_uncacheable_latency::total 1508409000 # number of ReadReq MSHR uncacheable cycles
1553system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1483681000 # number of overall MSHR uncacheable cycles
1554system.l2c.overall_mshr_uncacheable_latency::cpu1.data 24728000 # number of overall MSHR uncacheable cycles
1555system.l2c.overall_mshr_uncacheable_latency::total 1508409000 # number of overall MSHR uncacheable cycles
1556system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1557system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses

1558system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001585 # mshr miss rate for UpgradeReq accesses
1559system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000424 # mshr miss rate for UpgradeReq accesses
1560system.l2c.UpgradeReq_mshr_miss_rate::total 0.001089 # mshr miss rate for UpgradeReq accesses
1561system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476210 # mshr miss rate for ReadExReq accesses
1562system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129173 # mshr miss rate for ReadExReq accesses
1563system.l2c.ReadExReq_mshr_miss_rate::total 0.417756 # mshr miss rate for ReadExReq accesses
1564system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for ReadCleanReq accesses
1565system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for ReadCleanReq accesses
1566system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013162 # mshr miss rate for ReadCleanReq accesses
1567system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290454 # mshr miss rate for ReadSharedReq accesses
1568system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003126 # mshr miss rate for ReadSharedReq accesses
1569system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260510 # mshr miss rate for ReadSharedReq accesses
1570system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for demand accesses
1571system.l2c.demand_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for demand accesses
1572system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for demand accesses
1573system.l2c.demand_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for demand accesses
1574system.l2c.demand_mshr_miss_rate::total 0.173230 # mshr miss rate for demand accesses
1575system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for overall accesses
1576system.l2c.overall_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for overall accesses
1577system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for overall accesses
1578system.l2c.overall_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for overall accesses
1579system.l2c.overall_mshr_miss_rate::total 0.173230 # mshr miss rate for overall accesses

1558system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001584 # mshr miss rate for UpgradeReq accesses
1559system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000419 # mshr miss rate for UpgradeReq accesses
1560system.l2c.UpgradeReq_mshr_miss_rate::total 0.001082 # mshr miss rate for UpgradeReq accesses
1561system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476164 # mshr miss rate for ReadExReq accesses
1562system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129142 # mshr miss rate for ReadExReq accesses
1563system.l2c.ReadExReq_mshr_miss_rate::total 0.417700 # mshr miss rate for ReadExReq accesses
1564system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for ReadCleanReq accesses
1565system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for ReadCleanReq accesses
1566system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013161 # mshr miss rate for ReadCleanReq accesses
1567system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290461 # mshr miss rate for ReadSharedReq accesses
1568system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003116 # mshr miss rate for ReadSharedReq accesses
1569system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260506 # mshr miss rate for ReadSharedReq accesses
1570system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for demand accesses
1571system.l2c.demand_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for demand accesses
1572system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for demand accesses
1573system.l2c.demand_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for demand accesses
1574system.l2c.demand_mshr_miss_rate::total 0.173209 # mshr miss rate for demand accesses
1575system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for overall accesses
1576system.l2c.overall_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for overall accesses
1577system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for overall accesses
1578system.l2c.overall_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for overall accesses
1579system.l2c.overall_mshr_miss_rate::total 0.173209 # mshr miss rate for overall accesses

1580system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency
1581system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency
1582system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency

1583system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency
1584system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency
1585system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency
1586system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency
1587system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency
1588system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency
1589system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency
1590system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency
1591system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency
1592system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency
1593system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency
1594system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency
1595system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency
1596system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency
1597system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency
1598system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency
1599system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency
1600system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency
1601system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency

1583system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80939.978256 # average ReadExReq mshr miss latency
1584system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92736.563328 # average ReadExReq mshr miss latency
1585system.l2c.ReadExReq_avg_mshr_miss_latency::total 81554.432588 # average ReadExReq mshr miss latency
1586system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average ReadCleanReq mshr miss latency
1587system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average ReadCleanReq mshr miss latency
1588system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92885.159800 # average ReadCleanReq mshr miss latency
1589system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70825.841476 # average ReadSharedReq mshr miss latency
1590system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113205.014749 # average ReadSharedReq mshr miss latency
1591system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70878.687614 # average ReadSharedReq mshr miss latency
1592system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency
1593system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency
1594system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency
1595system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency
1596system.l2c.demand_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency
1597system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency
1598system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency
1599system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency
1600system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency
1601system.l2c.overall_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency

1602system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency
1603system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency
1604system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency
1605system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency
1606system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency
1607system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency

1608system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter.
1609system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1610system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

1608system.membus.snoop_filter.tot_requests 856478 # Total number of requests made to the snoop filter.
1609system.membus.snoop_filter.hit_single_requests 407046 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1610system.membus.snoop_filter.hit_multi_requests 512 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

1611system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1612system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1613system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1614system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states

1614system.membus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states

1615system.membus.trans_dist::ReadReq 7198 # Transaction distribution

1616system.membus.trans_dist::ReadResp 292654 # Transaction distribution

1616system.membus.trans_dist::ReadResp 292655 # Transaction distribution

1617system.membus.trans_dist::WriteReq 14123 # Transaction distribution
1618system.membus.trans_dist::WriteResp 14123 # Transaction distribution

1619system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution
1620system.membus.trans_dist::CleanEvict 262335 # Transaction distribution
1621system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution
1622system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution

1619system.membus.trans_dist::WritebackDirty 121475 # Transaction distribution
1620system.membus.trans_dist::CleanEvict 262336 # Transaction distribution
1621system.membus.trans_dist::UpgradeReq 11690 # Transaction distribution
1622system.membus.trans_dist::SCUpgradeReq 9942 # Transaction distribution

1623system.membus.trans_dist::UpgradeResp 3 # Transaction distribution

1624system.membus.trans_dist::ReadExReq 123969 # Transaction distribution
1625system.membus.trans_dist::ReadExResp 123101 # Transaction distribution
1626system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution

1624system.membus.trans_dist::ReadExReq 123955 # Transaction distribution
1625system.membus.trans_dist::ReadExResp 123087 # Transaction distribution
1626system.membus.trans_dist::ReadSharedReq 285457 # Transaction distribution

1627system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution

1628system.membus.trans_dist::InvalidateResp 148 # Transaction distribution

1628system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes)

1629system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes)

1629system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes)
1630system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes)

1630system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181082 # Packet count per connected master and slave (bytes)
1631system.membus.pkt_count_system.l2c.mem_side::total 1223724 # Packet count per connected master and slave (bytes)

1631system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes)
1632system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes)

1632system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes)
1633system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes)

1633system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes)

1634system.membus.pkt_count::total 1307167 # Packet count per connected master and slave (bytes)

1634system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes)

1635system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes)

1635system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes)
1636system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes)

1636system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235712 # Cumulative packet size per connected master and slave (bytes)
1637system.membus.pkt_size_system.l2c.mem_side::total 31318106 # Cumulative packet size per connected master and slave (bytes)

1637system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
1638system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)

1638system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
1639system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)

1639system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes)
1640system.membus.snoops 22774 # Total snoops (count)

1640system.membus.pkt_size::total 33976346 # Cumulative packet size per connected master and slave (bytes)
1641system.membus.snoops 22923 # Total snoops (count)

1641system.membus.snoopTraffic 27264 # Total snoop traffic (bytes)

1642system.membus.snoopTraffic 27264 # Total snoop traffic (bytes)

1642system.membus.snoop_fanout::samples 493929 # Request fanout histogram
1643system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram
1644system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram

1643system.membus.snoop_fanout::samples 493917 # Request fanout histogram
1644system.membus.snoop_fanout::mean 0.001373 # Request fanout histogram
1645system.membus.snoop_fanout::stdev 0.037025 # Request fanout histogram

1645system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1646system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1646system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram
1647system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram

1647system.membus.snoop_fanout::0 493239 99.86% 99.86% # Request fanout histogram
1648system.membus.snoop_fanout::1 678 0.14% 100.00% # Request fanout histogram

1648system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1649system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1650system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1651system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1649system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1650system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1651system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1652system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1652system.membus.snoop_fanout::total 493929 # Request fanout histogram
1653system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks)

1653system.membus.snoop_fanout::total 493917 # Request fanout histogram
1654system.membus.reqLayer0.occupancy 40493500 # Layer occupancy (ticks)

1654system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)

1655system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)

1655system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks)

1656system.membus.reqLayer1.occupancy 1322925099 # Layer occupancy (ticks)

1656system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)

1657system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)

1657system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks)

1658system.membus.respLayer1.occupancy 2182236750 # Layer occupancy (ticks)

1658system.membus.respLayer1.utilization 0.1 # Layer utilization (%)

1659system.membus.respLayer1.utilization 0.1 # Layer utilization (%)

1659system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks)

1660system.membus.respLayer2.occupancy 1074598 # Layer occupancy (ticks)

1660system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

1661system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

1661system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1662system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter.
1663system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1664system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1665system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter.
1666system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

1662system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1663system.toL2Bus.snoop_filter.tot_requests 4789722 # Total number of requests made to the snoop filter.
1664system.toL2Bus.snoop_filter.hit_single_requests 2388089 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1665system.toL2Bus.snoop_filter.hit_multi_requests 374620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1666system.toL2Bus.snoop_filter.tot_snoops 991 # Total number of snoops made to the snoop filter.
1667system.toL2Bus.snoop_filter.hit_single_snoops 930 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

1667system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1668system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1668system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states

1669system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states

1669system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution

1670system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution

1670system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution

1671system.toL2Bus.trans_dist::ReadResp 2107102 # Transaction distribution

1671system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution
1672system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution

1672system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution
1673system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution

1673system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution
1674system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution
1675system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution
1676system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution
1677system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution
1678system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution
1679system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution
1680system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution
1681system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution
1682system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution

1674system.toL2Bus.trans_dist::WritebackDirty 872860 # Transaction distribution
1675system.toL2Bus.trans_dist::WritebackClean 1018728 # Transaction distribution
1676system.toL2Bus.trans_dist::CleanEvict 815346 # Transaction distribution
1677system.toL2Bus.trans_dist::UpgradeReq 17080 # Transaction distribution
1678system.toL2Bus.trans_dist::SCUpgradeReq 11845 # Transaction distribution
1679system.toL2Bus.trans_dist::UpgradeResp 28925 # Transaction distribution
1680system.toL2Bus.trans_dist::ReadExReq 297046 # Transaction distribution
1681system.toL2Bus.trans_dist::ReadExResp 297046 # Transaction distribution
1682system.toL2Bus.trans_dist::ReadCleanReq 1019917 # Transaction distribution
1683system.toL2Bus.trans_dist::ReadSharedReq 1079990 # Transaction distribution

1683system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution

1684system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution

1684system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes)
1685system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes)
1686system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes)
1687system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes)
1688system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes)
1689system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes)
1690system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes)
1691system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes)
1692system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes)
1693system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes)
1694system.toL2Bus.snoops 403246 # Total snoops (count)
1695system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes)
1696system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram
1697system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram
1698system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram

1685system.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution
1686system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077759 # Packet count per connected master and slave (bytes)
1687system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616208 # Packet count per connected master and slave (bytes)
1688system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980781 # Packet count per connected master and slave (bytes)
1689system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523727 # Packet count per connected master and slave (bytes)
1690system.toL2Bus.pkt_count::total 7198475 # Packet count per connected master and slave (bytes)
1691system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88636992 # Cumulative packet size per connected master and slave (bytes)
1692system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119193988 # Cumulative packet size per connected master and slave (bytes)
1693system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41834880 # Cumulative packet size per connected master and slave (bytes)
1694system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17315286 # Cumulative packet size per connected master and slave (bytes)
1695system.toL2Bus.pkt_size::total 266981146 # Cumulative packet size per connected master and slave (bytes)
1696system.toL2Bus.snoops 403271 # Total snoops (count)
1697system.toL2Bus.snoopTraffic 7578112 # Total snoop traffic (bytes)
1698system.toL2Bus.snoop_fanout::samples 2790369 # Request fanout histogram
1699system.toL2Bus.snoop_fanout::mean 0.143087 # Request fanout histogram
1700system.toL2Bus.snoop_fanout::stdev 0.350419 # Request fanout histogram

1699system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1701system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

1700system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram
1701system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram
1702system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram

1702system.toL2Bus.snoop_fanout::0 2391353 85.70% 85.70% # Request fanout histogram
1703system.toL2Bus.snoop_fanout::1 398767 14.29% 99.99% # Request fanout histogram
1704system.toL2Bus.snoop_fanout::2 248 0.01% 100.00% # Request fanout histogram

1703system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram
1704system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1705system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1706system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1707system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

1705system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram
1706system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1707system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1708system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1709system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

1708system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram
1709system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks)

1710system.toL2Bus.snoop_fanout::total 2790369 # Request fanout histogram
1711system.toL2Bus.reqLayer0.occupancy 4224217497 # Layer occupancy (ticks)

1710system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)

1712system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)

1711system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks)

1713system.toL2Bus.snoopLayer0.occupancy 304383 # Layer occupancy (ticks)

1712system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

1714system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)

1713system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks)

1715system.toL2Bus.respLayer0.occupancy 1039374668 # Layer occupancy (ticks)

1714system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1716system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1715system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks)

1717system.toL2Bus.respLayer1.occupancy 1817986111 # Layer occupancy (ticks)

1716system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)

1718system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)

1717system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks)

1719system.toL2Bus.respLayer2.occupancy 491891046 # Layer occupancy (ticks)

1718system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)

1720system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)

1719system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks)

1721system.toL2Bus.respLayer3.occupancy 276353266 # Layer occupancy (ticks)

1720system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

1722system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

1721system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1722system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1723system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1724system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states

1723system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1724system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1725system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1726system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states

1725system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1726system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1727system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1728system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1729system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1730system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1731system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1732system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

1748system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1749system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1750system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1751system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1752system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1753system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1754system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1755system.tsunami.ethernet.droppedPackets 0 # number of packets dropped

1727system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1728system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1729system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1730system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1731system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1732system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1733system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1734system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

1750system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1751system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1752system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1753system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1754system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1755system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1756system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1757system.tsunami.ethernet.droppedPackets 0 # number of packets dropped

1756system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1757system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1758system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1759system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1760system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1761system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1762system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1763system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1764system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1765system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1766system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1767system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1768system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1769system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1770system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1771system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1772system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1773system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1774system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1775system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1776system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1777system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states
1778system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states

1758system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1759system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1760system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1761system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1762system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1763system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1764system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1765system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1766system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1767system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1768system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1769system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1770system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1771system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1772system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1773system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1774system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1775system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1776system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1777system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1778system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1779system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states
1780system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states