| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.963613 # Number of seconds simulated 4sim_ticks 1963612574000 # Number of ticks simulated 5final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.963613 # Number of seconds simulated 4sim_ticks 1963612574000 # Number of ticks simulated 5final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 993881 # Simulator instruction rate (inst/s) 8host_op_rate 993880 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32036346352 # Simulator tick rate (ticks/s) 10host_mem_usage 331076 # Number of bytes of host memory used 11host_seconds 61.29 # Real time elapsed on the host | 7host_inst_rate 1460699 # Simulator instruction rate (inst/s) 8host_op_rate 1460699 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47083590827 # Simulator tick rate (ticks/s) 10host_mem_usage 378804 # Number of bytes of host memory used 11host_seconds 41.70 # Real time elapsed on the host |
| 12sim_insts 60918165 # Number of instructions simulated 13sim_ops 60918165 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 60918165 # Number of instructions simulated 13sim_ops 60918165 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory --- 281 unchanged lines hidden (view full) --- 305system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ) 306system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ) 307system.physmem_1.averagePower 670.691088 # Core power per rank (mW) 308system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states 309system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states 310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 311system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states 312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory 21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory --- 281 unchanged lines hidden (view full) --- 306system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ) 308system.physmem_1.averagePower 670.691088 # Core power per rank (mW) 309system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states 310system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 312system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 314system.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 315system.bridge.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 313system.cpu_clk_domain.clock 500 # Clock period in ticks 314system.cpu0.dtb.fetch_hits 0 # ITB hits 315system.cpu0.dtb.fetch_misses 0 # ITB misses 316system.cpu0.dtb.fetch_acv 0 # ITB acv 317system.cpu0.dtb.fetch_accesses 0 # ITB accesses 318system.cpu0.dtb.read_hits 7494168 # DTB read hits 319system.cpu0.dtb.read_misses 7443 # DTB read misses 320system.cpu0.dtb.read_acv 210 # DTB read access violations --- 17 unchanged lines hidden (view full) --- 338system.cpu0.itb.write_hits 0 # DTB write hits 339system.cpu0.itb.write_misses 0 # DTB write misses 340system.cpu0.itb.write_acv 0 # DTB write access violations 341system.cpu0.itb.write_accesses 0 # DTB write accesses 342system.cpu0.itb.data_hits 0 # DTB hits 343system.cpu0.itb.data_misses 0 # DTB misses 344system.cpu0.itb.data_acv 0 # DTB access violations 345system.cpu0.itb.data_accesses 0 # DTB accesses | 316system.cpu_clk_domain.clock 500 # Clock period in ticks 317system.cpu0.dtb.fetch_hits 0 # ITB hits 318system.cpu0.dtb.fetch_misses 0 # ITB misses 319system.cpu0.dtb.fetch_acv 0 # ITB acv 320system.cpu0.dtb.fetch_accesses 0 # ITB accesses 321system.cpu0.dtb.read_hits 7494168 # DTB read hits 322system.cpu0.dtb.read_misses 7443 # DTB read misses 323system.cpu0.dtb.read_acv 210 # DTB read access violations --- 17 unchanged lines hidden (view full) --- 341system.cpu0.itb.write_hits 0 # DTB write hits 342system.cpu0.itb.write_misses 0 # DTB write misses 343system.cpu0.itb.write_acv 0 # DTB write access violations 344system.cpu0.itb.write_accesses 0 # DTB write accesses 345system.cpu0.itb.data_hits 0 # DTB hits 346system.cpu0.itb.data_misses 0 # DTB misses 347system.cpu0.itb.data_acv 0 # DTB access violations 348system.cpu0.itb.data_accesses 0 # DTB accesses |
| 349system.cpu0.numPwrStateTransitions 13591 # Number of power state transitions 350system.cpu0.pwrStateClkGateDist::samples 6796 # Distribution of time spent in the clock gated state 351system.cpu0.pwrStateClkGateDist::mean 272307750.367863 # Distribution of time spent in the clock gated state 352system.cpu0.pwrStateClkGateDist::stdev 432682187.397928 # Distribution of time spent in the clock gated state 353system.cpu0.pwrStateClkGateDist::1000-5e+10 6796 100.00% 100.00% # Distribution of time spent in the clock gated state 354system.cpu0.pwrStateClkGateDist::min_value 55000 # Distribution of time spent in the clock gated state 355system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 356system.cpu0.pwrStateClkGateDist::total 6796 # Distribution of time spent in the clock gated state 357system.cpu0.pwrStateResidencyTicks::ON 113009102500 # Cumulative time (in ticks) in various power states 358system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850603471500 # Cumulative time (in ticks) in various power states |
|
| 346system.cpu0.numCycles 3925790590 # number of cpu cycles simulated 347system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 348system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 349system.cpu0.kern.inst.arm 0 # number of arm instructions executed 350system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed 351system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed 352system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl 353system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl --- 131 unchanged lines hidden (view full) --- 485system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction 486system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction 487system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction 488system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction 489system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction 490system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction 491system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 492system.cpu0.op_class::total 47764191 # Class of executed instruction | 359system.cpu0.numCycles 3925790590 # number of cpu cycles simulated 360system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 361system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 362system.cpu0.kern.inst.arm 0 # number of arm instructions executed 363system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed 364system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed 365system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl 366system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl --- 131 unchanged lines hidden (view full) --- 498system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction 499system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction 500system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction 501system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction 502system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction 503system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction 504system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 505system.cpu0.op_class::total 47764191 # Class of executed instruction |
| 506system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 493system.cpu0.dcache.tags.replacements 1179864 # number of replacements 494system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use 495system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks. 496system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks. 497system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks. 498system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. 499system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor 500system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy 501system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy 502system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id 503system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id 504system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 505system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 506system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses 507system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses | 507system.cpu0.dcache.tags.replacements 1179864 # number of replacements 508system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use 509system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks. 510system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks. 511system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks. 512system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. 513system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor 514system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy 515system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy 516system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id 517system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id 518system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 519system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 520system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses 521system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses |
| 522system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 508system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits 509system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits 510system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits 511system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits 512system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits 513system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits 514system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits 515system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits --- 126 unchanged lines hidden (view full) --- 642system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency 643system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency 644system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency 645system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency 646system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency 647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency 648system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency 649system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency | 523system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits 524system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits 525system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits 526system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits 527system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits 528system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits 529system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits 530system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits --- 126 unchanged lines hidden (view full) --- 657system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency 658system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency 659system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency 660system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency 661system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency 662system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency 663system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency 664system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency |
| 665system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 650system.cpu0.icache.tags.replacements 698162 # number of replacements 651system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use 652system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks. 653system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks. 654system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks. 655system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit. 656system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor 657system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy 658system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy 659system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 660system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id 661system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 662system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 663system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses 664system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses | 666system.cpu0.icache.tags.replacements 698162 # number of replacements 667system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use 668system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks. 669system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks. 670system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks. 671system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit. 672system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor 673system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy 674system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy 675system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 676system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id 677system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 678system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 679system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses 680system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses |
| 681system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 665system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits 666system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits 667system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits 668system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits 669system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits 670system.cpu0.icache.overall_hits::total 47065399 # number of overall hits 671system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses 672system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses --- 84 unchanged lines hidden (view full) --- 757system.cpu1.itb.write_hits 0 # DTB write hits 758system.cpu1.itb.write_misses 0 # DTB write misses 759system.cpu1.itb.write_acv 0 # DTB write access violations 760system.cpu1.itb.write_accesses 0 # DTB write accesses 761system.cpu1.itb.data_hits 0 # DTB hits 762system.cpu1.itb.data_misses 0 # DTB misses 763system.cpu1.itb.data_acv 0 # DTB access violations 764system.cpu1.itb.data_accesses 0 # DTB accesses | 682system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits 683system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits 684system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits 685system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits 686system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits 687system.cpu0.icache.overall_hits::total 47065399 # number of overall hits 688system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses 689system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses --- 84 unchanged lines hidden (view full) --- 774system.cpu1.itb.write_hits 0 # DTB write hits 775system.cpu1.itb.write_misses 0 # DTB write misses 776system.cpu1.itb.write_acv 0 # DTB write access violations 777system.cpu1.itb.write_accesses 0 # DTB write accesses 778system.cpu1.itb.data_hits 0 # DTB hits 779system.cpu1.itb.data_misses 0 # DTB misses 780system.cpu1.itb.data_acv 0 # DTB access violations 781system.cpu1.itb.data_accesses 0 # DTB accesses |
| 782system.cpu1.numPwrStateTransitions 5480 # Number of power state transitions 783system.cpu1.pwrStateClkGateDist::samples 2740 # Distribution of time spent in the clock gated state 784system.cpu1.pwrStateClkGateDist::mean 707616074.452555 # Distribution of time spent in the clock gated state 785system.cpu1.pwrStateClkGateDist::stdev 409900069.702285 # Distribution of time spent in the clock gated state 786system.cpu1.pwrStateClkGateDist::1000-5e+10 2740 100.00% 100.00% # Distribution of time spent in the clock gated state 787system.cpu1.pwrStateClkGateDist::min_value 76500 # Distribution of time spent in the clock gated state 788system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state 789system.cpu1.pwrStateClkGateDist::total 2740 # Distribution of time spent in the clock gated state 790system.cpu1.pwrStateResidencyTicks::ON 24744530000 # Cumulative time (in ticks) in various power states 791system.cpu1.pwrStateResidencyTicks::CLK_GATED 1938868044000 # Cumulative time (in ticks) in various power states |
|
| 765system.cpu1.numCycles 3927225148 # number of cpu cycles simulated 766system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 767system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 768system.cpu1.kern.inst.arm 0 # number of arm instructions executed 769system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed 770system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed 771system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl 772system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl --- 110 unchanged lines hidden (view full) --- 883system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction 884system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction 885system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction 886system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction 887system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction 888system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction 889system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 890system.cpu1.op_class::total 13165936 # Class of executed instruction | 792system.cpu1.numCycles 3927225148 # number of cpu cycles simulated 793system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 794system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 795system.cpu1.kern.inst.arm 0 # number of arm instructions executed 796system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed 797system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed 798system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl 799system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl --- 110 unchanged lines hidden (view full) --- 910system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction 911system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction 912system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction 913system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction 914system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction 915system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction 916system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 917system.cpu1.op_class::total 13165936 # Class of executed instruction |
| 918system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 891system.cpu1.dcache.tags.replacements 166516 # number of replacements 892system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use 893system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks. 894system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks. 895system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks. 896system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit. 897system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor 898system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy 899system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy 900system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 901system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 902system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 903system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id 904system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 905system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses 906system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses | 919system.cpu1.dcache.tags.replacements 166516 # number of replacements 920system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use 921system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks. 922system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks. 923system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks. 924system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit. 925system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor 926system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy 927system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy 928system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 929system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 930system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 931system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id 932system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 933system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses 934system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses |
| 935system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 907system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits 908system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits 909system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits 910system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits 911system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits 912system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits 913system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits 914system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits --- 134 unchanged lines hidden (view full) --- 1049system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency 1050system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency 1051system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency 1052system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency 1053system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency 1054system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency 1055system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency 1056system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency | 936system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits 937system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits 938system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits 939system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits 940system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits 941system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits 942system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits 943system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits --- 134 unchanged lines hidden (view full) --- 1078system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency 1079system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency 1080system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency 1081system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency 1082system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency 1083system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency 1084system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency 1085system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency |
| 1086system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1057system.cpu1.icache.tags.replacements 316153 # number of replacements 1058system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use 1059system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks. 1060system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks. 1061system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks. 1062system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit. 1063system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor 1064system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy 1065system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy 1066system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1067system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1068system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 1069system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id 1070system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1071system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1072system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses 1073system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses | 1087system.cpu1.icache.tags.replacements 316153 # number of replacements 1088system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use 1089system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks. 1090system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks. 1091system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks. 1092system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit. 1093system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor 1094system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy 1095system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy 1096system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1097system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1098system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 1099system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id 1100system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1101system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1102system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses 1103system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses |
| 1104system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1074system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits 1075system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits 1076system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits 1077system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits 1078system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits 1079system.cpu1.icache.overall_hits::total 12849230 # number of overall hits 1080system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses 1081system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1146system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1147system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1148system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1149system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1150system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1151system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1152system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1153system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 1105system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits 1106system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits 1107system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits 1108system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits 1109system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits 1110system.cpu1.icache.overall_hits::total 12849230 # number of overall hits 1111system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses 1112system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1177system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1178system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1179system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1180system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1181system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1182system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1183system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1184system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 1185system.iobus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1154system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1155system.iobus.trans_dist::ReadResp 7373 # Transaction distribution 1156system.iobus.trans_dist::WriteReq 55610 # Transaction distribution 1157system.iobus.trans_dist::WriteResp 55610 # Transaction distribution 1158system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) 1159system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) 1160system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1161system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 1200system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1201system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks) 1203system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1204system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) 1205system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1206system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) 1207system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1186system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1187system.iobus.trans_dist::ReadResp 7373 # Transaction distribution 1188system.iobus.trans_dist::WriteReq 55610 # Transaction distribution 1189system.iobus.trans_dist::WriteResp 55610 # Transaction distribution 1190system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 38 unchanged lines hidden (view full) --- 1232system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1233system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1234system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks) 1235system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1236system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) 1237system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1238system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) 1239system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1240system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1208system.iocache.tags.replacements 41694 # number of replacements 1209system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use 1210system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1211system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. 1212system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1213system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit. 1214system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor 1215system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy 1216system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy 1217system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1218system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1219system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1220system.iocache.tags.tag_accesses 375534 # Number of tag accesses 1221system.iocache.tags.data_accesses 375534 # Number of data accesses | 1241system.iocache.tags.replacements 41694 # number of replacements 1242system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use 1243system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1244system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. 1245system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1246system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit. 1247system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor 1248system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy 1249system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy 1250system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1251system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1252system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1253system.iocache.tags.tag_accesses 375534 # Number of tag accesses 1254system.iocache.tags.data_accesses 375534 # Number of data accesses |
| 1255system.iocache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1222system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 1223system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 1224system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1225system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1226system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 1227system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 1228system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 1229system.iocache.overall_misses::total 41726 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1294system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency 1295system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency 1296system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency 1297system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency 1298system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency 1299system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency 1300system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency 1301system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency | 1256system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 1257system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 1258system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1259system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1260system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 1261system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 1262system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 1263system.iocache.overall_misses::total 41726 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1328system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency 1329system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency 1330system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency 1331system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency 1332system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency 1333system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency 1334system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency 1335system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency |
| 1336system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1302system.l2c.tags.replacements 341504 # number of replacements 1303system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use 1304system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks. 1305system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks. 1306system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks. 1307system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit. 1308system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor 1309system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor --- 10 unchanged lines hidden (view full) --- 1320system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 1321system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id 1322system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id 1323system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id 1324system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id 1325system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id 1326system.l2c.tags.tag_accesses 35882279 # Number of tag accesses 1327system.l2c.tags.data_accesses 35882279 # Number of data accesses | 1337system.l2c.tags.replacements 341504 # number of replacements 1338system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use 1339system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks. 1340system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks. 1341system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks. 1342system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit. 1343system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor 1344system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor --- 10 unchanged lines hidden (view full) --- 1355system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 1356system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id 1357system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id 1358system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id 1359system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id 1360system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id 1361system.l2c.tags.tag_accesses 35882279 # Number of tag accesses 1362system.l2c.tags.data_accesses 35882279 # Number of data accesses |
| 1363system.l2c.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1328system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits 1329system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits 1330system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits 1331system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits 1332system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits 1333system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits 1334system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits 1335system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits --- 287 unchanged lines hidden (view full) --- 1623system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency 1624system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency 1625system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter. 1626system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1627system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1628system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1629system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1630system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1364system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits 1365system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits 1366system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits 1367system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits 1368system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits 1369system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits 1370system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits 1371system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits --- 287 unchanged lines hidden (view full) --- 1659system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency 1660system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency 1661system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter. 1662system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1663system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1664system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1665system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1666system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1667system.membus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1631system.membus.trans_dist::ReadReq 7199 # Transaction distribution 1632system.membus.trans_dist::ReadResp 292676 # Transaction distribution 1633system.membus.trans_dist::WriteReq 14058 # Transaction distribution 1634system.membus.trans_dist::WriteResp 14058 # Transaction distribution 1635system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution 1636system.membus.trans_dist::CleanEvict 261938 # Transaction distribution 1637system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution 1638system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution --- 29 unchanged lines hidden (view full) --- 1668system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks) 1669system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1670system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks) 1671system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1672system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks) 1673system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1674system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks) 1675system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1668system.membus.trans_dist::ReadReq 7199 # Transaction distribution 1669system.membus.trans_dist::ReadResp 292676 # Transaction distribution 1670system.membus.trans_dist::WriteReq 14058 # Transaction distribution 1671system.membus.trans_dist::WriteResp 14058 # Transaction distribution 1672system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution 1673system.membus.trans_dist::CleanEvict 261938 # Transaction distribution 1674system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution 1675system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution --- 29 unchanged lines hidden (view full) --- 1705system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks) 1706system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1707system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks) 1708system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1709system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks) 1710system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1711system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks) 1712system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1713system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1676system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter. 1677system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1678system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1679system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter. 1680system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1681system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1714system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter. 1715system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1716system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1717system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter. 1718system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1719system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1720system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1682system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution 1683system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution 1684system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution 1685system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution 1686system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution 1687system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution 1688system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution 1689system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1727system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks) 1728system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1729system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks) 1730system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1731system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks) 1732system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1733system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks) 1734system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1721system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution 1722system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution 1723system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution 1724system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution 1725system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution 1726system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution 1727system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution 1728system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1766system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks) 1767system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1768system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks) 1769system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1770system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks) 1771system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1772system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks) 1773system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1774system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1775system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1776system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1777system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1735system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1736system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1737system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1738system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1739system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1740system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1741system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1742system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1758system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1759system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1760system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1761system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1762system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1763system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1764system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1765system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 1778system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1779system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1780system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1781system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1782system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1783system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1784system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1785system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1801system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1802system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1803system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1804system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1805system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1806system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1807system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1808system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1809system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1810system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1811system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1812system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1813system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1814system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1815system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1816system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1817system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1818system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1819system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1820system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1821system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1822system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1823system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1824system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1825system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1826system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1827system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1828system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1829system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1830system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1831system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states |
|
| 1766 1767---------- End Simulation Statistics ---------- | 1832 1833---------- End Simulation Statistics ---------- |