| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.962608 # Number of seconds simulated 4sim_ticks 1962608482500 # Number of ticks simulated 5final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.982585 # Number of seconds simulated 4sim_ticks 1982585357000 # Number of ticks simulated 5final_tick 1982585357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1019388 # Simulator instruction rate (inst/s) 8host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32859851956 # Simulator tick rate (ticks/s) 10host_mem_usage 375280 # Number of bytes of host memory used 11host_seconds 59.73 # Real time elapsed on the host 12sim_insts 60884587 # Number of instructions simulated 13sim_ops 60884587 # Number of ops (including micro ops) simulated | 7host_inst_rate 1043358 # Simulator instruction rate (inst/s) 8host_op_rate 1043358 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33918612914 # Simulator tick rate (ticks/s) 10host_mem_usage 377952 # Number of bytes of host memory used 11host_seconds 58.45 # Real time elapsed on the host 12sim_insts 60985541 # Number of instructions simulated 13sim_ops 60985541 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.inst 804544 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24689088 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 59456 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 522432 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory | 21system.physmem.bytes_read::total 26076480 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 804544 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 59456 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 864000 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7738240 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7738240 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 12571 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 385767 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 929 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 8163 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 406729 # Number of read requests accepted 54system.physmem.writeReqs 120393 # Number of write requests accepted 55system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue | 32system.physmem.num_reads::total 407445 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120910 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120910 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 405805 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12452976 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 29989 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 263510 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13152765 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 405805 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 29989 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 435795 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3903106 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3903106 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3903106 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 405805 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12452976 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 29989 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 263510 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17055871 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 407445 # Number of read requests accepted 54system.physmem.writeReqs 120910 # Number of write requests accepted 55system.physmem.readBursts 407445 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 120910 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26068672 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7736640 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26076480 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7738240 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue |
| 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 64system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25025 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25421 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25447 # Per bank write bursts 68system.physmem.perBankRdBursts::3 24899 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25181 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25235 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25799 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25539 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25681 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25348 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25259 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25592 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25653 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25554 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25887 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25094 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7701 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7641 # Per bank write bursts 83system.physmem.perBankWrBursts::2 7454 # Per bank write bursts 84system.physmem.perBankWrBursts::3 6926 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7165 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7117 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7626 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7252 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7527 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7238 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7225 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7418 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7843 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8207 # Per bank write bursts 95system.physmem.perBankWrBursts::14 8447 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7584 # Per bank write bursts | 64system.physmem.neitherReadNorWriteReqs 48696 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25232 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25377 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25433 # Per bank write bursts 68system.physmem.perBankRdBursts::3 24853 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25156 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25421 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25501 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25341 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25248 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25578 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25745 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25922 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25991 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25558 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25312 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25655 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7850 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7774 # Per bank write bursts 83system.physmem.perBankWrBursts::2 7467 # Per bank write bursts 84system.physmem.perBankWrBursts::3 6887 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7102 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7345 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7434 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7145 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7156 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7306 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7741 # Per bank write bursts 92system.physmem.perBankWrBursts::11 8153 # Per bank write bursts 93system.physmem.perBankWrBursts::12 8257 # Per bank write bursts 94system.physmem.perBankWrBursts::13 7909 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7539 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7820 # Per bank write bursts |
| 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 98system.physmem.numWrRetry 20 # Number of times write queue was full causing retry 99system.physmem.totGap 1962561950500 # Total gap between requests | 98system.physmem.numWrRetry 21 # Number of times write queue was full causing retry 99system.physmem.totGap 1982577992500 # Total gap between requests |
| 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) | 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 106system.physmem.readPktSize::6 406729 # Read request sizes (log2) | 106system.physmem.readPktSize::6 407445 # Read request sizes (log2) |
| 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) | 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 113system.physmem.writePktSize::6 120393 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see | 113system.physmem.writePktSize::6 120910 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 407244 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see |
| 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes | 161system.physmem.wrQLenPdf::15 1841 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 2227 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 5744 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 5781 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 6325 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6708 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 6144 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 6527 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 7869 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 8351 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 9333 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8456 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 8729 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7617 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 6920 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 6325 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 5922 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 5590 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 178 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 209 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 201 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 120 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 195 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 174 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 170 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 148 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 116 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 95 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 138 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 86 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 94 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 67564 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 500.345036 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 302.441164 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 405.330516 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 16348 24.20% 24.20% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12278 18.17% 42.37% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5298 7.84% 50.21% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3150 4.66% 54.87% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2433 3.60% 58.47% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 4298 6.36% 64.83% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1531 2.27% 67.10% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 2195 3.25% 70.35% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 20033 29.65% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 67564 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5409 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 75.303198 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2854.593157 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5406 99.94% 99.94% # Reads before turning the bus around for writes |
| 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes | 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 231system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads 265system.physmem.totQLat 2204423500 # Total ticks spent queuing 266system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst | 231system.physmem.rdPerTurnAround::total 5409 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5409 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.348863 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.981514 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 21.757339 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 4806 88.85% 88.85% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 190 3.51% 92.36% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 24 0.44% 92.81% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 50 0.92% 93.73% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 37 0.68% 94.42% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 6 0.11% 94.53% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 18 0.33% 94.86% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 42 0.78% 95.64% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 29 0.54% 96.17% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 3 0.06% 96.23% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 162 3.00% 99.22% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 1 0.02% 99.24% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::128-135 4 0.07% 99.32% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::136-143 3 0.06% 99.37% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::144-151 2 0.04% 99.41% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::152-159 2 0.04% 99.45% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::160-167 4 0.07% 99.52% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::168-175 6 0.11% 99.63% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::176-183 10 0.18% 99.82% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::184-191 2 0.04% 99.85% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::208-215 2 0.04% 99.89% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::224-231 4 0.07% 99.96% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::312-319 1 0.02% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::total 5409 # Writes before turning the bus around for reads 261system.physmem.totQLat 2792890500 # Total ticks spent queuing 262system.physmem.totMemAccLat 10430196750 # Total ticks spent from burst creation until serviced by the DRAM 263system.physmem.totBusLat 2036615000 # Total ticks spent in databus transfers 264system.physmem.avgQLat 6856.70 # Average queueing delay per DRAM burst |
| 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 265system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 270system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst 271system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s 273system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s 274system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s | 266system.physmem.avgMemAccLat 25606.70 # Average memory access latency per DRAM burst 267system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s 268system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s 269system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s 270system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s |
| 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.13 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 271system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 272system.physmem.busUtil 0.13 # Data bus utilization in percentage 273system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 274system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 275system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 280system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing 281system.physmem.readRowHits 363741 # Number of row buffer hits during reads 282system.physmem.writeRowHits 96228 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes 285system.physmem.avgGap 3723164.56 # Average gap between requests 286system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined 287system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ) 288system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ) 289system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ) 290system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ) 291system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) 292system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ) 293system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ) 294system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ) 295system.physmem_0.averagePower 670.630269 # Core power per rank (mW) 296system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states 297system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states | 276system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing 277system.physmem.readRowHits 363877 # Number of row buffer hits during reads 278system.physmem.writeRowHits 96767 # Number of row buffer hits during writes 279system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads 280system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes 281system.physmem.avgGap 3752359.67 # Average gap between requests 282system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined 283system.physmem_0.actEnergy 243303480 # Energy for activate commands per rank (pJ) 284system.physmem_0.preEnergy 132754875 # Energy for precharge commands per rank (pJ) 285system.physmem_0.readEnergy 1578049200 # Energy for read commands per rank (pJ) 286system.physmem_0.writeEnergy 382345920 # Energy for write commands per rank (pJ) 287system.physmem_0.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) 288system.physmem_0.actBackEnergy 72929786580 # Energy for active background per rank (pJ) 289system.physmem_0.preBackEnergy 1125575674500 # Energy for precharge background per rank (pJ) 290system.physmem_0.totalEnergy 1330334513115 # Total energy per rank (pJ) 291system.physmem_0.averagePower 671.011108 # Core power per rank (mW) 292system.physmem_0.memoryStateTime::IDLE 1872213779250 # Time in different power states 293system.physmem_0.memoryStateTime::REF 66202760000 # Time in different power states |
| 298system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 294system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 299system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states | 295system.physmem_0.memoryStateTime::ACT 44165427000 # Time in different power states |
| 300system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 296system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 301system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ) 302system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ) 303system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ) 304system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ) 305system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ) 306system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ) 307system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ) 308system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ) 309system.physmem_1.averagePower 670.683332 # Core power per rank (mW) 310system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states 311system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states | 297system.physmem_1.actEnergy 267480360 # Energy for activate commands per rank (pJ) 298system.physmem_1.preEnergy 145946625 # Energy for precharge commands per rank (pJ) 299system.physmem_1.readEnergy 1599070200 # Energy for read commands per rank (pJ) 300system.physmem_1.writeEnergy 400988880 # Energy for write commands per rank (pJ) 301system.physmem_1.refreshEnergy 129492598560 # Energy for refresh commands per rank (pJ) 302system.physmem_1.actBackEnergy 74043413820 # Energy for active background per rank (pJ) 303system.physmem_1.preBackEnergy 1124598800250 # Energy for precharge background per rank (pJ) 304system.physmem_1.totalEnergy 1330548298695 # Total energy per rank (pJ) 305system.physmem_1.averagePower 671.118945 # Core power per rank (mW) 306system.physmem_1.memoryStateTime::IDLE 1870589115500 # Time in different power states 307system.physmem_1.memoryStateTime::REF 66202760000 # Time in different power states |
| 312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 308system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 313system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states | 309system.physmem_1.memoryStateTime::ACT 45790077000 # Time in different power states |
| 314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 315system.cpu_clk_domain.clock 500 # Clock period in ticks 316system.cpu0.dtb.fetch_hits 0 # ITB hits 317system.cpu0.dtb.fetch_misses 0 # ITB misses 318system.cpu0.dtb.fetch_acv 0 # ITB acv 319system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 310system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 311system.cpu_clk_domain.clock 500 # Clock period in ticks 312system.cpu0.dtb.fetch_hits 0 # ITB hits 313system.cpu0.dtb.fetch_misses 0 # ITB misses 314system.cpu0.dtb.fetch_acv 0 # ITB acv 315system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 320system.cpu0.dtb.read_hits 7500026 # DTB read hits 321system.cpu0.dtb.read_misses 7443 # DTB read misses | 316system.cpu0.dtb.read_hits 7416955 # DTB read hits 317system.cpu0.dtb.read_misses 7442 # DTB read misses |
| 322system.cpu0.dtb.read_acv 210 # DTB read access violations | 318system.cpu0.dtb.read_acv 210 # DTB read access violations |
| 323system.cpu0.dtb.read_accesses 490673 # DTB read accesses 324system.cpu0.dtb.write_hits 5074087 # DTB write hits 325system.cpu0.dtb.write_misses 813 # DTB write misses | 319system.cpu0.dtb.read_accesses 490672 # DTB read accesses 320system.cpu0.dtb.write_hits 5004564 # DTB write hits 321system.cpu0.dtb.write_misses 812 # DTB write misses |
| 326system.cpu0.dtb.write_acv 134 # DTB write access violations | 322system.cpu0.dtb.write_acv 134 # DTB write access violations |
| 327system.cpu0.dtb.write_accesses 187452 # DTB write accesses 328system.cpu0.dtb.data_hits 12574113 # DTB hits 329system.cpu0.dtb.data_misses 8256 # DTB misses | 323system.cpu0.dtb.write_accesses 187451 # DTB write accesses 324system.cpu0.dtb.data_hits 12421519 # DTB hits 325system.cpu0.dtb.data_misses 8254 # DTB misses |
| 330system.cpu0.dtb.data_acv 344 # DTB access violations | 326system.cpu0.dtb.data_acv 344 # DTB access violations |
| 331system.cpu0.dtb.data_accesses 678125 # DTB accesses 332system.cpu0.itb.fetch_hits 3504450 # ITB hits | 327system.cpu0.dtb.data_accesses 678123 # DTB accesses 328system.cpu0.itb.fetch_hits 3482641 # ITB hits |
| 333system.cpu0.itb.fetch_misses 3871 # ITB misses 334system.cpu0.itb.fetch_acv 184 # ITB acv | 329system.cpu0.itb.fetch_misses 3871 # ITB misses 330system.cpu0.itb.fetch_acv 184 # ITB acv |
| 335system.cpu0.itb.fetch_accesses 3508321 # ITB accesses | 331system.cpu0.itb.fetch_accesses 3486512 # ITB accesses |
| 336system.cpu0.itb.read_hits 0 # DTB read hits 337system.cpu0.itb.read_misses 0 # DTB read misses 338system.cpu0.itb.read_acv 0 # DTB read access violations 339system.cpu0.itb.read_accesses 0 # DTB read accesses 340system.cpu0.itb.write_hits 0 # DTB write hits 341system.cpu0.itb.write_misses 0 # DTB write misses 342system.cpu0.itb.write_acv 0 # DTB write access violations 343system.cpu0.itb.write_accesses 0 # DTB write accesses 344system.cpu0.itb.data_hits 0 # DTB hits 345system.cpu0.itb.data_misses 0 # DTB misses 346system.cpu0.itb.data_acv 0 # DTB access violations 347system.cpu0.itb.data_accesses 0 # DTB accesses | 332system.cpu0.itb.read_hits 0 # DTB read hits 333system.cpu0.itb.read_misses 0 # DTB read misses 334system.cpu0.itb.read_acv 0 # DTB read access violations 335system.cpu0.itb.read_accesses 0 # DTB read accesses 336system.cpu0.itb.write_hits 0 # DTB write hits 337system.cpu0.itb.write_misses 0 # DTB write misses 338system.cpu0.itb.write_acv 0 # DTB write access violations 339system.cpu0.itb.write_accesses 0 # DTB write accesses 340system.cpu0.itb.data_hits 0 # DTB hits 341system.cpu0.itb.data_misses 0 # DTB misses 342system.cpu0.itb.data_acv 0 # DTB access violations 343system.cpu0.itb.data_accesses 0 # DTB accesses |
| 348system.cpu0.numCycles 3923838721 # number of cpu cycles simulated | 344system.cpu0.numCycles 3964851833 # number of cpu cycles simulated |
| 349system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 350system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 345system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 346system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 351system.cpu0.committedInsts 47783493 # Number of instructions committed 352system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed 353system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses 354system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses 355system.cpu0.num_func_calls 1203861 # number of times a function call or return occured 356system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls 357system.cpu0.num_int_insts 44315744 # number of integer instructions 358system.cpu0.num_fp_insts 211234 # number of float instructions 359system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read 360system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written 361system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read 362system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written 363system.cpu0.num_mem_refs 12614351 # number of memory refs 364system.cpu0.num_load_insts 7527207 # Number of load instructions 365system.cpu0.num_store_insts 5087144 # Number of store instructions 366system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles 367system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles 368system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles 369system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles 370system.cpu0.Branches 7204257 # Number of branches fetched 371system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction 372system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction 373system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction 374system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction 375system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction 376system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction 377system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction 378system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction 379system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction 380system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction 381system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction 382system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction 383system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction 384system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction 385system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction 386system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction 387system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction 388system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction 389system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction 390system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction 391system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction 392system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction 393system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction 394system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction 395system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction 396system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction 397system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction 398system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction 399system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction 400system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction 401system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction 402system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction 403system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction | 347system.cpu0.committedInsts 47325532 # Number of instructions committed 348system.cpu0.committedOps 47325532 # Number of ops (including micro ops) committed 349system.cpu0.num_int_alu_accesses 43895499 # Number of integer alu accesses 350system.cpu0.num_fp_alu_accesses 207106 # Number of float alu accesses 351system.cpu0.num_func_calls 1185742 # number of times a function call or return occured 352system.cpu0.num_conditional_control_insts 5567031 # number of instructions that are conditional controls 353system.cpu0.num_int_insts 43895499 # number of integer instructions 354system.cpu0.num_fp_insts 207106 # number of float instructions 355system.cpu0.num_int_register_reads 60349527 # number of times the integer registers were read 356system.cpu0.num_int_register_writes 32725613 # number of times the integer registers were written 357system.cpu0.num_fp_register_reads 100583 # number of times the floating registers were read 358system.cpu0.num_fp_register_writes 102386 # number of times the floating registers were written 359system.cpu0.num_mem_refs 12461430 # number of memory refs 360system.cpu0.num_load_insts 7443904 # Number of load instructions 361system.cpu0.num_store_insts 5017526 # Number of store instructions 362system.cpu0.num_idle_cycles 3700363584.987226 # Number of idle cycles 363system.cpu0.num_busy_cycles 264488248.012774 # Number of busy cycles 364system.cpu0.not_idle_fraction 0.066708 # Percentage of non-idle cycles 365system.cpu0.idle_fraction 0.933292 # Percentage of idle cycles 366system.cpu0.Branches 7135463 # Number of branches fetched 367system.cpu0.op_class::No_OpClass 2703242 5.71% 5.71% # Class of executed instruction 368system.cpu0.op_class::IntAlu 31183402 65.88% 71.59% # Class of executed instruction 369system.cpu0.op_class::IntMult 51823 0.11% 71.70% # Class of executed instruction 370system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction 371system.cpu0.op_class::FloatAdd 25571 0.05% 71.75% # Class of executed instruction 372system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction 373system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction 374system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction 375system.cpu0.op_class::FloatDiv 1656 0.00% 71.76% # Class of executed instruction 376system.cpu0.op_class::FloatSqrt 0 0.00% 71.76% # Class of executed instruction 377system.cpu0.op_class::SimdAdd 0 0.00% 71.76% # Class of executed instruction 378system.cpu0.op_class::SimdAddAcc 0 0.00% 71.76% # Class of executed instruction 379system.cpu0.op_class::SimdAlu 0 0.00% 71.76% # Class of executed instruction 380system.cpu0.op_class::SimdCmp 0 0.00% 71.76% # Class of executed instruction 381system.cpu0.op_class::SimdCvt 0 0.00% 71.76% # Class of executed instruction 382system.cpu0.op_class::SimdMisc 0 0.00% 71.76% # Class of executed instruction 383system.cpu0.op_class::SimdMult 0 0.00% 71.76% # Class of executed instruction 384system.cpu0.op_class::SimdMultAcc 0 0.00% 71.76% # Class of executed instruction 385system.cpu0.op_class::SimdShift 0 0.00% 71.76% # Class of executed instruction 386system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.76% # Class of executed instruction 387system.cpu0.op_class::SimdSqrt 0 0.00% 71.76% # Class of executed instruction 388system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.76% # Class of executed instruction 389system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.76% # Class of executed instruction 390system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.76% # Class of executed instruction 391system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.76% # Class of executed instruction 392system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.76% # Class of executed instruction 393system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.76% # Class of executed instruction 394system.cpu0.op_class::SimdFloatMult 0 0.00% 71.76% # Class of executed instruction 395system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.76% # Class of executed instruction 396system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.76% # Class of executed instruction 397system.cpu0.op_class::MemRead 7617030 16.09% 87.85% # Class of executed instruction 398system.cpu0.op_class::MemWrite 5023630 10.61% 98.46% # Class of executed instruction 399system.cpu0.op_class::IprAccess 727776 1.54% 100.00% # Class of executed instruction |
| 404system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 400system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 405system.cpu0.op_class::total 47792093 # Class of executed instruction | 401system.cpu0.op_class::total 47334130 # Class of executed instruction |
| 406system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 402system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 407system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed 408system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed 409system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl 410system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl 411system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl 412system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl 413system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl 414system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl 415system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl 416system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl 417system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl 418system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl 419system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl 420system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl 421system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl 422system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl 423system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl 424system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl 425system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl 426system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl 427system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl | 403system.cpu0.kern.inst.quiesce 6807 # number of quiesce instructions executed 404system.cpu0.kern.inst.hwrei 162813 # number of hwrei instructions executed 405system.cpu0.kern.ipl_count::0 55930 40.12% 40.12% # number of times we switched to this ipl 406system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl 407system.cpu0.kern.ipl_count::22 1978 1.42% 41.63% # number of times we switched to this ipl 408system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl 409system.cpu0.kern.ipl_count::31 80947 58.06% 100.00% # number of times we switched to this ipl 410system.cpu0.kern.ipl_count::total 139423 # number of times we switched to this ipl 411system.cpu0.kern.ipl_good::0 55420 49.07% 49.07% # number of times we switched to this ipl from a different ipl 412system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl 413system.cpu0.kern.ipl_good::22 1978 1.75% 50.93% # number of times we switched to this ipl from a different ipl 414system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl 415system.cpu0.kern.ipl_good::31 54986 48.68% 100.00% # number of times we switched to this ipl from a different ipl 416system.cpu0.kern.ipl_good::total 112952 # number of times we switched to this ipl from a different ipl 417system.cpu0.kern.ipl_ticks::0 1904955657000 96.09% 96.09% # number of cycles we spent at this ipl 418system.cpu0.kern.ipl_ticks::21 92166000 0.00% 96.10% # number of cycles we spent at this ipl 419system.cpu0.kern.ipl_ticks::22 765642500 0.04% 96.14% # number of cycles we spent at this ipl 420system.cpu0.kern.ipl_ticks::30 319863500 0.02% 96.15% # number of cycles we spent at this ipl 421system.cpu0.kern.ipl_ticks::31 76292557500 3.85% 100.00% # number of cycles we spent at this ipl 422system.cpu0.kern.ipl_ticks::total 1982425886500 # number of cycles we spent at this ipl 423system.cpu0.kern.ipl_used::0 0.990881 # fraction of swpipl calls that actually changed the ipl |
| 428system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 429system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 430system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 424system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 425system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 426system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 431system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl 432system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl | 427system.cpu0.kern.ipl_used::31 0.679284 # fraction of swpipl calls that actually changed the ipl 428system.cpu0.kern.ipl_used::total 0.810139 # fraction of swpipl calls that actually changed the ipl |
| 433system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 434system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 435system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 436system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 437system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 438system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 439system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 440system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 456system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 457system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 458system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 459system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 460system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 461system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 462system.cpu0.kern.syscall::total 222 # number of syscalls executed 463system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 429system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 430system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 431system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 432system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 433system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 434system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 435system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 436system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 452system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 453system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 454system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 455system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 456system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 457system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 458system.cpu0.kern.syscall::total 222 # number of syscalls executed 459system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 464system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed 465system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed 466system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 467system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed 468system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed 469system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed 470system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed 471system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed 472system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed 473system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed 474system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed 475system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed 476system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed 477system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed 478system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed | 460system.cpu0.kern.callpal::wripir 523 0.35% 0.35% # number of callpals executed 461system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 462system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 463system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 464system.cpu0.kern.callpal::swpctx 3026 2.05% 2.41% # number of callpals executed 465system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 466system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 467system.cpu0.kern.callpal::swpipl 132550 89.80% 92.24% # number of callpals executed 468system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed 469system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed 470system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed 471system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed 472system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed 473system.cpu0.kern.callpal::rti 4327 2.93% 99.65% # number of callpals executed 474system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed |
| 479system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed | 475system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed |
| 480system.cpu0.kern.callpal::total 150081 # number of callpals executed 481system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches 482system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches | 476system.cpu0.kern.callpal::total 147613 # number of callpals executed 477system.cpu0.kern.mode_switch::kernel 6866 # number of protection mode switches 478system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches |
| 483system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 479system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 484system.cpu0.kern.mode_good::kernel 1282 485system.cpu0.kern.mode_good::user 1282 | 480system.cpu0.kern.mode_good::kernel 1281 481system.cpu0.kern.mode_good::user 1281 |
| 486system.cpu0.kern.mode_good::idle 0 | 482system.cpu0.kern.mode_good::idle 0 |
| 487system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches | 483system.cpu0.kern.mode_switch_good::kernel 0.186572 # fraction of useful protection mode switches |
| 488system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 489system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 484system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 485system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 490system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches 491system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode 492system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode | 486system.cpu0.kern.mode_switch_good::total 0.314472 # fraction of useful protection mode switches 487system.cpu0.kern.mode_ticks::kernel 1977675856500 99.80% 99.80% # number of ticks spent at the given mode 488system.cpu0.kern.mode_ticks::user 3900112000 0.20% 100.00% # number of ticks spent at the given mode |
| 493system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 489system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 494system.cpu0.kern.swap_context 3073 # number of times the context was actually changed 495system.cpu0.dcache.tags.replacements 1181794 # number of replacements 496system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use 497system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks. 498system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks. 499system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks. 500system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit. 501system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor 502system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy 503system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy 504system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id 505system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id 506system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id 507system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id 508system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses 509system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses 510system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits 511system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits 512system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits 513system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits 514system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # number of LoadLockedReq hits 515system.cpu0.dcache.LoadLockedReq_hits::total 140662 # number of LoadLockedReq hits 516system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148383 # number of StoreCondReq hits 517system.cpu0.dcache.StoreCondReq_hits::total 148383 # number of StoreCondReq hits 518system.cpu0.dcache.demand_hits::cpu0.data 11084304 # number of demand (read+write) hits 519system.cpu0.dcache.demand_hits::total 11084304 # number of demand (read+write) hits 520system.cpu0.dcache.overall_hits::cpu0.data 11084304 # number of overall hits 521system.cpu0.dcache.overall_hits::total 11084304 # number of overall hits 522system.cpu0.dcache.ReadReq_misses::cpu0.data 939259 # number of ReadReq misses 523system.cpu0.dcache.ReadReq_misses::total 939259 # number of ReadReq misses 524system.cpu0.dcache.WriteReq_misses::cpu0.data 251797 # number of WriteReq misses 525system.cpu0.dcache.WriteReq_misses::total 251797 # number of WriteReq misses 526system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13671 # number of LoadLockedReq misses 527system.cpu0.dcache.LoadLockedReq_misses::total 13671 # number of LoadLockedReq misses 528system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5399 # number of StoreCondReq misses 529system.cpu0.dcache.StoreCondReq_misses::total 5399 # number of StoreCondReq misses 530system.cpu0.dcache.demand_misses::cpu0.data 1191056 # number of demand (read+write) misses 531system.cpu0.dcache.demand_misses::total 1191056 # number of demand (read+write) misses 532system.cpu0.dcache.overall_misses::cpu0.data 1191056 # number of overall misses 533system.cpu0.dcache.overall_misses::total 1191056 # number of overall misses 534system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 28901225000 # number of ReadReq miss cycles 535system.cpu0.dcache.ReadReq_miss_latency::total 28901225000 # number of ReadReq miss cycles 536system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10875412500 # number of WriteReq miss cycles 537system.cpu0.dcache.WriteReq_miss_latency::total 10875412500 # number of WriteReq miss cycles 538system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles 539system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles 540system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles 541system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles 542system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles 543system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles 544system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles 545system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles 546system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses) 547system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses) 548system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses) 549system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses) 550system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses) 551system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses) 552system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses) 553system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses) 554system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses 555system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses 556system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses 557system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses 558system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses 559system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses 560system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses 561system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses 562system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses 563system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses 564system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses 565system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses 566system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses 567system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses 568system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses 569system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses 570system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency 571system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency 572system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency 573system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency 574system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency 575system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency 576system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency 577system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency 578system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency 579system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency 580system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency 581system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency | 490system.cpu0.kern.swap_context 3027 # number of times the context was actually changed 491system.cpu0.dcache.tags.replacements 1172695 # number of replacements 492system.cpu0.dcache.tags.tagsinuse 505.333942 # Cycle average of tags in use 493system.cpu0.dcache.tags.total_refs 11237582 # Total number of references to valid blocks. 494system.cpu0.dcache.tags.sampled_refs 1173114 # Sample count of references to valid blocks. 495system.cpu0.dcache.tags.avg_refs 9.579275 # Average number of references to valid blocks. 496system.cpu0.dcache.tags.warmup_cycle 143226500 # Cycle when the warmup percentage was hit. 497system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333942 # Average occupied blocks per requestor 498system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy 499system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy 500system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id 501system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 502system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id 503system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id 504system.cpu0.dcache.tags.tag_accesses 50910847 # Number of tag accesses 505system.cpu0.dcache.tags.data_accesses 50910847 # Number of data accesses 506system.cpu0.dcache.ReadReq_hits::cpu0.data 6343242 # number of ReadReq hits 507system.cpu0.dcache.ReadReq_hits::total 6343242 # number of ReadReq hits 508system.cpu0.dcache.WriteReq_hits::cpu0.data 4601243 # number of WriteReq hits 509system.cpu0.dcache.WriteReq_hits::total 4601243 # number of WriteReq hits 510system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138155 # number of LoadLockedReq hits 511system.cpu0.dcache.LoadLockedReq_hits::total 138155 # number of LoadLockedReq hits 512system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145460 # number of StoreCondReq hits 513system.cpu0.dcache.StoreCondReq_hits::total 145460 # number of StoreCondReq hits 514system.cpu0.dcache.demand_hits::cpu0.data 10944485 # number of demand (read+write) hits 515system.cpu0.dcache.demand_hits::total 10944485 # number of demand (read+write) hits 516system.cpu0.dcache.overall_hits::cpu0.data 10944485 # number of overall hits 517system.cpu0.dcache.overall_hits::total 10944485 # number of overall hits 518system.cpu0.dcache.ReadReq_misses::cpu0.data 934191 # number of ReadReq misses 519system.cpu0.dcache.ReadReq_misses::total 934191 # number of ReadReq misses 520system.cpu0.dcache.WriteReq_misses::cpu0.data 249028 # number of WriteReq misses 521system.cpu0.dcache.WriteReq_misses::total 249028 # number of WriteReq misses 522system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses 523system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses 524system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5734 # number of StoreCondReq misses 525system.cpu0.dcache.StoreCondReq_misses::total 5734 # number of StoreCondReq misses 526system.cpu0.dcache.demand_misses::cpu0.data 1183219 # number of demand (read+write) misses 527system.cpu0.dcache.demand_misses::total 1183219 # number of demand (read+write) misses 528system.cpu0.dcache.overall_misses::cpu0.data 1183219 # number of overall misses 529system.cpu0.dcache.overall_misses::total 1183219 # number of overall misses 530system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42879044000 # number of ReadReq miss cycles 531system.cpu0.dcache.ReadReq_miss_latency::total 42879044000 # number of ReadReq miss cycles 532system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16797420000 # number of WriteReq miss cycles 533system.cpu0.dcache.WriteReq_miss_latency::total 16797420000 # number of WriteReq miss cycles 534system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151036000 # number of LoadLockedReq miss cycles 535system.cpu0.dcache.LoadLockedReq_miss_latency::total 151036000 # number of LoadLockedReq miss cycles 536system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 96889000 # number of StoreCondReq miss cycles 537system.cpu0.dcache.StoreCondReq_miss_latency::total 96889000 # number of StoreCondReq miss cycles 538system.cpu0.dcache.demand_miss_latency::cpu0.data 59676464000 # number of demand (read+write) miss cycles 539system.cpu0.dcache.demand_miss_latency::total 59676464000 # number of demand (read+write) miss cycles 540system.cpu0.dcache.overall_miss_latency::cpu0.data 59676464000 # number of overall miss cycles 541system.cpu0.dcache.overall_miss_latency::total 59676464000 # number of overall miss cycles 542system.cpu0.dcache.ReadReq_accesses::cpu0.data 7277433 # number of ReadReq accesses(hits+misses) 543system.cpu0.dcache.ReadReq_accesses::total 7277433 # number of ReadReq accesses(hits+misses) 544system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850271 # number of WriteReq accesses(hits+misses) 545system.cpu0.dcache.WriteReq_accesses::total 4850271 # number of WriteReq accesses(hits+misses) 546system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151733 # number of LoadLockedReq accesses(hits+misses) 547system.cpu0.dcache.LoadLockedReq_accesses::total 151733 # number of LoadLockedReq accesses(hits+misses) 548system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151194 # number of StoreCondReq accesses(hits+misses) 549system.cpu0.dcache.StoreCondReq_accesses::total 151194 # number of StoreCondReq accesses(hits+misses) 550system.cpu0.dcache.demand_accesses::cpu0.data 12127704 # number of demand (read+write) accesses 551system.cpu0.dcache.demand_accesses::total 12127704 # number of demand (read+write) accesses 552system.cpu0.dcache.overall_accesses::cpu0.data 12127704 # number of overall (read+write) accesses 553system.cpu0.dcache.overall_accesses::total 12127704 # number of overall (read+write) accesses 554system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128368 # miss rate for ReadReq accesses 555system.cpu0.dcache.ReadReq_miss_rate::total 0.128368 # miss rate for ReadReq accesses 556system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051343 # miss rate for WriteReq accesses 557system.cpu0.dcache.WriteReq_miss_rate::total 0.051343 # miss rate for WriteReq accesses 558system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089486 # miss rate for LoadLockedReq accesses 559system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089486 # miss rate for LoadLockedReq accesses 560system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037925 # miss rate for StoreCondReq accesses 561system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037925 # miss rate for StoreCondReq accesses 562system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097563 # miss rate for demand accesses 563system.cpu0.dcache.demand_miss_rate::total 0.097563 # miss rate for demand accesses 564system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097563 # miss rate for overall accesses 565system.cpu0.dcache.overall_miss_rate::total 0.097563 # miss rate for overall accesses 566system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45899.654353 # average ReadReq miss latency 567system.cpu0.dcache.ReadReq_avg_miss_latency::total 45899.654353 # average ReadReq miss latency 568system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67451.933116 # average WriteReq miss latency 569system.cpu0.dcache.WriteReq_avg_miss_latency::total 67451.933116 # average WriteReq miss latency 570system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11123.582265 # average LoadLockedReq miss latency 571system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11123.582265 # average LoadLockedReq miss latency 572system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16897.279386 # average StoreCondReq miss latency 573system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16897.279386 # average StoreCondReq miss latency 574system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency 575system.cpu0.dcache.demand_avg_miss_latency::total 50435.687730 # average overall miss latency 576system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50435.687730 # average overall miss latency 577system.cpu0.dcache.overall_avg_miss_latency::total 50435.687730 # average overall miss latency |
| 582system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 583system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 584system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 585system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 586system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 587system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 588system.cpu0.dcache.fast_writes 0 # number of fast writes performed 589system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 578system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 579system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 580system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 581system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 582system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 583system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 584system.cpu0.dcache.fast_writes 0 # number of fast writes performed 585system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 590system.cpu0.dcache.writebacks::writebacks 679941 # number of writebacks 591system.cpu0.dcache.writebacks::total 679941 # number of writebacks 592system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939259 # number of ReadReq MSHR misses 593system.cpu0.dcache.ReadReq_mshr_misses::total 939259 # number of ReadReq MSHR misses 594system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251797 # number of WriteReq MSHR misses 595system.cpu0.dcache.WriteReq_mshr_misses::total 251797 # number of WriteReq MSHR misses 596system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13671 # number of LoadLockedReq MSHR misses 597system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13671 # number of LoadLockedReq MSHR misses 598system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5399 # number of StoreCondReq MSHR misses 599system.cpu0.dcache.StoreCondReq_mshr_misses::total 5399 # number of StoreCondReq MSHR misses 600system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191056 # number of demand (read+write) MSHR misses 601system.cpu0.dcache.demand_mshr_misses::total 1191056 # number of demand (read+write) MSHR misses 602system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191056 # number of overall MSHR misses 603system.cpu0.dcache.overall_mshr_misses::total 1191056 # number of overall MSHR misses 604system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable 605system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable 606system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable 607system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10829 # number of WriteReq MSHR uncacheable 608system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses 609system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17939 # number of overall MSHR uncacheable misses 610system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27961966000 # number of ReadReq MSHR miss cycles 611system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27961966000 # number of ReadReq MSHR miss cycles 612system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10623615500 # number of WriteReq MSHR miss cycles 613system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10623615500 # number of WriteReq MSHR miss cycles 614system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136697000 # number of LoadLockedReq MSHR miss cycles 615system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136697000 # number of LoadLockedReq MSHR miss cycles 616system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42311000 # number of StoreCondReq MSHR miss cycles 617system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42311000 # number of StoreCondReq MSHR miss cycles 618system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38585581500 # number of demand (read+write) MSHR miss cycles 619system.cpu0.dcache.demand_mshr_miss_latency::total 38585581500 # number of demand (read+write) MSHR miss cycles 620system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38585581500 # number of overall MSHR miss cycles 621system.cpu0.dcache.overall_mshr_miss_latency::total 38585581500 # number of overall MSHR miss cycles 622system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1492228000 # number of ReadReq MSHR uncacheable cycles 623system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1492228000 # number of ReadReq MSHR uncacheable cycles 624system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2319869500 # number of WriteReq MSHR uncacheable cycles 625system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2319869500 # number of WriteReq MSHR uncacheable cycles 626system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3812097500 # number of overall MSHR uncacheable cycles 627system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3812097500 # number of overall MSHR uncacheable cycles 628system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses 629system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses 630system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses 631system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses 632system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses 633system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses 634system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses 635system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses 636system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses 637system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses 638system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses 639system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses 640system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency 641system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency 642system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency 643system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency 644system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency 645system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency 646system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency 647system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency 648system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency 649system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency 650system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency 651system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency 652system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency 653system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency 654system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency 655system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency 656system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency 657system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # average overall mshr uncacheable latency | 586system.cpu0.dcache.writebacks::writebacks 672708 # number of writebacks 587system.cpu0.dcache.writebacks::total 672708 # number of writebacks 588system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934191 # number of ReadReq MSHR misses 589system.cpu0.dcache.ReadReq_mshr_misses::total 934191 # number of ReadReq MSHR misses 590system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249028 # number of WriteReq MSHR misses 591system.cpu0.dcache.WriteReq_mshr_misses::total 249028 # number of WriteReq MSHR misses 592system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses 593system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses 594system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5734 # number of StoreCondReq MSHR misses 595system.cpu0.dcache.StoreCondReq_mshr_misses::total 5734 # number of StoreCondReq MSHR misses 596system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183219 # number of demand (read+write) MSHR misses 597system.cpu0.dcache.demand_mshr_misses::total 1183219 # number of demand (read+write) MSHR misses 598system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183219 # number of overall MSHR misses 599system.cpu0.dcache.overall_mshr_misses::total 1183219 # number of overall MSHR misses 600system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7086 # number of ReadReq MSHR uncacheable 601system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7086 # number of ReadReq MSHR uncacheable 602system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10784 # number of WriteReq MSHR uncacheable 603system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10784 # number of WriteReq MSHR uncacheable 604system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17870 # number of overall MSHR uncacheable misses 605system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17870 # number of overall MSHR uncacheable misses 606system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41944853000 # number of ReadReq MSHR miss cycles 607system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41944853000 # number of ReadReq MSHR miss cycles 608system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16548392000 # number of WriteReq MSHR miss cycles 609system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16548392000 # number of WriteReq MSHR miss cycles 610system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137458000 # number of LoadLockedReq MSHR miss cycles 611system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137458000 # number of LoadLockedReq MSHR miss cycles 612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91155000 # number of StoreCondReq MSHR miss cycles 613system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91155000 # number of StoreCondReq MSHR miss cycles 614system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58493245000 # number of demand (read+write) MSHR miss cycles 615system.cpu0.dcache.demand_mshr_miss_latency::total 58493245000 # number of demand (read+write) MSHR miss cycles 616system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58493245000 # number of overall MSHR miss cycles 617system.cpu0.dcache.overall_mshr_miss_latency::total 58493245000 # number of overall MSHR miss cycles 618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1488672000 # number of ReadReq MSHR uncacheable cycles 619system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1488672000 # number of ReadReq MSHR uncacheable cycles 620system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2316060500 # number of WriteReq MSHR uncacheable cycles 621system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2316060500 # number of WriteReq MSHR uncacheable cycles 622system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3804732500 # number of overall MSHR uncacheable cycles 623system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3804732500 # number of overall MSHR uncacheable cycles 624system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128368 # mshr miss rate for ReadReq accesses 625system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128368 # mshr miss rate for ReadReq accesses 626system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051343 # mshr miss rate for WriteReq accesses 627system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051343 # mshr miss rate for WriteReq accesses 628system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089486 # mshr miss rate for LoadLockedReq accesses 629system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089486 # mshr miss rate for LoadLockedReq accesses 630system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037925 # mshr miss rate for StoreCondReq accesses 631system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037925 # mshr miss rate for StoreCondReq accesses 632system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for demand accesses 633system.cpu0.dcache.demand_mshr_miss_rate::total 0.097563 # mshr miss rate for demand accesses 634system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097563 # mshr miss rate for overall accesses 635system.cpu0.dcache.overall_mshr_miss_rate::total 0.097563 # mshr miss rate for overall accesses 636system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44899.654353 # average ReadReq mshr miss latency 637system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44899.654353 # average ReadReq mshr miss latency 638system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66451.933116 # average WriteReq mshr miss latency 639system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66451.933116 # average WriteReq mshr miss latency 640system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10123.582265 # average LoadLockedReq mshr miss latency 641system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10123.582265 # average LoadLockedReq mshr miss latency 642system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15897.279386 # average StoreCondReq mshr miss latency 643system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15897.279386 # average StoreCondReq mshr miss latency 644system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency 645system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency 646system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.687730 # average overall mshr miss latency 647system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.687730 # average overall mshr miss latency 648system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210086.367485 # average ReadReq mshr uncacheable latency 649system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210086.367485 # average ReadReq mshr uncacheable latency 650system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214768.221439 # average WriteReq mshr uncacheable latency 651system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214768.221439 # average WriteReq mshr uncacheable latency 652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212911.723559 # average overall mshr uncacheable latency 653system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212911.723559 # average overall mshr uncacheable latency |
| 658system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 654system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 659system.cpu0.icache.tags.replacements 700401 # number of replacements 660system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use 661system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks. 662system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks. 663system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks. 664system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit. 665system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor 666system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy 667system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy | 655system.cpu0.icache.tags.replacements 686863 # number of replacements 656system.cpu0.icache.tags.tagsinuse 506.493433 # Cycle average of tags in use 657system.cpu0.icache.tags.total_refs 46646633 # Total number of references to valid blocks. 658system.cpu0.icache.tags.sampled_refs 687375 # Sample count of references to valid blocks. 659system.cpu0.icache.tags.avg_refs 67.861987 # Average number of references to valid blocks. 660system.cpu0.icache.tags.warmup_cycle 58997592500 # Cycle when the warmup percentage was hit. 661system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.493433 # Average occupied blocks per requestor 662system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989245 # Average percentage of cache occupancy 663system.cpu0.icache.tags.occ_percent::total 0.989245 # Average percentage of cache occupancy |
| 668system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 664system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 669system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id 670system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id | 665system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id 666system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id |
| 671system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 667system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 672system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses 673system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses 674system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits 675system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits 676system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits 677system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits 678system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits 679system.cpu0.icache.overall_hits::total 47091062 # number of overall hits 680system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses 681system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses 682system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses 683system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses 684system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses 685system.cpu0.icache.overall_misses::total 701031 # number of overall misses 686system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles 687system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles 688system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles 689system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles 690system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles 691system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles 692system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses) 693system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses) 694system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses 695system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses 696system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses 697system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses 698system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses 699system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses 700system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses 701system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses 702system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses 703system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses 704system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency 705system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency 706system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency 707system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency 708system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency 709system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency | 668system.cpu0.icache.tags.tag_accesses 48021627 # Number of tag accesses 669system.cpu0.icache.tags.data_accesses 48021627 # Number of data accesses 670system.cpu0.icache.ReadReq_hits::cpu0.inst 46646633 # number of ReadReq hits 671system.cpu0.icache.ReadReq_hits::total 46646633 # number of ReadReq hits 672system.cpu0.icache.demand_hits::cpu0.inst 46646633 # number of demand (read+write) hits 673system.cpu0.icache.demand_hits::total 46646633 # number of demand (read+write) hits 674system.cpu0.icache.overall_hits::cpu0.inst 46646633 # number of overall hits 675system.cpu0.icache.overall_hits::total 46646633 # number of overall hits 676system.cpu0.icache.ReadReq_misses::cpu0.inst 687497 # number of ReadReq misses 677system.cpu0.icache.ReadReq_misses::total 687497 # number of ReadReq misses 678system.cpu0.icache.demand_misses::cpu0.inst 687497 # number of demand (read+write) misses 679system.cpu0.icache.demand_misses::total 687497 # number of demand (read+write) misses 680system.cpu0.icache.overall_misses::cpu0.inst 687497 # number of overall misses 681system.cpu0.icache.overall_misses::total 687497 # number of overall misses 682system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10629492500 # number of ReadReq miss cycles 683system.cpu0.icache.ReadReq_miss_latency::total 10629492500 # number of ReadReq miss cycles 684system.cpu0.icache.demand_miss_latency::cpu0.inst 10629492500 # number of demand (read+write) miss cycles 685system.cpu0.icache.demand_miss_latency::total 10629492500 # number of demand (read+write) miss cycles 686system.cpu0.icache.overall_miss_latency::cpu0.inst 10629492500 # number of overall miss cycles 687system.cpu0.icache.overall_miss_latency::total 10629492500 # number of overall miss cycles 688system.cpu0.icache.ReadReq_accesses::cpu0.inst 47334130 # number of ReadReq accesses(hits+misses) 689system.cpu0.icache.ReadReq_accesses::total 47334130 # number of ReadReq accesses(hits+misses) 690system.cpu0.icache.demand_accesses::cpu0.inst 47334130 # number of demand (read+write) accesses 691system.cpu0.icache.demand_accesses::total 47334130 # number of demand (read+write) accesses 692system.cpu0.icache.overall_accesses::cpu0.inst 47334130 # number of overall (read+write) accesses 693system.cpu0.icache.overall_accesses::total 47334130 # number of overall (read+write) accesses 694system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses 695system.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses 696system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses 697system.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses 698system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses 699system.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses 700system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15461.147467 # average ReadReq miss latency 701system.cpu0.icache.ReadReq_avg_miss_latency::total 15461.147467 # average ReadReq miss latency 702system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency 703system.cpu0.icache.demand_avg_miss_latency::total 15461.147467 # average overall miss latency 704system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15461.147467 # average overall miss latency 705system.cpu0.icache.overall_avg_miss_latency::total 15461.147467 # average overall miss latency |
| 710system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 711system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 712system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 713system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 714system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 715system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 716system.cpu0.icache.fast_writes 0 # number of fast writes performed 717system.cpu0.icache.cache_copies 0 # number of cache copies performed | 706system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 707system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 708system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 709system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 710system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 711system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu0.icache.fast_writes 0 # number of fast writes performed 713system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 718system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses 719system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses 720system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses 721system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses 722system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses 723system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses 724system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles 725system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles 726system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles 727system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles 728system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles 729system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles 730system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses 731system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses 732system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses 733system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses 734system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses 735system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses 736system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency 737system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency 738system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency 739system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency 740system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency 741system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency | 714system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687497 # number of ReadReq MSHR misses 715system.cpu0.icache.ReadReq_mshr_misses::total 687497 # number of ReadReq MSHR misses 716system.cpu0.icache.demand_mshr_misses::cpu0.inst 687497 # number of demand (read+write) MSHR misses 717system.cpu0.icache.demand_mshr_misses::total 687497 # number of demand (read+write) MSHR misses 718system.cpu0.icache.overall_mshr_misses::cpu0.inst 687497 # number of overall MSHR misses 719system.cpu0.icache.overall_mshr_misses::total 687497 # number of overall MSHR misses 720system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9941995500 # number of ReadReq MSHR miss cycles 721system.cpu0.icache.ReadReq_mshr_miss_latency::total 9941995500 # number of ReadReq MSHR miss cycles 722system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9941995500 # number of demand (read+write) MSHR miss cycles 723system.cpu0.icache.demand_mshr_miss_latency::total 9941995500 # number of demand (read+write) MSHR miss cycles 724system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9941995500 # number of overall MSHR miss cycles 725system.cpu0.icache.overall_mshr_miss_latency::total 9941995500 # number of overall MSHR miss cycles 726system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses 727system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses 728system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses 729system.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses 730system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses 731system.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses 732system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average ReadReq mshr miss latency 733system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14461.147467 # average ReadReq mshr miss latency 734system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency 735system.cpu0.icache.demand_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency 736system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14461.147467 # average overall mshr miss latency 737system.cpu0.icache.overall_avg_mshr_miss_latency::total 14461.147467 # average overall mshr miss latency |
| 742system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 743system.cpu1.dtb.fetch_hits 0 # ITB hits 744system.cpu1.dtb.fetch_misses 0 # ITB misses 745system.cpu1.dtb.fetch_acv 0 # ITB acv 746system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 738system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 739system.cpu1.dtb.fetch_hits 0 # ITB hits 740system.cpu1.dtb.fetch_misses 0 # ITB misses 741system.cpu1.dtb.fetch_acv 0 # ITB acv 742system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 747system.cpu1.dtb.read_hits 2409623 # DTB read hits 748system.cpu1.dtb.read_misses 2992 # DTB read misses | 743system.cpu1.dtb.read_hits 2508569 # DTB read hits 744system.cpu1.dtb.read_misses 2993 # DTB read misses |
| 749system.cpu1.dtb.read_acv 0 # DTB read access violations | 745system.cpu1.dtb.read_acv 0 # DTB read access violations |
| 750system.cpu1.dtb.read_accesses 239363 # DTB read accesses 751system.cpu1.dtb.write_hits 1749165 # DTB write hits 752system.cpu1.dtb.write_misses 341 # DTB write misses | 746system.cpu1.dtb.read_accesses 239364 # DTB read accesses 747system.cpu1.dtb.write_hits 1828737 # DTB write hits 748system.cpu1.dtb.write_misses 342 # DTB write misses |
| 753system.cpu1.dtb.write_acv 29 # DTB write access violations | 749system.cpu1.dtb.write_acv 29 # DTB write access violations |
| 754system.cpu1.dtb.write_accesses 105247 # DTB write accesses 755system.cpu1.dtb.data_hits 4158788 # DTB hits 756system.cpu1.dtb.data_misses 3333 # DTB misses | 750system.cpu1.dtb.write_accesses 105248 # DTB write accesses 751system.cpu1.dtb.data_hits 4337306 # DTB hits 752system.cpu1.dtb.data_misses 3335 # DTB misses |
| 757system.cpu1.dtb.data_acv 29 # DTB access violations | 753system.cpu1.dtb.data_acv 29 # DTB access violations |
| 758system.cpu1.dtb.data_accesses 344610 # DTB accesses 759system.cpu1.itb.fetch_hits 1960477 # ITB hits | 754system.cpu1.dtb.data_accesses 344612 # DTB accesses 755system.cpu1.itb.fetch_hits 1989876 # ITB hits |
| 760system.cpu1.itb.fetch_misses 1216 # ITB misses 761system.cpu1.itb.fetch_acv 0 # ITB acv | 756system.cpu1.itb.fetch_misses 1216 # ITB misses 757system.cpu1.itb.fetch_acv 0 # ITB acv |
| 762system.cpu1.itb.fetch_accesses 1961693 # ITB accesses | 758system.cpu1.itb.fetch_accesses 1991092 # ITB accesses |
| 763system.cpu1.itb.read_hits 0 # DTB read hits 764system.cpu1.itb.read_misses 0 # DTB read misses 765system.cpu1.itb.read_acv 0 # DTB read access violations 766system.cpu1.itb.read_accesses 0 # DTB read accesses 767system.cpu1.itb.write_hits 0 # DTB write hits 768system.cpu1.itb.write_misses 0 # DTB write misses 769system.cpu1.itb.write_acv 0 # DTB write access violations 770system.cpu1.itb.write_accesses 0 # DTB write accesses 771system.cpu1.itb.data_hits 0 # DTB hits 772system.cpu1.itb.data_misses 0 # DTB misses 773system.cpu1.itb.data_acv 0 # DTB access violations 774system.cpu1.itb.data_accesses 0 # DTB accesses | 759system.cpu1.itb.read_hits 0 # DTB read hits 760system.cpu1.itb.read_misses 0 # DTB read misses 761system.cpu1.itb.read_acv 0 # DTB read access violations 762system.cpu1.itb.read_accesses 0 # DTB read accesses 763system.cpu1.itb.write_hits 0 # DTB write hits 764system.cpu1.itb.write_misses 0 # DTB write misses 765system.cpu1.itb.write_acv 0 # DTB write access violations 766system.cpu1.itb.write_accesses 0 # DTB write accesses 767system.cpu1.itb.data_hits 0 # DTB hits 768system.cpu1.itb.data_misses 0 # DTB misses 769system.cpu1.itb.data_acv 0 # DTB access violations 770system.cpu1.itb.data_accesses 0 # DTB accesses |
| 775system.cpu1.numCycles 3925216965 # number of cpu cycles simulated | 771system.cpu1.numCycles 3965170714 # number of cpu cycles simulated |
| 776system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 777system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 772system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 773system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 778system.cpu1.committedInsts 13101094 # Number of instructions committed 779system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed 780system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses 781system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses 782system.cpu1.num_func_calls 409417 # number of times a function call or return occured 783system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls 784system.cpu1.num_int_insts 12083765 # number of integer instructions 785system.cpu1.num_fp_insts 172106 # number of float instructions 786system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read 787system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written 788system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read 789system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written 790system.cpu1.num_mem_refs 4182249 # number of memory refs 791system.cpu1.num_load_insts 2423870 # Number of load instructions 792system.cpu1.num_store_insts 1758379 # Number of store instructions 793system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles 794system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles 795system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles 796system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles 797system.cpu1.Branches 1864071 # Number of branches fetched 798system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction 799system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction 800system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction 801system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction 802system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction 803system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction 804system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction 805system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction 806system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction 807system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction 808system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction 809system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction 810system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction 811system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction 812system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction 813system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction 814system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction 815system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction 816system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction 817system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction 818system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction 819system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction 820system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction 821system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction 822system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction 823system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction 824system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction 825system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction 826system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction 827system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction 828system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction 829system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction 830system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction | 774system.cpu1.committedInsts 13660009 # Number of instructions committed 775system.cpu1.committedOps 13660009 # Number of ops (including micro ops) committed 776system.cpu1.num_int_alu_accesses 12598388 # Number of integer alu accesses 777system.cpu1.num_fp_alu_accesses 178445 # Number of float alu accesses 778system.cpu1.num_func_calls 429702 # number of times a function call or return occured 779system.cpu1.num_conditional_control_insts 1355296 # number of instructions that are conditional controls 780system.cpu1.num_int_insts 12598388 # number of integer instructions 781system.cpu1.num_fp_insts 178445 # number of float instructions 782system.cpu1.num_int_register_reads 17340989 # number of times the integer registers were read 783system.cpu1.num_int_register_writes 9240436 # number of times the integer registers were written 784system.cpu1.num_fp_register_reads 93179 # number of times the floating registers were read 785system.cpu1.num_fp_register_writes 95134 # number of times the floating registers were written 786system.cpu1.num_mem_refs 4361445 # number of memory refs 787system.cpu1.num_load_insts 2523214 # Number of load instructions 788system.cpu1.num_store_insts 1838231 # Number of store instructions 789system.cpu1.num_idle_cycles 3912374881.998026 # Number of idle cycles 790system.cpu1.num_busy_cycles 52795832.001973 # Number of busy cycles 791system.cpu1.not_idle_fraction 0.013315 # Percentage of non-idle cycles 792system.cpu1.idle_fraction 0.986685 # Percentage of idle cycles 793system.cpu1.Branches 1945174 # Number of branches fetched 794system.cpu1.op_class::No_OpClass 733210 5.37% 5.37% # Class of executed instruction 795system.cpu1.op_class::IntAlu 8079835 59.13% 64.50% # Class of executed instruction 796system.cpu1.op_class::IntMult 22791 0.17% 64.67% # Class of executed instruction 797system.cpu1.op_class::IntDiv 0 0.00% 64.67% # Class of executed instruction 798system.cpu1.op_class::FloatAdd 14367 0.11% 64.77% # Class of executed instruction 799system.cpu1.op_class::FloatCmp 0 0.00% 64.77% # Class of executed instruction 800system.cpu1.op_class::FloatCvt 0 0.00% 64.77% # Class of executed instruction 801system.cpu1.op_class::FloatMult 0 0.00% 64.77% # Class of executed instruction 802system.cpu1.op_class::FloatDiv 1986 0.01% 64.79% # Class of executed instruction 803system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction 804system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction 805system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction 806system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction 807system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction 808system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction 809system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction 810system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction 811system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction 812system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction 813system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction 814system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction 815system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction 816system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction 817system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction 818system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction 819system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction 820system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.79% # Class of executed instruction 821system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction 822system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction 823system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction 824system.cpu1.op_class::MemRead 2597857 19.01% 83.80% # Class of executed instruction 825system.cpu1.op_class::MemWrite 1839254 13.46% 97.26% # Class of executed instruction 826system.cpu1.op_class::IprAccess 374073 2.74% 100.00% # Class of executed instruction |
| 831system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 827system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 832system.cpu1.op_class::total 13104456 # Class of executed instruction | 828system.cpu1.op_class::total 13663373 # Class of executed instruction |
| 833system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 829system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 834system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed 835system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed 836system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl 837system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl 838system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl 839system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl 840system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl 841system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl 842system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl 843system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl 844system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl 845system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl 846system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl 847system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl 848system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl 849system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl 850system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl 851system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl | 830system.cpu1.kern.inst.quiesce 2868 # number of quiesce instructions executed 831system.cpu1.kern.inst.hwrei 81018 # number of hwrei instructions executed 832system.cpu1.kern.ipl_count::0 27534 38.52% 38.52% # number of times we switched to this ipl 833system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl 834system.cpu1.kern.ipl_count::30 523 0.73% 42.01% # number of times we switched to this ipl 835system.cpu1.kern.ipl_count::31 41447 57.99% 100.00% # number of times we switched to this ipl 836system.cpu1.kern.ipl_count::total 71475 # number of times we switched to this ipl 837system.cpu1.kern.ipl_good::0 26667 48.22% 48.22% # number of times we switched to this ipl from a different ipl 838system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl 839system.cpu1.kern.ipl_good::30 523 0.95% 52.73% # number of times we switched to this ipl from a different ipl 840system.cpu1.kern.ipl_good::31 26144 47.27% 100.00% # number of times we switched to this ipl from a different ipl 841system.cpu1.kern.ipl_good::total 55305 # number of times we switched to this ipl from a different ipl 842system.cpu1.kern.ipl_ticks::0 1912303307000 96.46% 96.46% # number of cycles we spent at this ipl 843system.cpu1.kern.ipl_ticks::22 705769500 0.04% 96.49% # number of cycles we spent at this ipl 844system.cpu1.kern.ipl_ticks::30 367699000 0.02% 96.51% # number of cycles we spent at this ipl 845system.cpu1.kern.ipl_ticks::31 69207844500 3.49% 100.00% # number of cycles we spent at this ipl 846system.cpu1.kern.ipl_ticks::total 1982584620000 # number of cycles we spent at this ipl 847system.cpu1.kern.ipl_used::0 0.968512 # fraction of swpipl calls that actually changed the ipl |
| 852system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 853system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 848system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 849system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 854system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl 855system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl | 850system.cpu1.kern.ipl_used::31 0.630781 # fraction of swpipl calls that actually changed the ipl 851system.cpu1.kern.ipl_used::total 0.773767 # fraction of swpipl calls that actually changed the ipl |
| 856system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 857system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 858system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 859system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 860system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 861system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 862system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 863system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 864system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 865system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 866system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 867system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 868system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 869system.cpu1.kern.syscall::total 104 # number of syscalls executed 870system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 852system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 853system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 854system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 855system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 856system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 857system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 858system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 859system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 860system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 861system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 862system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 863system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 864system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 865system.cpu1.kern.syscall::total 104 # number of syscalls executed 866system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 871system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed | 867system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed |
| 872system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 873system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed | 868system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 869system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed |
| 874system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed | 870system.cpu1.kern.callpal::swpctx 2064 2.79% 3.38% # number of callpals executed |
| 875system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed 876system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed | 871system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed 872system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed |
| 877system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed 878system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed 879system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed 880system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed 881system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed 882system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed 883system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed | 873system.cpu1.kern.callpal::swpipl 65156 88.12% 91.51% # number of callpals executed 874system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed 875system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed 876system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed 877system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed 878system.cpu1.kern.callpal::rti 3824 5.17% 99.76% # number of callpals executed 879system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed |
| 884system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 885system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 880system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 881system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 886system.cpu1.kern.callpal::total 71137 # number of callpals executed 887system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches 888system.cpu1.kern.mode_switch::user 465 # number of protection mode switches 889system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches 890system.cpu1.kern.mode_good::kernel 889 891system.cpu1.kern.mode_good::user 465 892system.cpu1.kern.mode_good::idle 424 893system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches | 882system.cpu1.kern.callpal::total 73942 # number of callpals executed 883system.cpu1.kern.mode_switch::kernel 2112 # number of protection mode switches 884system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 885system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches 886system.cpu1.kern.mode_good::kernel 911 887system.cpu1.kern.mode_good::user 464 888system.cpu1.kern.mode_good::idle 447 889system.cpu1.kern.mode_switch_good::kernel 0.431345 # fraction of useful protection mode switches |
| 894system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 890system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 895system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches 896system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches 897system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode 898system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode 899system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode 900system.cpu1.kern.swap_context 1986 # number of times the context was actually changed 901system.cpu1.dcache.tags.replacements 165381 # number of replacements 902system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use 903system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks. 904system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks. 905system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks. 906system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit. 907system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor 908system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy 909system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy | 891system.cpu1.kern.mode_switch_good::idle 0.153030 # fraction of useful protection mode switches 892system.cpu1.kern.mode_switch_good::total 0.331454 # fraction of useful protection mode switches 893system.cpu1.kern.mode_ticks::kernel 19415818500 0.98% 0.98% # number of ticks spent at the given mode 894system.cpu1.kern.mode_ticks::user 1728972000 0.09% 1.07% # number of ticks spent at the given mode 895system.cpu1.kern.mode_ticks::idle 1961439827500 98.93% 100.00% # number of ticks spent at the given mode 896system.cpu1.kern.swap_context 2065 # number of times the context was actually changed 897system.cpu1.dcache.tags.replacements 173710 # number of replacements 898system.cpu1.dcache.tags.tagsinuse 481.751289 # Cycle average of tags in use 899system.cpu1.dcache.tags.total_refs 4161033 # Total number of references to valid blocks. 900system.cpu1.dcache.tags.sampled_refs 174222 # Sample count of references to valid blocks. 901system.cpu1.dcache.tags.avg_refs 23.883511 # Average number of references to valid blocks. 902system.cpu1.dcache.tags.warmup_cycle 90304766500 # Cycle when the warmup percentage was hit. 903system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.751289 # Average occupied blocks per requestor 904system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940920 # Average percentage of cache occupancy 905system.cpu1.dcache.tags.occ_percent::total 0.940920 # Average percentage of cache occupancy |
| 910system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 906system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 911system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 912system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id 913system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id | 907system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 908system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 909system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id |
| 914system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 910system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 915system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses 916system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses 917system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits 918system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits 919system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits 920system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits 921system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits 922system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits 923system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits 924system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits 925system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits 926system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits 927system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits 928system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits 929system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses 930system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses 931system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses 932system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses 933system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses 934system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses 935system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses 936system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses 937system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses 938system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses 939system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses 940system.cpu1.dcache.overall_misses::total 179876 # number of overall misses 941system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles 942system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles 943system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles 944system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles 945system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles 946system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles 947system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles 948system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles 949system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles 950system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles 951system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles 952system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles 953system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses) 954system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses) 955system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses) 956system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses) 957system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses) 958system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses) 959system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses) 960system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses) 961system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses 962system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses 963system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses 964system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses 965system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses 966system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses 967system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses 968system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses 969system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses 970system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses 971system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses 972system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses 973system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses 974system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses 975system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses 976system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses 977system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency 978system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency 979system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency 980system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency 981system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency 982system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency 983system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency 984system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency 985system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency 986system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency 987system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency 988system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency | 911system.cpu1.dcache.tags.tag_accesses 17592927 # Number of tag accesses 912system.cpu1.dcache.tags.data_accesses 17592927 # Number of data accesses 913system.cpu1.dcache.ReadReq_hits::cpu1.data 2337017 # number of ReadReq hits 914system.cpu1.dcache.ReadReq_hits::total 2337017 # number of ReadReq hits 915system.cpu1.dcache.WriteReq_hits::cpu1.data 1705874 # number of WriteReq hits 916system.cpu1.dcache.WriteReq_hits::total 1705874 # number of WriteReq hits 917system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50407 # number of LoadLockedReq hits 918system.cpu1.dcache.LoadLockedReq_hits::total 50407 # number of LoadLockedReq hits 919system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53062 # number of StoreCondReq hits 920system.cpu1.dcache.StoreCondReq_hits::total 53062 # number of StoreCondReq hits 921system.cpu1.dcache.demand_hits::cpu1.data 4042891 # number of demand (read+write) hits 922system.cpu1.dcache.demand_hits::total 4042891 # number of demand (read+write) hits 923system.cpu1.dcache.overall_hits::cpu1.data 4042891 # number of overall hits 924system.cpu1.dcache.overall_hits::total 4042891 # number of overall hits 925system.cpu1.dcache.ReadReq_misses::cpu1.data 123430 # number of ReadReq misses 926system.cpu1.dcache.ReadReq_misses::total 123430 # number of ReadReq misses 927system.cpu1.dcache.WriteReq_misses::cpu1.data 65652 # number of WriteReq misses 928system.cpu1.dcache.WriteReq_misses::total 65652 # number of WriteReq misses 929system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9249 # number of LoadLockedReq misses 930system.cpu1.dcache.LoadLockedReq_misses::total 9249 # number of LoadLockedReq misses 931system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6101 # number of StoreCondReq misses 932system.cpu1.dcache.StoreCondReq_misses::total 6101 # number of StoreCondReq misses 933system.cpu1.dcache.demand_misses::cpu1.data 189082 # number of demand (read+write) misses 934system.cpu1.dcache.demand_misses::total 189082 # number of demand (read+write) misses 935system.cpu1.dcache.overall_misses::cpu1.data 189082 # number of overall misses 936system.cpu1.dcache.overall_misses::total 189082 # number of overall misses 937system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1554368000 # number of ReadReq miss cycles 938system.cpu1.dcache.ReadReq_miss_latency::total 1554368000 # number of ReadReq miss cycles 939system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1876323500 # number of WriteReq miss cycles 940system.cpu1.dcache.WriteReq_miss_latency::total 1876323500 # number of WriteReq miss cycles 941system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84244000 # number of LoadLockedReq miss cycles 942system.cpu1.dcache.LoadLockedReq_miss_latency::total 84244000 # number of LoadLockedReq miss cycles 943system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 98989500 # number of StoreCondReq miss cycles 944system.cpu1.dcache.StoreCondReq_miss_latency::total 98989500 # number of StoreCondReq miss cycles 945system.cpu1.dcache.demand_miss_latency::cpu1.data 3430691500 # number of demand (read+write) miss cycles 946system.cpu1.dcache.demand_miss_latency::total 3430691500 # number of demand (read+write) miss cycles 947system.cpu1.dcache.overall_miss_latency::cpu1.data 3430691500 # number of overall miss cycles 948system.cpu1.dcache.overall_miss_latency::total 3430691500 # number of overall miss cycles 949system.cpu1.dcache.ReadReq_accesses::cpu1.data 2460447 # number of ReadReq accesses(hits+misses) 950system.cpu1.dcache.ReadReq_accesses::total 2460447 # number of ReadReq accesses(hits+misses) 951system.cpu1.dcache.WriteReq_accesses::cpu1.data 1771526 # number of WriteReq accesses(hits+misses) 952system.cpu1.dcache.WriteReq_accesses::total 1771526 # number of WriteReq accesses(hits+misses) 953system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59656 # number of LoadLockedReq accesses(hits+misses) 954system.cpu1.dcache.LoadLockedReq_accesses::total 59656 # number of LoadLockedReq accesses(hits+misses) 955system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59163 # number of StoreCondReq accesses(hits+misses) 956system.cpu1.dcache.StoreCondReq_accesses::total 59163 # number of StoreCondReq accesses(hits+misses) 957system.cpu1.dcache.demand_accesses::cpu1.data 4231973 # number of demand (read+write) accesses 958system.cpu1.dcache.demand_accesses::total 4231973 # number of demand (read+write) accesses 959system.cpu1.dcache.overall_accesses::cpu1.data 4231973 # number of overall (read+write) accesses 960system.cpu1.dcache.overall_accesses::total 4231973 # number of overall (read+write) accesses 961system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050166 # miss rate for ReadReq accesses 962system.cpu1.dcache.ReadReq_miss_rate::total 0.050166 # miss rate for ReadReq accesses 963system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.037060 # miss rate for WriteReq accesses 964system.cpu1.dcache.WriteReq_miss_rate::total 0.037060 # miss rate for WriteReq accesses 965system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155039 # miss rate for LoadLockedReq accesses 966system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155039 # miss rate for LoadLockedReq accesses 967system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103122 # miss rate for StoreCondReq accesses 968system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103122 # miss rate for StoreCondReq accesses 969system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044679 # miss rate for demand accesses 970system.cpu1.dcache.demand_miss_rate::total 0.044679 # miss rate for demand accesses 971system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044679 # miss rate for overall accesses 972system.cpu1.dcache.overall_miss_rate::total 0.044679 # miss rate for overall accesses 973system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12593.113506 # average ReadReq miss latency 974system.cpu1.dcache.ReadReq_avg_miss_latency::total 12593.113506 # average ReadReq miss latency 975system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28579.837629 # average WriteReq miss latency 976system.cpu1.dcache.WriteReq_avg_miss_latency::total 28579.837629 # average WriteReq miss latency 977system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.444156 # average LoadLockedReq miss latency 978system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.444156 # average LoadLockedReq miss latency 979system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16225.127028 # average StoreCondReq miss latency 980system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16225.127028 # average StoreCondReq miss latency 981system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency 982system.cpu1.dcache.demand_avg_miss_latency::total 18143.934907 # average overall miss latency 983system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18143.934907 # average overall miss latency 984system.cpu1.dcache.overall_avg_miss_latency::total 18143.934907 # average overall miss latency |
| 989system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 990system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 991system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 992system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 993system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 994system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 995system.cpu1.dcache.fast_writes 0 # number of fast writes performed 996system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 985system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 986system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 987system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 988system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 989system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 990system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 991system.cpu1.dcache.fast_writes 0 # number of fast writes performed 992system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 997system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks 998system.cpu1.dcache.writebacks::total 113645 # number of writebacks 999system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses 1000system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses 1001system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses 1002system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses 1003system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses 1004system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses 1005system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses 1006system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses 1007system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses 1008system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses 1009system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses 1010system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses 1011system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable 1012system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable 1013system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable 1014system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable 1015system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses 1016system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses 1017system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles 1018system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles 1019system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles 1020system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles 1021system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles 1022system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles 1023system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles 1024system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles 1025system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles 1026system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles 1027system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles 1028system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles 1029system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles 1030system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles 1031system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles 1032system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles 1033system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles 1034system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles 1035system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses 1036system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses 1037system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses 1038system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses 1039system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses 1040system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses 1041system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses 1042system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses 1043system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses 1044system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses 1045system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses 1046system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses 1047system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency 1048system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency 1049system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency 1050system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency 1051system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency 1052system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency 1053system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency 1054system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency 1055system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency 1056system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency 1057system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency 1058system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency 1059system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency 1060system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency 1061system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency 1062system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency 1063system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency 1064system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency | 993system.cpu1.dcache.writebacks::writebacks 119711 # number of writebacks 994system.cpu1.dcache.writebacks::total 119711 # number of writebacks 995system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123430 # number of ReadReq MSHR misses 996system.cpu1.dcache.ReadReq_mshr_misses::total 123430 # number of ReadReq MSHR misses 997system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65652 # number of WriteReq MSHR misses 998system.cpu1.dcache.WriteReq_mshr_misses::total 65652 # number of WriteReq MSHR misses 999system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9249 # number of LoadLockedReq MSHR misses 1000system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9249 # number of LoadLockedReq MSHR misses 1001system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6101 # number of StoreCondReq MSHR misses 1002system.cpu1.dcache.StoreCondReq_mshr_misses::total 6101 # number of StoreCondReq MSHR misses 1003system.cpu1.dcache.demand_mshr_misses::cpu1.data 189082 # number of demand (read+write) MSHR misses 1004system.cpu1.dcache.demand_mshr_misses::total 189082 # number of demand (read+write) MSHR misses 1005system.cpu1.dcache.overall_mshr_misses::cpu1.data 189082 # number of overall MSHR misses 1006system.cpu1.dcache.overall_mshr_misses::total 189082 # number of overall MSHR misses 1007system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable 1008system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable 1009system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3347 # number of WriteReq MSHR uncacheable 1010system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3347 # number of WriteReq MSHR uncacheable 1011system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3465 # number of overall MSHR uncacheable misses 1012system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3465 # number of overall MSHR uncacheable misses 1013system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1430938000 # number of ReadReq MSHR miss cycles 1014system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1430938000 # number of ReadReq MSHR miss cycles 1015system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1810671500 # number of WriteReq MSHR miss cycles 1016system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1810671500 # number of WriteReq MSHR miss cycles 1017system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74995000 # number of LoadLockedReq MSHR miss cycles 1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74995000 # number of LoadLockedReq MSHR miss cycles 1019system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 92888500 # number of StoreCondReq MSHR miss cycles 1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 92888500 # number of StoreCondReq MSHR miss cycles 1021system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3241609500 # number of demand (read+write) MSHR miss cycles 1022system.cpu1.dcache.demand_mshr_miss_latency::total 3241609500 # number of demand (read+write) MSHR miss cycles 1023system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3241609500 # number of overall MSHR miss cycles 1024system.cpu1.dcache.overall_mshr_miss_latency::total 3241609500 # number of overall MSHR miss cycles 1025system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23714500 # number of ReadReq MSHR uncacheable cycles 1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23714500 # number of ReadReq MSHR uncacheable cycles 1027system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 747400000 # number of WriteReq MSHR uncacheable cycles 1028system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 747400000 # number of WriteReq MSHR uncacheable cycles 1029system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 771114500 # number of overall MSHR uncacheable cycles 1030system.cpu1.dcache.overall_mshr_uncacheable_latency::total 771114500 # number of overall MSHR uncacheable cycles 1031system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050166 # mshr miss rate for ReadReq accesses 1032system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050166 # mshr miss rate for ReadReq accesses 1033system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037060 # mshr miss rate for WriteReq accesses 1034system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037060 # mshr miss rate for WriteReq accesses 1035system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155039 # mshr miss rate for LoadLockedReq accesses 1036system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155039 # mshr miss rate for LoadLockedReq accesses 1037system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103122 # mshr miss rate for StoreCondReq accesses 1038system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103122 # mshr miss rate for StoreCondReq accesses 1039system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for demand accesses 1040system.cpu1.dcache.demand_mshr_miss_rate::total 0.044679 # mshr miss rate for demand accesses 1041system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044679 # mshr miss rate for overall accesses 1042system.cpu1.dcache.overall_mshr_miss_rate::total 0.044679 # mshr miss rate for overall accesses 1043system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11593.113506 # average ReadReq mshr miss latency 1044system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11593.113506 # average ReadReq mshr miss latency 1045system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27579.837629 # average WriteReq mshr miss latency 1046system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27579.837629 # average WriteReq mshr miss latency 1047system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8108.444156 # average LoadLockedReq mshr miss latency 1048system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8108.444156 # average LoadLockedReq mshr miss latency 1049system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15225.127028 # average StoreCondReq mshr miss latency 1050system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15225.127028 # average StoreCondReq mshr miss latency 1051system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency 1052system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency 1053system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17143.934907 # average overall mshr miss latency 1054system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17143.934907 # average overall mshr miss latency 1055system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200970.338983 # average ReadReq mshr uncacheable latency 1056system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 200970.338983 # average ReadReq mshr uncacheable latency 1057system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223304.451748 # average WriteReq mshr uncacheable latency 1058system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 223304.451748 # average WriteReq mshr uncacheable latency 1059system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222543.867244 # average overall mshr uncacheable latency 1060system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222543.867244 # average overall mshr uncacheable latency |
| 1065system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1061system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1066system.cpu1.icache.tags.replacements 313887 # number of replacements 1067system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use 1068system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks. 1069system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks. 1070system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks. 1071system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit. 1072system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor 1073system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy 1074system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy | 1062system.cpu1.icache.tags.replacements 331160 # number of replacements 1063system.cpu1.icache.tags.tagsinuse 442.919388 # Cycle average of tags in use 1064system.cpu1.icache.tags.total_refs 13331662 # Total number of references to valid blocks. 1065system.cpu1.icache.tags.sampled_refs 331672 # Sample count of references to valid blocks. 1066system.cpu1.icache.tags.avg_refs 40.195319 # Average number of references to valid blocks. 1067system.cpu1.icache.tags.warmup_cycle 1976558526500 # Cycle when the warmup percentage was hit. 1068system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.919388 # Average occupied blocks per requestor 1069system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865077 # Average percentage of cache occupancy 1070system.cpu1.icache.tags.occ_percent::total 0.865077 # Average percentage of cache occupancy |
| 1075system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1071system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1076system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1077system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 1078system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id 1079system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id | 1072system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id 1073system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 1074system.cpu1.icache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id 1075system.cpu1.icache.tags.age_task_id_blocks_1024::3 31 # Occupied blocks per task id |
| 1080system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1076system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1081system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses 1082system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses 1083system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits 1084system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits 1085system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits 1086system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits 1087system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits 1088system.cpu1.icache.overall_hits::total 12790016 # number of overall hits 1089system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses 1090system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses 1091system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses 1092system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses 1093system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses 1094system.cpu1.icache.overall_misses::total 314441 # number of overall misses 1095system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles 1096system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles 1097system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles 1098system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles 1099system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles 1100system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles 1101system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses) 1102system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses) 1103system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses 1104system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses 1105system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses 1106system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses 1107system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses 1108system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses 1109system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses 1110system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses 1111system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses 1112system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses 1113system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency 1114system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency 1115system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency 1116system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency 1117system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency 1118system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency | 1077system.cpu1.icache.tags.tag_accesses 13995086 # Number of tag accesses 1078system.cpu1.icache.tags.data_accesses 13995086 # Number of data accesses 1079system.cpu1.icache.ReadReq_hits::cpu1.inst 13331662 # number of ReadReq hits 1080system.cpu1.icache.ReadReq_hits::total 13331662 # number of ReadReq hits 1081system.cpu1.icache.demand_hits::cpu1.inst 13331662 # number of demand (read+write) hits 1082system.cpu1.icache.demand_hits::total 13331662 # number of demand (read+write) hits 1083system.cpu1.icache.overall_hits::cpu1.inst 13331662 # number of overall hits 1084system.cpu1.icache.overall_hits::total 13331662 # number of overall hits 1085system.cpu1.icache.ReadReq_misses::cpu1.inst 331712 # number of ReadReq misses 1086system.cpu1.icache.ReadReq_misses::total 331712 # number of ReadReq misses 1087system.cpu1.icache.demand_misses::cpu1.inst 331712 # number of demand (read+write) misses 1088system.cpu1.icache.demand_misses::total 331712 # number of demand (read+write) misses 1089system.cpu1.icache.overall_misses::cpu1.inst 331712 # number of overall misses 1090system.cpu1.icache.overall_misses::total 331712 # number of overall misses 1091system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4531331500 # number of ReadReq miss cycles 1092system.cpu1.icache.ReadReq_miss_latency::total 4531331500 # number of ReadReq miss cycles 1093system.cpu1.icache.demand_miss_latency::cpu1.inst 4531331500 # number of demand (read+write) miss cycles 1094system.cpu1.icache.demand_miss_latency::total 4531331500 # number of demand (read+write) miss cycles 1095system.cpu1.icache.overall_miss_latency::cpu1.inst 4531331500 # number of overall miss cycles 1096system.cpu1.icache.overall_miss_latency::total 4531331500 # number of overall miss cycles 1097system.cpu1.icache.ReadReq_accesses::cpu1.inst 13663374 # number of ReadReq accesses(hits+misses) 1098system.cpu1.icache.ReadReq_accesses::total 13663374 # number of ReadReq accesses(hits+misses) 1099system.cpu1.icache.demand_accesses::cpu1.inst 13663374 # number of demand (read+write) accesses 1100system.cpu1.icache.demand_accesses::total 13663374 # number of demand (read+write) accesses 1101system.cpu1.icache.overall_accesses::cpu1.inst 13663374 # number of overall (read+write) accesses 1102system.cpu1.icache.overall_accesses::total 13663374 # number of overall (read+write) accesses 1103system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024277 # miss rate for ReadReq accesses 1104system.cpu1.icache.ReadReq_miss_rate::total 0.024277 # miss rate for ReadReq accesses 1105system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024277 # miss rate for demand accesses 1106system.cpu1.icache.demand_miss_rate::total 0.024277 # miss rate for demand accesses 1107system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024277 # miss rate for overall accesses 1108system.cpu1.icache.overall_miss_rate::total 0.024277 # miss rate for overall accesses 1109system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13660.438875 # average ReadReq miss latency 1110system.cpu1.icache.ReadReq_avg_miss_latency::total 13660.438875 # average ReadReq miss latency 1111system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency 1112system.cpu1.icache.demand_avg_miss_latency::total 13660.438875 # average overall miss latency 1113system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13660.438875 # average overall miss latency 1114system.cpu1.icache.overall_avg_miss_latency::total 13660.438875 # average overall miss latency |
| 1119system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1120system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1121system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1122system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1123system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1124system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1125system.cpu1.icache.fast_writes 0 # number of fast writes performed 1126system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1115system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1116system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1117system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1118system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1119system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1120system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1121system.cpu1.icache.fast_writes 0 # number of fast writes performed 1122system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1127system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses 1128system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses 1129system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses 1130system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses 1131system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses 1132system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses 1133system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles 1134system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles 1135system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles 1136system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles 1137system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles 1138system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles 1139system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses 1140system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses 1141system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses 1142system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses 1143system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses 1144system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses 1145system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency 1146system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency 1147system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency 1148system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency 1149system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency 1150system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency | 1123system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331712 # number of ReadReq MSHR misses 1124system.cpu1.icache.ReadReq_mshr_misses::total 331712 # number of ReadReq MSHR misses 1125system.cpu1.icache.demand_mshr_misses::cpu1.inst 331712 # number of demand (read+write) MSHR misses 1126system.cpu1.icache.demand_mshr_misses::total 331712 # number of demand (read+write) MSHR misses 1127system.cpu1.icache.overall_mshr_misses::cpu1.inst 331712 # number of overall MSHR misses 1128system.cpu1.icache.overall_mshr_misses::total 331712 # number of overall MSHR misses 1129system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4199619500 # number of ReadReq MSHR miss cycles 1130system.cpu1.icache.ReadReq_mshr_miss_latency::total 4199619500 # number of ReadReq MSHR miss cycles 1131system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4199619500 # number of demand (read+write) MSHR miss cycles 1132system.cpu1.icache.demand_mshr_miss_latency::total 4199619500 # number of demand (read+write) MSHR miss cycles 1133system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4199619500 # number of overall MSHR miss cycles 1134system.cpu1.icache.overall_mshr_miss_latency::total 4199619500 # number of overall MSHR miss cycles 1135system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for ReadReq accesses 1136system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024277 # mshr miss rate for ReadReq accesses 1137system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for demand accesses 1138system.cpu1.icache.demand_mshr_miss_rate::total 0.024277 # mshr miss rate for demand accesses 1139system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024277 # mshr miss rate for overall accesses 1140system.cpu1.icache.overall_mshr_miss_rate::total 0.024277 # mshr miss rate for overall accesses 1141system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average ReadReq mshr miss latency 1142system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12660.438875 # average ReadReq mshr miss latency 1143system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency 1144system.cpu1.icache.demand_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency 1145system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12660.438875 # average overall mshr miss latency 1146system.cpu1.icache.overall_avg_mshr_miss_latency::total 12660.438875 # average overall mshr miss latency |
| 1151system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1152system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1153system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1154system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1155system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1156system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1157system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1158system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1159system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1160system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1161system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1162system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1163system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 1147system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1148system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1149system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1150system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1151system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1152system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1153system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1154system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1155system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1156system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1157system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1158system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1159system.disk2.dma_write_txs 1 # Number of DMA write transactions. |
| 1164system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1165system.iobus.trans_dist::ReadResp 7373 # Transaction distribution 1166system.iobus.trans_dist::WriteReq 55595 # Transaction distribution 1167system.iobus.trans_dist::WriteResp 55595 # Transaction distribution 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) | 1160system.iobus.trans_dist::ReadReq 7379 # Transaction distribution 1161system.iobus.trans_dist::ReadResp 7379 # Transaction distribution 1162system.iobus.trans_dist::WriteReq 55683 # Transaction distribution 1163system.iobus.trans_dist::WriteResp 55683 # Transaction distribution 1164system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14064 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) |
| 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) | 1166system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) |
| 1174system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) | 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) |
| 1176system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 1180system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 1183system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) | 1176system.iobus.pkt_count_system.bridge.master::total 42670 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count::total 126124 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56256 # Cumulative packet size per connected master and slave (bytes) 1181system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) |
| 1186system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) | 1182system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) |
| 1190system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) | 1186system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) |
| 1192system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 1188system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1196system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks) | 1192system.iobus.pkt_size_system.bridge.master::total 82499 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size::total 2744123 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.reqLayer0.occupancy 13414000 # Layer occupancy (ticks) |
| 1201system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1197system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1202system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) | 1198system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) |
| 1203system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1205system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1207system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1209system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1211system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1199system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1200system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1201system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1203system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1205system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1207system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1212system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) | 1208system.iobus.reqLayer24.occupancy 2454000 # Layer occupancy (ticks) |
| 1213system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1209system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1214system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) | 1210system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) |
| 1215system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1216system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1217system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1218system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1219system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1220system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1221system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1211system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1212system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1213system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1214system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1215system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1216system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1217system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1222system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks) | 1218system.iobus.reqLayer29.occupancy 215099489 # Layer occupancy (ticks) |
| 1223system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1224system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1225system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 1219system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1220system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1221system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 1226system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks) | 1222system.iobus.respLayer0.occupancy 28539000 # Layer occupancy (ticks) |
| 1227system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1223system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1228system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) | 1224system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) |
| 1229system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1225system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1230system.iocache.tags.replacements 41694 # number of replacements 1231system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use | 1226system.iocache.tags.replacements 41695 # number of replacements 1227system.iocache.tags.tagsinuse 0.566806 # Cycle average of tags in use |
| 1232system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1228system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1233system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. | 1229system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. |
| 1234system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1230system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1235system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit. 1236system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor 1237system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy 1238system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy | 1231system.iocache.tags.warmup_cycle 1775098751000 # Cycle when the warmup percentage was hit. 1232system.iocache.tags.occ_blocks::tsunami.ide 0.566806 # Average occupied blocks per requestor 1233system.iocache.tags.occ_percent::tsunami.ide 0.035425 # Average percentage of cache occupancy 1234system.iocache.tags.occ_percent::total 0.035425 # Average percentage of cache occupancy |
| 1239system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1240system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1241system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1235system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1236system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1237system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1242system.iocache.tags.tag_accesses 375534 # Number of tag accesses 1243system.iocache.tags.data_accesses 375534 # Number of data accesses 1244system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 1245system.iocache.ReadReq_misses::total 174 # number of ReadReq misses | 1238system.iocache.tags.tag_accesses 375543 # Number of tag accesses 1239system.iocache.tags.data_accesses 375543 # Number of data accesses 1240system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 1241system.iocache.ReadReq_misses::total 175 # number of ReadReq misses |
| 1246system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1247system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses | 1242system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1243system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses |
| 1248system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses 1249system.iocache.demand_misses::total 174 # number of demand (read+write) misses 1250system.iocache.overall_misses::tsunami.ide 174 # number of overall misses 1251system.iocache.overall_misses::total 174 # number of overall misses 1252system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles 1253system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles 1254system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles 1255system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles 1256system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles 1257system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles 1258system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles 1259system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles 1260system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 1261system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) | 1244system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses 1245system.iocache.demand_misses::total 175 # number of demand (read+write) misses 1246system.iocache.overall_misses::tsunami.ide 175 # number of overall misses 1247system.iocache.overall_misses::total 175 # number of overall misses 1248system.iocache.ReadReq_miss_latency::tsunami.ide 22127883 # number of ReadReq miss cycles 1249system.iocache.ReadReq_miss_latency::total 22127883 # number of ReadReq miss cycles 1250system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428057606 # number of WriteLineReq miss cycles 1251system.iocache.WriteLineReq_miss_latency::total 5428057606 # number of WriteLineReq miss cycles 1252system.iocache.demand_miss_latency::tsunami.ide 22127883 # number of demand (read+write) miss cycles 1253system.iocache.demand_miss_latency::total 22127883 # number of demand (read+write) miss cycles 1254system.iocache.overall_miss_latency::tsunami.ide 22127883 # number of overall miss cycles 1255system.iocache.overall_miss_latency::total 22127883 # number of overall miss cycles 1256system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 1257system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) |
| 1262system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1263system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) | 1258system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1259system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) |
| 1264system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses 1265system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses 1266system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses 1267system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses | 1260system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses 1261system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses 1262system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses 1263system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses |
| 1268system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1269system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1270system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1271system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1272system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1273system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1274system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1275system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1264system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1265system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1266system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1267system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1268system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1269system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1270system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1271system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1276system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency 1277system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency 1278system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency 1279system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency 1280system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency 1281system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency 1282system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency 1283system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency 1284system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1272system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126445.045714 # average ReadReq miss latency 1273system.iocache.ReadReq_avg_miss_latency::total 126445.045714 # average ReadReq miss latency 1274system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130632.884241 # average WriteLineReq miss latency 1275system.iocache.WriteLineReq_avg_miss_latency::total 130632.884241 # average WriteLineReq miss latency 1276system.iocache.demand_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency 1277system.iocache.demand_avg_miss_latency::total 126445.045714 # average overall miss latency 1278system.iocache.overall_avg_miss_latency::tsunami.ide 126445.045714 # average overall miss latency 1279system.iocache.overall_avg_miss_latency::total 126445.045714 # average overall miss latency 1280system.iocache.blocked_cycles::no_mshrs 55 # number of cycles access was blocked |
| 1285system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1281system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1286system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 1282system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked |
| 1287system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1283system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1288system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1284system.iocache.avg_blocked_cycles::no_mshrs 18.333333 # average number of cycles each access was blocked |
| 1289system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1290system.iocache.fast_writes 0 # number of fast writes performed 1291system.iocache.cache_copies 0 # number of cache copies performed 1292system.iocache.writebacks::writebacks 41520 # number of writebacks 1293system.iocache.writebacks::total 41520 # number of writebacks | 1285system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1286system.iocache.fast_writes 0 # number of fast writes performed 1287system.iocache.cache_copies 0 # number of cache copies performed 1288system.iocache.writebacks::writebacks 41520 # number of writebacks 1289system.iocache.writebacks::total 41520 # number of writebacks |
| 1294system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 1295system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses | 1290system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 1291system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses |
| 1296system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1297system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses | 1292system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1293system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses |
| 1298system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses 1299system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 1300system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses 1301system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses 1302system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles 1303system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles 1304system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles 1305system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles 1306system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles 1307system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles 1308system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles 1309system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles | 1294system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses 1295system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses 1296system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses 1297system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses 1298system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13377883 # number of ReadReq MSHR miss cycles 1299system.iocache.ReadReq_mshr_miss_latency::total 13377883 # number of ReadReq MSHR miss cycles 1300system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350457606 # number of WriteLineReq MSHR miss cycles 1301system.iocache.WriteLineReq_mshr_miss_latency::total 3350457606 # number of WriteLineReq MSHR miss cycles 1302system.iocache.demand_mshr_miss_latency::tsunami.ide 13377883 # number of demand (read+write) MSHR miss cycles 1303system.iocache.demand_mshr_miss_latency::total 13377883 # number of demand (read+write) MSHR miss cycles 1304system.iocache.overall_mshr_miss_latency::tsunami.ide 13377883 # number of overall MSHR miss cycles 1305system.iocache.overall_mshr_miss_latency::total 13377883 # number of overall MSHR miss cycles |
| 1310system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1311system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1312system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1313system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1314system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1315system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1316system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1317system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1306system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1307system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1308system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1309system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1310system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1311system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1312system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1313system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1318system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency 1319system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency 1320system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency 1321system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency 1322system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency 1323system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency 1324system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency 1325system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency | 1314system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average ReadReq mshr miss latency 1315system.iocache.ReadReq_avg_mshr_miss_latency::total 76445.045714 # average ReadReq mshr miss latency 1316system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80632.884241 # average WriteLineReq mshr miss latency 1317system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80632.884241 # average WriteLineReq mshr miss latency 1318system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency 1319system.iocache.demand_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency 1320system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76445.045714 # average overall mshr miss latency 1321system.iocache.overall_avg_mshr_miss_latency::total 76445.045714 # average overall mshr miss latency |
| 1326system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1322system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1327system.l2c.tags.replacements 341250 # number of replacements 1328system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use 1329system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks. 1330system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks. 1331system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks. 1332system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit. 1333system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor 1334system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor 1335system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor 1336system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor 1337system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor 1338system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy 1339system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy 1340system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy 1341system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy 1342system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy 1343system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy 1344system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id 1345system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id 1346system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id 1347system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id 1348system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id 1349system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id 1350system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id 1351system.l2c.tags.tag_accesses 35905885 # Number of tag accesses 1352system.l2c.tags.data_accesses 35905885 # Number of data accesses 1353system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits 1354system.l2c.Writeback_hits::total 793586 # number of Writeback hits 1355system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits 1356system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits 1357system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits 1358system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits | 1323system.l2c.tags.replacements 341926 # number of replacements 1324system.l2c.tags.tagsinuse 65167.982973 # Cycle average of tags in use 1325system.l2c.tags.total_refs 3685196 # Total number of references to valid blocks. 1326system.l2c.tags.sampled_refs 406932 # Sample count of references to valid blocks. 1327system.l2c.tags.avg_refs 9.056049 # Average number of references to valid blocks. 1328system.l2c.tags.warmup_cycle 12918028000 # Cycle when the warmup percentage was hit. 1329system.l2c.tags.occ_blocks::writebacks 54774.174056 # Average occupied blocks per requestor 1330system.l2c.tags.occ_blocks::cpu0.inst 4860.572445 # Average occupied blocks per requestor 1331system.l2c.tags.occ_blocks::cpu0.data 5374.369214 # Average occupied blocks per requestor 1332system.l2c.tags.occ_blocks::cpu1.inst 120.511186 # Average occupied blocks per requestor 1333system.l2c.tags.occ_blocks::cpu1.data 38.356073 # Average occupied blocks per requestor 1334system.l2c.tags.occ_percent::writebacks 0.835788 # Average percentage of cache occupancy 1335system.l2c.tags.occ_percent::cpu0.inst 0.074166 # Average percentage of cache occupancy 1336system.l2c.tags.occ_percent::cpu0.data 0.082006 # Average percentage of cache occupancy 1337system.l2c.tags.occ_percent::cpu1.inst 0.001839 # Average percentage of cache occupancy 1338system.l2c.tags.occ_percent::cpu1.data 0.000585 # Average percentage of cache occupancy 1339system.l2c.tags.occ_percent::total 0.994385 # Average percentage of cache occupancy 1340system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id 1341system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 1342system.l2c.tags.age_task_id_blocks_1024::1 516 # Occupied blocks per task id 1343system.l2c.tags.age_task_id_blocks_1024::2 5383 # Occupied blocks per task id 1344system.l2c.tags.age_task_id_blocks_1024::3 6300 # Occupied blocks per task id 1345system.l2c.tags.age_task_id_blocks_1024::4 52705 # Occupied blocks per task id 1346system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id 1347system.l2c.tags.tag_accesses 35906123 # Number of tag accesses 1348system.l2c.tags.data_accesses 35906123 # Number of data accesses 1349system.l2c.Writeback_hits::writebacks 792419 # number of Writeback hits 1350system.l2c.Writeback_hits::total 792419 # number of Writeback hits 1351system.l2c.UpgradeReq_hits::cpu0.data 186 # number of UpgradeReq hits 1352system.l2c.UpgradeReq_hits::cpu1.data 557 # number of UpgradeReq hits 1353system.l2c.UpgradeReq_hits::total 743 # number of UpgradeReq hits 1354system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits |
| 1359system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits | 1355system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits |
| 1360system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits 1361system.l2c.ReadExReq_hits::cpu0.data 126818 # number of ReadExReq hits 1362system.l2c.ReadExReq_hits::cpu1.data 46992 # number of ReadExReq hits 1363system.l2c.ReadExReq_hits::total 173810 # number of ReadExReq hits 1364system.l2c.ReadCleanReq_hits::cpu0.inst 688011 # number of ReadCleanReq hits 1365system.l2c.ReadCleanReq_hits::cpu1.inst 313935 # number of ReadCleanReq hits 1366system.l2c.ReadCleanReq_hits::total 1001946 # number of ReadCleanReq hits 1367system.l2c.ReadSharedReq_hits::cpu0.data 665063 # number of ReadSharedReq hits 1368system.l2c.ReadSharedReq_hits::cpu1.data 108615 # number of ReadSharedReq hits 1369system.l2c.ReadSharedReq_hits::total 773678 # number of ReadSharedReq hits 1370system.l2c.demand_hits::cpu0.inst 688011 # number of demand (read+write) hits 1371system.l2c.demand_hits::cpu0.data 791881 # number of demand (read+write) hits 1372system.l2c.demand_hits::cpu1.inst 313935 # number of demand (read+write) hits 1373system.l2c.demand_hits::cpu1.data 155607 # number of demand (read+write) hits 1374system.l2c.demand_hits::total 1949434 # number of demand (read+write) hits 1375system.l2c.overall_hits::cpu0.inst 688011 # number of overall hits 1376system.l2c.overall_hits::cpu0.data 791881 # number of overall hits 1377system.l2c.overall_hits::cpu1.inst 313935 # number of overall hits 1378system.l2c.overall_hits::cpu1.data 155607 # number of overall hits 1379system.l2c.overall_hits::total 1949434 # number of overall hits 1380system.l2c.UpgradeReq_misses::cpu0.data 2935 # number of UpgradeReq misses 1381system.l2c.UpgradeReq_misses::cpu1.data 1733 # number of UpgradeReq misses 1382system.l2c.UpgradeReq_misses::total 4668 # number of UpgradeReq misses 1383system.l2c.SCUpgradeReq_misses::cpu0.data 882 # number of SCUpgradeReq misses 1384system.l2c.SCUpgradeReq_misses::cpu1.data 893 # number of SCUpgradeReq misses 1385system.l2c.SCUpgradeReq_misses::total 1775 # number of SCUpgradeReq misses 1386system.l2c.ReadExReq_misses::cpu0.data 115542 # number of ReadExReq misses 1387system.l2c.ReadExReq_misses::cpu1.data 6588 # number of ReadExReq misses 1388system.l2c.ReadExReq_misses::total 122130 # number of ReadExReq misses 1389system.l2c.ReadCleanReq_misses::cpu0.inst 12999 # number of ReadCleanReq misses 1390system.l2c.ReadCleanReq_misses::cpu1.inst 505 # number of ReadCleanReq misses 1391system.l2c.ReadCleanReq_misses::total 13504 # number of ReadCleanReq misses 1392system.l2c.ReadSharedReq_misses::cpu0.data 271618 # number of ReadSharedReq misses 1393system.l2c.ReadSharedReq_misses::cpu1.data 236 # number of ReadSharedReq misses 1394system.l2c.ReadSharedReq_misses::total 271854 # number of ReadSharedReq misses 1395system.l2c.demand_misses::cpu0.inst 12999 # number of demand (read+write) misses 1396system.l2c.demand_misses::cpu0.data 387160 # number of demand (read+write) misses 1397system.l2c.demand_misses::cpu1.inst 505 # number of demand (read+write) misses 1398system.l2c.demand_misses::cpu1.data 6824 # number of demand (read+write) misses 1399system.l2c.demand_misses::total 407488 # number of demand (read+write) misses 1400system.l2c.overall_misses::cpu0.inst 12999 # number of overall misses 1401system.l2c.overall_misses::cpu0.data 387160 # number of overall misses 1402system.l2c.overall_misses::cpu1.inst 505 # number of overall misses 1403system.l2c.overall_misses::cpu1.data 6824 # number of overall misses 1404system.l2c.overall_misses::total 407488 # number of overall misses 1405system.l2c.UpgradeReq_miss_latency::cpu0.data 1432000 # number of UpgradeReq miss cycles 1406system.l2c.UpgradeReq_miss_latency::cpu1.data 13109500 # number of UpgradeReq miss cycles 1407system.l2c.UpgradeReq_miss_latency::total 14541500 # number of UpgradeReq miss cycles 1408system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1162500 # number of SCUpgradeReq miss cycles 1409system.l2c.SCUpgradeReq_miss_latency::cpu1.data 214000 # number of SCUpgradeReq miss cycles 1410system.l2c.SCUpgradeReq_miss_latency::total 1376500 # number of SCUpgradeReq miss cycles 1411system.l2c.ReadExReq_miss_latency::cpu0.data 8812996500 # number of ReadExReq miss cycles 1412system.l2c.ReadExReq_miss_latency::cpu1.data 538144500 # number of ReadExReq miss cycles 1413system.l2c.ReadExReq_miss_latency::total 9351141000 # number of ReadExReq miss cycles 1414system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1038304000 # number of ReadCleanReq miss cycles 1415system.l2c.ReadCleanReq_miss_latency::cpu1.inst 40757500 # number of ReadCleanReq miss cycles 1416system.l2c.ReadCleanReq_miss_latency::total 1079061500 # number of ReadCleanReq miss cycles 1417system.l2c.ReadSharedReq_miss_latency::cpu0.data 19659409500 # number of ReadSharedReq miss cycles 1418system.l2c.ReadSharedReq_miss_latency::cpu1.data 18967000 # number of ReadSharedReq miss cycles 1419system.l2c.ReadSharedReq_miss_latency::total 19678376500 # number of ReadSharedReq miss cycles 1420system.l2c.demand_miss_latency::cpu0.inst 1038304000 # number of demand (read+write) miss cycles 1421system.l2c.demand_miss_latency::cpu0.data 28472406000 # number of demand (read+write) miss cycles 1422system.l2c.demand_miss_latency::cpu1.inst 40757500 # number of demand (read+write) miss cycles 1423system.l2c.demand_miss_latency::cpu1.data 557111500 # number of demand (read+write) miss cycles 1424system.l2c.demand_miss_latency::total 30108579000 # number of demand (read+write) miss cycles 1425system.l2c.overall_miss_latency::cpu0.inst 1038304000 # number of overall miss cycles 1426system.l2c.overall_miss_latency::cpu0.data 28472406000 # number of overall miss cycles 1427system.l2c.overall_miss_latency::cpu1.inst 40757500 # number of overall miss cycles 1428system.l2c.overall_miss_latency::cpu1.data 557111500 # number of overall miss cycles 1429system.l2c.overall_miss_latency::total 30108579000 # number of overall miss cycles 1430system.l2c.Writeback_accesses::writebacks 793586 # number of Writeback accesses(hits+misses) 1431system.l2c.Writeback_accesses::total 793586 # number of Writeback accesses(hits+misses) 1432system.l2c.UpgradeReq_accesses::cpu0.data 3108 # number of UpgradeReq accesses(hits+misses) 1433system.l2c.UpgradeReq_accesses::cpu1.data 2268 # number of UpgradeReq accesses(hits+misses) 1434system.l2c.UpgradeReq_accesses::total 5376 # number of UpgradeReq accesses(hits+misses) 1435system.l2c.SCUpgradeReq_accesses::cpu0.data 925 # number of SCUpgradeReq accesses(hits+misses) 1436system.l2c.SCUpgradeReq_accesses::cpu1.data 917 # number of SCUpgradeReq accesses(hits+misses) 1437system.l2c.SCUpgradeReq_accesses::total 1842 # number of SCUpgradeReq accesses(hits+misses) 1438system.l2c.ReadExReq_accesses::cpu0.data 242360 # number of ReadExReq accesses(hits+misses) 1439system.l2c.ReadExReq_accesses::cpu1.data 53580 # number of ReadExReq accesses(hits+misses) 1440system.l2c.ReadExReq_accesses::total 295940 # number of ReadExReq accesses(hits+misses) 1441system.l2c.ReadCleanReq_accesses::cpu0.inst 701010 # number of ReadCleanReq accesses(hits+misses) 1442system.l2c.ReadCleanReq_accesses::cpu1.inst 314440 # number of ReadCleanReq accesses(hits+misses) 1443system.l2c.ReadCleanReq_accesses::total 1015450 # number of ReadCleanReq accesses(hits+misses) 1444system.l2c.ReadSharedReq_accesses::cpu0.data 936681 # number of ReadSharedReq accesses(hits+misses) 1445system.l2c.ReadSharedReq_accesses::cpu1.data 108851 # number of ReadSharedReq accesses(hits+misses) 1446system.l2c.ReadSharedReq_accesses::total 1045532 # number of ReadSharedReq accesses(hits+misses) 1447system.l2c.demand_accesses::cpu0.inst 701010 # number of demand (read+write) accesses 1448system.l2c.demand_accesses::cpu0.data 1179041 # number of demand (read+write) accesses 1449system.l2c.demand_accesses::cpu1.inst 314440 # number of demand (read+write) accesses 1450system.l2c.demand_accesses::cpu1.data 162431 # number of demand (read+write) accesses 1451system.l2c.demand_accesses::total 2356922 # number of demand (read+write) accesses 1452system.l2c.overall_accesses::cpu0.inst 701010 # number of overall (read+write) accesses 1453system.l2c.overall_accesses::cpu0.data 1179041 # number of overall (read+write) accesses 1454system.l2c.overall_accesses::cpu1.inst 314440 # number of overall (read+write) accesses 1455system.l2c.overall_accesses::cpu1.data 162431 # number of overall (read+write) accesses 1456system.l2c.overall_accesses::total 2356922 # number of overall (read+write) accesses 1457system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944337 # miss rate for UpgradeReq accesses 1458system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764109 # miss rate for UpgradeReq accesses 1459system.l2c.UpgradeReq_miss_rate::total 0.868304 # miss rate for UpgradeReq accesses 1460system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.953514 # miss rate for SCUpgradeReq accesses 1461system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973828 # miss rate for SCUpgradeReq accesses 1462system.l2c.SCUpgradeReq_miss_rate::total 0.963626 # miss rate for SCUpgradeReq accesses 1463system.l2c.ReadExReq_miss_rate::cpu0.data 0.476737 # miss rate for ReadExReq accesses 1464system.l2c.ReadExReq_miss_rate::cpu1.data 0.122956 # miss rate for ReadExReq accesses 1465system.l2c.ReadExReq_miss_rate::total 0.412685 # miss rate for ReadExReq accesses 1466system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018543 # miss rate for ReadCleanReq accesses 1467system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001606 # miss rate for ReadCleanReq accesses 1468system.l2c.ReadCleanReq_miss_rate::total 0.013299 # miss rate for ReadCleanReq accesses 1469system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.289979 # miss rate for ReadSharedReq accesses 1470system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002168 # miss rate for ReadSharedReq accesses 1471system.l2c.ReadSharedReq_miss_rate::total 0.260015 # miss rate for ReadSharedReq accesses 1472system.l2c.demand_miss_rate::cpu0.inst 0.018543 # miss rate for demand accesses 1473system.l2c.demand_miss_rate::cpu0.data 0.328369 # miss rate for demand accesses 1474system.l2c.demand_miss_rate::cpu1.inst 0.001606 # miss rate for demand accesses 1475system.l2c.demand_miss_rate::cpu1.data 0.042012 # miss rate for demand accesses 1476system.l2c.demand_miss_rate::total 0.172890 # miss rate for demand accesses 1477system.l2c.overall_miss_rate::cpu0.inst 0.018543 # miss rate for overall accesses 1478system.l2c.overall_miss_rate::cpu0.data 0.328369 # miss rate for overall accesses 1479system.l2c.overall_miss_rate::cpu1.inst 0.001606 # miss rate for overall accesses 1480system.l2c.overall_miss_rate::cpu1.data 0.042012 # miss rate for overall accesses 1481system.l2c.overall_miss_rate::total 0.172890 # miss rate for overall accesses 1482system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 487.904600 # average UpgradeReq miss latency 1483system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7564.627813 # average UpgradeReq miss latency 1484system.l2c.UpgradeReq_avg_miss_latency::total 3115.145673 # average UpgradeReq miss latency 1485system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1318.027211 # average SCUpgradeReq miss latency 1486system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 239.641657 # average SCUpgradeReq miss latency 1487system.l2c.SCUpgradeReq_avg_miss_latency::total 775.492958 # average SCUpgradeReq miss latency 1488system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76275.263541 # average ReadExReq miss latency 1489system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81685.564663 # average ReadExReq miss latency 1490system.l2c.ReadExReq_avg_miss_latency::total 76567.108818 # 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number of SCUpgradeReq MSHR miss cycles 1561system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13467684500 # number of ReadExReq MSHR miss cycles 1562system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958316000 # number of ReadExReq MSHR miss cycles 1563system.l2c.ReadExReq_mshr_miss_latency::total 14426000500 # number of ReadExReq MSHR miss cycles 1564system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1525917500 # number of ReadCleanReq MSHR miss cycles 1565system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 114051500 # number of ReadCleanReq MSHR miss cycles 1566system.l2c.ReadCleanReq_mshr_miss_latency::total 1639969000 # number of ReadCleanReq MSHR miss cycles 1567system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30955354500 # number of ReadSharedReq MSHR miss cycles 1568system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 40284000 # number of ReadSharedReq MSHR miss cycles 1569system.l2c.ReadSharedReq_mshr_miss_latency::total 30995638500 # number of ReadSharedReq MSHR miss cycles 1570system.l2c.demand_mshr_miss_latency::cpu0.inst 1525917500 # number of demand (read+write) MSHR miss cycles 1571system.l2c.demand_mshr_miss_latency::cpu0.data 44423039000 # number of demand (read+write) MSHR miss cycles 1572system.l2c.demand_mshr_miss_latency::cpu1.inst 114051500 # number of demand (read+write) MSHR miss cycles 1573system.l2c.demand_mshr_miss_latency::cpu1.data 998600000 # number of demand (read+write) MSHR miss cycles 1574system.l2c.demand_mshr_miss_latency::total 47061608000 # number of demand (read+write) MSHR miss cycles 1575system.l2c.overall_mshr_miss_latency::cpu0.inst 1525917500 # number of overall MSHR miss cycles 1576system.l2c.overall_mshr_miss_latency::cpu0.data 44423039000 # number of overall MSHR miss cycles 1577system.l2c.overall_mshr_miss_latency::cpu1.inst 114051500 # number of overall MSHR miss cycles 1578system.l2c.overall_mshr_miss_latency::cpu1.data 998600000 # number of overall MSHR miss cycles 1579system.l2c.overall_mshr_miss_latency::total 47061608000 # number of overall MSHR miss cycles 1580system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1400094000 # number of ReadReq MSHR uncacheable cycles 1581system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 22239000 # number of ReadReq MSHR uncacheable cycles 1582system.l2c.ReadReq_mshr_uncacheable_latency::total 1422333000 # number of ReadReq MSHR uncacheable cycles 1583system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2192043000 # number of WriteReq MSHR uncacheable cycles 1584system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 708908500 # number of WriteReq MSHR uncacheable cycles 1585system.l2c.WriteReq_mshr_uncacheable_latency::total 2900951500 # number of WriteReq MSHR uncacheable cycles 1586system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3592137000 # number of overall MSHR uncacheable cycles 1587system.l2c.overall_mshr_uncacheable_latency::cpu1.data 731147500 # number of overall MSHR uncacheable cycles 1588system.l2c.overall_mshr_uncacheable_latency::total 4323284500 # number of overall MSHR uncacheable cycles |
| 1593system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1594system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 1589system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1590system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 1595system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944337 # mshr miss rate for UpgradeReq accesses 1596system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764109 # mshr miss rate for UpgradeReq accesses 1597system.l2c.UpgradeReq_mshr_miss_rate::total 0.868304 # mshr miss rate for UpgradeReq accesses 1598system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.953514 # mshr miss rate for SCUpgradeReq accesses 1599system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973828 # mshr miss rate for SCUpgradeReq accesses 1600system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.963626 # mshr miss rate for SCUpgradeReq accesses 1601system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476737 # mshr miss rate for ReadExReq accesses 1602system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122956 # mshr miss rate for ReadExReq accesses 1603system.l2c.ReadExReq_mshr_miss_rate::total 0.412685 # mshr miss rate for ReadExReq accesses 1604system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for ReadCleanReq accesses 1605system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for ReadCleanReq accesses 1606system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013288 # mshr miss rate for ReadCleanReq accesses 1607system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.289979 # mshr miss rate for ReadSharedReq accesses 1608system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002168 # mshr miss rate for ReadSharedReq accesses 1609system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260015 # mshr miss rate for ReadSharedReq accesses 1610system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for demand accesses 1611system.l2c.demand_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for demand accesses 1612system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for demand accesses 1613system.l2c.demand_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for demand accesses 1614system.l2c.demand_mshr_miss_rate::total 0.172885 # mshr miss rate for demand accesses 1615system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for overall accesses 1616system.l2c.overall_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for overall accesses 1617system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for overall accesses 1618system.l2c.overall_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for overall accesses 1619system.l2c.overall_mshr_miss_rate::total 0.172885 # mshr miss rate for overall accesses 1620system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20637.989779 # average UpgradeReq mshr miss latency 1621system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20700.230814 # average UpgradeReq mshr miss latency 1622system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20661.096829 # average UpgradeReq mshr miss latency 1623system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20657.029478 # average SCUpgradeReq mshr miss latency 1624system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20520.156775 # average SCUpgradeReq mshr miss latency 1625system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20588.169014 # average SCUpgradeReq mshr miss latency 1626system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66275.263541 # average ReadExReq mshr miss latency 1627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71685.564663 # average ReadExReq mshr miss latency 1628system.l2c.ReadExReq_avg_mshr_miss_latency::total 66567.108818 # average ReadExReq mshr miss latency 1629system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average ReadCleanReq mshr miss latency 1630system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average ReadCleanReq mshr miss latency 1631system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 69912.287853 # average ReadCleanReq mshr miss latency 1632system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62378.890574 # average ReadSharedReq mshr miss latency 1633system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70368.644068 # average ReadSharedReq mshr miss latency 1634system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency 1635system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency 1636system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency 1637system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency 1638system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency 1639system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency 1640system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency 1641system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency 1642system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency 1643system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency 1644system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency 1645system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency 1646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency 1647system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency 1648system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency 1649system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency 1650system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency 1651system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency 1652system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency 1653system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency | 1591system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941009 # mshr miss rate for UpgradeReq accesses 1592system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764482 # mshr miss rate for UpgradeReq accesses 1593system.l2c.UpgradeReq_mshr_miss_rate::total 0.865350 # mshr miss rate for UpgradeReq accesses 1594system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959544 # mshr miss rate for SCUpgradeReq accesses 1595system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974816 # mshr miss rate for SCUpgradeReq accesses 1596system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967136 # mshr miss rate for SCUpgradeReq accesses 1597system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480915 # mshr miss rate for ReadExReq accesses 1598system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139213 # mshr miss rate for ReadExReq accesses 1599system.l2c.ReadExReq_mshr_miss_rate::total 0.415606 # mshr miss rate for ReadExReq accesses 1600system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for ReadCleanReq accesses 1601system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for ReadCleanReq accesses 1602system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses 1603system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291677 # mshr miss rate for ReadSharedReq accesses 1604system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses 1605system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260159 # mshr miss rate for ReadSharedReq accesses 1606system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for demand accesses 1607system.l2c.demand_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for demand accesses 1608system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for demand accesses 1609system.l2c.demand_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for demand accesses 1610system.l2c.demand_mshr_miss_rate::total 0.172987 # mshr miss rate for demand accesses 1611system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018286 # mshr miss rate for overall accesses 1612system.l2c.overall_mshr_miss_rate::cpu0.data 0.330343 # mshr miss rate for overall accesses 1613system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002801 # mshr miss rate for overall accesses 1614system.l2c.overall_mshr_miss_rate::cpu1.data 0.048080 # mshr miss rate for overall accesses 1615system.l2c.overall_mshr_miss_rate::total 0.172987 # mshr miss rate for overall accesses 1616system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71556.285811 # average UpgradeReq mshr miss latency 1617system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71793.694690 # average UpgradeReq mshr miss latency 1618system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71646.178010 # average UpgradeReq mshr miss latency 1619system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71034.054054 # average SCUpgradeReq mshr miss latency 1620system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71513.455328 # average SCUpgradeReq mshr miss latency 1621system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71274.271845 # average SCUpgradeReq mshr miss latency 1622system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117140.858485 # average ReadExReq mshr miss latency 1623system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121861.139369 # average ReadExReq mshr miss latency 1624system.l2c.ReadExReq_avg_mshr_miss_latency::total 117443.057297 # average ReadExReq mshr miss latency 1625system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average ReadCleanReq mshr miss latency 1626system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average ReadCleanReq mshr miss latency 1627system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121479.185185 # average ReadCleanReq mshr miss latency 1628system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113999.243205 # average ReadSharedReq mshr miss latency 1629system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 119537.091988 # average ReadSharedReq mshr miss latency 1630system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114006.107541 # average ReadSharedReq mshr miss latency 1631system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency 1632system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency 1633system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency 1634system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency 1635system.l2c.demand_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency 1636system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121383.939225 # average overall mshr miss latency 1637system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114933.737808 # average overall mshr miss latency 1638system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122768.030140 # average overall mshr miss latency 1639system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121765.638337 # average overall mshr miss latency 1640system.l2c.overall_avg_mshr_miss_latency::total 115287.456732 # average overall mshr miss latency 1641system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197585.944115 # average ReadReq mshr uncacheable latency 1642system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188466.101695 # average ReadReq mshr uncacheable latency 1643system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197436.563021 # average ReadReq mshr uncacheable latency 1644system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 203268.082344 # average WriteReq mshr uncacheable latency 1645system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 211804.152973 # average WriteReq mshr uncacheable latency 1646system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205289.894558 # average WriteReq mshr uncacheable latency 1647system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 201014.941242 # average overall mshr uncacheable latency 1648system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 211009.379509 # average overall mshr uncacheable latency 1649system.l2c.overall_avg_mshr_uncacheable_latency::total 202638.129834 # average overall mshr uncacheable latency |
| 1654system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 1650system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1655system.membus.trans_dist::ReadReq 7199 # Transaction distribution 1656system.membus.trans_dist::ReadResp 292720 # Transaction distribution 1657system.membus.trans_dist::WriteReq 14043 # Transaction distribution 1658system.membus.trans_dist::WriteResp 14043 # Transaction distribution 1659system.membus.trans_dist::Writeback 120393 # Transaction distribution 1660system.membus.trans_dist::CleanEvict 261901 # Transaction distribution 1661system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution 1662system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution 1663system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution 1664system.membus.trans_dist::ReadExReq 122456 # Transaction distribution 1665system.membus.trans_dist::ReadExResp 121630 # Transaction distribution 1666system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution | 1651system.membus.trans_dist::ReadReq 7204 # Transaction distribution 1652system.membus.trans_dist::ReadResp 292756 # Transaction distribution 1653system.membus.trans_dist::WriteReq 14131 # Transaction distribution 1654system.membus.trans_dist::WriteResp 14131 # Transaction distribution 1655system.membus.trans_dist::Writeback 120910 # Transaction distribution 1656system.membus.trans_dist::CleanEvict 262059 # Transaction distribution 1657system.membus.trans_dist::UpgradeReq 16821 # Transaction distribution 1658system.membus.trans_dist::SCUpgradeReq 11772 # Transaction distribution 1659system.membus.trans_dist::UpgradeResp 7147 # Transaction distribution 1660system.membus.trans_dist::ReadExReq 123180 # Transaction distribution 1661system.membus.trans_dist::ReadExResp 122316 # Transaction distribution 1662system.membus.trans_dist::ReadSharedReq 285552 # Transaction distribution |
| 1667system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1668system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution | 1663system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1664system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution |
| 1669system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes) 1670system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes) 1671system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes) 1672system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes) 1673system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes) 1674system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes) 1675system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes) 1676system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes) 1677system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes) | 1665system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42670 # Packet count per connected master and slave (bytes) 1666system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193160 # Packet count per connected master and slave (bytes) 1667system.membus.pkt_count_system.l2c.mem_side::total 1235830 # Packet count per connected master and slave (bytes) 1668system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) 1669system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) 1670system.membus.pkt_count::total 1360657 # Packet count per connected master and slave (bytes) 1671system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82499 # Cumulative packet size per connected master and slave (bytes) 1672system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31156480 # Cumulative packet size per connected master and slave (bytes) 1673system.membus.pkt_size_system.l2c.mem_side::total 31238979 # Cumulative packet size per connected master and slave (bytes) |
| 1678system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 1679system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) | 1674system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 1675system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) |
| 1680system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes) 1681system.membus.snoops 21449 # Total snoops (count) 1682system.membus.snoop_fanout::samples 880387 # Request fanout histogram | 1676system.membus.pkt_size::total 33897219 # Cumulative packet size per connected master and slave (bytes) 1677system.membus.snoops 22736 # Total snoops (count) 1678system.membus.snoop_fanout::samples 883364 # Request fanout histogram |
| 1683system.membus.snoop_fanout::mean 1 # Request fanout histogram 1684system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1685system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1686system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1679system.membus.snoop_fanout::mean 1 # Request fanout histogram 1680system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1681system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1682system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1687system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram | 1683system.membus.snoop_fanout::1 883364 100.00% 100.00% # Request fanout histogram |
| 1688system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1689system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1690system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1691system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1684system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1685system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1686system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1687system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1692system.membus.snoop_fanout::total 880387 # Request fanout histogram 1693system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks) | 1688system.membus.snoop_fanout::total 883364 # Request fanout histogram 1689system.membus.reqLayer0.occupancy 40609000 # Layer occupancy (ticks) |
| 1694system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1690system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1695system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks) | 1691system.membus.reqLayer1.occupancy 1325313892 # Layer occupancy (ticks) |
| 1696system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1692system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1697system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks) | 1693system.membus.respLayer1.occupancy 2193032106 # Layer occupancy (ticks) |
| 1698system.membus.respLayer1.utilization 0.1 # Layer utilization (%) | 1694system.membus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1699system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks) | 1695system.membus.respLayer2.occupancy 69837727 # Layer occupancy (ticks) |
| 1700system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1696system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1701system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution 1702system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution 1703system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution 1704system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution 1705system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution 1706system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution 1707system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution 1708system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution 1709system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution 1710system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution 1711system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution 1712system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution 1713system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution | 1697system.toL2Bus.snoop_filter.tot_requests 4790600 # Total number of requests made to the snoop filter. 1698system.toL2Bus.snoop_filter.hit_single_requests 2395468 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1699system.toL2Bus.snoop_filter.hit_multi_requests 361643 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1700system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. 1701system.toL2Bus.snoop_filter.hit_single_snoops 1180 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1702system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1703system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution 1704system.toL2Bus.trans_dist::ReadResp 2107021 # Transaction distribution 1705system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution 1706system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution 1707system.toL2Bus.trans_dist::Writeback 913350 # Transaction distribution 1708system.toL2Bus.trans_dist::CleanEvict 1503335 # Transaction distribution 1709system.toL2Bus.trans_dist::UpgradeReq 17046 # Transaction distribution 1710system.toL2Bus.trans_dist::SCUpgradeReq 11835 # Transaction distribution 1711system.toL2Bus.trans_dist::UpgradeResp 28881 # Transaction distribution 1712system.toL2Bus.trans_dist::ReadExReq 297634 # Transaction distribution 1713system.toL2Bus.trans_dist::ReadExResp 297634 # Transaction distribution 1714system.toL2Bus.trans_dist::ReadCleanReq 1019209 # Transaction distribution 1715system.toL2Bus.trans_dist::ReadSharedReq 1080623 # Transaction distribution |
| 1714system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution | 1716system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution |
| 1715system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes) 1716system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes) 1717system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes) 1718system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes) 1719system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes) 1720system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes) 1721system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes) 1722system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes) 1723system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes) 1724system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes) 1725system.toL2Bus.snoops 480853 # Total snoops (count) 1726system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram 1727system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram 1728system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram | 1717system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1918193 # Packet count per connected master and slave (bytes) 1718system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544327 # Packet count per connected master and slave (bytes) 1719system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867106 # Packet count per connected master and slave (bytes) 1720system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539630 # Packet count per connected master and slave (bytes) 1721system.toL2Bus.pkt_count::total 6869256 # Packet count per connected master and slave (bytes) 1722system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43998144 # Cumulative packet size per connected master and slave (bytes) 1723system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118001405 # Cumulative packet size per connected master and slave (bytes) 1724system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 21229504 # Cumulative packet size per connected master and slave (bytes) 1725system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604166 # Cumulative packet size per connected master and slave (bytes) 1726system.toL2Bus.pkt_size::total 201833219 # Cumulative packet size per connected master and slave (bytes) 1727system.toL2Bus.snoops 484490 # Total snoops (count) 1728system.toL2Bus.snoop_fanout::samples 5237304 # Request fanout histogram 1729system.toL2Bus.snoop_fanout::mean 0.138719 # Request fanout histogram 1730system.toL2Bus.snoop_fanout::stdev 0.345885 # Request fanout histogram |
| 1729system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1731system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1730system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1731system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1732system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1733system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram 1734system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram | 1732system.toL2Bus.snoop_fanout::0 4511205 86.14% 86.14% # Request fanout histogram 1733system.toL2Bus.snoop_fanout::1 725687 13.86% 99.99% # Request fanout histogram 1734system.toL2Bus.snoop_fanout::2 408 0.01% 100.00% # Request fanout histogram 1735system.toL2Bus.snoop_fanout::3 4 0.00% 100.00% # Request fanout histogram 1736system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram |
| 1735system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1737system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1736system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1737system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1738system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram 1739system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks) | 1738system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1739system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1740system.toL2Bus.snoop_fanout::total 5237304 # Request fanout histogram 1741system.toL2Bus.reqLayer0.occupancy 3205453497 # Layer occupancy (ticks) |
| 1740system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1742system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1741system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) | 1743system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) |
| 1742system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1744system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1743system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks) | 1745system.toL2Bus.respLayer0.occupancy 1031366757 # Layer occupancy (ticks) |
| 1744system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1746system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1745system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks) | 1747system.toL2Bus.respLayer1.occupancy 1802104925 # Layer occupancy (ticks) |
| 1746system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1748system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1747system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks) | 1749system.toL2Bus.respLayer2.occupancy 498533066 # Layer occupancy (ticks) |
| 1748system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1750system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1749system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks) | 1751system.toL2Bus.respLayer3.occupancy 293884764 # Layer occupancy (ticks) |
| 1750system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1751system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1752system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1753system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1754system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1755system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1756system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1757system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- | 1752system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1753system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1754system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1755system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1756system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1757system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1758system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1759system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- |