| stats.txt (10765:ee0e03afd9da) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.962613 # Number of seconds simulated 4sim_ticks 1962612686500 # Number of ticks simulated 5final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.962613 # Number of seconds simulated 4sim_ticks 1962612686500 # Number of ticks simulated 5final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1051716 # Simulator instruction rate (inst/s) 8host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33894179183 # Simulator tick rate (ticks/s) 10host_mem_usage 374244 # Number of bytes of host memory used 11host_seconds 57.90 # Real time elapsed on the host | 7host_inst_rate 1118839 # Simulator instruction rate (inst/s) 8host_op_rate 1118839 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36057415911 # Simulator tick rate (ticks/s) 10host_mem_usage 319640 # Number of bytes of host memory used 11host_seconds 54.43 # Real time elapsed on the host |
| 12sim_insts 60898638 # Number of instructions simulated 13sim_ops 60898638 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory --- 585 unchanged lines hidden (view full) --- 605system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses 606system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses 607system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses 608system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses 609system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses 610system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses 611system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses 612system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses | 12sim_insts 60898638 # Number of instructions simulated 13sim_ops 60898638 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory --- 585 unchanged lines hidden (view full) --- 605system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses 606system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses 607system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses 608system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses 609system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses 610system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses 611system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses 612system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses |
| 613system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable 614system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable 615system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable 616system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10834 # number of WriteReq MSHR uncacheable 617system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses 618system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17944 # number of overall MSHR uncacheable misses |
|
| 613system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles 614system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles 615system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles 616system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles 617system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles 618system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles 619system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles 620system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles --- 26 unchanged lines hidden (view full) --- 647system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency 648system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency 649system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency 650system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency 651system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency 652system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency 653system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency 654system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency | 619system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles 620system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles 621system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles 622system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles 623system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles 624system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles 625system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles 626system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles --- 26 unchanged lines hidden (view full) --- 653system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency 654system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency 655system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency 656system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency 657system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency 658system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency 659system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency 660system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency |
| 655system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 656system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 657system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 658system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 659system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 660system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 661system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899 # average ReadReq mshr uncacheable latency 662system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899 # average ReadReq mshr uncacheable latency 663system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 211730.893483 # average WriteReq mshr uncacheable latency 664system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483 # average WriteReq mshr uncacheable latency 665system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210003.817432 # average overall mshr uncacheable latency 666system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432 # average overall mshr uncacheable latency |
| 661system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 662system.cpu0.icache.tags.replacements 698758 # number of replacements 663system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use 664system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks. 665system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks. 666system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks. 667system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit. 668system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor --- 337 unchanged lines hidden (view full) --- 1006system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses 1007system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses 1008system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses 1009system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses 1010system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses 1011system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses 1012system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses 1013system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses | 667system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 668system.cpu0.icache.tags.replacements 698758 # number of replacements 669system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use 670system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks. 671system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks. 672system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks. 673system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit. 674system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor --- 337 unchanged lines hidden (view full) --- 1012system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses 1013system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses 1014system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses 1015system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses 1016system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses 1017system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses 1018system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses 1019system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses |
| 1020system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable 1021system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable 1022system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable 1023system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3218 # number of WriteReq MSHR uncacheable 1024system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses 1025system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3307 # number of overall MSHR uncacheable misses |
|
| 1014system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles 1015system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles 1016system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles 1017system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles 1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles 1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles 1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles 1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles --- 26 unchanged lines hidden (view full) --- 1048system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency 1049system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency 1050system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency 1051system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency 1052system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency 1053system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency 1054system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency 1055system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency | 1026system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles 1027system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles 1028system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles 1029system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles 1030system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles 1031system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles 1032system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles 1033system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles --- 26 unchanged lines hidden (view full) --- 1060system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency 1061system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency 1062system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency 1063system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency 1064system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency 1065system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency 1066system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency 1067system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency |
| 1056system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1058system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1059system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1060system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1061system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1068system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090 # average ReadReq mshr uncacheable latency 1069system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090 # average ReadReq mshr uncacheable latency 1070system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487 # average WriteReq mshr uncacheable latency 1071system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487 # average WriteReq mshr uncacheable latency 1072system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760 # average overall mshr uncacheable latency 1073system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760 # average overall mshr uncacheable latency |
| 1062system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1063system.cpu1.icache.tags.replacements 315648 # number of replacements 1064system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use 1065system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. 1066system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. 1067system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. 1068system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. 1069system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor --- 464 unchanged lines hidden (view full) --- 1534system.l2c.demand_mshr_misses::cpu1.inst 449 # number of demand (read+write) MSHR misses 1535system.l2c.demand_mshr_misses::cpu1.data 6823 # number of demand (read+write) MSHR misses 1536system.l2c.demand_mshr_misses::total 407602 # number of demand (read+write) MSHR misses 1537system.l2c.overall_mshr_misses::cpu0.inst 13067 # number of overall MSHR misses 1538system.l2c.overall_mshr_misses::cpu0.data 387263 # number of overall MSHR misses 1539system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses 1540system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses 1541system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses | 1074system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu1.icache.tags.replacements 315648 # number of replacements 1076system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use 1077system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. 1078system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. 1079system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. 1080system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. 1081system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor --- 464 unchanged lines hidden (view full) --- 1546system.l2c.demand_mshr_misses::cpu1.inst 449 # number of demand (read+write) MSHR misses 1547system.l2c.demand_mshr_misses::cpu1.data 6823 # number of demand (read+write) MSHR misses 1548system.l2c.demand_mshr_misses::total 407602 # number of demand (read+write) MSHR misses 1549system.l2c.overall_mshr_misses::cpu0.inst 13067 # number of overall MSHR misses 1550system.l2c.overall_mshr_misses::cpu0.data 387263 # number of overall MSHR misses 1551system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses 1552system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses 1553system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses |
| 1554system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable 1555system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable 1556system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable 1557system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable 1558system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable 1559system.l2c.WriteReq_mshr_uncacheable::total 14052 # number of WriteReq MSHR uncacheable 1560system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses 1561system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses 1562system.l2c.overall_mshr_uncacheable_misses::total 21251 # number of overall MSHR uncacheable misses |
|
| 1542system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles 1543system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles 1544system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles 1545system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles 1546system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles 1547system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles 1548system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles 1549system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles --- 65 unchanged lines hidden (view full) --- 1615system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency 1616system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency 1617system.l2c.demand_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency 1618system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency 1619system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency 1620system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency 1621system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency 1622system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency | 1563system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles 1564system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles 1565system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles 1566system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles 1567system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles 1568system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles 1569system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles 1570system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles --- 65 unchanged lines hidden (view full) --- 1636system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency 1637system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency 1638system.l2c.demand_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency 1639system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency 1640system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency 1641system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency 1642system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency 1643system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency |
| 1623system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1624system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1625system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1626system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1627system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1628system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1629system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1630system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1631system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1644system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193372.151899 # average ReadReq mshr uncacheable latency 1645system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197977.528090 # average ReadReq mshr uncacheable latency 1646system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193429.087373 # average ReadReq mshr uncacheable latency 1647system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 198730.893483 # average WriteReq mshr uncacheable latency 1648system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209613.424487 # average WriteReq mshr uncacheable latency 1649system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201223.064332 # average WriteReq mshr uncacheable latency 1650system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 196607.584708 # average overall mshr uncacheable latency 1651system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 209300.272150 # average overall mshr uncacheable latency 1652system.l2c.overall_avg_mshr_uncacheable_latency::total 198582.772575 # average overall mshr uncacheable latency |
| 1632system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1633system.membus.trans_dist::ReadReq 292759 # Transaction distribution 1634system.membus.trans_dist::ReadResp 292759 # Transaction distribution 1635system.membus.trans_dist::WriteReq 14052 # Transaction distribution 1636system.membus.trans_dist::WriteResp 14052 # Transaction distribution 1637system.membus.trans_dist::Writeback 120350 # Transaction distribution 1638system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1639system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution --- 10 unchanged lines hidden (view full) --- 1650system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) 1651system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) 1652system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) 1653system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) 1654system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) 1655system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) 1656system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) 1657system.membus.snoops 21558 # Total snoops (count) | 1653system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1654system.membus.trans_dist::ReadReq 292759 # Transaction distribution 1655system.membus.trans_dist::ReadResp 292759 # Transaction distribution 1656system.membus.trans_dist::WriteReq 14052 # Transaction distribution 1657system.membus.trans_dist::WriteResp 14052 # Transaction distribution 1658system.membus.trans_dist::Writeback 120350 # Transaction distribution 1659system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1660system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution --- 10 unchanged lines hidden (view full) --- 1671system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) 1672system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) 1673system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) 1674system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) 1675system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) 1676system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) 1677system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) 1678system.membus.snoops 21558 # Total snoops (count) |
| 1658system.membus.snoop_fanout::samples 597341 # Request fanout histogram | 1679system.membus.snoop_fanout::samples 618592 # Request fanout histogram |
| 1659system.membus.snoop_fanout::mean 1 # Request fanout histogram 1660system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1661system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1662system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1680system.membus.snoop_fanout::mean 1 # Request fanout histogram 1681system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1682system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1683system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1663system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram | 1684system.membus.snoop_fanout::1 618592 100.00% 100.00% # Request fanout histogram |
| 1664system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1665system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1666system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1667system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1685system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1686system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1687system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1688system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1668system.membus.snoop_fanout::total 597341 # Request fanout histogram | 1689system.membus.snoop_fanout::total 618592 # Request fanout histogram |
| 1669system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks) 1670system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1671system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) 1672system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1673system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks) 1674system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1675system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) 1676system.membus.respLayer2.utilization 0.0 # Layer utilization (%) --- 14 unchanged lines hidden (view full) --- 1691system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) 1692system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) 1693system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) 1694system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) 1695system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) 1696system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) 1697system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) 1698system.toL2Bus.snoops 98552 # Total snoops (count) | 1690system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks) 1691system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1692system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) 1693system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1694system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks) 1695system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1696system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) 1697system.membus.respLayer2.utilization 0.0 # Layer utilization (%) --- 14 unchanged lines hidden (view full) --- 1712system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) 1713system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) 1714system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) 1715system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) 1716system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) 1717system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) 1718system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) 1719system.toL2Bus.snoops 98552 # Total snoops (count) |
| 1699system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram 1700system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram 1701system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram | 1720system.toL2Bus.snoop_fanout::samples 3276706 # Request fanout histogram 1721system.toL2Bus.snoop_fanout::mean 3.012746 # Request fanout histogram 1722system.toL2Bus.snoop_fanout::stdev 0.112175 # Request fanout histogram |
| 1702system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1703system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1704system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1705system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1723system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1724system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1725system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1726system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1706system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram 1707system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram | 1727system.toL2Bus.snoop_fanout::3 3234942 98.73% 98.73% # Request fanout histogram 1728system.toL2Bus.snoop_fanout::4 41764 1.27% 100.00% # Request fanout histogram |
| 1708system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1709system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1710system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1729system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1730system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1731system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1711system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram | 1732system.toL2Bus.snoop_fanout::total 3276706 # Request fanout histogram |
| 1712system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) 1713system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1714system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) 1715system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1716system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) 1717system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1718system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks) 1719system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) --- 37 unchanged lines hidden --- | 1733system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) 1734system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1735system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) 1736system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1737system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) 1738system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1739system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks) 1740system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) --- 37 unchanged lines hidden --- |