Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.962613 # Number of seconds simulated
4sim_ticks 1962612686500 # Number of ticks simulated
5final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1121045 # Simulator instruction rate (inst/s)
8host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 36128483856 # Simulator tick rate (ticks/s)
10host_mem_usage 373592 # Number of bytes of host memory used
11host_seconds 54.32 # Real time elapsed on the host

7host_inst_rate 1051716 # Simulator instruction rate (inst/s)
8host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 33894179183 # Simulator tick rate (ticks/s)
10host_mem_usage 374244 # Number of bytes of host memory used
11host_seconds 57.90 # Real time elapsed on the host

12sim_insts 60898638 # Number of instructions simulated
13sim_ops 60898638 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory

--- 246 unchanged lines hidden (view full) ---

266system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads

274system.physmem.totQLat 2137453500 # Total ticks spent queuing
275system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM

274system.physmem.totQLat 2137457500 # Total ticks spent queuing
275system.physmem.totMemAccLat 9763982500 # Total ticks spent from burst creation until serviced by the DRAM

276system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers

277system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst

277system.physmem.avgQLat 5254.99 # Average queueing delay per DRAM burst

278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

279system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst

279system.physmem.avgMemAccLat 24004.99 # Average memory access latency per DRAM burst

280system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s
281system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s
282system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s
283system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s
284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
285system.physmem.busUtil 0.14 # Data bus utilization in percentage
286system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
287system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes

--- 5 unchanged lines hidden (view full) ---

293system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes
294system.physmem.avgGap 3450647.54 # Average gap between requests
295system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined
296system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ)
297system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ)
298system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ)
299system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ)
300system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ)

301system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ)
302system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ)
303system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ)

301system.physmem_0.actBackEnergy 66287824245 # Energy for active background per rank (pJ)
302system.physmem_0.preBackEnergy 1119418910250 # Energy for precharge background per rank (pJ)
303system.physmem_0.totalEnergy 1316300550720 # Total energy per rank (pJ)

304system.physmem_0.averagePower 670.688732 # Core power per rank (mW)

305system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states

305system.physmem_0.memoryStateTime::IDLE 1862013796212 # Time in different power states

306system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states
307system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

308system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states

308system.physmem_0.memoryStateTime::ACT 35060565038 # Time in different power states

309system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
310system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ)
311system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ)
312system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ)
313system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ)
314system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ)

315system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ)
316system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ)
317system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ)

315system.physmem_1.actBackEnergy 66523575105 # Energy for active background per rank (pJ)
316system.physmem_1.preBackEnergy 1119212111250 # Energy for precharge background per rank (pJ)
317system.physmem_1.totalEnergy 1316364135975 # Total energy per rank (pJ)

318system.physmem_1.averagePower 670.721130 # Core power per rank (mW)

319system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states

319system.physmem_1.memoryStateTime::IDLE 1861673236216 # Time in different power states

320system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states
321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states

322system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states

322system.physmem_1.memoryStateTime::ACT 35401125034 # Time in different power states

323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
324system.cpu_clk_domain.clock 500 # Clock period in ticks
325system.cpu0.dtb.fetch_hits 0 # ITB hits
326system.cpu0.dtb.fetch_misses 0 # ITB misses
327system.cpu0.dtb.fetch_acv 0 # ITB acv
328system.cpu0.dtb.fetch_accesses 0 # ITB accesses
329system.cpu0.dtb.read_hits 7492205 # DTB read hits
330system.cpu0.dtb.read_misses 7443 # DTB read misses

--- 206 unchanged lines hidden (view full) ---

537system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses
538system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses
539system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses
540system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses
541system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses
542system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses
543system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles
544system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles

545system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles
546system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles

545system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906402435 # number of WriteReq miss cycles
546system.cpu0.dcache.WriteReq_miss_latency::total 10906402435 # number of WriteReq miss cycles

547system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles
548system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles
549system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles
550system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles

551system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles
552system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles
553system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles
554system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles

551system.cpu0.dcache.demand_miss_latency::cpu0.data 39966793434 # number of demand (read+write) miss cycles
552system.cpu0.dcache.demand_miss_latency::total 39966793434 # number of demand (read+write) miss cycles
553system.cpu0.dcache.overall_miss_latency::cpu0.data 39966793434 # number of overall miss cycles
554system.cpu0.dcache.overall_miss_latency::total 39966793434 # number of overall miss cycles

555system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses)
556system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses)
557system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses)
558system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses)
559system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses)
560system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses)
561system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses)
562system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses)

--- 10 unchanged lines hidden (view full) ---

573system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses
574system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses
575system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses
576system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses
577system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses
578system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses
579system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency
580system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency

581system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency
582system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency

581system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232 # average WriteReq miss latency
582system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232 # average WriteReq miss latency

583system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency
584system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency
585system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency
586system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency

587system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency
588system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency
589system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency
590system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency

587system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
588system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101 # average overall miss latency
589system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
590system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101 # average overall miss latency

591system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
592system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
593system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
594system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
595system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
596system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
597system.cpu0.dcache.fast_writes 0 # number of fast writes performed
598system.cpu0.dcache.cache_copies 0 # number of cache copies performed

--- 8 unchanged lines hidden (view full) ---

607system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses
608system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses
609system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses
610system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses
611system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses
612system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses
613system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles
614system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles

615system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476948315 # number of WriteReq MSHR miss cycles
616system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476948315 # number of WriteReq MSHR miss cycles

615system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
616system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles

617system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles
618system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles
619system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles
620system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles

621system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles
622system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles
623system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles
624system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles

621system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003535066 # number of demand (read+write) MSHR miss cycles
622system.cpu0.dcache.demand_mshr_miss_latency::total 38003535066 # number of demand (read+write) MSHR miss cycles
623system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003535066 # number of overall MSHR miss cycles
624system.cpu0.dcache.overall_mshr_miss_latency::total 38003535066 # number of overall MSHR miss cycles

625system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles
626system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles

627system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles
628system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles
629system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # number of overall MSHR uncacheable cycles
630system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768311500 # number of overall MSHR uncacheable cycles

627system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles
628system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles
629system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles
630system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles

631system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses
632system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses
633system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses
634system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses
635system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses
636system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses
637system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses
638system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses
639system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses
640system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses
641system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses
642system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses
643system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency
644system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency

645system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.195596 # average WriteReq mshr miss latency
646system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.195596 # average WriteReq mshr miss latency

645system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497 # average WriteReq mshr miss latency
646system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497 # average WriteReq mshr miss latency

647system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency
648system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency
649system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency
650system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency

651system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency
652system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency
653system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency
654system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency

651system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
652system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
653system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
654system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency

655system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
656system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
657system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
658system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
659system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
660system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
661system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
662system.cpu0.icache.tags.replacements 698758 # number of replacements

--- 125 unchanged lines hidden (view full) ---

788system.cpu1.num_fp_insts 173111 # number of float instructions
789system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read
790system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written
791system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read
792system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written
793system.cpu1.num_mem_refs 4200357 # number of memory refs
794system.cpu1.num_load_insts 2433886 # Number of load instructions
795system.cpu1.num_store_insts 1766471 # Number of store instructions

796system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles
797system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles

796system.cpu1.num_idle_cycles 3876126901.998025 # Number of idle cycles
797system.cpu1.num_busy_cycles 49098471.001975 # Number of busy cycles

798system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles
799system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles
800system.cpu1.Branches 1871330 # Number of branches fetched
801system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction
802system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction
803system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction
804system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction
805system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction

--- 134 unchanged lines hidden (view full) ---

940system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses
941system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses
942system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses
943system.cpu1.dcache.overall_misses::total 180698 # number of overall misses
944system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles
945system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles
946system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles
947system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles

948system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81194500 # number of LoadLockedReq miss cycles
949system.cpu1.dcache.LoadLockedReq_miss_latency::total 81194500 # number of LoadLockedReq miss cycles

948system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81193500 # number of LoadLockedReq miss cycles
949system.cpu1.dcache.LoadLockedReq_miss_latency::total 81193500 # number of LoadLockedReq miss cycles

950system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles
951system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles
952system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles
953system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles
954system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles
955system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles
956system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses)
957system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses)

--- 18 unchanged lines hidden (view full) ---

976system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses
977system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses
978system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses
979system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses
980system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency
981system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency
982system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency
983system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency

984system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.649316 # average LoadLockedReq miss latency
985system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.649316 # average LoadLockedReq miss latency

984system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.537133 # average LoadLockedReq miss latency
985system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.537133 # average LoadLockedReq miss latency

986system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency
987system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency
988system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency
989system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency
990system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency
991system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency
992system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
993system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

--- 16 unchanged lines hidden (view full) ---

1010system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses
1011system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses
1012system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses
1013system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses
1014system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles
1015system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles
1016system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles
1017system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles

1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67823500 # number of LoadLockedReq MSHR miss cycles
1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67823500 # number of LoadLockedReq MSHR miss cycles

1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles
1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles

1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles
1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles
1022system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles
1023system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles
1024system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles
1025system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles

1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18864000 # number of ReadReq MSHR uncacheable cycles
1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18864000 # number of ReadReq MSHR uncacheable cycles
1028system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716373000 # number of WriteReq MSHR uncacheable cycles
1029system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716373000 # number of WriteReq MSHR uncacheable cycles
1030system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735237000 # number of overall MSHR uncacheable cycles
1031system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735237000 # number of overall MSHR uncacheable cycles

1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18866000 # number of ReadReq MSHR uncacheable cycles
1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18866000 # number of ReadReq MSHR uncacheable cycles
1028system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716370000 # number of WriteReq MSHR uncacheable cycles
1029system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716370000 # number of WriteReq MSHR uncacheable cycles
1030system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735236000 # number of overall MSHR uncacheable cycles
1031system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735236000 # number of overall MSHR uncacheable cycles

1032system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses
1033system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses
1034system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses
1035system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses
1036system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses
1037system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses
1038system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses
1039system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses
1040system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses
1041system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses
1042system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses
1043system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses
1044system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency
1045system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency
1046system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency
1047system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency

1048system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.649316 # average LoadLockedReq mshr miss latency
1049system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency

1048system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency
1049system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency

1050system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency
1051system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency
1052system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
1053system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
1054system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
1055system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
1056system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency

--- 260 unchanged lines hidden (view full) ---

1318system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency
1319system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency
1320system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency
1321system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency
1322system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency
1323system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency
1324system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1325system.l2c.tags.replacements 341367 # number of replacements

1326system.l2c.tags.tagsinuse 65207.739778 # Cycle average of tags in use

1326system.l2c.tags.tagsinuse 65207.739779 # Cycle average of tags in use

1327system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks.
1328system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks.
1329system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks.
1330system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit.
1331system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor
1332system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor
1333system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor
1334system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor

--- 69 unchanged lines hidden (view full) ---

1404system.l2c.ReadReq_miss_latency::cpu1.data 18492250 # number of ReadReq miss cycles
1405system.l2c.ReadReq_miss_latency::total 20809461500 # number of ReadReq miss cycles
1406system.l2c.UpgradeReq_miss_latency::cpu0.data 1635455 # number of UpgradeReq miss cycles
1407system.l2c.UpgradeReq_miss_latency::cpu1.data 13268077 # number of UpgradeReq miss cycles
1408system.l2c.UpgradeReq_miss_latency::total 14903532 # number of UpgradeReq miss cycles
1409system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1334957 # number of SCUpgradeReq miss cycles
1410system.l2c.SCUpgradeReq_miss_latency::cpu1.data 185994 # number of SCUpgradeReq miss cycles
1411system.l2c.SCUpgradeReq_miss_latency::total 1520951 # number of SCUpgradeReq miss cycles

1412system.l2c.ReadExReq_miss_latency::cpu0.data 8793297261 # number of ReadExReq miss cycles

1412system.l2c.ReadExReq_miss_latency::cpu0.data 8793301011 # number of ReadExReq miss cycles

1413system.l2c.ReadExReq_miss_latency::cpu1.data 540094736 # number of ReadExReq miss cycles

1414system.l2c.ReadExReq_miss_latency::total 9333391997 # number of ReadExReq miss cycles

1414system.l2c.ReadExReq_miss_latency::total 9333395747 # number of ReadExReq miss cycles

1415system.l2c.demand_miss_latency::cpu0.inst 1052716500 # number of demand (read+write) miss cycles

1416system.l2c.demand_miss_latency::cpu0.data 28494183761 # number of demand (read+write) miss cycles

1416system.l2c.demand_miss_latency::cpu0.data 28494187511 # number of demand (read+write) miss cycles

1417system.l2c.demand_miss_latency::cpu1.inst 37366250 # number of demand (read+write) miss cycles
1418system.l2c.demand_miss_latency::cpu1.data 558586986 # number of demand (read+write) miss cycles

1419system.l2c.demand_miss_latency::total 30142853497 # number of demand (read+write) miss cycles

1419system.l2c.demand_miss_latency::total 30142857247 # number of demand (read+write) miss cycles

1420system.l2c.overall_miss_latency::cpu0.inst 1052716500 # number of overall miss cycles

1421system.l2c.overall_miss_latency::cpu0.data 28494183761 # number of overall miss cycles

1421system.l2c.overall_miss_latency::cpu0.data 28494187511 # number of overall miss cycles

1422system.l2c.overall_miss_latency::cpu1.inst 37366250 # number of overall miss cycles
1423system.l2c.overall_miss_latency::cpu1.data 558586986 # number of overall miss cycles

1424system.l2c.overall_miss_latency::total 30142853497 # number of overall miss cycles

1424system.l2c.overall_miss_latency::total 30142857247 # number of overall miss cycles

1425system.l2c.ReadReq_accesses::cpu0.inst 699367 # number of ReadReq accesses(hits+misses)
1426system.l2c.ReadReq_accesses::cpu0.data 936074 # number of ReadReq accesses(hits+misses)
1427system.l2c.ReadReq_accesses::cpu1.inst 316201 # number of ReadReq accesses(hits+misses)
1428system.l2c.ReadReq_accesses::cpu1.data 108940 # number of ReadReq accesses(hits+misses)
1429system.l2c.ReadReq_accesses::total 2060582 # number of ReadReq accesses(hits+misses)
1430system.l2c.Writeback_accesses::writebacks 793248 # number of Writeback accesses(hits+misses)
1431system.l2c.Writeback_accesses::total 793248 # number of Writeback accesses(hits+misses)
1432system.l2c.UpgradeReq_accesses::cpu0.data 3132 # number of UpgradeReq accesses(hits+misses)

--- 45 unchanged lines hidden (view full) ---

1478system.l2c.ReadReq_avg_miss_latency::cpu1.data 79026.709402 # average ReadReq miss latency
1479system.l2c.ReadReq_avg_miss_latency::total 72914.086343 # average ReadReq miss latency
1480system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 554.579518 # average UpgradeReq miss latency
1481system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7642.901498 # average UpgradeReq miss latency
1482system.l2c.UpgradeReq_avg_miss_latency::total 3181.116756 # average UpgradeReq miss latency
1483system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1496.588565 # average SCUpgradeReq miss latency
1484system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 207.351171 # average SCUpgradeReq miss latency
1485system.l2c.SCUpgradeReq_avg_miss_latency::total 850.168250 # average SCUpgradeReq miss latency

1486system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.823034 # average ReadExReq miss latency

1486system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.855466 # average ReadExReq miss latency

1487system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81969.151009 # average ReadExReq miss latency

1488system.l2c.ReadExReq_avg_miss_latency::total 76368.004165 # average ReadExReq miss latency

1488system.l2c.ReadExReq_avg_miss_latency::total 76368.034848 # average ReadExReq miss latency

1489system.l2c.demand_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency

1490system.l2c.demand_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency

1490system.l2c.demand_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency

1491system.l2c.demand_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency
1492system.l2c.demand_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency

1493system.l2c.demand_avg_miss_latency::total 73949.686337 # average overall miss latency

1493system.l2c.demand_avg_miss_latency::total 73949.695537 # average overall miss latency

1494system.l2c.overall_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency

1495system.l2c.overall_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency

1495system.l2c.overall_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency

1496system.l2c.overall_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency
1497system.l2c.overall_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency

1498system.l2c.overall_avg_miss_latency::total 73949.686337 # average overall miss latency

1498system.l2c.overall_avg_miss_latency::total 73949.695537 # average overall miss latency

1499system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1500system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1501system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1502system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1503system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1504system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1505system.l2c.fast_writes 0 # number of fast writes performed
1506system.l2c.cache_copies 0 # number of cache copies performed

--- 38 unchanged lines hidden (view full) ---

1545system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles
1546system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles
1547system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles
1548system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles
1549system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles
1550system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15769892 # number of SCUpgradeReq MSHR miss cycles
1551system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15706897 # number of SCUpgradeReq MSHR miss cycles
1552system.l2c.SCUpgradeReq_mshr_miss_latency::total 31476789 # number of SCUpgradeReq MSHR miss cycles

1553system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347142739 # number of ReadExReq MSHR miss cycles

1553system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347146989 # number of ReadExReq MSHR miss cycles

1554system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457723764 # number of ReadExReq MSHR miss cycles

1555system.l2c.ReadExReq_mshr_miss_latency::total 7804866503 # number of ReadExReq MSHR miss cycles

1555system.l2c.ReadExReq_mshr_miss_latency::total 7804870753 # number of ReadExReq MSHR miss cycles

1556system.l2c.demand_mshr_miss_latency::cpu0.inst 888765750 # number of demand (read+write) MSHR miss cycles

1557system.l2c.demand_mshr_miss_latency::cpu0.data 23652210239 # number of demand (read+write) MSHR miss cycles

1557system.l2c.demand_mshr_miss_latency::cpu0.data 23652214489 # number of demand (read+write) MSHR miss cycles

1558system.l2c.demand_mshr_miss_latency::cpu1.inst 31138500 # number of demand (read+write) MSHR miss cycles
1559system.l2c.demand_mshr_miss_latency::cpu1.data 473285514 # number of demand (read+write) MSHR miss cycles

1560system.l2c.demand_mshr_miss_latency::total 25045400003 # number of demand (read+write) MSHR miss cycles

1560system.l2c.demand_mshr_miss_latency::total 25045404253 # number of demand (read+write) MSHR miss cycles

1561system.l2c.overall_mshr_miss_latency::cpu0.inst 888765750 # number of overall MSHR miss cycles

1562system.l2c.overall_mshr_miss_latency::cpu0.data 23652210239 # number of overall MSHR miss cycles

1562system.l2c.overall_mshr_miss_latency::cpu0.data 23652214489 # number of overall MSHR miss cycles

1563system.l2c.overall_mshr_miss_latency::cpu1.inst 31138500 # number of overall MSHR miss cycles
1564system.l2c.overall_mshr_miss_latency::cpu1.data 473285514 # number of overall MSHR miss cycles

1565system.l2c.overall_mshr_miss_latency::total 25045400003 # number of overall MSHR miss cycles

1565system.l2c.overall_mshr_miss_latency::total 25045404253 # number of overall MSHR miss cycles

1566system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1374876000 # number of ReadReq MSHR uncacheable cycles

1567system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17618000 # number of ReadReq MSHR uncacheable cycles
1568system.l2c.ReadReq_mshr_uncacheable_latency::total 1392494000 # number of ReadReq MSHR uncacheable cycles
1569system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153053500 # number of WriteReq MSHR uncacheable cycles
1570system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674538500 # number of WriteReq MSHR uncacheable cycles
1571system.l2c.WriteReq_mshr_uncacheable_latency::total 2827592000 # number of WriteReq MSHR uncacheable cycles
1572system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527929500 # number of overall MSHR uncacheable cycles
1573system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156500 # number of overall MSHR uncacheable cycles
1574system.l2c.overall_mshr_uncacheable_latency::total 4220086000 # number of overall MSHR uncacheable cycles

1567system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17620000 # number of ReadReq MSHR uncacheable cycles
1568system.l2c.ReadReq_mshr_uncacheable_latency::total 1392496000 # number of ReadReq MSHR uncacheable cycles
1569system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153050500 # number of WriteReq MSHR uncacheable cycles
1570system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674536000 # number of WriteReq MSHR uncacheable cycles
1571system.l2c.WriteReq_mshr_uncacheable_latency::total 2827586500 # number of WriteReq MSHR uncacheable cycles
1572system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527926500 # number of overall MSHR uncacheable cycles
1573system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156000 # number of overall MSHR uncacheable cycles
1574system.l2c.overall_mshr_uncacheable_latency::total 4220082500 # number of overall MSHR uncacheable cycles

1575system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for ReadReq accesses
1576system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290186 # mshr miss rate for ReadReq accesses
1577system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for ReadReq accesses
1578system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002148 # mshr miss rate for ReadReq accesses
1579system.l2c.ReadReq_mshr_miss_rate::total 0.138498 # mshr miss rate for ReadReq accesses
1580system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941571 # mshr miss rate for UpgradeReq accesses
1581system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses
1582system.l2c.UpgradeReq_mshr_miss_rate::total 0.868880 # mshr miss rate for UpgradeReq accesses

--- 19 unchanged lines hidden (view full) ---

1602system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128 # average ReadReq mshr miss latency
1603system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811 # average ReadReq mshr miss latency
1604system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875 # average UpgradeReq mshr miss latency
1605system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency
1606system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency
1607system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency
1608system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency
1609system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency

1610system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency

1610system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777 # average ReadExReq mshr miss latency

1611system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency

1612system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency

1612system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554 # average ReadExReq mshr miss latency

1613system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency

1614system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency

1614system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency

1615system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
1616system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency

1617system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency

1617system.l2c.demand_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency

1618system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency

1619system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency

1619system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency

1620system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
1621system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency

1622system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency

1622system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency

1623system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1624system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1625system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1626system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1627system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1628system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1629system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1630system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency

--- 30 unchanged lines hidden (view full) ---

1661system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1662system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1663system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram
1664system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1665system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1666system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1667system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1668system.membus.snoop_fanout::total 597341 # Request fanout histogram

1669system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks)

1669system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks)

1670system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1671system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks)
1672system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)

1673system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks)

1673system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks)

1674system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1675system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks)
1676system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1677system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution
1678system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution
1679system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution
1680system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution
1681system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution

--- 28 unchanged lines hidden (view full) ---

1710system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1711system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram
1712system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks)
1713system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1714system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks)
1715system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1716system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks)
1717system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)

1718system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks)

1718system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks)