| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.962843 # Number of seconds simulated 4sim_ticks 1962842856000 # Number of ticks simulated 5final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.962613 # Number of seconds simulated 4sim_ticks 1962612686500 # Number of ticks simulated 5final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1228880 # Simulator instruction rate (inst/s) 8host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39594262798 # Simulator tick rate (ticks/s) 10host_mem_usage 373652 # Number of bytes of host memory used 11host_seconds 49.57 # Real time elapsed on the host 12sim_insts 60920382 # Number of instructions simulated 13sim_ops 60920382 # Number of ops (including micro ops) simulated | 7host_inst_rate 1121045 # Simulator instruction rate (inst/s) 8host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36128483856 # Simulator tick rate (ticks/s) 10host_mem_usage 373592 # Number of bytes of host memory used 11host_seconds 54.32 # Real time elapsed on the host 12sim_insts 60898638 # Number of instructions simulated 13sim_ops 60898638 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory | 21system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) | 39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) | 40system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) | 51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) |
| 52system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 408371 # Number of read requests accepted 54system.physmem.writeReqs 162787 # Number of write requests accepted 55system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue 59system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25705 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25985 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25737 # Per bank write bursts 68system.physmem.perBankRdBursts::3 25534 # Per bank write bursts 69system.physmem.perBankRdBursts::4 24847 # Per bank write bursts 70system.physmem.perBankRdBursts::5 24754 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25534 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25489 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25150 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25518 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25462 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25296 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25577 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25454 # Per bank write bursts 79system.physmem.perBankRdBursts::14 26241 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25977 # Per bank write bursts 81system.physmem.perBankWrBursts::0 10598 # Per bank write bursts 82system.physmem.perBankWrBursts::1 10761 # Per bank write bursts 83system.physmem.perBankWrBursts::2 9727 # Per bank write bursts 84system.physmem.perBankWrBursts::3 9433 # Per bank write bursts 85system.physmem.perBankWrBursts::4 8910 # Per bank write bursts 86system.physmem.perBankWrBursts::5 9140 # Per bank write bursts 87system.physmem.perBankWrBursts::6 9908 # Per bank write bursts 88system.physmem.perBankWrBursts::7 9771 # Per bank write bursts 89system.physmem.perBankWrBursts::8 9710 # Per bank write bursts 90system.physmem.perBankWrBursts::9 9867 # Per bank write bursts 91system.physmem.perBankWrBursts::10 9923 # Per bank write bursts 92system.physmem.perBankWrBursts::11 10306 # Per bank write bursts 93system.physmem.perBankWrBursts::12 10733 # Per bank write bursts 94system.physmem.perBankWrBursts::13 10678 # Per bank write bursts 95system.physmem.perBankWrBursts::14 10553 # Per bank write bursts 96system.physmem.perBankWrBursts::15 10567 # Per bank write bursts | 52system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 406851 # Number of read requests accepted 54system.physmem.writeReqs 161902 # Number of write requests accepted 55system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue 59system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25141 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25398 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25524 # Per bank write bursts 68system.physmem.perBankRdBursts::3 24918 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25169 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25258 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25808 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25541 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25675 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25330 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25284 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25615 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25647 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25653 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25754 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25033 # Per bank write bursts 81system.physmem.perBankWrBursts::0 8965 # Per bank write bursts 82system.physmem.perBankWrBursts::1 8625 # Per bank write bursts 83system.physmem.perBankWrBursts::2 8456 # Per bank write bursts 84system.physmem.perBankWrBursts::3 7799 # Per bank write bursts 85system.physmem.perBankWrBursts::4 8065 # Per bank write bursts 86system.physmem.perBankWrBursts::5 8041 # Per bank write bursts 87system.physmem.perBankWrBursts::6 8610 # Per bank write bursts 88system.physmem.perBankWrBursts::7 8172 # Per bank write bursts 89system.physmem.perBankWrBursts::8 8465 # Per bank write bursts 90system.physmem.perBankWrBursts::9 8053 # Per bank write bursts 91system.physmem.perBankWrBursts::10 8222 # Per bank write bursts 92system.physmem.perBankWrBursts::11 8481 # Per bank write bursts 93system.physmem.perBankWrBursts::12 8850 # Per bank write bursts 94system.physmem.perBankWrBursts::13 9510 # Per bank write bursts 95system.physmem.perBankWrBursts::14 9309 # Per bank write bursts 96system.physmem.perBankWrBursts::15 8651 # Per bank write bursts |
| 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 98system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 99system.physmem.totGap 1962837817500 # Total gap between requests | 98system.physmem.numWrRetry 56 # Number of times write queue was full causing retry 99system.physmem.totGap 1962566141500 # Total gap between requests |
| 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) | 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 106system.physmem.readPktSize::6 408371 # Read request sizes (log2) | 106system.physmem.readPktSize::6 406851 # Read request sizes (log2) |
| 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) | 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 113system.physmem.writePktSize::6 162787 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see | 113system.physmem.writePktSize::6 161902 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see |
| 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads 269system.physmem.totQLat 2189518000 # Total ticks spent queuing 270system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers 272system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst | 161system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads 274system.physmem.totQLat 2137453500 # Total ticks spent queuing 275system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM 276system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers 277system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst |
| 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 274system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s 277system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s 278system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s | 279system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst 280system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s 281system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s 282system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s 283system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s |
| 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 280system.physmem.busUtil 0.14 # Data bus utilization in percentage 281system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads | 284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 285system.physmem.busUtil 0.14 # Data bus utilization in percentage 286system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads |
| 282system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes | 287system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 283system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 288system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 284system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing 285system.physmem.readRowHits 365775 # Number of row buffer hits during reads 286system.physmem.writeRowHits 133752 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes 289system.physmem.avgGap 3436593.41 # Average gap between requests 290system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined 291system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) 292system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) 293system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) 294system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) 295system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) 296system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) 297system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) 298system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) 299system.physmem_0.averagePower 670.687203 # Core power per rank (mW) 300system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states 301system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states | 289system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing 290system.physmem.readRowHits 364433 # Number of row buffer hits during reads 291system.physmem.writeRowHits 110956 # Number of row buffer hits during writes 292system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads 293system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes 294system.physmem.avgGap 3450647.54 # Average gap between requests 295system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined 296system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ) 297system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ) 298system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ) 299system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ) 300system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) 301system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ) 302system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ) 303system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ) 304system.physmem_0.averagePower 670.688732 # Core power per rank (mW) 305system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states 306system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states |
| 302system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 307system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 303system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states | 308system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states |
| 304system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 309system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 305system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) 306system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) 307system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) 308system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) 309system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) 310system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) 311system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) 312system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) 313system.physmem_1.averagePower 670.737211 # Core power per rank (mW) 314system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states 315system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states | 310system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ) 311system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ) 312system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ) 313system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ) 314system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) 315system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ) 316system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ) 317system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ) 318system.physmem_1.averagePower 670.721130 # Core power per rank (mW) 319system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states 320system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states |
| 316system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 317system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states | 322system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states |
| 318system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 319system.cpu_clk_domain.clock 500 # Clock period in ticks 320system.cpu0.dtb.fetch_hits 0 # ITB hits 321system.cpu0.dtb.fetch_misses 0 # ITB misses 322system.cpu0.dtb.fetch_acv 0 # ITB acv 323system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 324system.cpu_clk_domain.clock 500 # Clock period in ticks 325system.cpu0.dtb.fetch_hits 0 # ITB hits 326system.cpu0.dtb.fetch_misses 0 # ITB misses 327system.cpu0.dtb.fetch_acv 0 # ITB acv 328system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 324system.cpu0.dtb.read_hits 7535038 # DTB read hits 325system.cpu0.dtb.read_misses 7765 # DTB read misses | 329system.cpu0.dtb.read_hits 7492205 # DTB read hits 330system.cpu0.dtb.read_misses 7443 # DTB read misses |
| 326system.cpu0.dtb.read_acv 210 # DTB read access violations | 331system.cpu0.dtb.read_acv 210 # DTB read access violations |
| 327system.cpu0.dtb.read_accesses 524069 # DTB read accesses 328system.cpu0.dtb.write_hits 5127057 # DTB write hits 329system.cpu0.dtb.write_misses 910 # DTB write misses 330system.cpu0.dtb.write_acv 133 # DTB write access violations 331system.cpu0.dtb.write_accesses 202595 # DTB write accesses 332system.cpu0.dtb.data_hits 12662095 # DTB hits 333system.cpu0.dtb.data_misses 8675 # DTB misses 334system.cpu0.dtb.data_acv 343 # DTB access violations 335system.cpu0.dtb.data_accesses 726664 # DTB accesses 336system.cpu0.itb.fetch_hits 3654300 # ITB hits 337system.cpu0.itb.fetch_misses 3984 # ITB misses | 332system.cpu0.dtb.read_accesses 490673 # DTB read accesses 333system.cpu0.dtb.write_hits 5067323 # DTB write hits 334system.cpu0.dtb.write_misses 813 # DTB write misses 335system.cpu0.dtb.write_acv 134 # DTB write access violations 336system.cpu0.dtb.write_accesses 187452 # DTB write accesses 337system.cpu0.dtb.data_hits 12559528 # DTB hits 338system.cpu0.dtb.data_misses 8256 # DTB misses 339system.cpu0.dtb.data_acv 344 # DTB access violations 340system.cpu0.dtb.data_accesses 678125 # DTB accesses 341system.cpu0.itb.fetch_hits 3501951 # ITB hits 342system.cpu0.itb.fetch_misses 3871 # ITB misses |
| 338system.cpu0.itb.fetch_acv 184 # ITB acv | 343system.cpu0.itb.fetch_acv 184 # ITB acv |
| 339system.cpu0.itb.fetch_accesses 3658284 # ITB accesses | 344system.cpu0.itb.fetch_accesses 3505822 # ITB accesses |
| 340system.cpu0.itb.read_hits 0 # DTB read hits 341system.cpu0.itb.read_misses 0 # DTB read misses 342system.cpu0.itb.read_acv 0 # DTB read access violations 343system.cpu0.itb.read_accesses 0 # DTB read accesses 344system.cpu0.itb.write_hits 0 # DTB write hits 345system.cpu0.itb.write_misses 0 # DTB write misses 346system.cpu0.itb.write_acv 0 # DTB write access violations 347system.cpu0.itb.write_accesses 0 # DTB write accesses 348system.cpu0.itb.data_hits 0 # DTB hits 349system.cpu0.itb.data_misses 0 # DTB misses 350system.cpu0.itb.data_acv 0 # DTB access violations 351system.cpu0.itb.data_accesses 0 # DTB accesses | 345system.cpu0.itb.read_hits 0 # DTB read hits 346system.cpu0.itb.read_misses 0 # DTB read misses 347system.cpu0.itb.read_acv 0 # DTB read access violations 348system.cpu0.itb.read_accesses 0 # DTB read accesses 349system.cpu0.itb.write_hits 0 # DTB write hits 350system.cpu0.itb.write_misses 0 # DTB write misses 351system.cpu0.itb.write_acv 0 # DTB write access violations 352system.cpu0.itb.write_accesses 0 # DTB write accesses 353system.cpu0.itb.data_hits 0 # DTB hits 354system.cpu0.itb.data_misses 0 # DTB misses 355system.cpu0.itb.data_acv 0 # DTB access violations 356system.cpu0.itb.data_accesses 0 # DTB accesses |
| 352system.cpu0.numCycles 3925685712 # number of cpu cycles simulated | 357system.cpu0.numCycles 3923838766 # number of cpu cycles simulated |
| 353system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 354system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 358system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 359system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 355system.cpu0.committedInsts 47981838 # Number of instructions committed 356system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed 357system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses 358system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses 359system.cpu0.num_func_calls 1202945 # number of times a function call or return occured 360system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls 361system.cpu0.num_int_insts 44508329 # number of integer instructions 362system.cpu0.num_fp_insts 212945 # number of float instructions 363system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read 364system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written 365system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read 366system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written 367system.cpu0.num_mem_refs 12703139 # number of memory refs 368system.cpu0.num_load_insts 7562835 # Number of load instructions 369system.cpu0.num_store_insts 5140304 # Number of store instructions 370system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles 371system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles 372system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles 373system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles 374system.cpu0.Branches 7224625 # Number of branches fetched 375system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction 376system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction 377system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction 378system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction 379system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction 380system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction 381system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction 382system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction 383system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction 384system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction 385system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction 386system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction 387system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction 388system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction 389system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction 390system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction 391system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction 392system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction 393system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction 394system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction 395system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction 396system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction 397system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction 398system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction 399system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction 400system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction 401system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction 402system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction 403system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction 404system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction 405system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction 406system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction 407system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction | 360system.cpu0.committedInsts 47743384 # Number of instructions committed 361system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed 362system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses 363system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses 364system.cpu0.num_func_calls 1202353 # number of times a function call or return occured 365system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls 366system.cpu0.num_int_insts 44279734 # number of integer instructions 367system.cpu0.num_fp_insts 210698 # number of float instructions 368system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read 369system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written 370system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read 371system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written 372system.cpu0.num_mem_refs 12599731 # number of memory refs 373system.cpu0.num_load_insts 7519361 # Number of load instructions 374system.cpu0.num_store_insts 5080370 # Number of store instructions 375system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles 376system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles 377system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles 378system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles 379system.cpu0.Branches 7198745 # Number of branches fetched 380system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction 381system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction 382system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction 383system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction 384system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction 385system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction 386system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction 387system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction 388system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction 389system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction 390system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction 391system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction 392system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction 393system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction 394system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction 395system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction 396system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction 397system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction 398system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction 399system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction 400system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction 401system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction 402system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction 403system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction 404system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction 405system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction 406system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction 407system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction 408system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction 409system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction 410system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction 411system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction 412system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction |
| 408system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 413system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 409system.cpu0.op_class::total 47990856 # Class of executed instruction | 414system.cpu0.op_class::total 47751984 # Class of executed instruction |
| 410system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 415system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 411system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed 412system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed 413system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl 414system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl 415system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl 416system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl 417system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl 418system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl 419system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl | 416system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed 417system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed 418system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl 419system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl 420system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl 421system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl 422system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl 423system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl 424system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl |
| 420system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl | 425system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl |
| 421system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl 422system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl 423system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl 424system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl 425system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl 426system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl 427system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl 428system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl 429system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl 430system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl 431system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl | 426system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl 427system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl 428system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl 429system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl 430system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl 431system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl 432system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl 433system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl 434system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl 435system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl 436system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl |
| 432system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 433system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 434system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 437system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 438system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 439system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 435system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl 436system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl 437system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 438system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 439system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 440system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 441system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 442system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 443system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 444system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed 445system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed 446system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed 447system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed 448system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed 449system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed 450system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed 451system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed 452system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed 453system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed 454system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed 455system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed 456system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed 457system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed 458system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed 459system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed 460system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 461system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 462system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 463system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 464system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 465system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 466system.cpu0.kern.syscall::total 234 # number of syscalls executed | 440system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl 441system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl 442system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 443system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 444system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 445system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 446system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 447system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 448system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 449system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 450system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 451system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 452system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 453system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 454system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 455system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 456system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 457system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 458system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 459system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 460system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 461system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 462system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 463system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 464system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 465system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 466system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 467system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 468system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 469system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 470system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 471system.cpu0.kern.syscall::total 222 # number of syscalls executed |
| 467system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 472system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 468system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed | 473system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed |
| 469system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 470system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 471system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed | 474system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 475system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 476system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed |
| 472system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed 473system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 474system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 475system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed 476system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed 477system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed 478system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed 479system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed 480system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed 481system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed 482system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed 483system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed 484system.cpu0.kern.callpal::total 149871 # number of callpals executed 485system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches 486system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches | 477system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed 478system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed 479system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed 480system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed 481system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed 482system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed 483system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed 484system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed 485system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed 486system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed 487system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed 488system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed 489system.cpu0.kern.callpal::total 149812 # number of callpals executed 490system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches 491system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches |
| 487system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 492system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 488system.cpu0.kern.mode_good::kernel 1369 489system.cpu0.kern.mode_good::user 1370 | 493system.cpu0.kern.mode_good::kernel 1282 494system.cpu0.kern.mode_good::user 1282 |
| 490system.cpu0.kern.mode_good::idle 0 | 495system.cpu0.kern.mode_good::idle 0 |
| 491system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches | 496system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches |
| 492system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 493system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 497system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 498system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 494system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches 495system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode 496system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode | 499system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches 500system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode 501system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode |
| 497system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 502system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 498system.cpu0.kern.swap_context 3098 # number of times the context was actually changed 499system.cpu0.dcache.tags.replacements 1190069 # number of replacements 500system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use 501system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. 502system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. 503system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. 504system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. 505system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor 506system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy 507system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy 508system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 509system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 510system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id 511system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 512system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 513system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses 514system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses 515system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits 516system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits 517system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits 518system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits 519system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits 520system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits 521system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits 522system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits 523system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits 524system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits 525system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits 526system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits 527system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses 528system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses 529system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses 530system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses 531system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses 532system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses 533system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses 534system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses 535system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses 536system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses 537system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses 538system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses 539system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles 540system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles 541system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles 542system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles 543system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles 544system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles 545system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles 546system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles 547system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles 548system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles 549system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles 550system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles 551system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) 552system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) 553system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) 554system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) 555system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) 556system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) 557system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) 558system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) 559system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses 560system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses 561system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses 562system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses 563system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses 564system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses 565system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses 566system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses 567system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses 568system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses 569system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses 570system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq accesses 571system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097053 # miss rate for demand accesses 572system.cpu0.dcache.demand_miss_rate::total 0.097053 # miss rate for demand accesses 573system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097053 # miss rate for overall accesses 574system.cpu0.dcache.overall_miss_rate::total 0.097053 # miss rate for overall accesses 575system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28892.823107 # average ReadReq miss latency 576system.cpu0.dcache.ReadReq_avg_miss_latency::total 28892.823107 # average ReadReq miss latency 577system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40142.699833 # average WriteReq miss latency 578system.cpu0.dcache.WriteReq_avg_miss_latency::total 40142.699833 # average WriteReq miss latency 579system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.717120 # average LoadLockedReq miss latency 580system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.717120 # average LoadLockedReq miss latency 581system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency 582system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency 583system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency 584system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency 585system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency 586system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency | 503system.cpu0.kern.swap_context 3068 # number of times the context was actually changed 504system.cpu0.dcache.tags.replacements 1180939 # number of replacements 505system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use 506system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks. 507system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks. 508system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks. 509system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. 510system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor 511system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy 512system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy 513system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id 514system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id 515system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id 516system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id 517system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses 518system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses 519system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits 520system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits 521system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits 522system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits 523system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits 524system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits 525system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits 526system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits 527system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits 528system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits 529system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits 530system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits 531system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses 532system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses 533system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses 534system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses 535system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses 536system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses 537system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses 538system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses 539system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses 540system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses 541system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses 542system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses 543system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles 544system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles 545system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles 546system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles 547system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles 548system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles 549system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles 550system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles 551system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles 552system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles 553system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles 554system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles 555system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses) 556system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses) 557system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses) 558system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses) 559system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses) 560system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses) 561system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses) 562system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses) 563system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses 564system.cpu0.dcache.demand_accesses::total 12261297 # number of demand (read+write) accesses 565system.cpu0.dcache.overall_accesses::cpu0.data 12261297 # number of overall (read+write) accesses 566system.cpu0.dcache.overall_accesses::total 12261297 # number of overall (read+write) accesses 567system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127696 # miss rate for ReadReq accesses 568system.cpu0.dcache.ReadReq_miss_rate::total 0.127696 # miss rate for ReadReq accesses 569system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051247 # miss rate for WriteReq accesses 570system.cpu0.dcache.WriteReq_miss_rate::total 0.051247 # miss rate for WriteReq accesses 571system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088684 # miss rate for LoadLockedReq accesses 572system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088684 # miss rate for LoadLockedReq accesses 573system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses 574system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses 575system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses 576system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses 577system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses 578system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses 579system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency 580system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency 581system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency 582system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency 583system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency 584system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency 585system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency 586system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency 587system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency 588system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency 589system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency 590system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency |
| 587system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 588system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 589system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 590system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 591system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 592system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 593system.cpu0.dcache.fast_writes 0 # number of fast writes performed 594system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 591system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 592system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 594system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 596system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 597system.cpu0.dcache.fast_writes 0 # number of fast writes performed 598system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 595system.cpu0.dcache.writebacks::writebacks 685914 # number of writebacks 596system.cpu0.dcache.writebacks::total 685914 # number of writebacks 597system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942274 # number of ReadReq MSHR misses 598system.cpu0.dcache.ReadReq_mshr_misses::total 942274 # number of ReadReq MSHR misses 599system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257633 # number of WriteReq MSHR misses 600system.cpu0.dcache.WriteReq_mshr_misses::total 257633 # number of WriteReq MSHR misses 601system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13709 # number of LoadLockedReq MSHR misses 602system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13709 # number of LoadLockedReq MSHR misses 603system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5579 # number of StoreCondReq MSHR misses 604system.cpu0.dcache.StoreCondReq_mshr_misses::total 5579 # number of StoreCondReq MSHR misses 605system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199907 # number of demand (read+write) MSHR misses 606system.cpu0.dcache.demand_mshr_misses::total 1199907 # number of demand (read+write) MSHR misses 607system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199907 # number of overall MSHR misses 608system.cpu0.dcache.overall_mshr_misses::total 1199907 # number of overall MSHR misses 609system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25214933000 # number of ReadReq MSHR miss cycles 610system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25214933000 # number of ReadReq MSHR miss cycles 611system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9773693814 # number of WriteReq MSHR miss cycles 612system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9773693814 # number of WriteReq MSHR miss cycles 613system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122568000 # number of LoadLockedReq MSHR miss cycles 614system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122568000 # number of LoadLockedReq MSHR miss cycles 615system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31544105 # number of StoreCondReq MSHR miss cycles 616system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31544105 # number of StoreCondReq MSHR miss cycles 617system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34988626814 # number of demand (read+write) MSHR miss cycles 618system.cpu0.dcache.demand_mshr_miss_latency::total 34988626814 # number of demand (read+write) MSHR miss cycles 619system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34988626814 # number of overall MSHR miss cycles 620system.cpu0.dcache.overall_mshr_miss_latency::total 34988626814 # number of overall MSHR miss cycles 621system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461501000 # number of ReadReq MSHR uncacheable cycles 622system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461501000 # number of ReadReq MSHR uncacheable cycles 623system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267119000 # number of WriteReq MSHR uncacheable cycles 624system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267119000 # number of WriteReq MSHR uncacheable cycles 625system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728620000 # number of overall MSHR uncacheable cycles 626system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728620000 # number of overall MSHR uncacheable cycles 627system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127450 # mshr miss rate for ReadReq accesses 628system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127450 # mshr miss rate for ReadReq accesses 629system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses 630system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses 631system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088742 # mshr miss rate for LoadLockedReq accesses 632system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088742 # mshr miss rate for LoadLockedReq accesses 633system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036243 # mshr miss rate for StoreCondReq accesses 634system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036243 # mshr miss rate for StoreCondReq accesses 635system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for demand accesses 636system.cpu0.dcache.demand_mshr_miss_rate::total 0.097053 # mshr miss rate for demand accesses 637system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for overall accesses 638system.cpu0.dcache.overall_mshr_miss_rate::total 0.097053 # mshr miss rate for overall accesses 639system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26759.661203 # average ReadReq mshr miss latency 640system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26759.661203 # average ReadReq mshr miss latency 641system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37936.498096 # average WriteReq mshr miss latency 642system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37936.498096 # average WriteReq mshr miss latency 643system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.695893 # average LoadLockedReq mshr miss latency 644system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.695893 # average LoadLockedReq mshr miss latency 645system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5654.078688 # average StoreCondReq mshr miss latency 646system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5654.078688 # average StoreCondReq mshr miss latency 647system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency 648system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency 649system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency 650system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency | 599system.cpu0.dcache.writebacks::writebacks 679102 # number of writebacks 600system.cpu0.dcache.writebacks::total 679102 # number of writebacks 601system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938638 # number of ReadReq MSHR misses 602system.cpu0.dcache.ReadReq_mshr_misses::total 938638 # number of ReadReq MSHR misses 603system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251661 # number of WriteReq MSHR misses 604system.cpu0.dcache.WriteReq_mshr_misses::total 251661 # number of WriteReq MSHR misses 605system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses 606system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses 607system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses 608system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses 609system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses 610system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses 611system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses 612system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses 613system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles 614system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles 615system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476948315 # number of WriteReq MSHR miss cycles 616system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476948315 # number of WriteReq MSHR miss cycles 617system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles 618system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles 619system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles 620system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles 621system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles 622system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles 623system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles 624system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles 625system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles 626system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles 627system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles 628system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles 629system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # number of overall MSHR uncacheable cycles 630system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768311500 # number of overall MSHR uncacheable cycles 631system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses 632system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses 633system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses 634system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses 635system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses 636system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses 637system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses 638system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses 639system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses 640system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses 641system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses 642system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses 643system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency 644system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency 645system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.195596 # average WriteReq mshr miss latency 646system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.195596 # average WriteReq mshr miss latency 647system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency 648system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency 649system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency 650system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency 651system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency 652system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency 653system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency 654system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency |
| 651system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 652system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 653system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 654system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 655system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 656system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 657system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 655system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 656system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 657system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 658system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 659system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 660system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 661system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 658system.cpu0.icache.tags.replacements 699791 # number of replacements 659system.cpu0.icache.tags.tagsinuse 508.391652 # Cycle average of tags in use 660system.cpu0.icache.tags.total_refs 47290432 # Total number of references to valid blocks. 661system.cpu0.icache.tags.sampled_refs 700302 # Sample count of references to valid blocks. 662system.cpu0.icache.tags.avg_refs 67.528626 # Average number of references to valid blocks. 663system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. 664system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391652 # Average occupied blocks per requestor 665system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy 666system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy 667system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 668system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 669system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 670system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id 671system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 672system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 673system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses 674system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses 675system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits 676system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits 677system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits 678system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits 679system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits 680system.cpu0.icache.overall_hits::total 47290432 # number of overall hits 681system.cpu0.icache.ReadReq_misses::cpu0.inst 700425 # number of ReadReq misses 682system.cpu0.icache.ReadReq_misses::total 700425 # number of ReadReq misses 683system.cpu0.icache.demand_misses::cpu0.inst 700425 # number of demand (read+write) misses 684system.cpu0.icache.demand_misses::total 700425 # number of demand (read+write) misses 685system.cpu0.icache.overall_misses::cpu0.inst 700425 # number of overall misses 686system.cpu0.icache.overall_misses::total 700425 # number of overall misses 687system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9965953746 # number of ReadReq miss cycles 688system.cpu0.icache.ReadReq_miss_latency::total 9965953746 # number of ReadReq miss cycles 689system.cpu0.icache.demand_miss_latency::cpu0.inst 9965953746 # number of demand (read+write) miss cycles 690system.cpu0.icache.demand_miss_latency::total 9965953746 # number of demand (read+write) miss cycles 691system.cpu0.icache.overall_miss_latency::cpu0.inst 9965953746 # number of overall miss cycles 692system.cpu0.icache.overall_miss_latency::total 9965953746 # number of overall miss cycles 693system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) 694system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) 695system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses 696system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses 697system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses 698system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses 699system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses 700system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses 701system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses 702system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses 703system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses 704system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses 705system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency 706system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency 707system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency 708system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency 709system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency 710system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency | 662system.cpu0.icache.tags.replacements 698758 # number of replacements 663system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use 664system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks. 665system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks. 666system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks. 667system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit. 668system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor 669system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992492 # Average percentage of cache occupancy 670system.cpu0.icache.tags.occ_percent::total 0.992492 # Average percentage of cache occupancy 671system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 672system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id 673system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id 674system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 675system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses 676system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses 677system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits 678system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits 679system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits 680system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits 681system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits 682system.cpu0.icache.overall_hits::total 47052596 # number of overall hits 683system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses 684system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses 685system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses 686system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses 687system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses 688system.cpu0.icache.overall_misses::total 699388 # number of overall misses 689system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles 690system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles 691system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles 692system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles 693system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles 694system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles 695system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses) 696system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses) 697system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses 698system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses 699system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses 700system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses 701system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses 702system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses 703system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses 704system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses 705system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses 706system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses 707system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency 708system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency 709system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency 710system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency 711system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency 712system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency |
| 711system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 712system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 713system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 714system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 715system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 716system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu0.icache.fast_writes 0 # number of fast writes performed 718system.cpu0.icache.cache_copies 0 # number of cache copies performed | 713system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 714system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 715system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 716system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 717system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 718system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 719system.cpu0.icache.fast_writes 0 # number of fast writes performed 720system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 719system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses 720system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses 721system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses 722system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses 723system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses 724system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses 725system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles 726system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles 727system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles 728system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles 729system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles 730system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles 731system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses 732system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses 733system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses 734system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses 735system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses 736system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses 737system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency 738system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency 739system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency 740system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency 741system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency 742system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency | 721system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses 722system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses 723system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses 724system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses 725system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses 726system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses 727system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles 728system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles 729system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles 730system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles 731system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles 732system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles 733system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses 734system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses 735system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses 736system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses 737system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses 738system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses 739system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency 740system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency 741system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency 742system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency 743system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency 744system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency |
| 743system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 744system.cpu1.dtb.fetch_hits 0 # ITB hits 745system.cpu1.dtb.fetch_misses 0 # ITB misses 746system.cpu1.dtb.fetch_acv 0 # ITB acv 747system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 745system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 746system.cpu1.dtb.fetch_hits 0 # ITB hits 747system.cpu1.dtb.fetch_misses 0 # ITB misses 748system.cpu1.dtb.fetch_acv 0 # ITB acv 749system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 748system.cpu1.dtb.read_hits 2381610 # DTB read hits 749system.cpu1.dtb.read_misses 2620 # DTB read misses | 750system.cpu1.dtb.read_hits 2419579 # DTB read hits 751system.cpu1.dtb.read_misses 2992 # DTB read misses |
| 750system.cpu1.dtb.read_acv 0 # DTB read access violations | 752system.cpu1.dtb.read_acv 0 # DTB read access violations |
| 751system.cpu1.dtb.read_accesses 205337 # DTB read accesses 752system.cpu1.dtb.write_hits 1701782 # DTB write hits 753system.cpu1.dtb.write_misses 235 # DTB write misses 754system.cpu1.dtb.write_acv 24 # DTB write access violations 755system.cpu1.dtb.write_accesses 89739 # DTB write accesses 756system.cpu1.dtb.data_hits 4083392 # DTB hits 757system.cpu1.dtb.data_misses 2855 # DTB misses 758system.cpu1.dtb.data_acv 24 # DTB access violations 759system.cpu1.dtb.data_accesses 295076 # DTB accesses 760system.cpu1.itb.fetch_hits 1808769 # ITB hits 761system.cpu1.itb.fetch_misses 1064 # ITB misses | 753system.cpu1.dtb.read_accesses 239363 # DTB read accesses 754system.cpu1.dtb.write_hits 1757217 # DTB write hits 755system.cpu1.dtb.write_misses 341 # DTB write misses 756system.cpu1.dtb.write_acv 29 # DTB write access violations 757system.cpu1.dtb.write_accesses 105247 # DTB write accesses 758system.cpu1.dtb.data_hits 4176796 # DTB hits 759system.cpu1.dtb.data_misses 3333 # DTB misses 760system.cpu1.dtb.data_acv 29 # DTB access violations 761system.cpu1.dtb.data_accesses 344610 # DTB accesses 762system.cpu1.itb.fetch_hits 1964101 # ITB hits 763system.cpu1.itb.fetch_misses 1216 # ITB misses |
| 762system.cpu1.itb.fetch_acv 0 # ITB acv | 764system.cpu1.itb.fetch_acv 0 # ITB acv |
| 763system.cpu1.itb.fetch_accesses 1809833 # ITB accesses | 765system.cpu1.itb.fetch_accesses 1965317 # ITB accesses |
| 764system.cpu1.itb.read_hits 0 # DTB read hits 765system.cpu1.itb.read_misses 0 # DTB read misses 766system.cpu1.itb.read_acv 0 # DTB read access violations 767system.cpu1.itb.read_accesses 0 # DTB read accesses 768system.cpu1.itb.write_hits 0 # DTB write hits 769system.cpu1.itb.write_misses 0 # DTB write misses 770system.cpu1.itb.write_acv 0 # DTB write access violations 771system.cpu1.itb.write_accesses 0 # DTB write accesses 772system.cpu1.itb.data_hits 0 # DTB hits 773system.cpu1.itb.data_misses 0 # DTB misses 774system.cpu1.itb.data_acv 0 # DTB access violations 775system.cpu1.itb.data_accesses 0 # DTB accesses | 766system.cpu1.itb.read_hits 0 # DTB read hits 767system.cpu1.itb.read_misses 0 # DTB read misses 768system.cpu1.itb.read_acv 0 # DTB read access violations 769system.cpu1.itb.read_accesses 0 # DTB read accesses 770system.cpu1.itb.write_hits 0 # DTB write hits 771system.cpu1.itb.write_misses 0 # DTB write misses 772system.cpu1.itb.write_acv 0 # DTB write access violations 773system.cpu1.itb.write_accesses 0 # DTB write accesses 774system.cpu1.itb.data_hits 0 # DTB hits 775system.cpu1.itb.data_misses 0 # DTB misses 776system.cpu1.itb.data_acv 0 # DTB access violations 777system.cpu1.itb.data_accesses 0 # DTB accesses |
| 776system.cpu1.numCycles 3923834021 # number of cpu cycles simulated | 778system.cpu1.numCycles 3925225373 # number of cpu cycles simulated |
| 777system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 778system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 779system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 780system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 779system.cpu1.committedInsts 12938544 # Number of instructions committed 780system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed 781system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses 782system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses 783system.cpu1.num_func_calls 411382 # number of times a function call or return occured 784system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls 785system.cpu1.num_int_insts 11924615 # number of integer instructions 786system.cpu1.num_fp_insts 171199 # number of float instructions 787system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read 788system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written 789system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read 790system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written 791system.cpu1.num_mem_refs 4106042 # number of memory refs 792system.cpu1.num_load_insts 2395192 # Number of load instructions 793system.cpu1.num_store_insts 1710850 # Number of store instructions 794system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles 795system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles 796system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles 797system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles 798system.cpu1.Branches 1847277 # Number of branches fetched 799system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction 800system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction 801system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction 802system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction 803system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction 804system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction 805system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction 806system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction 807system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction 808system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction 809system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction 810system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction 811system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction 812system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction 813system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction 814system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction 815system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction 816system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction 817system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction 818system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction 819system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction 820system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction 821system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction 822system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction 823system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction 824system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction 825system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction 826system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction 827system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction 828system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction 829system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction 830system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction 831system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction | 781system.cpu1.committedInsts 13155254 # Number of instructions committed 782system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed 783system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses 784system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses 785system.cpu1.num_func_calls 411301 # number of times a function call or return occured 786system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls 787system.cpu1.num_int_insts 12132982 # number of integer instructions 788system.cpu1.num_fp_insts 173111 # number of float instructions 789system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read 790system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written 791system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read 792system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written 793system.cpu1.num_mem_refs 4200357 # number of memory refs 794system.cpu1.num_load_insts 2433886 # Number of load instructions 795system.cpu1.num_store_insts 1766471 # Number of store instructions 796system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles 797system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles 798system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles 799system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles 800system.cpu1.Branches 1871330 # Number of branches fetched 801system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction 802system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction 803system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction 804system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction 805system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction 806system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction 807system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction 808system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction 809system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction 810system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction 811system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction 812system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction 813system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction 814system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction 815system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction 816system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction 817system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction 818system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction 819system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction 820system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction 821system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction 822system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction 823system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction 824system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction 825system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction 826system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction 827system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction 828system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction 829system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction 830system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction 831system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction 832system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction 833system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction |
| 832system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 834system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 833system.cpu1.op_class::total 12941423 # Class of executed instruction | 835system.cpu1.op_class::total 13158616 # Class of executed instruction |
| 834system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 836system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 835system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed 836system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed 837system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl 838system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl 839system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl 840system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl 841system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl 842system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl 843system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl 844system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl 845system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl 846system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl 847system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl 848system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl 849system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl 850system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl 851system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl 852system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl | 837system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed 838system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed 839system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl 840system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl 841system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl 842system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl 843system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl 844system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl 845system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl 846system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl 847system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl 848system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl 849system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl 850system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl 851system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl 852system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl 853system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl 854system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl |
| 853system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 854system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 855system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 856system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 855system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl 856system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl 857system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 858system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 859system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 860system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 861system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 862system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 863system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 864system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 865system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 866system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 867system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 868system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 869system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 870system.cpu1.kern.syscall::total 92 # number of syscalls executed | 857system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl 858system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl 859system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 860system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 861system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 862system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 863system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 864system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 865system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 866system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 867system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 868system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 869system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 870system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 871system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 872system.cpu1.kern.syscall::total 104 # number of syscalls executed |
| 871system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 873system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 872system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed 873system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed 874system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed 875system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed 876system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed 877system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed 878system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed 879system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed 880system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed 881system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed 882system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed 883system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed 884system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed 885system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed | 874system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed 875system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 876system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 877system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed 878system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed 879system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed 880system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed 881system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed 882system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed 883system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed 884system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed 885system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed 886system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed 887system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed |
| 886system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 888system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 887system.cpu1.kern.callpal::total 71468 # number of callpals executed 888system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches 889system.cpu1.kern.mode_switch::user 368 # number of protection mode switches 890system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches 891system.cpu1.kern.mode_good::kernel 804 892system.cpu1.kern.mode_good::user 368 893system.cpu1.kern.mode_good::idle 436 894system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches | 889system.cpu1.kern.callpal::total 71473 # number of callpals executed 890system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches 891system.cpu1.kern.mode_switch::user 463 # number of protection mode switches 892system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches 893system.cpu1.kern.mode_good::kernel 890 894system.cpu1.kern.mode_good::user 463 895system.cpu1.kern.mode_good::idle 427 896system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches |
| 895system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 897system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 896system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches 897system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches 898system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode 899system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode 900system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode 901system.cpu1.kern.swap_context 1968 # number of times the context was actually changed 902system.cpu1.dcache.tags.replacements 157282 # number of replacements 903system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use 904system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. 905system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. 906system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. 907system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. 908system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor 909system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy 910system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy 911system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id 912system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 913system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id 914system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id 915system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses 916system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses 917system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits 918system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits 919system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits 920system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits 921system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits 922system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits 923system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits 924system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits 925system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits 926system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits 927system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits 928system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits 929system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses 930system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses 931system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses 932system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses 933system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses 934system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses 935system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses 936system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses 937system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses 938system.cpu1.dcache.demand_misses::total 172235 # number of demand (read+write) misses 939system.cpu1.dcache.overall_misses::cpu1.data 172235 # number of overall misses 940system.cpu1.dcache.overall_misses::total 172235 # number of overall misses 941system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1388298999 # number of ReadReq miss cycles 942system.cpu1.dcache.ReadReq_miss_latency::total 1388298999 # number of ReadReq miss cycles 943system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079375302 # number of WriteReq miss cycles 944system.cpu1.dcache.WriteReq_miss_latency::total 1079375302 # number of WriteReq miss cycles 945system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80583500 # number of LoadLockedReq miss cycles 946system.cpu1.dcache.LoadLockedReq_miss_latency::total 80583500 # number of LoadLockedReq miss cycles 947system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43835417 # number of StoreCondReq miss cycles 948system.cpu1.dcache.StoreCondReq_miss_latency::total 43835417 # number of StoreCondReq miss cycles 949system.cpu1.dcache.demand_miss_latency::cpu1.data 2467674301 # number of demand (read+write) miss cycles 950system.cpu1.dcache.demand_miss_latency::total 2467674301 # number of demand (read+write) miss cycles 951system.cpu1.dcache.overall_miss_latency::cpu1.data 2467674301 # number of overall miss cycles 952system.cpu1.dcache.overall_miss_latency::total 2467674301 # number of overall miss cycles 953system.cpu1.dcache.ReadReq_accesses::cpu1.data 2335780 # number of ReadReq accesses(hits+misses) 954system.cpu1.dcache.ReadReq_accesses::total 2335780 # number of ReadReq accesses(hits+misses) 955system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647384 # number of WriteReq accesses(hits+misses) 956system.cpu1.dcache.WriteReq_accesses::total 1647384 # number of WriteReq accesses(hits+misses) 957system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56679 # number of LoadLockedReq accesses(hits+misses) 958system.cpu1.dcache.LoadLockedReq_accesses::total 56679 # number of LoadLockedReq accesses(hits+misses) 959system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56204 # number of StoreCondReq accesses(hits+misses) 960system.cpu1.dcache.StoreCondReq_accesses::total 56204 # number of StoreCondReq accesses(hits+misses) 961system.cpu1.dcache.demand_accesses::cpu1.data 3983164 # number of demand (read+write) accesses 962system.cpu1.dcache.demand_accesses::total 3983164 # number of demand (read+write) accesses 963system.cpu1.dcache.overall_accesses::cpu1.data 3983164 # number of overall (read+write) accesses 964system.cpu1.dcache.overall_accesses::total 3983164 # number of overall (read+write) accesses 965system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049276 # miss rate for ReadReq accesses 966system.cpu1.dcache.ReadReq_miss_rate::total 0.049276 # miss rate for ReadReq accesses 967system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034684 # miss rate for WriteReq accesses 968system.cpu1.dcache.WriteReq_miss_rate::total 0.034684 # miss rate for WriteReq accesses 969system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157078 # miss rate for LoadLockedReq accesses 970system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157078 # miss rate for LoadLockedReq accesses 971system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106167 # miss rate for StoreCondReq accesses 972system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106167 # miss rate for StoreCondReq accesses 973system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043241 # miss rate for demand accesses 974system.cpu1.dcache.demand_miss_rate::total 0.043241 # miss rate for demand accesses 975system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043241 # miss rate for overall accesses 976system.cpu1.dcache.overall_miss_rate::total 0.043241 # miss rate for overall accesses 977system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.991181 # average ReadReq miss latency 978system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.991181 # average ReadReq miss latency 979system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18890.673492 # average WriteReq miss latency 980system.cpu1.dcache.WriteReq_avg_miss_latency::total 18890.673492 # average WriteReq miss latency 981system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9051.274851 # average LoadLockedReq miss latency 982system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9051.274851 # average LoadLockedReq miss latency 983system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.307525 # average StoreCondReq miss latency 984system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.307525 # average StoreCondReq miss latency 985system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency 986system.cpu1.dcache.demand_avg_miss_latency::total 14327.368427 # average overall miss latency 987system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency 988system.cpu1.dcache.overall_avg_miss_latency::total 14327.368427 # average overall miss latency | 898system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches 899system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches 900system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode 901system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode 902system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode 903system.cpu1.kern.swap_context 1998 # number of times the context was actually changed 904system.cpu1.dcache.tags.replacements 166165 # number of replacements 905system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use 906system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks. 907system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks. 908system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks. 909system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit. 910system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor 911system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy 912system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy 913system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 914system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 915system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id 916system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id 917system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 918system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses 919system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses 920system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits 921system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits 922system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits 923system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits 924system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits 925system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits 926system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits 927system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits 928system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits 929system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits 930system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits 931system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits 932system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses 933system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses 934system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses 935system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses 936system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses 937system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses 938system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses 939system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses 940system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses 941system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses 942system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses 943system.cpu1.dcache.overall_misses::total 180698 # number of overall misses 944system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles 945system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles 946system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles 947system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles 948system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81194500 # number of LoadLockedReq miss cycles 949system.cpu1.dcache.LoadLockedReq_miss_latency::total 81194500 # number of LoadLockedReq miss cycles 950system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles 951system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles 952system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles 953system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles 954system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles 955system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles 956system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses) 957system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses) 958system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses) 959system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses) 960system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses) 961system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses) 962system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses) 963system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses) 964system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses 965system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses 966system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses 967system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses 968system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses 969system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses 970system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses 971system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses 972system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses 973system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses 974system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses 975system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses 976system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses 977system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses 978system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses 979system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses 980system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency 981system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency 982system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency 983system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency 984system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.649316 # average LoadLockedReq miss latency 985system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.649316 # average LoadLockedReq miss latency 986system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency 987system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency 988system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency 989system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency 990system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency 991system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency |
| 989system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 990system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 991system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 992system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 993system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 994system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 995system.cpu1.dcache.fast_writes 0 # number of fast writes performed 996system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 992system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 993system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 994system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 995system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 996system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 997system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 998system.cpu1.dcache.fast_writes 0 # number of fast writes performed 999system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 997system.cpu1.dcache.writebacks::writebacks 107942 # number of writebacks 998system.cpu1.dcache.writebacks::total 107942 # number of writebacks 999system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses 1000system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses 1001system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57138 # number of WriteReq MSHR misses 1002system.cpu1.dcache.WriteReq_mshr_misses::total 57138 # number of WriteReq MSHR misses 1003system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8903 # number of LoadLockedReq MSHR misses 1004system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8903 # number of LoadLockedReq MSHR misses 1005system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5967 # number of StoreCondReq MSHR misses 1006system.cpu1.dcache.StoreCondReq_mshr_misses::total 5967 # number of StoreCondReq MSHR misses 1007system.cpu1.dcache.demand_mshr_misses::cpu1.data 172235 # number of demand (read+write) MSHR misses 1008system.cpu1.dcache.demand_mshr_misses::total 172235 # number of demand (read+write) MSHR misses 1009system.cpu1.dcache.overall_mshr_misses::cpu1.data 172235 # number of overall MSHR misses 1010system.cpu1.dcache.overall_mshr_misses::total 172235 # number of overall MSHR misses 1011system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1158014001 # number of ReadReq MSHR miss cycles 1012system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1158014001 # number of ReadReq MSHR miss cycles 1013system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962534698 # number of WriteReq MSHR miss cycles 1014system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962534698 # number of WriteReq MSHR miss cycles 1015system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62777500 # number of LoadLockedReq MSHR miss cycles 1016system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62777500 # number of LoadLockedReq MSHR miss cycles 1017system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31899583 # number of StoreCondReq MSHR miss cycles 1018system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31899583 # number of StoreCondReq MSHR miss cycles 1019system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2120548699 # number of demand (read+write) MSHR miss cycles 1020system.cpu1.dcache.demand_mshr_miss_latency::total 2120548699 # number of demand (read+write) MSHR miss cycles 1021system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2120548699 # number of overall MSHR miss cycles 1022system.cpu1.dcache.overall_mshr_miss_latency::total 2120548699 # number of overall MSHR miss cycles 1023system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles 1024system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles 1025system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726754500 # number of WriteReq MSHR uncacheable cycles 1026system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726754500 # number of WriteReq MSHR uncacheable cycles 1027system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749201000 # number of overall MSHR uncacheable cycles 1028system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749201000 # number of overall MSHR uncacheable cycles 1029system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049276 # mshr miss rate for ReadReq accesses 1030system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049276 # mshr miss rate for ReadReq accesses 1031system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034684 # mshr miss rate for WriteReq accesses 1032system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034684 # mshr miss rate for WriteReq accesses 1033system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157078 # mshr miss rate for LoadLockedReq accesses 1034system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157078 # mshr miss rate for LoadLockedReq accesses 1035system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for StoreCondReq accesses 1036system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106167 # mshr miss rate for StoreCondReq accesses 1037system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses 1038system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses 1039system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses 1040system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses 1041system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency 1042system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency 1043system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency 1044system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency 1045system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency 1046system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency 1047system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency 1048system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency 1049system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency 1050system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency 1051system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency 1052system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency | 1000system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks 1001system.cpu1.dcache.writebacks::total 114146 # number of writebacks 1002system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses 1003system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses 1004system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses 1005system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses 1006system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses 1007system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses 1008system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses 1009system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses 1010system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses 1011system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses 1012system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses 1013system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses 1014system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles 1015system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles 1016system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles 1017system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles 1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67823500 # number of LoadLockedReq MSHR miss cycles 1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67823500 # number of LoadLockedReq MSHR miss cycles 1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles 1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles 1022system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles 1023system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles 1024system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles 1025system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles 1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18864000 # number of ReadReq MSHR uncacheable cycles 1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18864000 # number of ReadReq MSHR uncacheable cycles 1028system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716373000 # number of WriteReq MSHR uncacheable cycles 1029system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716373000 # number of WriteReq MSHR uncacheable cycles 1030system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735237000 # number of overall MSHR uncacheable cycles 1031system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735237000 # number of overall MSHR uncacheable cycles 1032system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses 1033system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses 1034system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses 1035system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses 1036system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses 1037system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses 1038system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses 1039system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses 1040system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses 1041system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses 1042system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses 1043system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses 1044system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency 1045system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency 1046system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency 1047system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency 1048system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.649316 # average LoadLockedReq mshr miss latency 1049system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency 1050system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency 1051system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency 1052system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency 1053system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency 1054system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency 1055system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency |
| 1053system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1054system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1055system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1056system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1057system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1058system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1059system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1056system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1058system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1059system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1060system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1061system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1062system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1060system.cpu1.icache.tags.replacements 318148 # number of replacements 1061system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use 1062system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. 1063system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. 1064system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. 1065system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. 1066system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor 1067system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy 1068system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy | 1063system.cpu1.icache.tags.replacements 315648 # number of replacements 1064system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use 1065system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. 1066system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. 1067system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. 1068system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. 1069system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor 1070system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy 1071system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy |
| 1069system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1072system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1070system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 1071system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id 1072system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id | 1073system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1074system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 1075system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id 1076system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id |
| 1073system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1077system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1074system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses 1075system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses 1076system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits 1077system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits 1078system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits 1079system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits 1080system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits 1081system.cpu1.icache.overall_hits::total 12622723 # number of overall hits 1082system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses 1083system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses 1084system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses 1085system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses 1086system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses 1087system.cpu1.icache.overall_misses::total 318700 # number of overall misses 1088system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles 1089system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles 1090system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles 1091system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles 1092system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles 1093system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles 1094system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) 1095system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) 1096system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses 1097system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses 1098system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses 1099system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses 1100system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses 1101system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses 1102system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses 1103system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses 1104system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses 1105system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses 1106system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency 1107system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency 1108system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency 1109system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency 1110system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency 1111system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency | 1078system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses 1079system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses 1080system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits 1081system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits 1082system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits 1083system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits 1084system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits 1085system.cpu1.icache.overall_hits::total 12842415 # number of overall hits 1086system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses 1087system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses 1088system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses 1089system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses 1090system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses 1091system.cpu1.icache.overall_misses::total 316202 # number of overall misses 1092system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles 1093system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles 1094system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles 1095system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles 1096system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles 1097system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles 1098system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses) 1099system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses) 1100system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses 1101system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses 1102system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses 1103system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses 1104system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses 1105system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses 1106system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses 1107system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses 1108system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses 1109system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses 1110system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency 1111system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency 1112system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency 1113system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency 1114system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency 1115system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency |
| 1112system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1113system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1114system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1115system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1116system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1117system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1118system.cpu1.icache.fast_writes 0 # number of fast writes performed 1119system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1116system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1117system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1118system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1119system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1120system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1121system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1122system.cpu1.icache.fast_writes 0 # number of fast writes performed 1123system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1120system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses 1121system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses 1122system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses 1123system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses 1124system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses 1125system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses 1126system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles 1127system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles 1128system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles 1129system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles 1130system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles 1131system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles 1132system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses 1133system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses 1134system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses 1135system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses 1136system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses 1137system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses 1138system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency 1139system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency 1140system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency 1141system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency 1142system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency 1143system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency | 1124system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses 1125system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses 1126system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses 1127system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses 1128system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses 1129system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses 1130system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles 1131system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles 1132system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles 1133system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles 1134system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles 1135system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles 1136system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses 1137system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses 1138system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses 1139system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses 1140system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses 1141system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses 1142system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency 1143system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency 1144system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency 1145system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency 1146system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency 1147system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency |
| 1144system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1145system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1146system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1147system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1148system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1149system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1150system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1151system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1152system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1153system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1154system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1155system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1156system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1157system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1158system.iobus.trans_dist::ReadResp 7373 # Transaction distribution | 1148system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1149system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1150system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1151system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1152system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1153system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1154system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1155system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1156system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1157system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1158system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1159system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1160system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1161system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1162system.iobus.trans_dist::ReadResp 7373 # Transaction distribution |
| 1159system.iobus.trans_dist::WriteReq 55631 # Transaction distribution 1160system.iobus.trans_dist::WriteResp 14079 # Transaction distribution | 1163system.iobus.trans_dist::WriteReq 55604 # Transaction distribution 1164system.iobus.trans_dist::WriteResp 14052 # Transaction distribution |
| 1161system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution | 1165system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 1162system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) | 1166system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) |
| 1164system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 1174system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes) 1179system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) | 1178system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 1181system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) |
| 1180system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1181system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 1184system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1190system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes) 1194system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks) | 1194system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes) 1195system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 1196system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 1197system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks) |
| 1195system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1199system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1196system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) | 1200system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) |
| 1197system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1198system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1199system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1200system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1201system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1203system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1205system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) 1207system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1209system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1211system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1212system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1213system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1214system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1215system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1201system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1203system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1205system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1207system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1209system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) 1211system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1212system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1213system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1214system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1215system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1216system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1217system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1218system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1219system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1216system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) | 1220system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks) |
| 1217system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1218system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1219system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 1221system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1222system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1223system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 1220system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks) | 1224system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks) |
| 1221system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1225system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1222system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) | 1226system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks) |
| 1223system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1227system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1224system.iocache.tags.replacements 41696 # number of replacements 1225system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use | 1228system.iocache.tags.replacements 41694 # number of replacements 1229system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use |
| 1226system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1230system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1227system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. | 1231system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. |
| 1228system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1232system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1229system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. 1230system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor 1231system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy 1232system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy | 1233system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit. 1234system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor 1235system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy 1236system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy |
| 1233system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1234system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1235system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1237system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1238system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1239system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1236system.iocache.tags.tag_accesses 375552 # Number of tag accesses 1237system.iocache.tags.data_accesses 375552 # Number of data accesses 1238system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 1239system.iocache.ReadReq_misses::total 176 # number of ReadReq misses | 1240system.iocache.tags.tag_accesses 375534 # Number of tag accesses 1241system.iocache.tags.data_accesses 375534 # Number of data accesses 1242system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 1243system.iocache.ReadReq_misses::total 174 # number of ReadReq misses |
| 1240system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 1241system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses | 1244system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 1245system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses |
| 1242system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses 1243system.iocache.demand_misses::total 176 # number of demand (read+write) misses 1244system.iocache.overall_misses::tsunami.ide 176 # number of overall misses 1245system.iocache.overall_misses::total 176 # number of overall misses 1246system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles 1247system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles 1248system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles 1249system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles 1250system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles 1251system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles 1252system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles 1253system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles 1254system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 1255system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) | 1246system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses 1247system.iocache.demand_misses::total 174 # number of demand (read+write) misses 1248system.iocache.overall_misses::tsunami.ide 174 # number of overall misses 1249system.iocache.overall_misses::total 174 # number of overall misses 1250system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles 1251system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles 1252system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles 1253system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles 1254system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles 1255system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles 1256system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles 1257system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles 1258system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 1259system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) |
| 1256system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1257system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) | 1260system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1261system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) |
| 1258system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses 1259system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses 1260system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses 1261system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses | 1262system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses 1263system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses 1264system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses 1265system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses |
| 1262system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1263system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1264system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1265system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1266system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1267system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1268system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1269system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1266system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1267system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1268system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1269system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1270system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1271system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1272system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1273system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1270system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency 1271system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency 1272system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency 1273system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency 1274system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency 1275system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency 1276system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency 1277system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency 1278system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked | 1274system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency 1275system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency 1276system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency 1277system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency 1278system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency 1279system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency 1280system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency 1281system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency 1282system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked |
| 1279system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1283system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1280system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked | 1284system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked |
| 1281system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1285system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1282system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked | 1286system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked |
| 1283system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1284system.iocache.fast_writes 0 # number of fast writes performed 1285system.iocache.cache_copies 0 # number of cache copies performed 1286system.iocache.writebacks::writebacks 41520 # number of writebacks 1287system.iocache.writebacks::total 41520 # number of writebacks | 1287system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1288system.iocache.fast_writes 0 # number of fast writes performed 1289system.iocache.cache_copies 0 # number of cache copies performed 1290system.iocache.writebacks::writebacks 41520 # number of writebacks 1291system.iocache.writebacks::total 41520 # number of writebacks |
| 1288system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 1289system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses | 1292system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 1293system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses |
| 1290system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1291system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses | 1294system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1295system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses |
| 1292system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses 1293system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses 1294system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses 1295system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses 1296system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles 1297system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles 1298system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles 1299system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles 1300system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles 1301system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles 1302system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles 1303system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles | 1296system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses 1297system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 1298system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses 1299system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses 1300system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles 1301system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles 1302system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles 1303system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles 1304system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles 1305system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles 1306system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles 1307system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles |
| 1304system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1305system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1306system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1307system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1308system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1309system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1310system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1311system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1308system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1309system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1310system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1311system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1312system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1313system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1314system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1315system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1312system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency 1313system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency 1314system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276130.244056 # average WriteInvalidateReq mshr miss latency 1315system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276130.244056 # average WriteInvalidateReq mshr miss latency 1316system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency 1317system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency 1318system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency 1319system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency | 1316system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency 1317system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency 1318system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency 1319system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency 1320system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency 1321system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency 1322system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency 1323system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency |
| 1320system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1324system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1321system.l2c.tags.replacements 342765 # number of replacements 1322system.l2c.tags.tagsinuse 65220.427494 # Cycle average of tags in use 1323system.l2c.tags.total_refs 2449404 # Total number of references to valid blocks. 1324system.l2c.tags.sampled_refs 407938 # Sample count of references to valid blocks. 1325system.l2c.tags.avg_refs 6.004354 # Average number of references to valid blocks. 1326system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. 1327system.l2c.tags.occ_blocks::writebacks 55273.007246 # Average occupied blocks per requestor 1328system.l2c.tags.occ_blocks::cpu0.inst 4809.132503 # Average occupied blocks per requestor 1329system.l2c.tags.occ_blocks::cpu0.data 4932.058830 # Average occupied blocks per requestor 1330system.l2c.tags.occ_blocks::cpu1.inst 161.965185 # Average occupied blocks per requestor 1331system.l2c.tags.occ_blocks::cpu1.data 44.263730 # Average occupied blocks per requestor 1332system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy 1333system.l2c.tags.occ_percent::cpu0.inst 0.073382 # Average percentage of cache occupancy 1334system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy 1335system.l2c.tags.occ_percent::cpu1.inst 0.002471 # Average percentage of cache occupancy 1336system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy 1337system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy 1338system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id 1339system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 1340system.l2c.tags.age_task_id_blocks_1024::1 767 # Occupied blocks per task id 1341system.l2c.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id 1342system.l2c.tags.age_task_id_blocks_1024::3 7222 # Occupied blocks per task id 1343system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id 1344system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id 1345system.l2c.tags.tag_accesses 25999302 # Number of tag accesses 1346system.l2c.tags.data_accesses 25999302 # Number of data accesses 1347system.l2c.ReadReq_hits::cpu0.inst 687538 # number of ReadReq hits 1348system.l2c.ReadReq_hits::cpu0.data 668153 # number of ReadReq hits 1349system.l2c.ReadReq_hits::cpu1.inst 318040 # number of ReadReq hits 1350system.l2c.ReadReq_hits::cpu1.data 105234 # number of ReadReq hits 1351system.l2c.ReadReq_hits::total 1778965 # number of ReadReq hits 1352system.l2c.Writeback_hits::writebacks 793856 # number of Writeback hits 1353system.l2c.Writeback_hits::total 793856 # number of Writeback hits 1354system.l2c.UpgradeReq_hits::cpu0.data 179 # number of UpgradeReq hits 1355system.l2c.UpgradeReq_hits::cpu1.data 542 # number of UpgradeReq hits 1356system.l2c.UpgradeReq_hits::total 721 # number of UpgradeReq hits 1357system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits 1358system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 1359system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits 1360system.l2c.ReadExReq_hits::cpu0.data 129887 # number of ReadExReq hits 1361system.l2c.ReadExReq_hits::cpu1.data 42518 # number of ReadExReq hits 1362system.l2c.ReadExReq_hits::total 172405 # number of ReadExReq hits 1363system.l2c.demand_hits::cpu0.inst 687538 # number of demand (read+write) hits 1364system.l2c.demand_hits::cpu0.data 798040 # number of demand (read+write) hits 1365system.l2c.demand_hits::cpu1.inst 318040 # number of demand (read+write) hits 1366system.l2c.demand_hits::cpu1.data 147752 # number of demand (read+write) hits 1367system.l2c.demand_hits::total 1951370 # number of demand (read+write) hits 1368system.l2c.overall_hits::cpu0.inst 687538 # number of overall hits 1369system.l2c.overall_hits::cpu0.data 798040 # number of overall hits 1370system.l2c.overall_hits::cpu1.inst 318040 # number of overall hits 1371system.l2c.overall_hits::cpu1.data 147752 # number of overall hits 1372system.l2c.overall_hits::total 1951370 # number of overall hits 1373system.l2c.ReadReq_misses::cpu0.inst 12866 # number of ReadReq misses 1374system.l2c.ReadReq_misses::cpu0.data 271551 # number of ReadReq misses 1375system.l2c.ReadReq_misses::cpu1.inst 659 # number of ReadReq misses 1376system.l2c.ReadReq_misses::cpu1.data 293 # number of ReadReq misses 1377system.l2c.ReadReq_misses::total 285369 # number of ReadReq misses 1378system.l2c.UpgradeReq_misses::cpu0.data 2958 # number of UpgradeReq misses 1379system.l2c.UpgradeReq_misses::cpu1.data 1782 # number of UpgradeReq misses 1380system.l2c.UpgradeReq_misses::total 4740 # number of UpgradeReq misses 1381system.l2c.SCUpgradeReq_misses::cpu0.data 895 # number of SCUpgradeReq misses 1382system.l2c.SCUpgradeReq_misses::cpu1.data 917 # number of SCUpgradeReq misses 1383system.l2c.SCUpgradeReq_misses::total 1812 # number of SCUpgradeReq misses 1384system.l2c.ReadExReq_misses::cpu0.data 117982 # number of ReadExReq misses 1385system.l2c.ReadExReq_misses::cpu1.data 5781 # number of ReadExReq misses 1386system.l2c.ReadExReq_misses::total 123763 # number of ReadExReq misses 1387system.l2c.demand_misses::cpu0.inst 12866 # number of demand (read+write) misses 1388system.l2c.demand_misses::cpu0.data 389533 # number of demand (read+write) misses 1389system.l2c.demand_misses::cpu1.inst 659 # number of demand (read+write) misses 1390system.l2c.demand_misses::cpu1.data 6074 # number of demand (read+write) misses 1391system.l2c.demand_misses::total 409132 # number of demand (read+write) misses 1392system.l2c.overall_misses::cpu0.inst 12866 # number of overall misses 1393system.l2c.overall_misses::cpu0.data 389533 # number of overall misses 1394system.l2c.overall_misses::cpu1.inst 659 # number of overall misses 1395system.l2c.overall_misses::cpu1.data 6074 # number of overall misses 1396system.l2c.overall_misses::total 409132 # number of overall misses 1397system.l2c.ReadReq_miss_latency::cpu0.inst 942533250 # number of ReadReq miss cycles 1398system.l2c.ReadReq_miss_latency::cpu0.data 17665276500 # number of ReadReq miss cycles 1399system.l2c.ReadReq_miss_latency::cpu1.inst 47722250 # number of ReadReq miss cycles 1400system.l2c.ReadReq_miss_latency::cpu1.data 21179000 # number of ReadReq miss cycles 1401system.l2c.ReadReq_miss_latency::total 18676711000 # number of ReadReq miss cycles 1402system.l2c.UpgradeReq_miss_latency::cpu0.data 1101962 # number of UpgradeReq miss cycles 1403system.l2c.UpgradeReq_miss_latency::cpu1.data 10166561 # number of UpgradeReq miss cycles 1404system.l2c.UpgradeReq_miss_latency::total 11268523 # number of UpgradeReq miss cycles 1405system.l2c.SCUpgradeReq_miss_latency::cpu0.data 873463 # number of SCUpgradeReq miss cycles 1406system.l2c.SCUpgradeReq_miss_latency::cpu1.data 278988 # number of SCUpgradeReq miss cycles 1407system.l2c.SCUpgradeReq_miss_latency::total 1152451 # number of SCUpgradeReq miss cycles 1408system.l2c.ReadExReq_miss_latency::cpu0.data 8137748269 # number of ReadExReq miss cycles 1409system.l2c.ReadExReq_miss_latency::cpu1.data 426449979 # number of ReadExReq miss cycles 1410system.l2c.ReadExReq_miss_latency::total 8564198248 # number of ReadExReq miss cycles 1411system.l2c.demand_miss_latency::cpu0.inst 942533250 # number of demand (read+write) miss cycles 1412system.l2c.demand_miss_latency::cpu0.data 25803024769 # number of demand (read+write) miss cycles 1413system.l2c.demand_miss_latency::cpu1.inst 47722250 # number of demand (read+write) miss cycles 1414system.l2c.demand_miss_latency::cpu1.data 447628979 # number of demand (read+write) miss cycles 1415system.l2c.demand_miss_latency::total 27240909248 # number of demand (read+write) miss cycles 1416system.l2c.overall_miss_latency::cpu0.inst 942533250 # number of overall miss cycles 1417system.l2c.overall_miss_latency::cpu0.data 25803024769 # number of overall miss cycles 1418system.l2c.overall_miss_latency::cpu1.inst 47722250 # number of overall miss cycles 1419system.l2c.overall_miss_latency::cpu1.data 447628979 # number of overall miss cycles 1420system.l2c.overall_miss_latency::total 27240909248 # number of overall miss cycles 1421system.l2c.ReadReq_accesses::cpu0.inst 700404 # number of ReadReq accesses(hits+misses) 1422system.l2c.ReadReq_accesses::cpu0.data 939704 # number of ReadReq accesses(hits+misses) 1423system.l2c.ReadReq_accesses::cpu1.inst 318699 # number of ReadReq accesses(hits+misses) 1424system.l2c.ReadReq_accesses::cpu1.data 105527 # number of ReadReq accesses(hits+misses) 1425system.l2c.ReadReq_accesses::total 2064334 # number of ReadReq accesses(hits+misses) 1426system.l2c.Writeback_accesses::writebacks 793856 # number of Writeback accesses(hits+misses) 1427system.l2c.Writeback_accesses::total 793856 # number of Writeback accesses(hits+misses) 1428system.l2c.UpgradeReq_accesses::cpu0.data 3137 # number of UpgradeReq accesses(hits+misses) 1429system.l2c.UpgradeReq_accesses::cpu1.data 2324 # number of UpgradeReq accesses(hits+misses) 1430system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses) 1431system.l2c.SCUpgradeReq_accesses::cpu0.data 938 # number of SCUpgradeReq accesses(hits+misses) 1432system.l2c.SCUpgradeReq_accesses::cpu1.data 940 # number of SCUpgradeReq accesses(hits+misses) 1433system.l2c.SCUpgradeReq_accesses::total 1878 # number of SCUpgradeReq accesses(hits+misses) 1434system.l2c.ReadExReq_accesses::cpu0.data 247869 # number of ReadExReq accesses(hits+misses) 1435system.l2c.ReadExReq_accesses::cpu1.data 48299 # number of ReadExReq accesses(hits+misses) 1436system.l2c.ReadExReq_accesses::total 296168 # number of ReadExReq accesses(hits+misses) 1437system.l2c.demand_accesses::cpu0.inst 700404 # number of demand (read+write) accesses 1438system.l2c.demand_accesses::cpu0.data 1187573 # number of demand (read+write) accesses 1439system.l2c.demand_accesses::cpu1.inst 318699 # number of demand (read+write) accesses 1440system.l2c.demand_accesses::cpu1.data 153826 # number of demand (read+write) accesses 1441system.l2c.demand_accesses::total 2360502 # number of demand (read+write) accesses 1442system.l2c.overall_accesses::cpu0.inst 700404 # number of overall (read+write) accesses 1443system.l2c.overall_accesses::cpu0.data 1187573 # number of overall (read+write) accesses 1444system.l2c.overall_accesses::cpu1.inst 318699 # number of overall (read+write) accesses 1445system.l2c.overall_accesses::cpu1.data 153826 # number of overall (read+write) accesses 1446system.l2c.overall_accesses::total 2360502 # number of overall (read+write) accesses 1447system.l2c.ReadReq_miss_rate::cpu0.inst 0.018369 # miss rate for ReadReq accesses 1448system.l2c.ReadReq_miss_rate::cpu0.data 0.288975 # miss rate for ReadReq accesses 1449system.l2c.ReadReq_miss_rate::cpu1.inst 0.002068 # miss rate for ReadReq accesses 1450system.l2c.ReadReq_miss_rate::cpu1.data 0.002777 # miss rate for ReadReq accesses 1451system.l2c.ReadReq_miss_rate::total 0.138238 # miss rate for ReadReq accesses 1452system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942939 # miss rate for UpgradeReq accesses 1453system.l2c.UpgradeReq_miss_rate::cpu1.data 0.766781 # miss rate for UpgradeReq accesses 1454system.l2c.UpgradeReq_miss_rate::total 0.867973 # miss rate for UpgradeReq accesses 1455system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.954158 # miss rate for SCUpgradeReq accesses 1456system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975532 # miss rate for SCUpgradeReq accesses 1457system.l2c.SCUpgradeReq_miss_rate::total 0.964856 # miss rate for SCUpgradeReq accesses 1458system.l2c.ReadExReq_miss_rate::cpu0.data 0.475985 # miss rate for ReadExReq accesses 1459system.l2c.ReadExReq_miss_rate::cpu1.data 0.119692 # miss rate for ReadExReq accesses 1460system.l2c.ReadExReq_miss_rate::total 0.417881 # miss rate for ReadExReq accesses 1461system.l2c.demand_miss_rate::cpu0.inst 0.018369 # miss rate for demand accesses 1462system.l2c.demand_miss_rate::cpu0.data 0.328008 # miss rate for demand accesses 1463system.l2c.demand_miss_rate::cpu1.inst 0.002068 # miss rate for demand accesses 1464system.l2c.demand_miss_rate::cpu1.data 0.039486 # miss rate for demand accesses 1465system.l2c.demand_miss_rate::total 0.173324 # miss rate for demand accesses 1466system.l2c.overall_miss_rate::cpu0.inst 0.018369 # miss rate for overall accesses 1467system.l2c.overall_miss_rate::cpu0.data 0.328008 # miss rate for overall accesses 1468system.l2c.overall_miss_rate::cpu1.inst 0.002068 # miss rate for overall accesses 1469system.l2c.overall_miss_rate::cpu1.data 0.039486 # miss rate for overall accesses 1470system.l2c.overall_miss_rate::total 0.173324 # miss rate for overall accesses 1471system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73257.675268 # average ReadReq miss latency 1472system.l2c.ReadReq_avg_miss_latency::cpu0.data 65053.255190 # average ReadReq miss latency 1473system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72416.160850 # average ReadReq miss latency 1474system.l2c.ReadReq_avg_miss_latency::cpu1.data 72283.276451 # average ReadReq miss latency 1475system.l2c.ReadReq_avg_miss_latency::total 65447.581903 # average ReadReq miss latency 1476system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 372.536173 # average UpgradeReq miss latency 1477system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5705.140853 # average UpgradeReq miss latency 1478system.l2c.UpgradeReq_avg_miss_latency::total 2377.325527 # average UpgradeReq miss latency 1479system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 975.936313 # average SCUpgradeReq miss latency 1480system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 304.239913 # average SCUpgradeReq miss latency 1481system.l2c.SCUpgradeReq_avg_miss_latency::total 636.010486 # average SCUpgradeReq miss latency 1482system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68974.489914 # average ReadExReq miss latency 1483system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73767.510638 # average ReadExReq miss latency 1484system.l2c.ReadExReq_avg_miss_latency::total 69198.373084 # average ReadExReq miss latency 1485system.l2c.demand_avg_miss_latency::cpu0.inst 73257.675268 # average overall miss latency 1486system.l2c.demand_avg_miss_latency::cpu0.data 66240.921229 # average overall miss latency 1487system.l2c.demand_avg_miss_latency::cpu1.inst 72416.160850 # average overall miss latency 1488system.l2c.demand_avg_miss_latency::cpu1.data 73695.913566 # average overall miss latency 1489system.l2c.demand_avg_miss_latency::total 66582.201461 # average overall miss latency 1490system.l2c.overall_avg_miss_latency::cpu0.inst 73257.675268 # average overall miss latency 1491system.l2c.overall_avg_miss_latency::cpu0.data 66240.921229 # average overall miss latency 1492system.l2c.overall_avg_miss_latency::cpu1.inst 72416.160850 # average overall miss latency 1493system.l2c.overall_avg_miss_latency::cpu1.data 73695.913566 # average overall miss latency 1494system.l2c.overall_avg_miss_latency::total 66582.201461 # average overall miss latency | 1325system.l2c.tags.replacements 341367 # number of replacements 1326system.l2c.tags.tagsinuse 65207.739778 # Cycle average of tags in use 1327system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks. 1328system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks. 1329system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks. 1330system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit. 1331system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor 1332system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor 1333system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor 1334system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor 1335system.l2c.tags.occ_blocks::cpu1.data 38.745274 # Average occupied blocks per requestor 1336system.l2c.tags.occ_percent::writebacks 0.842038 # Average percentage of cache occupancy 1337system.l2c.tags.occ_percent::cpu0.inst 0.074069 # Average percentage of cache occupancy 1338system.l2c.tags.occ_percent::cpu0.data 0.076558 # Average percentage of cache occupancy 1339system.l2c.tags.occ_percent::cpu1.inst 0.001735 # Average percentage of cache occupancy 1340system.l2c.tags.occ_percent::cpu1.data 0.000591 # Average percentage of cache occupancy 1341system.l2c.tags.occ_percent::total 0.994991 # Average percentage of cache occupancy 1342system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id 1343system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id 1344system.l2c.tags.age_task_id_blocks_1024::1 1104 # Occupied blocks per task id 1345system.l2c.tags.age_task_id_blocks_1024::2 5014 # Occupied blocks per task id 1346system.l2c.tags.age_task_id_blocks_1024::3 6093 # Occupied blocks per task id 1347system.l2c.tags.age_task_id_blocks_1024::4 52607 # Occupied blocks per task id 1348system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id 1349system.l2c.tags.tag_accesses 25960355 # Number of tag accesses 1350system.l2c.tags.data_accesses 25960355 # Number of data accesses 1351system.l2c.ReadReq_hits::cpu0.inst 686297 # number of ReadReq hits 1352system.l2c.ReadReq_hits::cpu0.data 664438 # number of ReadReq hits 1353system.l2c.ReadReq_hits::cpu1.inst 315744 # number of ReadReq hits 1354system.l2c.ReadReq_hits::cpu1.data 108706 # number of ReadReq hits 1355system.l2c.ReadReq_hits::total 1775185 # number of ReadReq hits 1356system.l2c.Writeback_hits::writebacks 793248 # number of Writeback hits 1357system.l2c.Writeback_hits::total 793248 # number of Writeback hits 1358system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits 1359system.l2c.UpgradeReq_hits::cpu1.data 524 # number of UpgradeReq hits 1360system.l2c.UpgradeReq_hits::total 707 # number of UpgradeReq hits 1361system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits 1362system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 1363system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits 1364system.l2c.ReadExReq_hits::cpu0.data 126541 # number of ReadExReq hits 1365system.l2c.ReadExReq_hits::cpu1.data 47234 # number of ReadExReq hits 1366system.l2c.ReadExReq_hits::total 173775 # number of ReadExReq hits 1367system.l2c.demand_hits::cpu0.inst 686297 # number of demand (read+write) hits 1368system.l2c.demand_hits::cpu0.data 790979 # number of demand (read+write) hits 1369system.l2c.demand_hits::cpu1.inst 315744 # number of demand (read+write) hits 1370system.l2c.demand_hits::cpu1.data 155940 # number of demand (read+write) hits 1371system.l2c.demand_hits::total 1948960 # number of demand (read+write) hits 1372system.l2c.overall_hits::cpu0.inst 686297 # number of overall hits 1373system.l2c.overall_hits::cpu0.data 790979 # number of overall hits 1374system.l2c.overall_hits::cpu1.inst 315744 # number of overall hits 1375system.l2c.overall_hits::cpu1.data 155940 # number of overall hits 1376system.l2c.overall_hits::total 1948960 # number of overall hits 1377system.l2c.ReadReq_misses::cpu0.inst 13070 # number of ReadReq misses 1378system.l2c.ReadReq_misses::cpu0.data 271636 # number of ReadReq misses 1379system.l2c.ReadReq_misses::cpu1.inst 457 # number of ReadReq misses 1380system.l2c.ReadReq_misses::cpu1.data 234 # number of ReadReq misses 1381system.l2c.ReadReq_misses::total 285397 # number of ReadReq misses 1382system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses 1383system.l2c.UpgradeReq_misses::cpu1.data 1736 # number of UpgradeReq misses 1384system.l2c.UpgradeReq_misses::total 4685 # number of UpgradeReq misses 1385system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses 1386system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses 1387system.l2c.SCUpgradeReq_misses::total 1789 # number of SCUpgradeReq misses 1388system.l2c.ReadExReq_misses::cpu0.data 115627 # number of ReadExReq misses 1389system.l2c.ReadExReq_misses::cpu1.data 6589 # number of ReadExReq misses 1390system.l2c.ReadExReq_misses::total 122216 # number of ReadExReq misses 1391system.l2c.demand_misses::cpu0.inst 13070 # number of demand (read+write) misses 1392system.l2c.demand_misses::cpu0.data 387263 # number of demand (read+write) misses 1393system.l2c.demand_misses::cpu1.inst 457 # number of demand (read+write) misses 1394system.l2c.demand_misses::cpu1.data 6823 # number of demand (read+write) misses 1395system.l2c.demand_misses::total 407613 # number of demand (read+write) misses 1396system.l2c.overall_misses::cpu0.inst 13070 # number of overall misses 1397system.l2c.overall_misses::cpu0.data 387263 # number of overall misses 1398system.l2c.overall_misses::cpu1.inst 457 # number of overall misses 1399system.l2c.overall_misses::cpu1.data 6823 # number of overall misses 1400system.l2c.overall_misses::total 407613 # number of overall misses 1401system.l2c.ReadReq_miss_latency::cpu0.inst 1052716500 # number of ReadReq miss cycles 1402system.l2c.ReadReq_miss_latency::cpu0.data 19700886500 # number of ReadReq miss cycles 1403system.l2c.ReadReq_miss_latency::cpu1.inst 37366250 # number of ReadReq miss cycles 1404system.l2c.ReadReq_miss_latency::cpu1.data 18492250 # number of ReadReq miss cycles 1405system.l2c.ReadReq_miss_latency::total 20809461500 # number of ReadReq miss cycles 1406system.l2c.UpgradeReq_miss_latency::cpu0.data 1635455 # number of UpgradeReq miss cycles 1407system.l2c.UpgradeReq_miss_latency::cpu1.data 13268077 # number of UpgradeReq miss cycles 1408system.l2c.UpgradeReq_miss_latency::total 14903532 # number of UpgradeReq miss cycles 1409system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1334957 # number of SCUpgradeReq miss cycles 1410system.l2c.SCUpgradeReq_miss_latency::cpu1.data 185994 # number of SCUpgradeReq miss cycles 1411system.l2c.SCUpgradeReq_miss_latency::total 1520951 # number of SCUpgradeReq miss cycles 1412system.l2c.ReadExReq_miss_latency::cpu0.data 8793297261 # number of ReadExReq miss cycles 1413system.l2c.ReadExReq_miss_latency::cpu1.data 540094736 # number of ReadExReq miss cycles 1414system.l2c.ReadExReq_miss_latency::total 9333391997 # number of ReadExReq miss cycles 1415system.l2c.demand_miss_latency::cpu0.inst 1052716500 # number of demand (read+write) miss cycles 1416system.l2c.demand_miss_latency::cpu0.data 28494183761 # number of demand (read+write) miss cycles 1417system.l2c.demand_miss_latency::cpu1.inst 37366250 # number of demand (read+write) miss cycles 1418system.l2c.demand_miss_latency::cpu1.data 558586986 # number of demand (read+write) miss cycles 1419system.l2c.demand_miss_latency::total 30142853497 # number of demand (read+write) miss cycles 1420system.l2c.overall_miss_latency::cpu0.inst 1052716500 # number of overall miss cycles 1421system.l2c.overall_miss_latency::cpu0.data 28494183761 # number of overall miss cycles 1422system.l2c.overall_miss_latency::cpu1.inst 37366250 # number of overall miss cycles 1423system.l2c.overall_miss_latency::cpu1.data 558586986 # number of overall miss cycles 1424system.l2c.overall_miss_latency::total 30142853497 # number of overall miss cycles 1425system.l2c.ReadReq_accesses::cpu0.inst 699367 # number of ReadReq accesses(hits+misses) 1426system.l2c.ReadReq_accesses::cpu0.data 936074 # number of ReadReq accesses(hits+misses) 1427system.l2c.ReadReq_accesses::cpu1.inst 316201 # number of ReadReq accesses(hits+misses) 1428system.l2c.ReadReq_accesses::cpu1.data 108940 # number of ReadReq accesses(hits+misses) 1429system.l2c.ReadReq_accesses::total 2060582 # number of ReadReq accesses(hits+misses) 1430system.l2c.Writeback_accesses::writebacks 793248 # number of Writeback accesses(hits+misses) 1431system.l2c.Writeback_accesses::total 793248 # number of Writeback accesses(hits+misses) 1432system.l2c.UpgradeReq_accesses::cpu0.data 3132 # number of UpgradeReq accesses(hits+misses) 1433system.l2c.UpgradeReq_accesses::cpu1.data 2260 # number of UpgradeReq accesses(hits+misses) 1434system.l2c.UpgradeReq_accesses::total 5392 # number of UpgradeReq accesses(hits+misses) 1435system.l2c.SCUpgradeReq_accesses::cpu0.data 928 # number of SCUpgradeReq accesses(hits+misses) 1436system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses) 1437system.l2c.SCUpgradeReq_accesses::total 1849 # number of SCUpgradeReq accesses(hits+misses) 1438system.l2c.ReadExReq_accesses::cpu0.data 242168 # number of ReadExReq accesses(hits+misses) 1439system.l2c.ReadExReq_accesses::cpu1.data 53823 # number of ReadExReq accesses(hits+misses) 1440system.l2c.ReadExReq_accesses::total 295991 # number of ReadExReq accesses(hits+misses) 1441system.l2c.demand_accesses::cpu0.inst 699367 # number of demand (read+write) accesses 1442system.l2c.demand_accesses::cpu0.data 1178242 # number of demand (read+write) accesses 1443system.l2c.demand_accesses::cpu1.inst 316201 # number of demand (read+write) accesses 1444system.l2c.demand_accesses::cpu1.data 162763 # number of demand (read+write) accesses 1445system.l2c.demand_accesses::total 2356573 # number of demand (read+write) accesses 1446system.l2c.overall_accesses::cpu0.inst 699367 # number of overall (read+write) accesses 1447system.l2c.overall_accesses::cpu0.data 1178242 # number of overall (read+write) accesses 1448system.l2c.overall_accesses::cpu1.inst 316201 # number of overall (read+write) accesses 1449system.l2c.overall_accesses::cpu1.data 162763 # number of overall (read+write) accesses 1450system.l2c.overall_accesses::total 2356573 # number of overall (read+write) accesses 1451system.l2c.ReadReq_miss_rate::cpu0.inst 0.018688 # miss rate for ReadReq accesses 1452system.l2c.ReadReq_miss_rate::cpu0.data 0.290186 # miss rate for ReadReq accesses 1453system.l2c.ReadReq_miss_rate::cpu1.inst 0.001445 # miss rate for ReadReq accesses 1454system.l2c.ReadReq_miss_rate::cpu1.data 0.002148 # miss rate for ReadReq accesses 1455system.l2c.ReadReq_miss_rate::total 0.138503 # miss rate for ReadReq accesses 1456system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941571 # miss rate for UpgradeReq accesses 1457system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768142 # miss rate for UpgradeReq accesses 1458system.l2c.UpgradeReq_miss_rate::total 0.868880 # miss rate for UpgradeReq accesses 1459system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961207 # miss rate for SCUpgradeReq accesses 1460system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses 1461system.l2c.SCUpgradeReq_miss_rate::total 0.967550 # miss rate for SCUpgradeReq accesses 1462system.l2c.ReadExReq_miss_rate::cpu0.data 0.477466 # miss rate for ReadExReq accesses 1463system.l2c.ReadExReq_miss_rate::cpu1.data 0.122420 # miss rate for ReadExReq accesses 1464system.l2c.ReadExReq_miss_rate::total 0.412904 # miss rate for ReadExReq accesses 1465system.l2c.demand_miss_rate::cpu0.inst 0.018688 # miss rate for demand accesses 1466system.l2c.demand_miss_rate::cpu0.data 0.328679 # miss rate for demand accesses 1467system.l2c.demand_miss_rate::cpu1.inst 0.001445 # miss rate for demand accesses 1468system.l2c.demand_miss_rate::cpu1.data 0.041920 # miss rate for demand accesses 1469system.l2c.demand_miss_rate::total 0.172969 # miss rate for demand accesses 1470system.l2c.overall_miss_rate::cpu0.inst 0.018688 # miss rate for overall accesses 1471system.l2c.overall_miss_rate::cpu0.data 0.328679 # miss rate for overall accesses 1472system.l2c.overall_miss_rate::cpu1.inst 0.001445 # miss rate for overall accesses 1473system.l2c.overall_miss_rate::cpu1.data 0.041920 # miss rate for overall accesses 1474system.l2c.overall_miss_rate::total 0.172969 # miss rate for overall accesses 1475system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80544.491201 # average ReadReq miss latency 1476system.l2c.ReadReq_avg_miss_latency::cpu0.data 72526.787686 # average ReadReq miss latency 1477system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81764.223195 # average ReadReq miss latency 1478system.l2c.ReadReq_avg_miss_latency::cpu1.data 79026.709402 # average ReadReq miss latency 1479system.l2c.ReadReq_avg_miss_latency::total 72914.086343 # average ReadReq miss latency 1480system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 554.579518 # average UpgradeReq miss latency 1481system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7642.901498 # average UpgradeReq miss latency 1482system.l2c.UpgradeReq_avg_miss_latency::total 3181.116756 # average UpgradeReq miss latency 1483system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1496.588565 # average SCUpgradeReq miss latency 1484system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 207.351171 # average SCUpgradeReq miss latency 1485system.l2c.SCUpgradeReq_avg_miss_latency::total 850.168250 # average SCUpgradeReq miss latency 1486system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.823034 # average ReadExReq miss latency 1487system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81969.151009 # average ReadExReq miss latency 1488system.l2c.ReadExReq_avg_miss_latency::total 76368.004165 # average ReadExReq miss latency 1489system.l2c.demand_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency 1490system.l2c.demand_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency 1491system.l2c.demand_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency 1492system.l2c.demand_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency 1493system.l2c.demand_avg_miss_latency::total 73949.686337 # average overall miss latency 1494system.l2c.overall_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency 1495system.l2c.overall_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency 1496system.l2c.overall_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency 1497system.l2c.overall_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency 1498system.l2c.overall_avg_miss_latency::total 73949.686337 # average overall miss latency |
| 1495system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1496system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1497system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1498system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1499system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1500system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1501system.l2c.fast_writes 0 # number of fast writes performed 1502system.l2c.cache_copies 0 # number of cache copies performed | 1499system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1500system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1501system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1502system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1503system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1504system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1505system.l2c.fast_writes 0 # number of fast writes performed 1506system.l2c.cache_copies 0 # number of cache copies performed |
| 1503system.l2c.writebacks::writebacks 79715 # number of writebacks 1504system.l2c.writebacks::total 79715 # number of writebacks | 1507system.l2c.writebacks::writebacks 78830 # number of writebacks 1508system.l2c.writebacks::total 78830 # number of writebacks |
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| 1514system.l2c.ReadReq_mshr_misses::cpu0.inst 12863 # number of ReadReq MSHR misses 1515system.l2c.ReadReq_mshr_misses::cpu0.data 271551 # number of ReadReq MSHR misses 1516system.l2c.ReadReq_mshr_misses::cpu1.inst 651 # number of ReadReq MSHR misses 1517system.l2c.ReadReq_mshr_misses::cpu1.data 293 # number of ReadReq MSHR misses 1518system.l2c.ReadReq_mshr_misses::total 285358 # number of ReadReq MSHR misses 1519system.l2c.UpgradeReq_mshr_misses::cpu0.data 2958 # number of UpgradeReq MSHR misses 1520system.l2c.UpgradeReq_mshr_misses::cpu1.data 1782 # number of UpgradeReq MSHR misses 1521system.l2c.UpgradeReq_mshr_misses::total 4740 # number of UpgradeReq MSHR misses 1522system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 895 # number of SCUpgradeReq MSHR misses 1523system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 917 # number of SCUpgradeReq MSHR misses 1524system.l2c.SCUpgradeReq_mshr_misses::total 1812 # number of SCUpgradeReq MSHR misses 1525system.l2c.ReadExReq_mshr_misses::cpu0.data 117982 # number of ReadExReq MSHR misses 1526system.l2c.ReadExReq_mshr_misses::cpu1.data 5781 # number of ReadExReq MSHR misses 1527system.l2c.ReadExReq_mshr_misses::total 123763 # number of ReadExReq MSHR misses 1528system.l2c.demand_mshr_misses::cpu0.inst 12863 # number of demand (read+write) MSHR misses 1529system.l2c.demand_mshr_misses::cpu0.data 389533 # number of demand (read+write) MSHR misses 1530system.l2c.demand_mshr_misses::cpu1.inst 651 # number of demand (read+write) MSHR misses 1531system.l2c.demand_mshr_misses::cpu1.data 6074 # number of demand (read+write) MSHR misses 1532system.l2c.demand_mshr_misses::total 409121 # number of demand (read+write) MSHR misses 1533system.l2c.overall_mshr_misses::cpu0.inst 12863 # number of overall MSHR misses 1534system.l2c.overall_mshr_misses::cpu0.data 389533 # number of overall MSHR misses 1535system.l2c.overall_mshr_misses::cpu1.inst 651 # number of overall MSHR misses 1536system.l2c.overall_mshr_misses::cpu1.data 6074 # number of overall MSHR misses 1537system.l2c.overall_mshr_misses::total 409121 # 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number of ReadReq MSHR misses 1519system.l2c.ReadReq_mshr_misses::cpu0.data 271636 # number of ReadReq MSHR misses 1520system.l2c.ReadReq_mshr_misses::cpu1.inst 449 # number of ReadReq MSHR misses 1521system.l2c.ReadReq_mshr_misses::cpu1.data 234 # number of ReadReq MSHR misses 1522system.l2c.ReadReq_mshr_misses::total 285386 # number of ReadReq MSHR misses 1523system.l2c.UpgradeReq_mshr_misses::cpu0.data 2949 # number of UpgradeReq MSHR misses 1524system.l2c.UpgradeReq_mshr_misses::cpu1.data 1736 # number of UpgradeReq MSHR misses 1525system.l2c.UpgradeReq_mshr_misses::total 4685 # number of UpgradeReq MSHR misses 1526system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 892 # number of SCUpgradeReq MSHR misses 1527system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses 1528system.l2c.SCUpgradeReq_mshr_misses::total 1789 # number of SCUpgradeReq MSHR misses 1529system.l2c.ReadExReq_mshr_misses::cpu0.data 115627 # number of ReadExReq MSHR misses 1530system.l2c.ReadExReq_mshr_misses::cpu1.data 6589 # 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number of overall MSHR miss cycles 1563system.l2c.overall_mshr_miss_latency::cpu1.inst 31138500 # number of overall MSHR miss cycles 1564system.l2c.overall_mshr_miss_latency::cpu1.data 473285514 # number of overall MSHR miss cycles 1565system.l2c.overall_mshr_miss_latency::total 25045400003 # number of overall MSHR miss cycles 1566system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1374876000 # number of ReadReq MSHR uncacheable cycles 1567system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17618000 # number of ReadReq MSHR uncacheable cycles 1568system.l2c.ReadReq_mshr_uncacheable_latency::total 1392494000 # number of ReadReq MSHR uncacheable cycles 1569system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153053500 # number of WriteReq MSHR uncacheable cycles 1570system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674538500 # number of WriteReq MSHR uncacheable cycles 1571system.l2c.WriteReq_mshr_uncacheable_latency::total 2827592000 # number of WriteReq MSHR uncacheable cycles 1572system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527929500 # number of overall MSHR uncacheable cycles 1573system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156500 # number of overall MSHR uncacheable cycles 1574system.l2c.overall_mshr_uncacheable_latency::total 4220086000 # number of overall MSHR uncacheable cycles 1575system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for ReadReq accesses 1576system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290186 # mshr miss rate for ReadReq accesses 1577system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for ReadReq accesses 1578system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002148 # mshr miss rate for ReadReq accesses 1579system.l2c.ReadReq_mshr_miss_rate::total 0.138498 # mshr miss rate for ReadReq accesses 1580system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941571 # mshr miss rate for UpgradeReq accesses 1581system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses 1582system.l2c.UpgradeReq_mshr_miss_rate::total 0.868880 # mshr miss rate for UpgradeReq accesses 1583system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961207 # mshr miss rate for SCUpgradeReq accesses 1584system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses 1585system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967550 # mshr miss rate for SCUpgradeReq accesses 1586system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477466 # mshr miss rate for ReadExReq accesses 1587system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122420 # mshr miss rate for ReadExReq accesses 1588system.l2c.ReadExReq_mshr_miss_rate::total 0.412904 # mshr miss rate for ReadExReq accesses 1589system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for demand accesses 1590system.l2c.demand_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for demand accesses 1591system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for demand accesses 1592system.l2c.demand_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for demand accesses 1593system.l2c.demand_mshr_miss_rate::total 0.172964 # mshr miss rate for demand accesses 1594system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for overall accesses 1595system.l2c.overall_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for overall accesses 1596system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for overall accesses 1597system.l2c.overall_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for overall accesses 1598system.l2c.overall_mshr_miss_rate::total 0.172964 # mshr miss rate for overall accesses 1599system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average ReadReq mshr miss latency 1600system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251 # average ReadReq mshr miss latency 1601system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average ReadReq mshr miss latency 1602system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128 # average ReadReq mshr miss latency 1603system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811 # average ReadReq mshr miss latency 1604system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875 # average UpgradeReq mshr miss latency 1605system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency 1606system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency 1607system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency 1608system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency 1609system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency 1610system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency 1611system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency 1612system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency 1613system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency 1614system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency 1615system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency 1616system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency 1617system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency 1618system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency 1619system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency 1620system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency 1621system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency 1622system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency |
| 1619system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1620system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1621system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1622system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1623system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1624system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1625system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1626system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1627system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1628system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 1623system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1624system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1625system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1626system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1627system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1628system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1629system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1630system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1631system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1632system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1629system.membus.trans_dist::ReadReq 292731 # Transaction distribution 1630system.membus.trans_dist::ReadResp 292731 # Transaction distribution 1631system.membus.trans_dist::WriteReq 14079 # Transaction distribution 1632system.membus.trans_dist::WriteResp 14079 # Transaction distribution 1633system.membus.trans_dist::Writeback 121235 # Transaction distribution | 1633system.membus.trans_dist::ReadReq 292759 # Transaction distribution 1634system.membus.trans_dist::ReadResp 292759 # Transaction distribution 1635system.membus.trans_dist::WriteReq 14052 # Transaction distribution 1636system.membus.trans_dist::WriteResp 14052 # Transaction distribution 1637system.membus.trans_dist::Writeback 120350 # Transaction distribution |
| 1634system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1635system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution | 1638system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1639system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution |
| 1636system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution 1637system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution 1638system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution 1639system.membus.trans_dist::ReadExReq 124107 # Transaction distribution 1640system.membus.trans_dist::ReadExResp 123261 # Transaction distribution 1641system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) 1642system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) 1643system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) 1644system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) 1645system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) 1646system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) 1647system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) 1648system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) 1649system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) | 1640system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution 1641system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution 1642system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution 1643system.membus.trans_dist::ReadExReq 122543 # Transaction distribution 1644system.membus.trans_dist::ReadExResp 121713 # Transaction distribution 1645system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes) 1646system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes) 1647system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes) 1648system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes) 1649system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes) 1650system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) 1651system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) 1652system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) 1653system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) |
| 1650system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) 1651system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) | 1654system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) 1655system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) |
| 1652system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) 1653system.membus.snoops 22119 # Total snoops (count) 1654system.membus.snoop_fanout::samples 600328 # Request fanout histogram | 1656system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) 1657system.membus.snoops 21558 # Total snoops (count) 1658system.membus.snoop_fanout::samples 597341 # Request fanout histogram |
| 1655system.membus.snoop_fanout::mean 1 # Request fanout histogram 1656system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1657system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1658system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1659system.membus.snoop_fanout::mean 1 # Request fanout histogram 1660system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1661system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1662system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1659system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram | 1663system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram |
| 1660system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1661system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1662system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1663system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1664system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1665system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1666system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1667system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1664system.membus.snoop_fanout::total 600328 # Request fanout histogram 1665system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) | 1668system.membus.snoop_fanout::total 597341 # Request fanout histogram 1669system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks) |
| 1666system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1670system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1667system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) | 1671system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) |
| 1668system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 1672system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 1669system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) 1670system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1671system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) | 1673system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks) 1674system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1675system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) |
| 1672system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1676system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1673system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution 1674system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution 1675system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution 1676system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution 1677system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution 1678system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1679system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution 1680system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution 1681system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution 1682system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution 1683system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution 1684system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) 1685system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) 1686system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) 1687system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) 1688system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) 1689system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) 1690system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) 1691system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) 1692system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) 1693system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) 1694system.toL2Bus.snoops 99473 # Total snoops (count) 1695system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram 1696system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram 1697system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram | 1677system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution 1678system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution 1679system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution 1680system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution 1681system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution 1682system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution 1683system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution 1684system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution 1685system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution 1686system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution 1687system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution 1688system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes) 1689system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes) 1690system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes) 1691system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) 1692system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) 1693system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) 1694system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) 1695system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) 1696system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) 1697system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) 1698system.toL2Bus.snoops 98552 # Total snoops (count) 1699system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram 1700system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram 1701system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram |
| 1698system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1699system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1700system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1701system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1702system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1703system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1704system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1705system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1702system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram 1703system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram | 1706system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram 1707system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram |
| 1704system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1705system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1706system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1708system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1709system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1710system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1707system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram 1708system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) 1709system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1710system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) | 1711system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram 1712system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) 1713system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1714system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) |
| 1711system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1715system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1712system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) 1713system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1714system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) 1715system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 1716system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) 1717system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) 1718system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) | 1716system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) 1717system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1718system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks) 1719system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1720system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks) 1721system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1722system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks) |
| 1719system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1720system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1721system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1722system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1723system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1724system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1725system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1726system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- | 1723system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1724system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1725system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1726system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1727system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1728system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1729system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1730system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 26 unchanged lines hidden --- |