| stats.txt (10513:ca4438b6e39a) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.961827 # Number of seconds simulated 4sim_ticks 1961826628500 # Number of ticks simulated 5final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.962845 # Number of seconds simulated 4sim_ticks 1962844580000 # Number of ticks simulated 5final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1248737 # Simulator instruction rate (inst/s) 8host_op_rate 1248737 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40231703865 # Simulator tick rate (ticks/s) 10host_mem_usage 312404 # Number of bytes of host memory used 11host_seconds 48.76 # Real time elapsed on the host 12sim_insts 60892387 # Number of instructions simulated 13sim_ops 60892387 # Number of ops (including micro ops) simulated | 7host_inst_rate 1184099 # Simulator instruction rate (inst/s) 8host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38148129943 # Simulator tick rate (ticks/s) 10host_mem_usage 318172 # Number of bytes of host memory used 11host_seconds 51.45 # Real time elapsed on the host 12sim_insts 60925667 # Number of instructions simulated 13sim_ops 60925667 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 336832 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26103680 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 833152 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 31872 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 5078656 # Number of bytes written to this memory 26system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7737984 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 13018 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 389076 # Number of read requests responded to by this memory | 21system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::cpu1.inst 498 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.data 5263 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 407870 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 79354 # Number of write requests responded to by this memory 35system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 120906 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 424682 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 12692693 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) | 39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::cpu1.inst 16246 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.data 171693 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 13305804 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu0.inst 424682 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu1.inst 16246 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 440928 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 2588738 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::tsunami.ide 1355537 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_write::total 3944275 # Write bandwidth from this memory (bytes/s) 49system.physmem.bw_total::writebacks 2588738 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu0.inst 424682 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu0.data 12692693 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 1356026 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 16246 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 171693 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::total 17250079 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.readReqs 407870 # Number of read requests accepted 57system.physmem.writeReqs 120906 # Number of write requests accepted 58system.physmem.readBursts 407870 # Number of DRAM read bursts, including those serviced by the write queue 59system.physmem.writeBursts 120906 # Number of DRAM write bursts, including those merged in the write queue 60system.physmem.bytesReadDRAM 26092032 # Total number of bytes read from DRAM 61system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue 62system.physmem.bytesWritten 7736064 # Total number of bytes written to DRAM 63system.physmem.bytesReadSys 26103680 # Total read bytes from the system interface side 64system.physmem.bytesWrittenSys 7737984 # Total written bytes from the system interface side 65system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue 66system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 67system.physmem.neitherReadNorWriteReqs 6995 # Number of requests that are neither read nor write 68system.physmem.perBankRdBursts::0 25277 # Per bank write bursts 69system.physmem.perBankRdBursts::1 25718 # Per bank write bursts 70system.physmem.perBankRdBursts::2 25598 # Per bank write bursts 71system.physmem.perBankRdBursts::3 25075 # Per bank write bursts 72system.physmem.perBankRdBursts::4 25186 # Per bank write bursts 73system.physmem.perBankRdBursts::5 25258 # Per bank write bursts 74system.physmem.perBankRdBursts::6 25824 # Per bank write bursts 75system.physmem.perBankRdBursts::7 25548 # Per bank write bursts 76system.physmem.perBankRdBursts::8 25573 # Per bank write bursts 77system.physmem.perBankRdBursts::9 25196 # Per bank write bursts 78system.physmem.perBankRdBursts::10 25177 # Per bank write bursts 79system.physmem.perBankRdBursts::11 25610 # Per bank write bursts 80system.physmem.perBankRdBursts::12 25669 # Per bank write bursts 81system.physmem.perBankRdBursts::13 25717 # Per bank write bursts 82system.physmem.perBankRdBursts::14 26016 # Per bank write bursts 83system.physmem.perBankRdBursts::15 25246 # Per bank write bursts 84system.physmem.perBankWrBursts::0 7929 # Per bank write bursts 85system.physmem.perBankWrBursts::1 7788 # Per bank write bursts 86system.physmem.perBankWrBursts::2 7545 # Per bank write bursts 87system.physmem.perBankWrBursts::3 7026 # Per bank write bursts 88system.physmem.perBankWrBursts::4 7134 # Per bank write bursts 89system.physmem.perBankWrBursts::5 7133 # Per bank write bursts 90system.physmem.perBankWrBursts::6 7657 # Per bank write bursts 91system.physmem.perBankWrBursts::7 7252 # Per bank write bursts 92system.physmem.perBankWrBursts::8 7395 # Per bank write bursts 93system.physmem.perBankWrBursts::9 7084 # Per bank write bursts 94system.physmem.perBankWrBursts::10 7119 # Per bank write bursts 95system.physmem.perBankWrBursts::11 7401 # Per bank write bursts 96system.physmem.perBankWrBursts::12 7832 # Per bank write bursts 97system.physmem.perBankWrBursts::13 8315 # Per bank write bursts 98system.physmem.perBankWrBursts::14 8567 # Per bank write bursts 99system.physmem.perBankWrBursts::15 7699 # Per bank write bursts | 40system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 408360 # Number of read requests accepted 54system.physmem.writeReqs 162776 # Number of write requests accepted 55system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue 59system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25705 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25985 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25732 # Per bank write bursts 68system.physmem.perBankRdBursts::3 25537 # Per bank write bursts 69system.physmem.perBankRdBursts::4 24847 # Per bank write bursts 70system.physmem.perBankRdBursts::5 24747 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25534 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25495 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25150 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25518 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25462 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25292 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25577 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25454 # Per bank write bursts 79system.physmem.perBankRdBursts::14 26241 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25973 # Per bank write bursts 81system.physmem.perBankWrBursts::0 10613 # Per bank write bursts 82system.physmem.perBankWrBursts::1 10753 # Per bank write bursts 83system.physmem.perBankWrBursts::2 9796 # Per bank write bursts 84system.physmem.perBankWrBursts::3 9387 # Per bank write bursts 85system.physmem.perBankWrBursts::4 8893 # Per bank write bursts 86system.physmem.perBankWrBursts::5 9110 # Per bank write bursts 87system.physmem.perBankWrBursts::6 9958 # Per bank write bursts 88system.physmem.perBankWrBursts::7 9669 # Per bank write bursts 89system.physmem.perBankWrBursts::8 9689 # Per bank write bursts 90system.physmem.perBankWrBursts::9 9901 # Per bank write bursts 91system.physmem.perBankWrBursts::10 9876 # Per bank write bursts 92system.physmem.perBankWrBursts::11 10215 # Per bank write bursts 93system.physmem.perBankWrBursts::12 10815 # Per bank write bursts 94system.physmem.perBankWrBursts::13 10652 # Per bank write bursts 95system.physmem.perBankWrBursts::14 10531 # Per bank write bursts 96system.physmem.perBankWrBursts::15 10637 # Per bank write bursts |
| 100system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 101system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 102system.physmem.totGap 1961819616500 # Total gap between requests | 98system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 99system.physmem.totGap 1962839541500 # Total gap between requests |
| 103system.physmem.readPktSize::0 0 # Read request sizes (log2) 104system.physmem.readPktSize::1 0 # Read request sizes (log2) 105system.physmem.readPktSize::2 0 # Read request sizes (log2) 106system.physmem.readPktSize::3 0 # Read request sizes (log2) 107system.physmem.readPktSize::4 0 # Read request sizes (log2) 108system.physmem.readPktSize::5 0 # Read request sizes (log2) | 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 109system.physmem.readPktSize::6 407870 # Read request sizes (log2) | 106system.physmem.readPktSize::6 408360 # Read request sizes (log2) |
| 110system.physmem.writePktSize::0 0 # Write request sizes (log2) 111system.physmem.writePktSize::1 0 # Write request sizes (log2) 112system.physmem.writePktSize::2 0 # Write request sizes (log2) 113system.physmem.writePktSize::3 0 # Write request sizes (log2) 114system.physmem.writePktSize::4 0 # Write request sizes (log2) 115system.physmem.writePktSize::5 0 # Write request sizes (log2) | 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 116system.physmem.writePktSize::6 120906 # Write request sizes (log2) 117system.physmem.rdQLenPdf::0 407616 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see | 113system.physmem.writePktSize::6 162776 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 156system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::15 1871 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::16 2613 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::17 5895 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::18 6008 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::19 6212 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::20 6964 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::21 7304 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::22 8598 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::23 8970 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::24 8975 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::25 8647 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::26 8791 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::28 6804 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::29 5901 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::30 5642 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::31 5617 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::33 164 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::34 148 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::35 141 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::36 133 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::54 82 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::59 61 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see 213system.physmem.bytesPerActivate::samples 66427 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::mean 509.252202 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::gmean 306.095148 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::stdev 413.238328 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::0-127 15972 24.04% 24.04% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::128-255 12116 18.24% 42.28% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::256-383 5140 7.74% 50.02% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::384-511 2994 4.51% 54.53% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::512-639 3304 4.97% 59.50% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::640-767 1746 2.63% 62.13% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::768-895 1491 2.24% 64.38% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::896-1023 1317 1.98% 66.36% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1024-1151 22347 33.64% 100.00% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::total 66427 # Bytes accessed per row activation 227system.physmem.rdPerTurnAround::samples 5433 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::mean 75.036996 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::stdev 2192.886898 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::0-4095 5428 99.91% 99.91% # Reads before turning the bus around for writes | 161system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes |
| 231system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes | 228system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes |
| 232system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes | 229system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes |
| 234system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes 235system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes | 231system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 236system.physmem.rdPerTurnAround::total 5433 # Reads before turning the bus around for writes 237system.physmem.wrPerTurnAround::samples 5433 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::mean 22.248482 # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::gmean 19.059784 # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::stdev 19.984616 # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::16-19 4773 87.85% 87.85% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::20-23 17 0.31% 88.16% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::24-27 17 0.31% 88.48% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::28-31 237 4.36% 92.84% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::32-35 33 0.61% 93.45% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::36-39 9 0.17% 93.61% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::40-43 6 0.11% 93.72% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::44-47 9 0.17% 93.89% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::48-51 24 0.44% 94.33% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::52-55 1 0.02% 94.35% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::64-67 10 0.18% 94.53% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::68-71 6 0.11% 94.64% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::72-75 3 0.06% 94.70% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::76-79 4 0.07% 94.77% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::80-83 32 0.59% 95.36% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::84-87 11 0.20% 95.56% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::88-91 3 0.06% 95.62% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::92-95 9 0.17% 95.79% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::96-99 180 3.31% 99.10% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::100-103 4 0.07% 99.17% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::108-111 1 0.02% 99.19% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::112-115 3 0.06% 99.25% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::120-123 1 0.02% 99.26% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 4 0.07% 99.34% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 4 0.07% 99.41% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::136-139 5 0.09% 99.50% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 7 0.13% 99.63% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::144-147 13 0.24% 99.87% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::152-155 2 0.04% 99.91% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::156-159 1 0.02% 99.93% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::160-163 1 0.02% 99.94% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::164-167 1 0.02% 99.96% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::total 5433 # Writes before turning the bus around for reads 275system.physmem.totQLat 2198653000 # Total ticks spent queuing 276system.physmem.totMemAccLat 9842803000 # Total ticks spent from burst creation until serviced by the DRAM 277system.physmem.totBusLat 2038440000 # Total ticks spent in databus transfers 278system.physmem.avgQLat 5392.98 # Average queueing delay per DRAM burst | 233system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads 269system.physmem.totQLat 2202002500 # Total ticks spent queuing 270system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM 271system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers 272system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst |
| 279system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 280system.physmem.avgMemAccLat 24142.98 # Average memory access latency per DRAM burst 281system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s 282system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s | 274system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst 275system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s 276system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s |
| 283system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s | 277system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s |
| 284system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s | 278system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s |
| 285system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 286system.physmem.busUtil 0.13 # Data bus utilization in percentage | 280system.physmem.busUtil 0.14 # Data bus utilization in percentage |
| 287system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads | 281system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads |
| 288system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 282system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes |
| 289system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 283system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 290system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing 291system.physmem.readRowHits 365377 # Number of row buffer hits during reads 292system.physmem.writeRowHits 96760 # Number of row buffer hits during writes 293system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads 294system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes 295system.physmem.avgGap 3710114.71 # Average gap between requests 296system.physmem.pageHitRate 87.43 # Row buffer hit rate, read and write combined 297system.physmem.memoryStateTime::IDLE 1840052567250 # Time in different power states 298system.physmem.memoryStateTime::REF 65509600000 # Time in different power states | 284system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing 285system.physmem.readRowHits 365785 # Number of row buffer hits during reads 286system.physmem.writeRowHits 133797 # Number of row buffer hits during writes 287system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads 288system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes 289system.physmem.avgGap 3436728.80 # Average gap between requests 290system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined 291system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states 292system.physmem.memoryStateTime::REF 65543660000 # Time in different power states |
| 299system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 293system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 300system.physmem.memoryStateTime::ACT 56261656500 # Time in different power states | 294system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states |
| 301system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 295system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 302system.physmem.actEnergy::0 248270400 # Energy for activate commands per rank (pJ) 303system.physmem.actEnergy::1 253917720 # Energy for activate commands per rank (pJ) 304system.physmem.preEnergy::0 135465000 # Energy for precharge commands per rank (pJ) 305system.physmem.preEnergy::1 138546375 # Energy for precharge commands per rank (pJ) 306system.physmem.readEnergy::0 1587175200 # Energy for read commands per rank (pJ) 307system.physmem.readEnergy::1 1592791200 # Energy for read commands per rank (pJ) 308system.physmem.writeEnergy::0 385326720 # Energy for write commands per rank (pJ) 309system.physmem.writeEnergy::1 397949760 # Energy for write commands per rank (pJ) 310system.physmem.refreshEnergy::0 128136777600 # Energy for refresh commands per rank (pJ) 311system.physmem.refreshEnergy::1 128136777600 # Energy for refresh commands per rank (pJ) 312system.physmem.actBackEnergy::0 65365947855 # Energy for active background per rank (pJ) 313system.physmem.actBackEnergy::1 65768853780 # Energy for active background per rank (pJ) 314system.physmem.preBackEnergy::0 1119755735250 # Energy for precharge background per rank (pJ) 315system.physmem.preBackEnergy::1 1119402309000 # Energy for precharge background per rank (pJ) 316system.physmem.totalEnergy::0 1315614698025 # Total energy per rank (pJ) 317system.physmem.totalEnergy::1 1315691145435 # Total energy per rank (pJ) 318system.physmem.averagePower::0 670.607978 # Core power per rank (mW) 319system.physmem.averagePower::1 670.646945 # Core power per rank (mW) 320system.membus.trans_dist::ReadReq 292757 # Transaction distribution 321system.membus.trans_dist::ReadResp 292757 # Transaction distribution 322system.membus.trans_dist::WriteReq 14067 # Transaction distribution 323system.membus.trans_dist::WriteResp 14067 # Transaction distribution 324system.membus.trans_dist::Writeback 79354 # Transaction distribution 325system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 326system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 327system.membus.trans_dist::UpgradeReq 16159 # Transaction distribution 328system.membus.trans_dist::SCUpgradeReq 11272 # Transaction distribution 329system.membus.trans_dist::UpgradeResp 6995 # Transaction distribution 330system.membus.trans_dist::ReadExReq 123294 # Transaction distribution 331system.membus.trans_dist::ReadExResp 122471 # Transaction distribution 332system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) 333system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930313 # Packet count per connected master and slave (bytes) 334system.membus.pkt_count_system.l2c.mem_side::total 972845 # Packet count per connected master and slave (bytes) 335system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83293 # Packet count per connected master and slave (bytes) 336system.membus.pkt_count_system.iocache.mem_side::total 83293 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count::total 1056138 # Packet count per connected master and slave (bytes) 338system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) 339system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31181376 # Cumulative packet size per connected master and slave (bytes) 340system.membus.pkt_size_system.l2c.mem_side::total 31263330 # Cumulative packet size per connected master and slave (bytes) 341system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 342system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 343system.membus.pkt_size::total 33923618 # Cumulative packet size per connected master and slave (bytes) 344system.membus.snoops 21418 # Total snoops (count) 345system.membus.snoop_fanout::samples 557197 # Request fanout histogram 346system.membus.snoop_fanout::mean 1 # Request fanout histogram 347system.membus.snoop_fanout::stdev 0 # Request fanout histogram 348system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 349system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 350system.membus.snoop_fanout::1 557197 100.00% 100.00% # Request fanout histogram 351system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 352system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 353system.membus.snoop_fanout::min_value 1 # Request fanout histogram 354system.membus.snoop_fanout::max_value 1 # Request fanout histogram 355system.membus.snoop_fanout::total 557197 # Request fanout histogram 356system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) 357system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 358system.membus.reqLayer1.occupancy 1536995500 # Layer occupancy (ticks) 359system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 360system.membus.respLayer1.occupancy 3833296255 # Layer occupancy (ticks) 361system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 362system.membus.respLayer2.occupancy 43122000 # Layer occupancy (ticks) 363system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 296system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ) 297system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ) 298system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ) 299system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ) 300system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ) 301system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ) 302system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ) 303system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ) 304system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ) 305system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ) 306system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ) 307system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ) 308system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ) 309system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ) 310system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ) 311system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ) 312system.physmem.averagePower::0 670.686708 # Core power per rank (mW) 313system.physmem.averagePower::1 670.738650 # Core power per rank (mW) |
| 364system.cpu_clk_domain.clock 500 # Clock period in ticks | 314system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 365system.l2c.tags.replacements 342092 # number of replacements 366system.l2c.tags.tagsinuse 65220.775537 # Cycle average of tags in use 367system.l2c.tags.total_refs 2444844 # Total number of references to valid blocks. 368system.l2c.tags.sampled_refs 407280 # Sample count of references to valid blocks. 369system.l2c.tags.avg_refs 6.002858 # Average number of references to valid blocks. 370system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. 371system.l2c.tags.occ_blocks::writebacks 55275.158075 # Average occupied blocks per requestor 372system.l2c.tags.occ_blocks::cpu0.inst 4808.073812 # Average occupied blocks per requestor 373system.l2c.tags.occ_blocks::cpu0.data 4934.415131 # Average occupied blocks per requestor 374system.l2c.tags.occ_blocks::cpu1.inst 159.916198 # Average occupied blocks per requestor 375system.l2c.tags.occ_blocks::cpu1.data 43.212322 # Average occupied blocks per requestor 376system.l2c.tags.occ_percent::writebacks 0.843432 # Average percentage of cache occupancy 377system.l2c.tags.occ_percent::cpu0.inst 0.073365 # Average percentage of cache occupancy 378system.l2c.tags.occ_percent::cpu0.data 0.075293 # Average percentage of cache occupancy 379system.l2c.tags.occ_percent::cpu1.inst 0.002440 # Average percentage of cache occupancy 380system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy 381system.l2c.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy 382system.l2c.tags.occ_task_id_blocks::1024 65188 # Occupied blocks per task id 383system.l2c.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 384system.l2c.tags.age_task_id_blocks_1024::1 763 # Occupied blocks per task id 385system.l2c.tags.age_task_id_blocks_1024::2 5265 # Occupied blocks per task id 386system.l2c.tags.age_task_id_blocks_1024::3 7161 # Occupied blocks per task id 387system.l2c.tags.age_task_id_blocks_1024::4 51884 # Occupied blocks per task id 388system.l2c.tags.occ_task_id_percent::1024 0.994690 # Percentage of cache occupancy per task id 389system.l2c.tags.tag_accesses 25951455 # Number of tag accesses 390system.l2c.tags.data_accesses 25951455 # Number of data accesses 391system.l2c.ReadReq_hits::cpu0.inst 690677 # number of ReadReq hits 392system.l2c.ReadReq_hits::cpu0.data 668171 # number of ReadReq hits 393system.l2c.ReadReq_hits::cpu1.inst 311497 # number of ReadReq hits 394system.l2c.ReadReq_hits::cpu1.data 104258 # number of ReadReq hits 395system.l2c.ReadReq_hits::total 1774603 # number of ReadReq hits 396system.l2c.Writeback_hits::writebacks 792816 # number of Writeback hits 397system.l2c.Writeback_hits::total 792816 # number of Writeback hits 398system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits 399system.l2c.UpgradeReq_hits::cpu1.data 541 # number of UpgradeReq hits 400system.l2c.UpgradeReq_hits::total 723 # number of UpgradeReq hits 401system.l2c.SCUpgradeReq_hits::cpu0.data 41 # number of SCUpgradeReq hits 402system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 403system.l2c.SCUpgradeReq_hits::total 64 # number of SCUpgradeReq hits 404system.l2c.ReadExReq_hits::cpu0.data 130531 # number of ReadExReq hits 405system.l2c.ReadExReq_hits::cpu1.data 42264 # number of ReadExReq hits 406system.l2c.ReadExReq_hits::total 172795 # number of ReadExReq hits 407system.l2c.demand_hits::cpu0.inst 690677 # number of demand (read+write) hits 408system.l2c.demand_hits::cpu0.data 798702 # number of demand (read+write) hits 409system.l2c.demand_hits::cpu1.inst 311497 # number of demand (read+write) hits 410system.l2c.demand_hits::cpu1.data 146522 # number of demand (read+write) hits 411system.l2c.demand_hits::total 1947398 # number of demand (read+write) hits 412system.l2c.overall_hits::cpu0.inst 690677 # number of overall hits 413system.l2c.overall_hits::cpu0.data 798702 # number of overall hits 414system.l2c.overall_hits::cpu1.inst 311497 # number of overall hits 415system.l2c.overall_hits::cpu1.data 146522 # number of overall hits 416system.l2c.overall_hits::total 1947398 # number of overall hits 417system.l2c.ReadReq_misses::cpu0.inst 13021 # number of ReadReq misses 418system.l2c.ReadReq_misses::cpu0.data 271630 # number of ReadReq misses 419system.l2c.ReadReq_misses::cpu1.inst 506 # number of ReadReq misses 420system.l2c.ReadReq_misses::cpu1.data 238 # number of ReadReq misses 421system.l2c.ReadReq_misses::total 285395 # number of ReadReq misses 422system.l2c.UpgradeReq_misses::cpu0.data 2954 # number of UpgradeReq misses 423system.l2c.UpgradeReq_misses::cpu1.data 1743 # number of UpgradeReq misses 424system.l2c.UpgradeReq_misses::total 4697 # number of UpgradeReq misses 425system.l2c.SCUpgradeReq_misses::cpu0.data 889 # number of SCUpgradeReq misses 426system.l2c.SCUpgradeReq_misses::cpu1.data 909 # number of SCUpgradeReq misses 427system.l2c.SCUpgradeReq_misses::total 1798 # number of SCUpgradeReq misses 428system.l2c.ReadExReq_misses::cpu0.data 117934 # number of ReadExReq misses 429system.l2c.ReadExReq_misses::cpu1.data 5037 # number of ReadExReq misses 430system.l2c.ReadExReq_misses::total 122971 # number of ReadExReq misses 431system.l2c.demand_misses::cpu0.inst 13021 # number of demand (read+write) misses 432system.l2c.demand_misses::cpu0.data 389564 # number of demand (read+write) misses 433system.l2c.demand_misses::cpu1.inst 506 # number of demand (read+write) misses 434system.l2c.demand_misses::cpu1.data 5275 # number of demand (read+write) misses 435system.l2c.demand_misses::total 408366 # number of demand (read+write) misses 436system.l2c.overall_misses::cpu0.inst 13021 # number of overall misses 437system.l2c.overall_misses::cpu0.data 389564 # number of overall misses 438system.l2c.overall_misses::cpu1.inst 506 # number of overall misses 439system.l2c.overall_misses::cpu1.data 5275 # number of overall misses 440system.l2c.overall_misses::total 408366 # number of overall misses 441system.l2c.ReadReq_miss_latency::cpu0.inst 953089000 # number of ReadReq miss cycles 442system.l2c.ReadReq_miss_latency::cpu0.data 17671814750 # number of ReadReq miss cycles 443system.l2c.ReadReq_miss_latency::cpu1.inst 36961500 # number of ReadReq miss cycles 444system.l2c.ReadReq_miss_latency::cpu1.data 17116250 # number of ReadReq miss cycles 445system.l2c.ReadReq_miss_latency::total 18678981500 # number of ReadReq miss cycles 446system.l2c.UpgradeReq_miss_latency::cpu0.data 1049955 # number of UpgradeReq miss cycles 447system.l2c.UpgradeReq_miss_latency::cpu1.data 9987069 # number of UpgradeReq miss cycles 448system.l2c.UpgradeReq_miss_latency::total 11037024 # number of UpgradeReq miss cycles 449system.l2c.SCUpgradeReq_miss_latency::cpu0.data 859463 # number of SCUpgradeReq miss cycles 450system.l2c.SCUpgradeReq_miss_latency::cpu1.data 161993 # number of SCUpgradeReq miss cycles 451system.l2c.SCUpgradeReq_miss_latency::total 1021456 # number of SCUpgradeReq miss cycles 452system.l2c.ReadExReq_miss_latency::cpu0.data 8143976512 # number of ReadExReq miss cycles 453system.l2c.ReadExReq_miss_latency::cpu1.data 374794238 # number of ReadExReq miss cycles 454system.l2c.ReadExReq_miss_latency::total 8518770750 # number of ReadExReq miss cycles 455system.l2c.demand_miss_latency::cpu0.inst 953089000 # number of demand (read+write) miss cycles 456system.l2c.demand_miss_latency::cpu0.data 25815791262 # number of demand (read+write) miss cycles 457system.l2c.demand_miss_latency::cpu1.inst 36961500 # number of demand (read+write) miss cycles 458system.l2c.demand_miss_latency::cpu1.data 391910488 # number of demand (read+write) miss cycles 459system.l2c.demand_miss_latency::total 27197752250 # number of demand (read+write) miss cycles 460system.l2c.overall_miss_latency::cpu0.inst 953089000 # number of overall miss cycles 461system.l2c.overall_miss_latency::cpu0.data 25815791262 # number of overall miss cycles 462system.l2c.overall_miss_latency::cpu1.inst 36961500 # number of overall miss cycles 463system.l2c.overall_miss_latency::cpu1.data 391910488 # number of overall miss cycles 464system.l2c.overall_miss_latency::total 27197752250 # number of overall miss cycles 465system.l2c.ReadReq_accesses::cpu0.inst 703698 # number of ReadReq accesses(hits+misses) 466system.l2c.ReadReq_accesses::cpu0.data 939801 # number of ReadReq accesses(hits+misses) 467system.l2c.ReadReq_accesses::cpu1.inst 312003 # number of ReadReq accesses(hits+misses) 468system.l2c.ReadReq_accesses::cpu1.data 104496 # number of ReadReq accesses(hits+misses) 469system.l2c.ReadReq_accesses::total 2059998 # number of ReadReq accesses(hits+misses) 470system.l2c.Writeback_accesses::writebacks 792816 # number of Writeback accesses(hits+misses) 471system.l2c.Writeback_accesses::total 792816 # number of Writeback accesses(hits+misses) 472system.l2c.UpgradeReq_accesses::cpu0.data 3136 # number of UpgradeReq accesses(hits+misses) 473system.l2c.UpgradeReq_accesses::cpu1.data 2284 # number of UpgradeReq accesses(hits+misses) 474system.l2c.UpgradeReq_accesses::total 5420 # number of UpgradeReq accesses(hits+misses) 475system.l2c.SCUpgradeReq_accesses::cpu0.data 930 # number of SCUpgradeReq accesses(hits+misses) 476system.l2c.SCUpgradeReq_accesses::cpu1.data 932 # number of SCUpgradeReq accesses(hits+misses) 477system.l2c.SCUpgradeReq_accesses::total 1862 # number of SCUpgradeReq accesses(hits+misses) 478system.l2c.ReadExReq_accesses::cpu0.data 248465 # number of ReadExReq accesses(hits+misses) 479system.l2c.ReadExReq_accesses::cpu1.data 47301 # number of ReadExReq accesses(hits+misses) 480system.l2c.ReadExReq_accesses::total 295766 # number of ReadExReq accesses(hits+misses) 481system.l2c.demand_accesses::cpu0.inst 703698 # number of demand (read+write) accesses 482system.l2c.demand_accesses::cpu0.data 1188266 # number of demand (read+write) accesses 483system.l2c.demand_accesses::cpu1.inst 312003 # number of demand (read+write) accesses 484system.l2c.demand_accesses::cpu1.data 151797 # number of demand (read+write) accesses 485system.l2c.demand_accesses::total 2355764 # number of demand (read+write) accesses 486system.l2c.overall_accesses::cpu0.inst 703698 # number of overall (read+write) accesses 487system.l2c.overall_accesses::cpu0.data 1188266 # number of overall (read+write) accesses 488system.l2c.overall_accesses::cpu1.inst 312003 # number of overall (read+write) accesses 489system.l2c.overall_accesses::cpu1.data 151797 # number of overall (read+write) accesses 490system.l2c.overall_accesses::total 2355764 # number of overall (read+write) accesses 491system.l2c.ReadReq_miss_rate::cpu0.inst 0.018504 # miss rate for ReadReq accesses 492system.l2c.ReadReq_miss_rate::cpu0.data 0.289029 # miss rate for ReadReq accesses 493system.l2c.ReadReq_miss_rate::cpu1.inst 0.001622 # miss rate for ReadReq accesses 494system.l2c.ReadReq_miss_rate::cpu1.data 0.002278 # miss rate for ReadReq accesses 495system.l2c.ReadReq_miss_rate::total 0.138541 # miss rate for ReadReq accesses 496system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941964 # miss rate for UpgradeReq accesses 497system.l2c.UpgradeReq_miss_rate::cpu1.data 0.763135 # miss rate for UpgradeReq accesses 498system.l2c.UpgradeReq_miss_rate::total 0.866605 # miss rate for UpgradeReq accesses 499system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.955914 # miss rate for SCUpgradeReq accesses 500system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975322 # miss rate for SCUpgradeReq accesses 501system.l2c.SCUpgradeReq_miss_rate::total 0.965628 # miss rate for SCUpgradeReq accesses 502system.l2c.ReadExReq_miss_rate::cpu0.data 0.474650 # miss rate for ReadExReq accesses 503system.l2c.ReadExReq_miss_rate::cpu1.data 0.106488 # miss rate for ReadExReq accesses 504system.l2c.ReadExReq_miss_rate::total 0.415771 # miss rate for ReadExReq accesses 505system.l2c.demand_miss_rate::cpu0.inst 0.018504 # miss rate for demand accesses 506system.l2c.demand_miss_rate::cpu0.data 0.327842 # miss rate for demand accesses 507system.l2c.demand_miss_rate::cpu1.inst 0.001622 # miss rate for demand accesses 508system.l2c.demand_miss_rate::cpu1.data 0.034750 # miss rate for demand accesses 509system.l2c.demand_miss_rate::total 0.173348 # miss rate for demand accesses 510system.l2c.overall_miss_rate::cpu0.inst 0.018504 # miss rate for overall accesses 511system.l2c.overall_miss_rate::cpu0.data 0.327842 # miss rate for overall accesses 512system.l2c.overall_miss_rate::cpu1.inst 0.001622 # miss rate for overall accesses 513system.l2c.overall_miss_rate::cpu1.data 0.034750 # miss rate for overall accesses 514system.l2c.overall_miss_rate::total 0.173348 # miss rate for overall accesses 515system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73196.298287 # average ReadReq miss latency 516system.l2c.ReadReq_avg_miss_latency::cpu0.data 65058.405736 # average ReadReq miss latency 517system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73046.442688 # average ReadReq miss latency 518system.l2c.ReadReq_avg_miss_latency::cpu1.data 71917.016807 # average ReadReq miss latency 519system.l2c.ReadReq_avg_miss_latency::total 65449.575150 # average ReadReq miss latency 520system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 355.435003 # average UpgradeReq miss latency 521system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5729.815835 # average UpgradeReq miss latency 522system.l2c.UpgradeReq_avg_miss_latency::total 2349.802853 # average UpgradeReq miss latency 523system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 966.775028 # average SCUpgradeReq miss latency 524system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 178.210121 # average SCUpgradeReq miss latency 525system.l2c.SCUpgradeReq_avg_miss_latency::total 568.106785 # average SCUpgradeReq miss latency 526system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69055.374294 # average ReadExReq miss latency 527system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74408.226722 # average ReadExReq miss latency 528system.l2c.ReadExReq_avg_miss_latency::total 69274.631824 # average ReadExReq miss latency 529system.l2c.demand_avg_miss_latency::cpu0.inst 73196.298287 # average overall miss latency 530system.l2c.demand_avg_miss_latency::cpu0.data 66268.421266 # average overall miss latency 531system.l2c.demand_avg_miss_latency::cpu1.inst 73046.442688 # average overall miss latency 532system.l2c.demand_avg_miss_latency::cpu1.data 74295.827109 # average overall miss latency 533system.l2c.demand_avg_miss_latency::total 66601.412091 # average overall miss latency 534system.l2c.overall_avg_miss_latency::cpu0.inst 73196.298287 # average overall miss latency 535system.l2c.overall_avg_miss_latency::cpu0.data 66268.421266 # average overall miss latency 536system.l2c.overall_avg_miss_latency::cpu1.inst 73046.442688 # average overall miss latency 537system.l2c.overall_avg_miss_latency::cpu1.data 74295.827109 # average overall miss latency 538system.l2c.overall_avg_miss_latency::total 66601.412091 # average overall miss latency 539system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 540system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 541system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 542system.l2c.blocked::no_targets 0 # number of cycles access was blocked 543system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 544system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 545system.l2c.fast_writes 0 # number of fast writes performed 546system.l2c.cache_copies 0 # number of cache copies performed 547system.l2c.writebacks::writebacks 79354 # number of writebacks 548system.l2c.writebacks::total 79354 # number of writebacks 549system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits 550system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits 551system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 552system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 553system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 554system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 555system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 556system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 557system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits 558system.l2c.ReadReq_mshr_misses::cpu0.inst 13018 # number of ReadReq MSHR misses 559system.l2c.ReadReq_mshr_misses::cpu0.data 271630 # number of ReadReq MSHR misses 560system.l2c.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses 561system.l2c.ReadReq_mshr_misses::cpu1.data 238 # number of ReadReq MSHR misses 562system.l2c.ReadReq_mshr_misses::total 285384 # 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number of demand (read+write) MSHR misses 575system.l2c.demand_mshr_misses::cpu1.data 5275 # number of demand (read+write) MSHR misses 576system.l2c.demand_mshr_misses::total 408355 # number of demand (read+write) MSHR misses 577system.l2c.overall_mshr_misses::cpu0.inst 13018 # number of overall MSHR misses 578system.l2c.overall_mshr_misses::cpu0.data 389564 # number of overall MSHR misses 579system.l2c.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses 580system.l2c.overall_mshr_misses::cpu1.data 5275 # number of overall MSHR misses 581system.l2c.overall_mshr_misses::total 408355 # number of overall MSHR misses 582system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 787294250 # number of ReadReq MSHR miss cycles 583system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14275629250 # number of ReadReq MSHR miss cycles 584system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 30082250 # number of ReadReq MSHR miss cycles 585system.l2c.ReadReq_mshr_miss_latency::cpu1.data 14147750 # number of ReadReq MSHR miss cycles 586system.l2c.ReadReq_mshr_miss_latency::total 15107153500 # number of ReadReq MSHR miss cycles 587system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29547954 # number of UpgradeReq MSHR miss cycles 588system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17431743 # number of UpgradeReq MSHR miss cycles 589system.l2c.UpgradeReq_mshr_miss_latency::total 46979697 # number of UpgradeReq MSHR miss cycles 590system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8890889 # number of SCUpgradeReq MSHR miss cycles 591system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9090909 # number of SCUpgradeReq MSHR miss cycles 592system.l2c.SCUpgradeReq_mshr_miss_latency::total 17981798 # number of SCUpgradeReq MSHR miss cycles 593system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6662795488 # number of ReadExReq MSHR miss cycles 594system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 311210762 # number of ReadExReq MSHR miss cycles 595system.l2c.ReadExReq_mshr_miss_latency::total 6974006250 # number of ReadExReq MSHR miss cycles 596system.l2c.demand_mshr_miss_latency::cpu0.inst 787294250 # number of demand (read+write) MSHR miss cycles 597system.l2c.demand_mshr_miss_latency::cpu0.data 20938424738 # number of demand (read+write) MSHR miss cycles 598system.l2c.demand_mshr_miss_latency::cpu1.inst 30082250 # number of demand (read+write) MSHR miss cycles 599system.l2c.demand_mshr_miss_latency::cpu1.data 325358512 # number of demand (read+write) MSHR miss cycles 600system.l2c.demand_mshr_miss_latency::total 22081159750 # number of demand (read+write) MSHR miss cycles 601system.l2c.overall_mshr_miss_latency::cpu0.inst 787294250 # number of overall MSHR miss cycles 602system.l2c.overall_mshr_miss_latency::cpu0.data 20938424738 # number of overall MSHR miss cycles 603system.l2c.overall_mshr_miss_latency::cpu1.inst 30082250 # number of overall MSHR miss cycles 604system.l2c.overall_mshr_miss_latency::cpu1.data 325358512 # number of overall MSHR miss cycles 605system.l2c.overall_mshr_miss_latency::total 22081159750 # number of overall MSHR miss cycles 606system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373183500 # number of ReadReq MSHR uncacheable cycles 607system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17608500 # number of ReadReq MSHR uncacheable cycles 608system.l2c.ReadReq_mshr_uncacheable_latency::total 1390792000 # number of ReadReq MSHR uncacheable cycles 609system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2147807000 # number of WriteReq MSHR uncacheable cycles 610system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674603500 # number of WriteReq MSHR uncacheable cycles 611system.l2c.WriteReq_mshr_uncacheable_latency::total 2822410500 # number of WriteReq MSHR uncacheable cycles 612system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3520990500 # number of overall MSHR uncacheable cycles 613system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692212000 # number of overall MSHR uncacheable cycles 614system.l2c.overall_mshr_uncacheable_latency::total 4213202500 # number of overall MSHR uncacheable cycles 615system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for ReadReq accesses 616system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289029 # mshr miss rate for ReadReq accesses 617system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for ReadReq accesses 618system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002278 # mshr miss rate for ReadReq accesses 619system.l2c.ReadReq_mshr_miss_rate::total 0.138536 # mshr miss rate for ReadReq accesses 620system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941964 # mshr miss rate for UpgradeReq accesses 621system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.763135 # mshr miss rate for UpgradeReq accesses 622system.l2c.UpgradeReq_mshr_miss_rate::total 0.866605 # mshr miss rate for UpgradeReq accesses 623system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.955914 # mshr miss rate for SCUpgradeReq accesses 624system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975322 # mshr miss rate for SCUpgradeReq accesses 625system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.965628 # mshr miss rate for SCUpgradeReq accesses 626system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.474650 # mshr miss rate for ReadExReq accesses 627system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.106488 # mshr miss rate for ReadExReq accesses 628system.l2c.ReadExReq_mshr_miss_rate::total 0.415771 # mshr miss rate for ReadExReq accesses 629system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for demand accesses 630system.l2c.demand_mshr_miss_rate::cpu0.data 0.327842 # mshr miss rate for demand accesses 631system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for demand accesses 632system.l2c.demand_mshr_miss_rate::cpu1.data 0.034750 # mshr miss rate for demand accesses 633system.l2c.demand_mshr_miss_rate::total 0.173343 # mshr miss rate for demand accesses 634system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for overall accesses 635system.l2c.overall_mshr_miss_rate::cpu0.data 0.327842 # mshr miss rate for overall accesses 636system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for overall accesses 637system.l2c.overall_mshr_miss_rate::cpu1.data 0.034750 # mshr miss rate for overall accesses 638system.l2c.overall_mshr_miss_rate::total 0.173343 # mshr miss rate for overall accesses 639system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average ReadReq mshr miss latency 640system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52555.421897 # average ReadReq mshr miss latency 641system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average ReadReq mshr miss latency 642system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59444.327731 # average ReadReq mshr miss latency 643system.l2c.ReadReq_avg_mshr_miss_latency::total 52936.231534 # average ReadReq mshr miss latency 644system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.692620 # average UpgradeReq mshr miss latency 645system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency 646system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.064509 # average UpgradeReq mshr miss latency 647system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency 648system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency 649system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 650system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56495.967982 # average ReadExReq mshr miss latency 651system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61784.943816 # average ReadExReq mshr miss latency 652system.l2c.ReadExReq_avg_mshr_miss_latency::total 56712.609070 # average ReadExReq mshr miss latency 653system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency 654system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency 655system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency 656system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency 657system.l2c.demand_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency 658system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency 659system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency 660system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency 661system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency 662system.l2c.overall_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency 663system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 664system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 665system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 666system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 667system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 668system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 669system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 670system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 671system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 672system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 673system.iocache.tags.replacements 41694 # number of replacements 674system.iocache.tags.tagsinuse 0.569739 # Cycle average of tags in use 675system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 676system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. 677system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 678system.iocache.tags.warmup_cycle 1755504878000 # Cycle when the warmup percentage was hit. 679system.iocache.tags.occ_blocks::tsunami.ide 0.569739 # Average occupied blocks per requestor 680system.iocache.tags.occ_percent::tsunami.ide 0.035609 # Average percentage of cache occupancy 681system.iocache.tags.occ_percent::total 0.035609 # Average percentage of cache occupancy 682system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 683system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 684system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 685system.iocache.tags.tag_accesses 375534 # Number of tag accesses 686system.iocache.tags.data_accesses 375534 # Number of data accesses 687system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 688system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 689system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 690system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 691system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses 692system.iocache.demand_misses::total 174 # number of demand (read+write) misses 693system.iocache.overall_misses::tsunami.ide 174 # number of overall misses 694system.iocache.overall_misses::total 174 # number of overall misses 695system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles 696system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles 697system.iocache.demand_miss_latency::tsunami.ide 21248383 # number of demand (read+write) miss cycles 698system.iocache.demand_miss_latency::total 21248383 # number of demand (read+write) miss cycles 699system.iocache.overall_miss_latency::tsunami.ide 21248383 # number of overall miss cycles 700system.iocache.overall_miss_latency::total 21248383 # number of overall miss cycles 701system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 702system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 703system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 704system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 705system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses 706system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses 707system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses 708system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses 709system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 710system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 711system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 712system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 713system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 714system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 715system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency 716system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency 717system.iocache.demand_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency 718system.iocache.demand_avg_miss_latency::total 122117.143678 # average overall miss latency 719system.iocache.overall_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency 720system.iocache.overall_avg_miss_latency::total 122117.143678 # average overall miss latency 721system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 722system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.iocache.blocked::no_targets 0 # number of cycles access was blocked 725system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.iocache.fast_writes 41552 # number of fast writes performed 728system.iocache.cache_copies 0 # number of cache copies performed 729system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 730system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 731system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses 732system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 733system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses 734system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses 735system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles 736system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles 737system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2501404806 # number of WriteInvalidateReq MSHR miss cycles 738system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2501404806 # number of WriteInvalidateReq MSHR miss cycles 739system.iocache.demand_mshr_miss_latency::tsunami.ide 12199383 # number of demand (read+write) MSHR miss cycles 740system.iocache.demand_mshr_miss_latency::total 12199383 # number of demand (read+write) MSHR miss cycles 741system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 # number of overall MSHR miss cycles 742system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles 743system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 744system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 745system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 746system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 747system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 748system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 749system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency 750system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency 751system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 752system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 753system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency 754system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency 755system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency 756system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency 757system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 758system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 759system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 760system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 761system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 762system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 763system.disk0.dma_write_txs 395 # Number of DMA write transactions. 764system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 765system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 766system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 767system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 768system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 769system.disk2.dma_write_txs 1 # Number of DMA write transactions. | |
| 770system.cpu0.dtb.fetch_hits 0 # ITB hits 771system.cpu0.dtb.fetch_misses 0 # ITB misses 772system.cpu0.dtb.fetch_acv 0 # ITB acv 773system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 315system.cpu0.dtb.fetch_hits 0 # ITB hits 316system.cpu0.dtb.fetch_misses 0 # ITB misses 317system.cpu0.dtb.fetch_acv 0 # ITB acv 318system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 774system.cpu0.dtb.read_hits 7562596 # DTB read hits | 319system.cpu0.dtb.read_hits 7534386 # DTB read hits |
| 775system.cpu0.dtb.read_misses 7765 # DTB read misses 776system.cpu0.dtb.read_acv 210 # DTB read access violations 777system.cpu0.dtb.read_accesses 524069 # DTB read accesses | 320system.cpu0.dtb.read_misses 7765 # DTB read misses 321system.cpu0.dtb.read_acv 210 # DTB read access violations 322system.cpu0.dtb.read_accesses 524069 # DTB read accesses |
| 778system.cpu0.dtb.write_hits 5147185 # DTB write hits | 323system.cpu0.dtb.write_hits 5126601 # DTB write hits |
| 779system.cpu0.dtb.write_misses 910 # DTB write misses 780system.cpu0.dtb.write_acv 133 # DTB write access violations 781system.cpu0.dtb.write_accesses 202595 # DTB write accesses | 324system.cpu0.dtb.write_misses 910 # DTB write misses 325system.cpu0.dtb.write_acv 133 # DTB write access violations 326system.cpu0.dtb.write_accesses 202595 # DTB write accesses |
| 782system.cpu0.dtb.data_hits 12709781 # DTB hits | 327system.cpu0.dtb.data_hits 12660987 # DTB hits |
| 783system.cpu0.dtb.data_misses 8675 # DTB misses 784system.cpu0.dtb.data_acv 343 # DTB access violations 785system.cpu0.dtb.data_accesses 726664 # DTB accesses | 328system.cpu0.dtb.data_misses 8675 # DTB misses 329system.cpu0.dtb.data_acv 343 # DTB access violations 330system.cpu0.dtb.data_accesses 726664 # DTB accesses |
| 786system.cpu0.itb.fetch_hits 3660706 # ITB hits | 331system.cpu0.itb.fetch_hits 3654300 # ITB hits |
| 787system.cpu0.itb.fetch_misses 3984 # ITB misses 788system.cpu0.itb.fetch_acv 184 # ITB acv | 332system.cpu0.itb.fetch_misses 3984 # ITB misses 333system.cpu0.itb.fetch_acv 184 # ITB acv |
| 789system.cpu0.itb.fetch_accesses 3664690 # ITB accesses | 334system.cpu0.itb.fetch_accesses 3658284 # ITB accesses |
| 790system.cpu0.itb.read_hits 0 # DTB read hits 791system.cpu0.itb.read_misses 0 # DTB read misses 792system.cpu0.itb.read_acv 0 # DTB read access violations 793system.cpu0.itb.read_accesses 0 # DTB read accesses 794system.cpu0.itb.write_hits 0 # DTB write hits 795system.cpu0.itb.write_misses 0 # DTB write misses 796system.cpu0.itb.write_acv 0 # DTB write access violations 797system.cpu0.itb.write_accesses 0 # DTB write accesses 798system.cpu0.itb.data_hits 0 # DTB hits 799system.cpu0.itb.data_misses 0 # DTB misses 800system.cpu0.itb.data_acv 0 # DTB access violations 801system.cpu0.itb.data_accesses 0 # DTB accesses | 335system.cpu0.itb.read_hits 0 # DTB read hits 336system.cpu0.itb.read_misses 0 # DTB read misses 337system.cpu0.itb.read_acv 0 # DTB read access violations 338system.cpu0.itb.read_accesses 0 # DTB read accesses 339system.cpu0.itb.write_hits 0 # DTB write hits 340system.cpu0.itb.write_misses 0 # DTB write misses 341system.cpu0.itb.write_acv 0 # DTB write access violations 342system.cpu0.itb.write_accesses 0 # DTB write accesses 343system.cpu0.itb.data_hits 0 # DTB hits 344system.cpu0.itb.data_misses 0 # DTB misses 345system.cpu0.itb.data_acv 0 # DTB access violations 346system.cpu0.itb.data_accesses 0 # DTB accesses |
| 802system.cpu0.numCycles 3923653257 # number of cpu cycles simulated | 347system.cpu0.numCycles 3925689160 # number of cpu cycles simulated |
| 803system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 804system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 348system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 349system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 805system.cpu0.committedInsts 48127777 # Number of instructions committed 806system.cpu0.committedOps 48127777 # Number of ops (including micro ops) committed 807system.cpu0.num_int_alu_accesses 44643925 # Number of integer alu accesses 808system.cpu0.num_fp_alu_accesses 213512 # Number of float alu accesses 809system.cpu0.num_func_calls 1209739 # number of times a function call or return occured 810system.cpu0.num_conditional_control_insts 5647172 # number of instructions that are conditional controls 811system.cpu0.num_int_insts 44643925 # number of integer instructions 812system.cpu0.num_fp_insts 213512 # number of float instructions 813system.cpu0.num_int_register_reads 61387452 # number of times the integer registers were read 814system.cpu0.num_int_register_writes 33242964 # number of times the integer registers were written 815system.cpu0.num_fp_register_reads 104337 # number of times the floating registers were read 816system.cpu0.num_fp_register_writes 106136 # number of times the floating registers were written 817system.cpu0.num_mem_refs 12750882 # number of memory refs 818system.cpu0.num_load_insts 7590433 # Number of load instructions 819system.cpu0.num_store_insts 5160449 # Number of store instructions 820system.cpu0.num_idle_cycles 3699495012.998114 # Number of idle cycles 821system.cpu0.num_busy_cycles 224158244.001886 # Number of busy cycles 822system.cpu0.not_idle_fraction 0.057130 # Percentage of non-idle cycles 823system.cpu0.idle_fraction 0.942870 # Percentage of idle cycles 824system.cpu0.Branches 7246936 # Number of branches fetched 825system.cpu0.op_class::No_OpClass 2741568 5.70% 5.70% # Class of executed instruction 826system.cpu0.op_class::IntAlu 31634980 65.72% 71.41% # Class of executed instruction 827system.cpu0.op_class::IntMult 52525 0.11% 71.52% # Class of executed instruction 828system.cpu0.op_class::IntDiv 0 0.00% 71.52% # Class of executed instruction 829system.cpu0.op_class::FloatAdd 26830 0.06% 71.58% # Class of executed instruction 830system.cpu0.op_class::FloatCmp 0 0.00% 71.58% # Class of executed instruction 831system.cpu0.op_class::FloatCvt 0 0.00% 71.58% # Class of executed instruction 832system.cpu0.op_class::FloatMult 0 0.00% 71.58% # Class of executed instruction 833system.cpu0.op_class::FloatDiv 1883 0.00% 71.58% # Class of executed instruction 834system.cpu0.op_class::FloatSqrt 0 0.00% 71.58% # Class of executed instruction 835system.cpu0.op_class::SimdAdd 0 0.00% 71.58% # Class of executed instruction 836system.cpu0.op_class::SimdAddAcc 0 0.00% 71.58% # Class of executed instruction 837system.cpu0.op_class::SimdAlu 0 0.00% 71.58% # Class of executed instruction 838system.cpu0.op_class::SimdCmp 0 0.00% 71.58% # Class of executed instruction 839system.cpu0.op_class::SimdCvt 0 0.00% 71.58% # Class of executed instruction 840system.cpu0.op_class::SimdMisc 0 0.00% 71.58% # Class of executed instruction 841system.cpu0.op_class::SimdMult 0 0.00% 71.58% # Class of executed instruction 842system.cpu0.op_class::SimdMultAcc 0 0.00% 71.58% # Class of executed instruction 843system.cpu0.op_class::SimdShift 0 0.00% 71.58% # Class of executed instruction 844system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.58% # Class of executed instruction 845system.cpu0.op_class::SimdSqrt 0 0.00% 71.58% # Class of executed instruction 846system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.58% # Class of executed instruction 847system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.58% # Class of executed instruction 848system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.58% # Class of executed instruction 849system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.58% # Class of executed instruction 850system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.58% # Class of executed instruction 851system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.58% # Class of executed instruction 852system.cpu0.op_class::SimdFloatMult 0 0.00% 71.58% # Class of executed instruction 853system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.58% # Class of executed instruction 854system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.58% # Class of executed instruction 855system.cpu0.op_class::MemRead 7767201 16.14% 87.72% # Class of executed instruction 856system.cpu0.op_class::MemWrite 5166567 10.73% 98.45% # Class of executed instruction 857system.cpu0.op_class::IprAccess 745241 1.55% 100.00% # Class of executed instruction | 350system.cpu0.committedInsts 47974635 # Number of instructions committed 351system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed 352system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses 353system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses 354system.cpu0.num_func_calls 1202793 # number of times a function call or return occured 355system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls 356system.cpu0.num_int_insts 44501266 # number of integer instructions 357system.cpu0.num_fp_insts 212945 # number of float instructions 358system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read 359system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written 360system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read 361system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written 362system.cpu0.num_mem_refs 12702031 # number of memory refs 363system.cpu0.num_load_insts 7562183 # Number of load instructions 364system.cpu0.num_store_insts 5139848 # Number of store instructions 365system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles 366system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles 367system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles 368system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles 369system.cpu0.Branches 7223323 # Number of branches fetched 370system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction 371system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction 372system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction 373system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction 374system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction 375system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction 376system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction 377system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction 378system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction 379system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction 380system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction 381system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction 382system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction 383system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction 384system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction 385system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction 386system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction 387system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction 388system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction 389system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction 390system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction 391system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction 392system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction 393system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction 394system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction 395system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction 396system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction 397system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction 398system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction 399system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction 400system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction 401system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction 402system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction |
| 858system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 403system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 859system.cpu0.op_class::total 48136795 # Class of executed instruction | 404system.cpu0.op_class::total 47983653 # Class of executed instruction |
| 860system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 405system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 861system.cpu0.kern.inst.quiesce 6805 # number of quiesce instructions executed 862system.cpu0.kern.inst.hwrei 166328 # number of hwrei instructions executed 863system.cpu0.kern.ipl_count::0 57239 40.25% 40.25% # number of times we switched to this ipl 864system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl 865system.cpu0.kern.ipl_count::22 1975 1.39% 41.73% # number of times we switched to this ipl 866system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl 867system.cpu0.kern.ipl_count::31 82449 57.97% 100.00% # number of times we switched to this ipl 868system.cpu0.kern.ipl_count::total 142218 # number of times we switched to this ipl 869system.cpu0.kern.ipl_good::0 56706 49.09% 49.09% # number of times we switched to this ipl from a different ipl | 406system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed 407system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed 408system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl 409system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl 410system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl 411system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl 412system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl 413system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl 414system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl |
| 870system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl | 415system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl |
| 871system.cpu0.kern.ipl_good::22 1975 1.71% 50.91% # number of times we switched to this ipl from a different ipl 872system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl 873system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl 874system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl 875system.cpu0.kern.ipl_ticks::0 1902225794500 96.96% 96.96% # number of cycles we spent at this ipl 876system.cpu0.kern.ipl_ticks::21 94977500 0.00% 96.97% # number of cycles we spent at this ipl 877system.cpu0.kern.ipl_ticks::22 767421000 0.04% 97.01% # number of cycles we spent at this ipl 878system.cpu0.kern.ipl_ticks::30 314336500 0.02% 97.02% # number of cycles we spent at this ipl 879system.cpu0.kern.ipl_ticks::31 58423341500 2.98% 100.00% # number of cycles we spent at this ipl 880system.cpu0.kern.ipl_ticks::total 1961825871000 # number of cycles we spent at this ipl 881system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl | 416system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl 417system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl 418system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl 419system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl 420system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl 421system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl 422system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl 423system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl 424system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl 425system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl 426system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl |
| 882system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 883system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 884system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 427system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 428system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 429system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 885system.cpu0.kern.ipl_used::31 0.682640 # fraction of swpipl calls that actually changed the ipl 886system.cpu0.kern.ipl_used::total 0.812267 # fraction of swpipl calls that actually changed the ipl | 430system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl 431system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl |
| 887system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 888system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 889system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 890system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 891system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 892system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 893system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 894system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 910system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 911system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 912system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 913system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 914system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 915system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 916system.cpu0.kern.syscall::total 234 # number of syscalls executed 917system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 432system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 433system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 434system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 435system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 436system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 437system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 438system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 439system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 455system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 456system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 457system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 458system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 459system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 460system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 461system.cpu0.kern.syscall::total 234 # number of syscalls executed 462system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 918system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed | 463system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed |
| 919system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 920system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 921system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed | 464system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 465system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 466system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed |
| 922system.cpu0.kern.callpal::swpctx 3105 2.06% 2.40% # number of callpals executed 923system.cpu0.kern.callpal::tbi 51 0.03% 2.43% # number of callpals executed 924system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed 925system.cpu0.kern.callpal::swpipl 135265 89.81% 92.25% # number of callpals executed 926system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed 927system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed 928system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed 929system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed 930system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed 931system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed | 467system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed 468system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 469system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 470system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed 471system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed 472system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed 473system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed 474system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed 475system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed 476system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed |
| 932system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed 933system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed | 477system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed 478system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed |
| 934system.cpu0.kern.callpal::total 150611 # number of callpals executed 935system.cpu0.kern.mode_switch::kernel 7020 # number of protection mode switches 936system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches | 479system.cpu0.kern.callpal::total 149871 # number of callpals executed 480system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches 481system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches |
| 937system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 482system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 938system.cpu0.kern.mode_good::kernel 1370 939system.cpu0.kern.mode_good::user 1371 | 483system.cpu0.kern.mode_good::kernel 1369 484system.cpu0.kern.mode_good::user 1370 |
| 940system.cpu0.kern.mode_good::idle 0 | 485system.cpu0.kern.mode_good::idle 0 |
| 941system.cpu0.kern.mode_switch_good::kernel 0.195157 # fraction of useful protection mode switches | 486system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches |
| 942system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 943system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 487system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 488system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 944system.cpu0.kern.mode_switch_good::total 0.326660 # fraction of useful protection mode switches 945system.cpu0.kern.mode_ticks::kernel 1958053140500 99.81% 99.81% # number of ticks spent at the given mode 946system.cpu0.kern.mode_ticks::user 3772726000 0.19% 100.00% # number of ticks spent at the given mode | 489system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches 490system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode 491system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode |
| 947system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 492system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 948system.cpu0.kern.swap_context 3106 # number of times the context was actually changed 949system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 950system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 951system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 952system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 953system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 954system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 955system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 956system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 957system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 958system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 959system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 960system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 961system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 962system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 963system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 964system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 965system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 966system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 967system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 968system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 969system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 970system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 971system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 972system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 973system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 974system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 975system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 976system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 977system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 978system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 979system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 980system.toL2Bus.trans_dist::ReadReq 2102030 # Transaction distribution 981system.toL2Bus.trans_dist::ReadResp 2102015 # Transaction distribution 982system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution 983system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution 984system.toL2Bus.trans_dist::Writeback 792816 # Transaction distribution 985system.toL2Bus.trans_dist::WriteInvalidateReq 41560 # Transaction distribution 986system.toL2Bus.trans_dist::UpgradeReq 16382 # Transaction distribution 987system.toL2Bus.trans_dist::SCUpgradeReq 11336 # Transaction distribution 988system.toL2Bus.trans_dist::UpgradeResp 27718 # Transaction distribution 989system.toL2Bus.trans_dist::ReadExReq 297616 # Transaction distribution 990system.toL2Bus.trans_dist::ReadExResp 297616 # Transaction distribution 991system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407417 # Packet count per connected master and slave (bytes) 992system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134555 # Packet count per connected master and slave (bytes) 993system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624007 # Packet count per connected master and slave (bytes) 994system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452565 # Packet count per connected master and slave (bytes) 995system.toL2Bus.pkt_count::total 5618544 # Packet count per connected master and slave (bytes) 996system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45036672 # Cumulative packet size per connected master and slave (bytes) 997system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120042720 # Cumulative packet size per connected master and slave (bytes) 998system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19968192 # Cumulative packet size per connected master and slave (bytes) 999system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16553666 # Cumulative packet size per connected master and slave (bytes) 1000system.toL2Bus.pkt_size::total 201601250 # Cumulative packet size per connected master and slave (bytes) 1001system.toL2Bus.snoops 98838 # Total snoops (count) 1002system.toL2Bus.snoop_fanout::samples 3254541 # Request fanout histogram 1003system.toL2Bus.snoop_fanout::mean 3.012823 # Request fanout histogram 1004system.toL2Bus.snoop_fanout::stdev 0.112512 # Request fanout histogram 1005system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1006system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1007system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1008system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1009system.toL2Bus.snoop_fanout::3 3212807 98.72% 98.72% # Request fanout histogram 1010system.toL2Bus.snoop_fanout::4 41734 1.28% 100.00% # Request fanout histogram 1011system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1012system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1013system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1014system.toL2Bus.snoop_fanout::total 3254541 # Request fanout histogram 1015system.toL2Bus.reqLayer0.occupancy 4795402363 # Layer occupancy (ticks) 1016system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1017system.toL2Bus.snoopLayer0.occupancy 715500 # Layer occupancy (ticks) 1018system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1019system.toL2Bus.respLayer0.occupancy 3169257997 # Layer occupancy (ticks) 1020system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1021system.toL2Bus.respLayer1.occupancy 5536514081 # Layer occupancy (ticks) 1022system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 1023system.toL2Bus.respLayer2.occupancy 1404115991 # Layer occupancy (ticks) 1024system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) 1025system.toL2Bus.respLayer3.occupancy 776560164 # Layer occupancy (ticks) 1026system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1027system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1028system.iobus.trans_dist::ReadResp 7373 # Transaction distribution 1029system.iobus.trans_dist::WriteReq 55619 # Transaction distribution 1030system.iobus.trans_dist::WriteResp 55619 # Transaction distribution 1031system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) 1032system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) 1033system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1034system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1035system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1036system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1037system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1038system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1039system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1040system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1041system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1042system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1043system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) 1044system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 1045system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 1046system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) 1047system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) 1049system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1051system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1052system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1053system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1054system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1055system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1056system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1057system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1058system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1059system.iobus.pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) 1060system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 1061system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 1062system.iobus.pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) 1063system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) 1064system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1065system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) 1066system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1067system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1068system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1069system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1070system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1071system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1072system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1073system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1074system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1075system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) 1076system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1077system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1078system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1079system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1080system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1081system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1082system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1083system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1084system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1085system.iobus.reqLayer29.occupancy 374410189 # Layer occupancy (ticks) 1086system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1087system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1088system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1089system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) 1090system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1091system.iobus.respLayer1.occupancy 42017000 # Layer occupancy (ticks) 1092system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1093system.cpu0.icache.tags.replacements 703089 # number of replacements 1094system.cpu0.icache.tags.tagsinuse 508.385515 # Cycle average of tags in use 1095system.cpu0.icache.tags.total_refs 47433077 # Total number of references to valid blocks. 1096system.cpu0.icache.tags.sampled_refs 703601 # Sample count of references to valid blocks. 1097system.cpu0.icache.tags.avg_refs 67.414738 # Average number of references to valid blocks. 1098system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. 1099system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.385515 # Average occupied blocks per requestor 1100system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992940 # Average percentage of cache occupancy 1101system.cpu0.icache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy 1102system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1103system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 1104system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 1105system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id 1106system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1107system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1108system.cpu0.icache.tags.tag_accesses 48840515 # Number of tag accesses 1109system.cpu0.icache.tags.data_accesses 48840515 # Number of data accesses 1110system.cpu0.icache.ReadReq_hits::cpu0.inst 47433077 # number of ReadReq hits 1111system.cpu0.icache.ReadReq_hits::total 47433077 # number of ReadReq hits 1112system.cpu0.icache.demand_hits::cpu0.inst 47433077 # number of demand (read+write) hits 1113system.cpu0.icache.demand_hits::total 47433077 # number of demand (read+write) hits 1114system.cpu0.icache.overall_hits::cpu0.inst 47433077 # number of overall hits 1115system.cpu0.icache.overall_hits::total 47433077 # number of overall hits 1116system.cpu0.icache.ReadReq_misses::cpu0.inst 703719 # number of ReadReq misses 1117system.cpu0.icache.ReadReq_misses::total 703719 # number of ReadReq misses 1118system.cpu0.icache.demand_misses::cpu0.inst 703719 # number of demand (read+write) misses 1119system.cpu0.icache.demand_misses::total 703719 # number of demand (read+write) misses 1120system.cpu0.icache.overall_misses::cpu0.inst 703719 # number of overall misses 1121system.cpu0.icache.overall_misses::total 703719 # number of overall misses 1122system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017635497 # number of ReadReq miss cycles 1123system.cpu0.icache.ReadReq_miss_latency::total 10017635497 # number of ReadReq miss cycles 1124system.cpu0.icache.demand_miss_latency::cpu0.inst 10017635497 # number of demand (read+write) miss cycles 1125system.cpu0.icache.demand_miss_latency::total 10017635497 # number of demand (read+write) miss cycles 1126system.cpu0.icache.overall_miss_latency::cpu0.inst 10017635497 # number of overall miss cycles 1127system.cpu0.icache.overall_miss_latency::total 10017635497 # number of overall miss cycles 1128system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136796 # number of ReadReq accesses(hits+misses) 1129system.cpu0.icache.ReadReq_accesses::total 48136796 # number of ReadReq accesses(hits+misses) 1130system.cpu0.icache.demand_accesses::cpu0.inst 48136796 # number of demand (read+write) accesses 1131system.cpu0.icache.demand_accesses::total 48136796 # number of demand (read+write) accesses 1132system.cpu0.icache.overall_accesses::cpu0.inst 48136796 # number of overall (read+write) accesses 1133system.cpu0.icache.overall_accesses::total 48136796 # number of overall (read+write) accesses 1134system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014619 # miss rate for ReadReq accesses 1135system.cpu0.icache.ReadReq_miss_rate::total 0.014619 # miss rate for ReadReq accesses 1136system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014619 # miss rate for demand accesses 1137system.cpu0.icache.demand_miss_rate::total 0.014619 # miss rate for demand accesses 1138system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014619 # miss rate for overall accesses 1139system.cpu0.icache.overall_miss_rate::total 0.014619 # miss rate for overall accesses 1140system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14235.277855 # average ReadReq miss latency 1141system.cpu0.icache.ReadReq_avg_miss_latency::total 14235.277855 # average ReadReq miss latency 1142system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency 1143system.cpu0.icache.demand_avg_miss_latency::total 14235.277855 # average overall miss latency 1144system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency 1145system.cpu0.icache.overall_avg_miss_latency::total 14235.277855 # average overall miss latency 1146system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1147system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1148system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1149system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1150system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1151system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1152system.cpu0.icache.fast_writes 0 # number of fast writes performed 1153system.cpu0.icache.cache_copies 0 # number of cache copies performed 1154system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703719 # number of ReadReq MSHR misses 1155system.cpu0.icache.ReadReq_mshr_misses::total 703719 # number of ReadReq MSHR misses 1156system.cpu0.icache.demand_mshr_misses::cpu0.inst 703719 # number of demand (read+write) MSHR misses 1157system.cpu0.icache.demand_mshr_misses::total 703719 # number of demand (read+write) MSHR misses 1158system.cpu0.icache.overall_mshr_misses::cpu0.inst 703719 # number of overall MSHR misses 1159system.cpu0.icache.overall_mshr_misses::total 703719 # number of overall MSHR misses 1160system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8605152503 # number of ReadReq MSHR miss cycles 1161system.cpu0.icache.ReadReq_mshr_miss_latency::total 8605152503 # number of ReadReq MSHR miss cycles 1162system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8605152503 # number of demand (read+write) MSHR miss cycles 1163system.cpu0.icache.demand_mshr_miss_latency::total 8605152503 # number of demand (read+write) MSHR miss cycles 1164system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8605152503 # number of overall MSHR miss cycles 1165system.cpu0.icache.overall_mshr_miss_latency::total 8605152503 # number of overall MSHR miss cycles 1166system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for ReadReq accesses 1167system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014619 # mshr miss rate for ReadReq accesses 1168system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for demand accesses 1169system.cpu0.icache.demand_mshr_miss_rate::total 0.014619 # mshr miss rate for demand accesses 1170system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for overall accesses 1171system.cpu0.icache.overall_mshr_miss_rate::total 0.014619 # mshr miss rate for overall accesses 1172system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average ReadReq mshr miss latency 1173system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.108809 # average ReadReq mshr miss latency 1174system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency 1175system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency 1176system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency 1177system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency 1178system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1179system.cpu0.dcache.tags.replacements 1191194 # number of replacements 1180system.cpu0.dcache.tags.tagsinuse 505.224955 # Cycle average of tags in use 1181system.cpu0.dcache.tags.total_refs 11513307 # Total number of references to valid blocks. 1182system.cpu0.dcache.tags.sampled_refs 1191706 # Sample count of references to valid blocks. 1183system.cpu0.dcache.tags.avg_refs 9.661197 # Average number of references to valid blocks. | 493system.cpu0.kern.swap_context 3098 # number of times the context was actually changed 494system.cpu0.dcache.tags.replacements 1190018 # number of replacements 495system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use 496system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks. 497system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks. 498system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks. |
| 1184system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. | 499system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. |
| 1185system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.224955 # Average occupied blocks per requestor 1186system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986767 # Average percentage of cache occupancy 1187system.cpu0.dcache.tags.occ_percent::total 0.986767 # Average percentage of cache occupancy | 500system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor 501system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy 502system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy |
| 1188system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 503system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1189system.cpu0.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 1190system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 1191system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id | 504system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 505system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id 506system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id |
| 1192system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 507system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1193system.cpu0.dcache.tags.tag_accesses 52084143 # Number of tag accesses 1194system.cpu0.dcache.tags.data_accesses 52084143 # Number of data accesses 1195system.cpu0.dcache.ReadReq_hits::cpu0.data 6477469 # number of ReadReq hits 1196system.cpu0.dcache.ReadReq_hits::total 6477469 # number of ReadReq hits 1197system.cpu0.dcache.WriteReq_hits::cpu0.data 4731394 # number of WriteReq hits 1198system.cpu0.dcache.WriteReq_hits::total 4731394 # number of WriteReq hits 1199system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141563 # number of LoadLockedReq hits 1200system.cpu0.dcache.LoadLockedReq_hits::total 141563 # number of LoadLockedReq hits 1201system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149256 # number of StoreCondReq hits 1202system.cpu0.dcache.StoreCondReq_hits::total 149256 # number of StoreCondReq hits 1203system.cpu0.dcache.demand_hits::cpu0.data 11208863 # number of demand (read+write) hits 1204system.cpu0.dcache.demand_hits::total 11208863 # number of demand (read+write) hits 1205system.cpu0.dcache.overall_hits::cpu0.data 11208863 # number of overall hits 1206system.cpu0.dcache.overall_hits::total 11208863 # number of overall hits 1207system.cpu0.dcache.ReadReq_misses::cpu0.data 942620 # number of ReadReq misses 1208system.cpu0.dcache.ReadReq_misses::total 942620 # number of ReadReq misses 1209system.cpu0.dcache.WriteReq_misses::cpu0.data 258040 # number of WriteReq misses 1210system.cpu0.dcache.WriteReq_misses::total 258040 # number of WriteReq misses 1211system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13696 # number of LoadLockedReq misses 1212system.cpu0.dcache.LoadLockedReq_misses::total 13696 # number of LoadLockedReq misses 1213system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses 1214system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses 1215system.cpu0.dcache.demand_misses::cpu0.data 1200660 # number of demand (read+write) misses 1216system.cpu0.dcache.demand_misses::total 1200660 # number of demand (read+write) misses 1217system.cpu0.dcache.overall_misses::cpu0.data 1200660 # number of overall misses 1218system.cpu0.dcache.overall_misses::total 1200660 # number of overall misses 1219system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27232981250 # number of ReadReq miss cycles 1220system.cpu0.dcache.ReadReq_miss_latency::total 27232981250 # number of ReadReq miss cycles 1221system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10355566942 # number of WriteReq miss cycles 1222system.cpu0.dcache.WriteReq_miss_latency::total 10355566942 # number of WriteReq miss cycles 1223system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149859500 # number of LoadLockedReq miss cycles 1224system.cpu0.dcache.LoadLockedReq_miss_latency::total 149859500 # number of LoadLockedReq miss cycles 1225system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42011389 # number of StoreCondReq miss cycles 1226system.cpu0.dcache.StoreCondReq_miss_latency::total 42011389 # number of StoreCondReq miss cycles 1227system.cpu0.dcache.demand_miss_latency::cpu0.data 37588548192 # number of demand (read+write) miss cycles 1228system.cpu0.dcache.demand_miss_latency::total 37588548192 # number of demand (read+write) miss cycles 1229system.cpu0.dcache.overall_miss_latency::cpu0.data 37588548192 # number of overall miss cycles 1230system.cpu0.dcache.overall_miss_latency::total 37588548192 # number of overall miss cycles 1231system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420089 # number of ReadReq accesses(hits+misses) 1232system.cpu0.dcache.ReadReq_accesses::total 7420089 # number of ReadReq accesses(hits+misses) 1233system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989434 # number of WriteReq accesses(hits+misses) 1234system.cpu0.dcache.WriteReq_accesses::total 4989434 # number of WriteReq accesses(hits+misses) 1235system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155259 # number of LoadLockedReq accesses(hits+misses) 1236system.cpu0.dcache.LoadLockedReq_accesses::total 155259 # number of LoadLockedReq accesses(hits+misses) 1237system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154708 # number of StoreCondReq accesses(hits+misses) 1238system.cpu0.dcache.StoreCondReq_accesses::total 154708 # number of StoreCondReq accesses(hits+misses) 1239system.cpu0.dcache.demand_accesses::cpu0.data 12409523 # number of demand (read+write) accesses 1240system.cpu0.dcache.demand_accesses::total 12409523 # number of demand (read+write) accesses 1241system.cpu0.dcache.overall_accesses::cpu0.data 12409523 # number of overall (read+write) accesses 1242system.cpu0.dcache.overall_accesses::total 12409523 # number of overall (read+write) accesses 1243system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127036 # miss rate for ReadReq accesses 1244system.cpu0.dcache.ReadReq_miss_rate::total 0.127036 # miss rate for ReadReq accesses 1245system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051717 # miss rate for WriteReq accesses 1246system.cpu0.dcache.WriteReq_miss_rate::total 0.051717 # miss rate for WriteReq accesses 1247system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088214 # miss rate for LoadLockedReq accesses 1248system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088214 # miss rate for LoadLockedReq accesses 1249system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035241 # miss rate for StoreCondReq accesses 1250system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035241 # miss rate for StoreCondReq accesses 1251system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096753 # miss rate for demand accesses 1252system.cpu0.dcache.demand_miss_rate::total 0.096753 # miss rate for demand accesses 1253system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096753 # miss rate for overall accesses 1254system.cpu0.dcache.overall_miss_rate::total 0.096753 # miss rate for overall accesses 1255system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28890.731419 # average ReadReq miss latency 1256system.cpu0.dcache.ReadReq_avg_miss_latency::total 28890.731419 # average ReadReq miss latency 1257system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40131.634406 # average WriteReq miss latency 1258system.cpu0.dcache.WriteReq_avg_miss_latency::total 40131.634406 # average WriteReq miss latency 1259system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.844334 # average LoadLockedReq miss latency 1260system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.844334 # average LoadLockedReq miss latency 1261system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7705.683969 # average StoreCondReq miss latency 1262system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7705.683969 # average StoreCondReq miss latency 1263system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency 1264system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546 # average overall miss latency 1265system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency 1266system.cpu0.dcache.overall_avg_miss_latency::total 31306.571546 # average overall miss latency | 508system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses 509system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses 510system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits 511system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits 512system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits 513system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits 514system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits 515system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits 516system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits 517system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits 518system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits 519system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits 520system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits 521system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits 522system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses 523system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses 524system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses 525system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses 526system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses 527system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses 528system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # number of StoreCondReq misses 529system.cpu0.dcache.StoreCondReq_misses::total 5575 # number of StoreCondReq misses 530system.cpu0.dcache.demand_misses::cpu0.data 1199856 # number of demand (read+write) misses 531system.cpu0.dcache.demand_misses::total 1199856 # number of demand (read+write) misses 532system.cpu0.dcache.overall_misses::cpu0.data 1199856 # number of overall misses 533system.cpu0.dcache.overall_misses::total 1199856 # number of overall misses 534system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27226306250 # number of ReadReq miss cycles 535system.cpu0.dcache.ReadReq_miss_latency::total 27226306250 # number of ReadReq miss cycles 536system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10348541688 # number of WriteReq miss cycles 537system.cpu0.dcache.WriteReq_miss_latency::total 10348541688 # number of WriteReq miss cycles 538system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149709000 # number of LoadLockedReq miss cycles 539system.cpu0.dcache.LoadLockedReq_miss_latency::total 149709000 # number of LoadLockedReq miss cycles 540system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles 541system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles 542system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles 543system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles 544system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles 545system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles 546system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses) 547system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses) 548system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses) 549system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses) 550system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses) 551system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses) 552system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses) 553system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses) 554system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses 555system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses 556system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses 557system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses 558system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses 559system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses 560system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses 561system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses 562system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses 563system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses 564system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses 565system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses 566system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses 567system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses 568system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses 569system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses 570system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency 571system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency 572system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency 573system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency 574system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency 575system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency 576system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency 577system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency 578system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency 579system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency 580system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency 581system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency |
| 1267system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1268system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1269system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1270system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1271system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1272system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1273system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1274system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 582system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 583system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 584system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 585system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 586system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 587system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 588system.cpu0.dcache.fast_writes 0 # number of fast writes performed 589system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1275system.cpu0.dcache.writebacks::writebacks 686359 # number of writebacks 1276system.cpu0.dcache.writebacks::total 686359 # number of writebacks 1277system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942620 # number of ReadReq MSHR misses 1278system.cpu0.dcache.ReadReq_mshr_misses::total 942620 # number of ReadReq MSHR misses 1279system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258040 # number of WriteReq MSHR misses 1280system.cpu0.dcache.WriteReq_mshr_misses::total 258040 # number of WriteReq MSHR misses 1281system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13696 # number of LoadLockedReq MSHR misses 1282system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13696 # number of LoadLockedReq MSHR misses 1283system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses 1284system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses 1285system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200660 # number of demand (read+write) MSHR misses 1286system.cpu0.dcache.demand_mshr_misses::total 1200660 # number of demand (read+write) MSHR misses 1287system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200660 # number of overall MSHR misses 1288system.cpu0.dcache.overall_mshr_misses::total 1200660 # number of overall MSHR misses 1289system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25222171750 # number of ReadReq MSHR miss cycles 1290system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25222171750 # number of ReadReq MSHR miss cycles 1291system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9786377058 # number of WriteReq MSHR miss cycles 1292system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9786377058 # number of WriteReq MSHR miss cycles 1293system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122453500 # number of LoadLockedReq MSHR miss cycles 1294system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122453500 # number of LoadLockedReq MSHR miss cycles 1295system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31105611 # number of StoreCondReq MSHR miss cycles 1296system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31105611 # number of StoreCondReq MSHR miss cycles 1297system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35008548808 # number of demand (read+write) MSHR miss cycles 1298system.cpu0.dcache.demand_mshr_miss_latency::total 35008548808 # number of demand (read+write) MSHR miss cycles 1299system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35008548808 # number of overall MSHR miss cycles 1300system.cpu0.dcache.overall_mshr_miss_latency::total 35008548808 # number of overall MSHR miss cycles 1301system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465625500 # number of ReadReq MSHR uncacheable cycles 1302system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465625500 # number of ReadReq MSHR uncacheable cycles 1303system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2277904000 # number of WriteReq MSHR uncacheable cycles 1304system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2277904000 # number of WriteReq MSHR uncacheable cycles 1305system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3743529500 # number of overall MSHR uncacheable cycles 1306system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3743529500 # number of overall MSHR uncacheable cycles 1307system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127036 # mshr miss rate for ReadReq accesses 1308system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127036 # mshr miss rate for ReadReq accesses 1309system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051717 # mshr miss rate for WriteReq accesses 1310system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051717 # mshr miss rate for WriteReq accesses 1311system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088214 # mshr miss rate for LoadLockedReq accesses 1312system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088214 # mshr miss rate for LoadLockedReq accesses 1313system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035241 # mshr miss rate for StoreCondReq accesses 1314system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035241 # mshr miss rate for StoreCondReq accesses 1315system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for demand accesses 1316system.cpu0.dcache.demand_mshr_miss_rate::total 0.096753 # mshr miss rate for demand accesses 1317system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for overall accesses 1318system.cpu0.dcache.overall_mshr_miss_rate::total 0.096753 # mshr miss rate for overall accesses 1319system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141 # average ReadReq mshr miss latency 1320system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141 # average ReadReq mshr miss latency 1321system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052 # average WriteReq mshr miss latency 1322system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052 # average WriteReq mshr miss latency 1323system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.822138 # average LoadLockedReq mshr miss latency 1324system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.822138 # average LoadLockedReq mshr miss latency 1325system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5705.357850 # average StoreCondReq mshr miss latency 1326system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5705.357850 # average StoreCondReq mshr miss latency 1327system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency 1328system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency 1329system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency 1330system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency | 590system.cpu0.dcache.writebacks::writebacks 685854 # number of writebacks 591system.cpu0.dcache.writebacks::total 685854 # number of writebacks 592system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942246 # number of ReadReq MSHR misses 593system.cpu0.dcache.ReadReq_mshr_misses::total 942246 # number of ReadReq MSHR misses 594system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257610 # number of WriteReq MSHR misses 595system.cpu0.dcache.WriteReq_mshr_misses::total 257610 # number of WriteReq MSHR misses 596system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13707 # number of LoadLockedReq MSHR misses 597system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13707 # number of LoadLockedReq MSHR misses 598system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5575 # number of StoreCondReq MSHR misses 599system.cpu0.dcache.StoreCondReq_mshr_misses::total 5575 # number of StoreCondReq MSHR misses 600system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199856 # number of demand (read+write) MSHR misses 601system.cpu0.dcache.demand_mshr_misses::total 1199856 # number of demand (read+write) MSHR misses 602system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199856 # number of overall MSHR misses 603system.cpu0.dcache.overall_mshr_misses::total 1199856 # number of overall MSHR misses 604system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25216322750 # number of ReadReq MSHR miss cycles 605system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25216322750 # number of ReadReq MSHR miss cycles 606system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9780175312 # number of WriteReq MSHR miss cycles 607system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9780175312 # number of WriteReq MSHR miss cycles 608system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122281000 # number of LoadLockedReq MSHR miss cycles 609system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122281000 # number of LoadLockedReq MSHR miss cycles 610system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31509106 # number of StoreCondReq MSHR miss cycles 611system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31509106 # number of StoreCondReq MSHR miss cycles 612system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34996498062 # number of demand (read+write) MSHR miss cycles 613system.cpu0.dcache.demand_mshr_miss_latency::total 34996498062 # number of demand (read+write) MSHR miss cycles 614system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34996498062 # number of overall MSHR miss cycles 615system.cpu0.dcache.overall_mshr_miss_latency::total 34996498062 # number of overall MSHR miss cycles 616system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461499500 # number of ReadReq MSHR uncacheable cycles 617system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461499500 # number of ReadReq MSHR uncacheable cycles 618system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267126500 # number of WriteReq MSHR uncacheable cycles 619system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267126500 # number of WriteReq MSHR uncacheable cycles 620system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728626000 # number of overall MSHR uncacheable cycles 621system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728626000 # number of overall MSHR uncacheable cycles 622system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127457 # mshr miss rate for ReadReq accesses 623system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127457 # mshr miss rate for ReadReq accesses 624system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses 625system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses 626system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses 627system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses 628system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses 629system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses 630system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses 631system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses 632system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses 633system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses 634system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency 635system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency 636system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency 637system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency 638system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency 639system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency 640system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency 641system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency 642system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency 643system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency 644system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency 645system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency |
| 1331system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1332system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1333system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1334system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1335system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1336system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1337system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 646system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 648system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 649system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 650system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 651system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 652system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 653system.cpu0.icache.tags.replacements 699671 # number of replacements 654system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use 655system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks. 656system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks. 657system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks. 658system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. 659system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor 660system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy 661system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy 662system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 663system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 664system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 665system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id 666system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 667system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 668system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses 669system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses 670system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits 671system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits 672system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits 673system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits 674system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits 675system.cpu0.icache.overall_hits::total 47283349 # number of overall hits 676system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses 677system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses 678system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses 679system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses 680system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses 681system.cpu0.icache.overall_misses::total 700305 # number of overall misses 682system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles 683system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles 684system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles 685system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles 686system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles 687system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles 688system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses) 689system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses) 690system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses 691system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses 692system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses 693system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses 694system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses 695system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses 696system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses 697system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses 698system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses 699system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses 700system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency 701system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency 702system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency 703system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency 704system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency 705system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency 706system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 707system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 708system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 709system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 710system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 711system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 712system.cpu0.icache.fast_writes 0 # number of fast writes performed 713system.cpu0.icache.cache_copies 0 # number of cache copies performed 714system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses 715system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses 716system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses 717system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses 718system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses 719system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses 720system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles 721system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles 722system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles 723system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles 724system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles 725system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles 726system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses 727system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses 728system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses 729system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses 730system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses 731system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses 732system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency 733system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency 734system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency 735system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency 736system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency 737system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency 738system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 1338system.cpu1.dtb.fetch_hits 0 # ITB hits 1339system.cpu1.dtb.fetch_misses 0 # ITB misses 1340system.cpu1.dtb.fetch_acv 0 # ITB acv 1341system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 739system.cpu1.dtb.fetch_hits 0 # ITB hits 740system.cpu1.dtb.fetch_misses 0 # ITB misses 741system.cpu1.dtb.fetch_acv 0 # ITB acv 742system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1342system.cpu1.dtb.read_hits 2348280 # DTB read hits | 743system.cpu1.dtb.read_hits 2382379 # DTB read hits |
| 1343system.cpu1.dtb.read_misses 2620 # DTB read misses 1344system.cpu1.dtb.read_acv 0 # DTB read access violations 1345system.cpu1.dtb.read_accesses 205337 # DTB read accesses | 744system.cpu1.dtb.read_misses 2620 # DTB read misses 745system.cpu1.dtb.read_acv 0 # DTB read access violations 746system.cpu1.dtb.read_accesses 205337 # DTB read accesses |
| 1346system.cpu1.dtb.write_hits 1676993 # DTB write hits | 747system.cpu1.dtb.write_hits 1702197 # DTB write hits |
| 1347system.cpu1.dtb.write_misses 235 # DTB write misses 1348system.cpu1.dtb.write_acv 24 # DTB write access violations 1349system.cpu1.dtb.write_accesses 89739 # DTB write accesses | 748system.cpu1.dtb.write_misses 235 # DTB write misses 749system.cpu1.dtb.write_acv 24 # DTB write access violations 750system.cpu1.dtb.write_accesses 89739 # DTB write accesses |
| 1350system.cpu1.dtb.data_hits 4025273 # DTB hits | 751system.cpu1.dtb.data_hits 4084576 # DTB hits |
| 1351system.cpu1.dtb.data_misses 2855 # DTB misses 1352system.cpu1.dtb.data_acv 24 # DTB access violations 1353system.cpu1.dtb.data_accesses 295076 # DTB accesses | 752system.cpu1.dtb.data_misses 2855 # DTB misses 753system.cpu1.dtb.data_acv 24 # DTB access violations 754system.cpu1.dtb.data_accesses 295076 # DTB accesses |
| 1354system.cpu1.itb.fetch_hits 1801078 # ITB hits | 755system.cpu1.itb.fetch_hits 1808740 # ITB hits |
| 1355system.cpu1.itb.fetch_misses 1064 # ITB misses 1356system.cpu1.itb.fetch_acv 0 # ITB acv | 756system.cpu1.itb.fetch_misses 1064 # ITB misses 757system.cpu1.itb.fetch_acv 0 # ITB acv |
| 1357system.cpu1.itb.fetch_accesses 1802142 # ITB accesses | 758system.cpu1.itb.fetch_accesses 1809804 # ITB accesses |
| 1358system.cpu1.itb.read_hits 0 # DTB read hits 1359system.cpu1.itb.read_misses 0 # DTB read misses 1360system.cpu1.itb.read_acv 0 # DTB read access violations 1361system.cpu1.itb.read_accesses 0 # DTB read accesses 1362system.cpu1.itb.write_hits 0 # DTB write hits 1363system.cpu1.itb.write_misses 0 # DTB write misses 1364system.cpu1.itb.write_acv 0 # DTB write access violations 1365system.cpu1.itb.write_accesses 0 # DTB write accesses 1366system.cpu1.itb.data_hits 0 # DTB hits 1367system.cpu1.itb.data_misses 0 # DTB misses 1368system.cpu1.itb.data_acv 0 # DTB access violations 1369system.cpu1.itb.data_accesses 0 # DTB accesses | 759system.cpu1.itb.read_hits 0 # DTB read hits 760system.cpu1.itb.read_misses 0 # DTB read misses 761system.cpu1.itb.read_acv 0 # DTB read access violations 762system.cpu1.itb.read_accesses 0 # DTB read accesses 763system.cpu1.itb.write_hits 0 # DTB write hits 764system.cpu1.itb.write_misses 0 # DTB write misses 765system.cpu1.itb.write_acv 0 # DTB write access violations 766system.cpu1.itb.write_accesses 0 # DTB write accesses 767system.cpu1.itb.data_hits 0 # DTB hits 768system.cpu1.itb.data_misses 0 # DTB misses 769system.cpu1.itb.data_acv 0 # DTB access violations 770system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1370system.cpu1.numCycles 3921880878 # number of cpu cycles simulated | 771system.cpu1.numCycles 3923834014 # number of cpu cycles simulated |
| 1371system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1372system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 772system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 773system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1373system.cpu1.committedInsts 12764610 # Number of instructions committed 1374system.cpu1.committedOps 12764610 # Number of ops (including micro ops) committed 1375system.cpu1.num_int_alu_accesses 11762987 # Number of integer alu accesses 1376system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses 1377system.cpu1.num_func_calls 404048 # number of times a function call or return occured 1378system.cpu1.num_conditional_control_insts 1265459 # number of instructions that are conditional controls 1379system.cpu1.num_int_insts 11762987 # number of integer instructions 1380system.cpu1.num_fp_insts 170364 # number of float instructions 1381system.cpu1.num_int_register_reads 16177090 # number of times the integer registers were read 1382system.cpu1.num_int_register_writes 8656212 # number of times the integer registers were written 1383system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read 1384system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written 1385system.cpu1.num_mem_refs 4047820 # number of memory refs 1386system.cpu1.num_load_insts 2361802 # Number of load instructions 1387system.cpu1.num_store_insts 1686018 # Number of store instructions 1388system.cpu1.num_idle_cycles 3873240792.459649 # Number of idle cycles 1389system.cpu1.num_busy_cycles 48640085.540351 # Number of busy cycles 1390system.cpu1.not_idle_fraction 0.012402 # Percentage of non-idle cycles 1391system.cpu1.idle_fraction 0.987598 # Percentage of idle cycles 1392system.cpu1.Branches 1821460 # Number of branches fetched 1393system.cpu1.op_class::No_OpClass 690637 5.41% 5.41% # Class of executed instruction 1394system.cpu1.op_class::IntAlu 7566798 59.27% 64.68% # Class of executed instruction 1395system.cpu1.op_class::IntMult 21839 0.17% 64.85% # Class of executed instruction 1396system.cpu1.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction 1397system.cpu1.op_class::FloatAdd 13058 0.10% 64.95% # Class of executed instruction 1398system.cpu1.op_class::FloatCmp 0 0.00% 64.95% # Class of executed instruction 1399system.cpu1.op_class::FloatCvt 0 0.00% 64.95% # Class of executed instruction 1400system.cpu1.op_class::FloatMult 0 0.00% 64.95% # Class of executed instruction 1401system.cpu1.op_class::FloatDiv 1759 0.01% 64.96% # Class of executed instruction 1402system.cpu1.op_class::FloatSqrt 0 0.00% 64.96% # Class of executed instruction 1403system.cpu1.op_class::SimdAdd 0 0.00% 64.96% # Class of executed instruction 1404system.cpu1.op_class::SimdAddAcc 0 0.00% 64.96% # Class of executed instruction 1405system.cpu1.op_class::SimdAlu 0 0.00% 64.96% # Class of executed instruction 1406system.cpu1.op_class::SimdCmp 0 0.00% 64.96% # Class of executed instruction 1407system.cpu1.op_class::SimdCvt 0 0.00% 64.96% # Class of executed instruction 1408system.cpu1.op_class::SimdMisc 0 0.00% 64.96% # Class of executed instruction 1409system.cpu1.op_class::SimdMult 0 0.00% 64.96% # Class of executed instruction 1410system.cpu1.op_class::SimdMultAcc 0 0.00% 64.96% # Class of executed instruction 1411system.cpu1.op_class::SimdShift 0 0.00% 64.96% # Class of executed instruction 1412system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.96% # Class of executed instruction 1413system.cpu1.op_class::SimdSqrt 0 0.00% 64.96% # Class of executed instruction 1414system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.96% # Class of executed instruction 1415system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.96% # Class of executed instruction 1416system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.96% # Class of executed instruction 1417system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.96% # Class of executed instruction 1418system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.96% # Class of executed instruction 1419system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.96% # Class of executed instruction 1420system.cpu1.op_class::SimdFloatMult 0 0.00% 64.96% # Class of executed instruction 1421system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.96% # Class of executed instruction 1422system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.96% # Class of executed instruction 1423system.cpu1.op_class::MemRead 2432293 19.05% 84.01% # Class of executed instruction 1424system.cpu1.op_class::MemWrite 1686990 13.21% 97.23% # Class of executed instruction 1425system.cpu1.op_class::IprAccess 354115 2.77% 100.00% # Class of executed instruction | 774system.cpu1.committedInsts 12951032 # Number of instructions committed 775system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed 776system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses 777system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses 778system.cpu1.num_func_calls 411532 # number of times a function call or return occured 779system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls 780system.cpu1.num_int_insts 11936898 # number of integer instructions 781system.cpu1.num_fp_insts 171199 # number of float instructions 782system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read 783system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written 784system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read 785system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written 786system.cpu1.num_mem_refs 4107226 # number of memory refs 787system.cpu1.num_load_insts 2395961 # Number of load instructions 788system.cpu1.num_store_insts 1711265 # Number of store instructions 789system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles 790system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles 791system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles 792system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles 793system.cpu1.Branches 1849703 # Number of branches fetched 794system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction 795system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction 796system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction 797system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction 798system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction 799system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction 800system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction 801system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction 802system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction 803system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction 804system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction 805system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction 806system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction 807system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction 808system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction 809system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction 810system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction 811system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction 812system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction 813system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction 814system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction 815system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction 816system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction 817system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction 818system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction 819system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction 820system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction 821system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction 822system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction 823system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction 824system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction 825system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction 826system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction |
| 1426system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 827system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1427system.cpu1.op_class::total 12767489 # Class of executed instruction | 828system.cpu1.op_class::total 12953911 # Class of executed instruction |
| 1428system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 829system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1429system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed 1430system.cpu1.kern.inst.hwrei 77083 # number of hwrei instructions executed 1431system.cpu1.kern.ipl_count::0 26133 38.19% 38.19% # number of times we switched to this ipl 1432system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl 1433system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl 1434system.cpu1.kern.ipl_count::31 39822 58.19% 100.00% # number of times we switched to this ipl 1435system.cpu1.kern.ipl_count::total 68430 # number of times we switched to this ipl 1436system.cpu1.kern.ipl_good::0 25289 48.13% 48.13% # number of times we switched to this ipl from a different ipl 1437system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl 1438system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl 1439system.cpu1.kern.ipl_good::31 24783 47.16% 100.00% # number of times we switched to this ipl from a different ipl 1440system.cpu1.kern.ipl_good::total 52547 # number of times we switched to this ipl from a different ipl 1441system.cpu1.kern.ipl_ticks::0 1909614154000 97.38% 97.38% # number of cycles we spent at this ipl 1442system.cpu1.kern.ipl_ticks::22 700846000 0.04% 97.42% # number of cycles we spent at this ipl 1443system.cpu1.kern.ipl_ticks::30 353816000 0.02% 97.44% # number of cycles we spent at this ipl 1444system.cpu1.kern.ipl_ticks::31 50271593000 2.56% 100.00% # number of cycles we spent at this ipl 1445system.cpu1.kern.ipl_ticks::total 1960940409000 # number of cycles we spent at this ipl 1446system.cpu1.kern.ipl_used::0 0.967704 # fraction of swpipl calls that actually changed the ipl | 830system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed 831system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed 832system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl 833system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl 834system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl 835system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl 836system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl 837system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl 838system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl 839system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl 840system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl 841system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl 842system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl 843system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl 844system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl 845system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl 846system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl 847system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl |
| 1447system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1448system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 848system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 849system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1449system.cpu1.kern.ipl_used::31 0.622344 # fraction of swpipl calls that actually changed the ipl 1450system.cpu1.kern.ipl_used::total 0.767894 # fraction of swpipl calls that actually changed the ipl | 850system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl 851system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl |
| 1451system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 1452system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 1453system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 1454system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 1455system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 1456system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 1457system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 1458system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 1459system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 1460system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 1461system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 1462system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 1463system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 1464system.cpu1.kern.syscall::total 92 # number of syscalls executed 1465system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 852system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 853system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 854system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 855system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 856system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 857system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 858system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 859system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 860system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 861system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 862system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 863system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 864system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 865system.cpu1.kern.syscall::total 92 # number of syscalls executed 866system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1466system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed | 867system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed |
| 1467system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed 1468system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed | 868system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed 869system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed |
| 1469system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed 1470system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed 1471system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed 1472system.cpu1.kern.callpal::swpipl 62269 88.12% 91.51% # number of callpals executed 1473system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed 1474system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed 1475system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed 1476system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed 1477system.cpu1.kern.callpal::rti 3685 5.21% 99.77% # number of callpals executed | 870system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed 871system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed 872system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed 873system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed 874system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed 875system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed 876system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed 877system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed 878system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed |
| 1478system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed 1479system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed 1480system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 879system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed 880system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed 881system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1481system.cpu1.kern.callpal::total 70663 # number of callpals executed 1482system.cpu1.kern.mode_switch::kernel 1918 # number of protection mode switches | 882system.cpu1.kern.callpal::total 71465 # number of callpals executed 883system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches |
| 1483system.cpu1.kern.mode_switch::user 367 # number of protection mode switches | 884system.cpu1.kern.mode_switch::user 367 # number of protection mode switches |
| 1484system.cpu1.kern.mode_switch::idle 2888 # number of protection mode switches 1485system.cpu1.kern.mode_good::kernel 797 | 885system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches 886system.cpu1.kern.mode_good::kernel 803 |
| 1486system.cpu1.kern.mode_good::user 367 | 887system.cpu1.kern.mode_good::user 367 |
| 1487system.cpu1.kern.mode_good::idle 430 1488system.cpu1.kern.mode_switch_good::kernel 0.415537 # fraction of useful protection mode switches | 888system.cpu1.kern.mode_good::idle 436 889system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches |
| 1489system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 890system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1490system.cpu1.kern.mode_switch_good::idle 0.148892 # fraction of useful protection mode switches 1491system.cpu1.kern.mode_switch_good::total 0.308138 # fraction of useful protection mode switches 1492system.cpu1.kern.mode_ticks::kernel 17565031500 0.90% 0.90% # number of ticks spent at the given mode 1493system.cpu1.kern.mode_ticks::user 1483893000 0.08% 0.97% # number of ticks spent at the given mode 1494system.cpu1.kern.mode_ticks::idle 1941003590000 99.03% 100.00% # number of ticks spent at the given mode 1495system.cpu1.kern.swap_context 1956 # number of times the context was actually changed 1496system.cpu1.icache.tags.replacements 311453 # number of replacements 1497system.cpu1.icache.tags.tagsinuse 446.345950 # Cycle average of tags in use 1498system.cpu1.icache.tags.total_refs 12455485 # Total number of references to valid blocks. 1499system.cpu1.icache.tags.sampled_refs 311964 # Sample count of references to valid blocks. 1500system.cpu1.icache.tags.avg_refs 39.926033 # Average number of references to valid blocks. 1501system.cpu1.icache.tags.warmup_cycle 1960014862500 # Cycle when the warmup percentage was hit. 1502system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.345950 # Average occupied blocks per requestor 1503system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871769 # Average percentage of cache occupancy 1504system.cpu1.icache.tags.occ_percent::total 0.871769 # Average percentage of cache occupancy 1505system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1506system.cpu1.icache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id 1507system.cpu1.icache.tags.age_task_id_blocks_1024::3 440 # Occupied blocks per task id 1508system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1509system.cpu1.icache.tags.tag_accesses 13079493 # Number of tag accesses 1510system.cpu1.icache.tags.data_accesses 13079493 # Number of data accesses 1511system.cpu1.icache.ReadReq_hits::cpu1.inst 12455485 # number of ReadReq hits 1512system.cpu1.icache.ReadReq_hits::total 12455485 # number of ReadReq hits 1513system.cpu1.icache.demand_hits::cpu1.inst 12455485 # number of demand (read+write) hits 1514system.cpu1.icache.demand_hits::total 12455485 # number of demand (read+write) hits 1515system.cpu1.icache.overall_hits::cpu1.inst 12455485 # number of overall hits 1516system.cpu1.icache.overall_hits::total 12455485 # number of overall hits 1517system.cpu1.icache.ReadReq_misses::cpu1.inst 312004 # number of ReadReq misses 1518system.cpu1.icache.ReadReq_misses::total 312004 # number of ReadReq misses 1519system.cpu1.icache.demand_misses::cpu1.inst 312004 # number of demand (read+write) misses 1520system.cpu1.icache.demand_misses::total 312004 # number of demand (read+write) misses 1521system.cpu1.icache.overall_misses::cpu1.inst 312004 # number of overall misses 1522system.cpu1.icache.overall_misses::total 312004 # number of overall misses 1523system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4105450991 # number of ReadReq miss cycles 1524system.cpu1.icache.ReadReq_miss_latency::total 4105450991 # number of ReadReq miss cycles 1525system.cpu1.icache.demand_miss_latency::cpu1.inst 4105450991 # number of demand (read+write) miss cycles 1526system.cpu1.icache.demand_miss_latency::total 4105450991 # number of demand (read+write) miss cycles 1527system.cpu1.icache.overall_miss_latency::cpu1.inst 4105450991 # number of overall miss cycles 1528system.cpu1.icache.overall_miss_latency::total 4105450991 # number of overall miss cycles 1529system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767489 # number of ReadReq accesses(hits+misses) 1530system.cpu1.icache.ReadReq_accesses::total 12767489 # number of ReadReq accesses(hits+misses) 1531system.cpu1.icache.demand_accesses::cpu1.inst 12767489 # number of demand (read+write) accesses 1532system.cpu1.icache.demand_accesses::total 12767489 # number of demand (read+write) accesses 1533system.cpu1.icache.overall_accesses::cpu1.inst 12767489 # number of overall (read+write) accesses 1534system.cpu1.icache.overall_accesses::total 12767489 # number of overall (read+write) accesses 1535system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024437 # miss rate for ReadReq accesses 1536system.cpu1.icache.ReadReq_miss_rate::total 0.024437 # miss rate for ReadReq accesses 1537system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024437 # miss rate for demand accesses 1538system.cpu1.icache.demand_miss_rate::total 0.024437 # miss rate for demand accesses 1539system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024437 # miss rate for overall accesses 1540system.cpu1.icache.overall_miss_rate::total 0.024437 # miss rate for overall accesses 1541system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13158.328070 # average ReadReq miss latency 1542system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070 # average ReadReq miss latency 1543system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency 1544system.cpu1.icache.demand_avg_miss_latency::total 13158.328070 # average overall miss latency 1545system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency 1546system.cpu1.icache.overall_avg_miss_latency::total 13158.328070 # average overall miss latency 1547system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1548system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1549system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1550system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1551system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1552system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1553system.cpu1.icache.fast_writes 0 # number of fast writes performed 1554system.cpu1.icache.cache_copies 0 # number of cache copies performed 1555system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312004 # number of ReadReq MSHR misses 1556system.cpu1.icache.ReadReq_mshr_misses::total 312004 # number of ReadReq MSHR misses 1557system.cpu1.icache.demand_mshr_misses::cpu1.inst 312004 # number of demand (read+write) MSHR misses 1558system.cpu1.icache.demand_mshr_misses::total 312004 # number of demand (read+write) MSHR misses 1559system.cpu1.icache.overall_mshr_misses::cpu1.inst 312004 # number of overall MSHR misses 1560system.cpu1.icache.overall_mshr_misses::total 312004 # number of overall MSHR misses 1561system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3481247009 # number of ReadReq MSHR miss cycles 1562system.cpu1.icache.ReadReq_mshr_miss_latency::total 3481247009 # number of ReadReq MSHR miss cycles 1563system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3481247009 # number of demand (read+write) MSHR miss cycles 1564system.cpu1.icache.demand_mshr_miss_latency::total 3481247009 # number of demand (read+write) MSHR miss cycles 1565system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3481247009 # number of overall MSHR miss cycles 1566system.cpu1.icache.overall_mshr_miss_latency::total 3481247009 # number of overall MSHR miss cycles 1567system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for ReadReq accesses 1568system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024437 # mshr miss rate for ReadReq accesses 1569system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for demand accesses 1570system.cpu1.icache.demand_mshr_miss_rate::total 0.024437 # mshr miss rate for demand accesses 1571system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for overall accesses 1572system.cpu1.icache.overall_mshr_miss_rate::total 0.024437 # mshr miss rate for overall accesses 1573system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average ReadReq mshr miss latency 1574system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930 # average ReadReq mshr miss latency 1575system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency 1576system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency 1577system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency 1578system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency 1579system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1580system.cpu1.dcache.tags.replacements 155174 # number of replacements 1581system.cpu1.dcache.tags.tagsinuse 486.308424 # Cycle average of tags in use 1582system.cpu1.dcache.tags.total_refs 3855056 # Total number of references to valid blocks. 1583system.cpu1.dcache.tags.sampled_refs 155503 # Sample count of references to valid blocks. 1584system.cpu1.dcache.tags.avg_refs 24.790879 # Average number of references to valid blocks. | 891system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches 892system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches 893system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode 894system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode 895system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode 896system.cpu1.kern.swap_context 1968 # number of times the context was actually changed 897system.cpu1.dcache.tags.replacements 157269 # number of replacements 898system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use 899system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks. 900system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks. 901system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks. |
| 1585system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. | 902system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. |
| 1586system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308424 # Average occupied blocks per requestor 1587system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949821 # Average percentage of cache occupancy 1588system.cpu1.dcache.tags.occ_percent::total 0.949821 # Average percentage of cache occupancy 1589system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id | 903system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor 904system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy 905system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy 906system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id |
| 1590system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id | 907system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id |
| 1591system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id 1592system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id 1593system.cpu1.dcache.tags.tag_accesses 16322131 # Number of tag accesses 1594system.cpu1.dcache.tags.data_accesses 16322131 # Number of data accesses 1595system.cpu1.dcache.ReadReq_hits::cpu1.data 2189503 # number of ReadReq hits 1596system.cpu1.dcache.ReadReq_hits::total 2189503 # number of ReadReq hits 1597system.cpu1.dcache.WriteReq_hits::cpu1.data 1567525 # number of WriteReq hits 1598system.cpu1.dcache.WriteReq_hits::total 1567525 # number of WriteReq hits 1599system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46972 # number of LoadLockedReq hits 1600system.cpu1.dcache.LoadLockedReq_hits::total 46972 # number of LoadLockedReq hits 1601system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49481 # number of StoreCondReq hits 1602system.cpu1.dcache.StoreCondReq_hits::total 49481 # number of StoreCondReq hits 1603system.cpu1.dcache.demand_hits::cpu1.data 3757028 # number of demand (read+write) hits 1604system.cpu1.dcache.demand_hits::total 3757028 # number of demand (read+write) hits 1605system.cpu1.dcache.overall_hits::cpu1.data 3757028 # number of overall hits 1606system.cpu1.dcache.overall_hits::total 3757028 # number of overall hits 1607system.cpu1.dcache.ReadReq_misses::cpu1.data 113756 # number of ReadReq misses 1608system.cpu1.dcache.ReadReq_misses::total 113756 # number of ReadReq misses 1609system.cpu1.dcache.WriteReq_misses::cpu1.data 55958 # number of WriteReq misses 1610system.cpu1.dcache.WriteReq_misses::total 55958 # number of WriteReq misses 1611system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8862 # number of LoadLockedReq misses 1612system.cpu1.dcache.LoadLockedReq_misses::total 8862 # number of LoadLockedReq misses 1613system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5884 # number of StoreCondReq misses 1614system.cpu1.dcache.StoreCondReq_misses::total 5884 # number of StoreCondReq misses 1615system.cpu1.dcache.demand_misses::cpu1.data 169714 # number of demand (read+write) misses 1616system.cpu1.dcache.demand_misses::total 169714 # number of demand (read+write) misses 1617system.cpu1.dcache.overall_misses::cpu1.data 169714 # number of overall misses 1618system.cpu1.dcache.overall_misses::total 169714 # number of overall misses 1619system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1372027750 # number of ReadReq miss cycles 1620system.cpu1.dcache.ReadReq_miss_latency::total 1372027750 # number of ReadReq miss cycles 1621system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1020320505 # number of WriteReq miss cycles 1622system.cpu1.dcache.WriteReq_miss_latency::total 1020320505 # number of WriteReq miss cycles 1623system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80442000 # number of LoadLockedReq miss cycles 1624system.cpu1.dcache.LoadLockedReq_miss_latency::total 80442000 # number of LoadLockedReq miss cycles 1625system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43305909 # number of StoreCondReq miss cycles 1626system.cpu1.dcache.StoreCondReq_miss_latency::total 43305909 # number of StoreCondReq miss cycles 1627system.cpu1.dcache.demand_miss_latency::cpu1.data 2392348255 # number of demand (read+write) miss cycles 1628system.cpu1.dcache.demand_miss_latency::total 2392348255 # number of demand (read+write) miss cycles 1629system.cpu1.dcache.overall_miss_latency::cpu1.data 2392348255 # number of overall miss cycles 1630system.cpu1.dcache.overall_miss_latency::total 2392348255 # number of overall miss cycles 1631system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303259 # number of ReadReq accesses(hits+misses) 1632system.cpu1.dcache.ReadReq_accesses::total 2303259 # number of ReadReq accesses(hits+misses) 1633system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623483 # number of WriteReq accesses(hits+misses) 1634system.cpu1.dcache.WriteReq_accesses::total 1623483 # number of WriteReq accesses(hits+misses) 1635system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55834 # number of LoadLockedReq accesses(hits+misses) 1636system.cpu1.dcache.LoadLockedReq_accesses::total 55834 # number of LoadLockedReq accesses(hits+misses) 1637system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55365 # number of StoreCondReq accesses(hits+misses) 1638system.cpu1.dcache.StoreCondReq_accesses::total 55365 # number of StoreCondReq accesses(hits+misses) 1639system.cpu1.dcache.demand_accesses::cpu1.data 3926742 # number of demand (read+write) accesses 1640system.cpu1.dcache.demand_accesses::total 3926742 # number of demand (read+write) accesses 1641system.cpu1.dcache.overall_accesses::cpu1.data 3926742 # number of overall (read+write) accesses 1642system.cpu1.dcache.overall_accesses::total 3926742 # number of overall (read+write) accesses 1643system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049389 # miss rate for ReadReq accesses 1644system.cpu1.dcache.ReadReq_miss_rate::total 0.049389 # miss rate for ReadReq accesses 1645system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034468 # miss rate for WriteReq accesses 1646system.cpu1.dcache.WriteReq_miss_rate::total 0.034468 # miss rate for WriteReq accesses 1647system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158720 # miss rate for LoadLockedReq accesses 1648system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158720 # miss rate for LoadLockedReq accesses 1649system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106277 # miss rate for StoreCondReq accesses 1650system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106277 # miss rate for StoreCondReq accesses 1651system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043220 # miss rate for demand accesses 1652system.cpu1.dcache.demand_miss_rate::total 0.043220 # miss rate for demand accesses 1653system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043220 # miss rate for overall accesses 1654system.cpu1.dcache.overall_miss_rate::total 0.043220 # miss rate for overall accesses 1655system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225 # average ReadReq miss latency 1656system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225 # average ReadReq miss latency 1657system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18233.684281 # average WriteReq miss latency 1658system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281 # average WriteReq miss latency 1659system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9077.183480 # average LoadLockedReq miss latency 1660system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9077.183480 # average LoadLockedReq miss latency 1661system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7359.943746 # average StoreCondReq miss latency 1662system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7359.943746 # average StoreCondReq miss latency 1663system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency 1664system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833 # average overall miss latency 1665system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency 1666system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833 # average overall miss latency | 908system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id 909system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id 910system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses 911system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses 912system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits 913system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits 914system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits 915system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits 916system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits 917system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits 918system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits 919system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits 920system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits 921system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits 922system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits 923system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits 924system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses 925system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses 926system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses 927system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses 928system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses 929system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses 930system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses 931system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses 932system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses 933system.cpu1.dcache.demand_misses::total 172223 # number of demand (read+write) misses 934system.cpu1.dcache.overall_misses::cpu1.data 172223 # number of overall misses 935system.cpu1.dcache.overall_misses::total 172223 # number of overall misses 936system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1389994499 # number of ReadReq miss cycles 937system.cpu1.dcache.ReadReq_miss_latency::total 1389994499 # number of ReadReq miss cycles 938system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079772299 # number of WriteReq miss cycles 939system.cpu1.dcache.WriteReq_miss_latency::total 1079772299 # number of WriteReq miss cycles 940system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80592000 # number of LoadLockedReq miss cycles 941system.cpu1.dcache.LoadLockedReq_miss_latency::total 80592000 # number of LoadLockedReq miss cycles 942system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43791416 # number of StoreCondReq miss cycles 943system.cpu1.dcache.StoreCondReq_miss_latency::total 43791416 # number of StoreCondReq miss cycles 944system.cpu1.dcache.demand_miss_latency::cpu1.data 2469766798 # number of demand (read+write) miss cycles 945system.cpu1.dcache.demand_miss_latency::total 2469766798 # number of demand (read+write) miss cycles 946system.cpu1.dcache.overall_miss_latency::cpu1.data 2469766798 # number of overall miss cycles 947system.cpu1.dcache.overall_miss_latency::total 2469766798 # number of overall miss cycles 948system.cpu1.dcache.ReadReq_accesses::cpu1.data 2336551 # number of ReadReq accesses(hits+misses) 949system.cpu1.dcache.ReadReq_accesses::total 2336551 # number of ReadReq accesses(hits+misses) 950system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647801 # number of WriteReq accesses(hits+misses) 951system.cpu1.dcache.WriteReq_accesses::total 1647801 # number of WriteReq accesses(hits+misses) 952system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56677 # number of LoadLockedReq accesses(hits+misses) 953system.cpu1.dcache.LoadLockedReq_accesses::total 56677 # number of LoadLockedReq accesses(hits+misses) 954system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56202 # number of StoreCondReq accesses(hits+misses) 955system.cpu1.dcache.StoreCondReq_accesses::total 56202 # number of StoreCondReq accesses(hits+misses) 956system.cpu1.dcache.demand_accesses::cpu1.data 3984352 # number of demand (read+write) accesses 957system.cpu1.dcache.demand_accesses::total 3984352 # number of demand (read+write) accesses 958system.cpu1.dcache.overall_accesses::cpu1.data 3984352 # number of overall (read+write) accesses 959system.cpu1.dcache.overall_accesses::total 3984352 # number of overall (read+write) accesses 960system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049259 # miss rate for ReadReq accesses 961system.cpu1.dcache.ReadReq_miss_rate::total 0.049259 # miss rate for ReadReq accesses 962system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034668 # miss rate for WriteReq accesses 963system.cpu1.dcache.WriteReq_miss_rate::total 0.034668 # miss rate for WriteReq accesses 964system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157065 # miss rate for LoadLockedReq accesses 965system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157065 # miss rate for LoadLockedReq accesses 966system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106082 # miss rate for StoreCondReq accesses 967system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106082 # miss rate for StoreCondReq accesses 968system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043225 # miss rate for demand accesses 969system.cpu1.dcache.demand_miss_rate::total 0.043225 # miss rate for demand accesses 970system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043225 # miss rate for overall accesses 971system.cpu1.dcache.overall_miss_rate::total 0.043225 # miss rate for overall accesses 972system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12076.722234 # average ReadReq miss latency 973system.cpu1.dcache.ReadReq_avg_miss_latency::total 12076.722234 # average ReadReq miss latency 974system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18901.591202 # average WriteReq miss latency 975system.cpu1.dcache.WriteReq_avg_miss_latency::total 18901.591202 # average WriteReq miss latency 976system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9053.246461 # average LoadLockedReq miss latency 977system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9053.246461 # average LoadLockedReq miss latency 978system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7345.088225 # average StoreCondReq miss latency 979system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7345.088225 # average StoreCondReq miss latency 980system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency 981system.cpu1.dcache.demand_avg_miss_latency::total 14340.516644 # average overall miss latency 982system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency 983system.cpu1.dcache.overall_avg_miss_latency::total 14340.516644 # average overall miss latency |
| 1667system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1668system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1669system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1670system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1671system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1672system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1673system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1674system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 984system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 985system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 986system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 987system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 988system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 989system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 990system.cpu1.dcache.fast_writes 0 # number of fast writes performed 991system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1675system.cpu1.dcache.writebacks::writebacks 106457 # number of writebacks 1676system.cpu1.dcache.writebacks::total 106457 # number of writebacks 1677system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113756 # number of ReadReq MSHR misses 1678system.cpu1.dcache.ReadReq_mshr_misses::total 113756 # number of ReadReq MSHR misses 1679system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55958 # number of WriteReq MSHR misses 1680system.cpu1.dcache.WriteReq_mshr_misses::total 55958 # number of WriteReq MSHR misses 1681system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8862 # number of LoadLockedReq MSHR misses 1682system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8862 # number of LoadLockedReq MSHR misses 1683system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5884 # number of StoreCondReq MSHR misses 1684system.cpu1.dcache.StoreCondReq_mshr_misses::total 5884 # number of StoreCondReq MSHR misses 1685system.cpu1.dcache.demand_mshr_misses::cpu1.data 169714 # number of demand (read+write) MSHR misses 1686system.cpu1.dcache.demand_mshr_misses::total 169714 # number of demand (read+write) MSHR misses 1687system.cpu1.dcache.overall_mshr_misses::cpu1.data 169714 # number of overall MSHR misses 1688system.cpu1.dcache.overall_mshr_misses::total 169714 # number of overall MSHR misses 1689system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144439250 # number of ReadReq MSHR miss cycles 1690system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144439250 # number of ReadReq MSHR miss cycles 1691system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 906162495 # number of WriteReq MSHR miss cycles 1692system.cpu1.dcache.WriteReq_mshr_miss_latency::total 906162495 # number of WriteReq MSHR miss cycles 1693system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62718000 # number of LoadLockedReq MSHR miss cycles 1694system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62718000 # number of LoadLockedReq MSHR miss cycles 1695system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31536091 # number of StoreCondReq MSHR miss cycles 1696system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31536091 # number of StoreCondReq MSHR miss cycles 1697system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2050601745 # number of demand (read+write) MSHR miss cycles 1698system.cpu1.dcache.demand_mshr_miss_latency::total 2050601745 # number of demand (read+write) MSHR miss cycles 1699system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2050601745 # number of overall MSHR miss cycles 1700system.cpu1.dcache.overall_mshr_miss_latency::total 2050601745 # number of overall MSHR miss cycles 1701system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18765500 # number of ReadReq MSHR uncacheable cycles 1702system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18765500 # number of ReadReq MSHR uncacheable cycles 1703system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713325000 # number of WriteReq MSHR uncacheable cycles 1704system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713325000 # number of WriteReq MSHR uncacheable cycles 1705system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732090500 # number of overall MSHR uncacheable cycles 1706system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732090500 # number of overall MSHR uncacheable cycles 1707system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049389 # mshr miss rate for ReadReq accesses 1708system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049389 # mshr miss rate for ReadReq accesses 1709system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034468 # mshr miss rate for WriteReq accesses 1710system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034468 # mshr miss rate for WriteReq accesses 1711system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158720 # mshr miss rate for LoadLockedReq accesses 1712system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158720 # mshr miss rate for LoadLockedReq accesses 1713system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106277 # mshr miss rate for StoreCondReq accesses 1714system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106277 # mshr miss rate for StoreCondReq accesses 1715system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for demand accesses 1716system.cpu1.dcache.demand_mshr_miss_rate::total 0.043220 # mshr miss rate for demand accesses 1717system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for overall accesses 1718system.cpu1.dcache.overall_mshr_miss_rate::total 0.043220 # mshr miss rate for overall accesses 1719system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733 # average ReadReq mshr miss latency 1720system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733 # average ReadReq mshr miss latency 1721system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339 # average WriteReq mshr miss latency 1722system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339 # average WriteReq mshr miss latency 1723system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7077.183480 # average LoadLockedReq mshr miss latency 1724system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7077.183480 # average LoadLockedReq mshr miss latency 1725system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5359.634772 # average StoreCondReq mshr miss latency 1726system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5359.634772 # average StoreCondReq mshr miss latency 1727system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency 1728system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency 1729system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency 1730system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency | 992system.cpu1.dcache.writebacks::writebacks 107940 # number of writebacks 993system.cpu1.dcache.writebacks::total 107940 # number of writebacks 994system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses 995system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses 996system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57126 # number of WriteReq MSHR misses 997system.cpu1.dcache.WriteReq_mshr_misses::total 57126 # number of WriteReq MSHR misses 998system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8902 # number of LoadLockedReq MSHR misses 999system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8902 # number of LoadLockedReq MSHR misses 1000system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5962 # number of StoreCondReq MSHR misses 1001system.cpu1.dcache.StoreCondReq_mshr_misses::total 5962 # number of StoreCondReq MSHR misses 1002system.cpu1.dcache.demand_mshr_misses::cpu1.data 172223 # number of demand (read+write) MSHR misses 1003system.cpu1.dcache.demand_mshr_misses::total 172223 # number of demand (read+write) MSHR misses 1004system.cpu1.dcache.overall_mshr_misses::cpu1.data 172223 # number of overall MSHR misses 1005system.cpu1.dcache.overall_mshr_misses::total 172223 # number of overall MSHR misses 1006system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1159712501 # number of ReadReq MSHR miss cycles 1007system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1159712501 # number of ReadReq MSHR miss cycles 1008system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962952701 # number of WriteReq MSHR miss cycles 1009system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962952701 # number of WriteReq MSHR miss cycles 1010system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62788000 # number of LoadLockedReq MSHR miss cycles 1011system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62788000 # number of LoadLockedReq MSHR miss cycles 1012system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31865584 # number of StoreCondReq MSHR miss cycles 1013system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31865584 # number of StoreCondReq MSHR miss cycles 1014system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2122665202 # number of demand (read+write) MSHR miss cycles 1015system.cpu1.dcache.demand_mshr_miss_latency::total 2122665202 # number of demand (read+write) MSHR miss cycles 1016system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2122665202 # number of overall MSHR miss cycles 1017system.cpu1.dcache.overall_mshr_miss_latency::total 2122665202 # number of overall MSHR miss cycles 1018system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles 1019system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles 1020system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726758000 # number of WriteReq MSHR uncacheable cycles 1021system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726758000 # number of WriteReq MSHR uncacheable cycles 1022system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749204500 # number of overall MSHR uncacheable cycles 1023system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749204500 # number of overall MSHR uncacheable cycles 1024system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for ReadReq accesses 1025system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049259 # mshr miss rate for ReadReq accesses 1026system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034668 # mshr miss rate for WriteReq accesses 1027system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034668 # mshr miss rate for WriteReq accesses 1028system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157065 # mshr miss rate for LoadLockedReq accesses 1029system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157065 # mshr miss rate for LoadLockedReq accesses 1030system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106082 # mshr miss rate for StoreCondReq accesses 1031system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106082 # mshr miss rate for StoreCondReq accesses 1032system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for demand accesses 1033system.cpu1.dcache.demand_mshr_miss_rate::total 0.043225 # mshr miss rate for demand accesses 1034system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for overall accesses 1035system.cpu1.dcache.overall_mshr_miss_rate::total 0.043225 # mshr miss rate for overall accesses 1036system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679 # average ReadReq mshr miss latency 1037system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679 # average ReadReq mshr miss latency 1038system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978 # average WriteReq mshr miss latency 1039system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978 # average WriteReq mshr miss latency 1040system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7053.246461 # average LoadLockedReq mshr miss latency 1041system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7053.246461 # average LoadLockedReq mshr miss latency 1042system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.780946 # average StoreCondReq mshr miss latency 1043system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.780946 # average StoreCondReq mshr miss latency 1044system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency 1045system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency 1046system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency 1047system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency |
| 1731system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1732system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1733system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1734system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1735system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1736system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1737system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1048system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1049system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1050system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1051system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1052system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1053system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1054system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1055system.cpu1.icache.tags.replacements 318302 # number of replacements 1056system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use 1057system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks. 1058system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks. 1059system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks. 1060system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit. 1061system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor 1062system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy 1063system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy 1064system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1065system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 1066system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id 1067system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 1068system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1069system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses 1070system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses 1071system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits 1072system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits 1073system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits 1074system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits 1075system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits 1076system.cpu1.icache.overall_hits::total 12635057 # number of overall hits 1077system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses 1078system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses 1079system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses 1080system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses 1081system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses 1082system.cpu1.icache.overall_misses::total 318854 # number of overall misses 1083system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles 1084system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles 1085system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles 1086system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles 1087system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles 1088system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles 1089system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses) 1090system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses) 1091system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses 1092system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses 1093system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses 1094system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses 1095system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses 1096system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses 1097system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses 1098system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses 1099system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses 1100system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses 1101system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency 1102system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency 1103system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency 1104system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency 1105system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency 1106system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency 1107system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1108system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1109system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1110system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1111system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1112system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1113system.cpu1.icache.fast_writes 0 # number of fast writes performed 1114system.cpu1.icache.cache_copies 0 # number of cache copies performed 1115system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses 1116system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses 1117system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses 1118system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses 1119system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses 1120system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses 1121system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles 1122system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles 1123system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles 1124system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles 1125system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles 1126system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles 1127system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses 1128system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses 1129system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses 1130system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses 1131system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses 1132system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses 1133system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency 1134system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency 1135system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency 1136system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency 1137system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency 1138system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency 1139system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1140system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1141system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1142system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1143system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1144system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1145system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1146system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1147system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1148system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1149system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1150system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1151system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1152system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1153system.iobus.trans_dist::ReadResp 7373 # Transaction distribution 1154system.iobus.trans_dist::WriteReq 55631 # Transaction distribution 1155system.iobus.trans_dist::WriteResp 14079 # Transaction distribution 1156system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 1157system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes) 1158system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 1159system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1160system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1161system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes) 1174system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 1175system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1176system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1177system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1178system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1179system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1180system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1181system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks) 1190system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1191system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 1192system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1193system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1194system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1195system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1196system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1197system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 1198system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1199system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) 1200system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1201system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks) 1202system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1203system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1204system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1205system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1206system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1207system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1208system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1209system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1210system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1211system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks) 1212system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1213system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1214system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1215system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks) 1216system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1217system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) 1218system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1219system.iocache.tags.replacements 41696 # number of replacements 1220system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use 1221system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1222system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. 1223system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1224system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit. 1225system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor 1226system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy 1227system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy 1228system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1229system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1230system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1231system.iocache.tags.tag_accesses 375552 # Number of tag accesses 1232system.iocache.tags.data_accesses 375552 # Number of data accesses 1233system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 1234system.iocache.ReadReq_misses::total 176 # number of ReadReq misses 1235system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 1236system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 1237system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses 1238system.iocache.demand_misses::total 176 # number of demand (read+write) misses 1239system.iocache.overall_misses::tsunami.ide 176 # number of overall misses 1240system.iocache.overall_misses::total 176 # number of overall misses 1241system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles 1242system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles 1243system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles 1244system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles 1245system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles 1246system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles 1247system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles 1248system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles 1249system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 1250system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) 1251system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 1252system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 1253system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses 1254system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses 1255system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses 1256system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses 1257system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1258system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1259system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 1260system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1261system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1262system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1263system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1264system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1265system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency 1266system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency 1267system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency 1268system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency 1269system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency 1270system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency 1271system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency 1272system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency 1273system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked 1274system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1275system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked 1276system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1277system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked 1278system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1279system.iocache.fast_writes 0 # number of fast writes performed 1280system.iocache.cache_copies 0 # number of cache copies performed 1281system.iocache.writebacks::writebacks 41520 # number of writebacks 1282system.iocache.writebacks::total 41520 # number of writebacks 1283system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 1284system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses 1285system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 1286system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 1287system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses 1288system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses 1289system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses 1290system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses 1291system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles 1292system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles 1293system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles 1294system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles 1295system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles 1296system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles 1297system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles 1298system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles 1299system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1300system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1301system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1302system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1303system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1304system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1305system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1306system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1307system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency 1308system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency 1309system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency 1310system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383 # average WriteInvalidateReq mshr miss latency 1311system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency 1312system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency 1313system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency 1314system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency 1315system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1316system.l2c.tags.replacements 342754 # number of replacements 1317system.l2c.tags.tagsinuse 65220.433043 # Cycle average of tags in use 1318system.l2c.tags.total_refs 2449371 # Total number of references to valid blocks. 1319system.l2c.tags.sampled_refs 407927 # Sample count of references to valid blocks. 1320system.l2c.tags.avg_refs 6.004435 # Average number of references to valid blocks. 1321system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. 1322system.l2c.tags.occ_blocks::writebacks 55272.994922 # Average occupied blocks per requestor 1323system.l2c.tags.occ_blocks::cpu0.inst 4808.176589 # Average occupied blocks per requestor 1324system.l2c.tags.occ_blocks::cpu0.data 4932.064474 # Average occupied blocks per requestor 1325system.l2c.tags.occ_blocks::cpu1.inst 162.933205 # Average occupied blocks per requestor 1326system.l2c.tags.occ_blocks::cpu1.data 44.263854 # Average occupied blocks per requestor 1327system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy 1328system.l2c.tags.occ_percent::cpu0.inst 0.073367 # Average percentage of cache occupancy 1329system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy 1330system.l2c.tags.occ_percent::cpu1.inst 0.002486 # Average percentage of cache occupancy 1331system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy 1332system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy 1333system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id 1334system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 1335system.l2c.tags.age_task_id_blocks_1024::1 764 # Occupied blocks per task id 1336system.l2c.tags.age_task_id_blocks_1024::2 5225 # Occupied blocks per task id 1337system.l2c.tags.age_task_id_blocks_1024::3 7223 # Occupied blocks per task id 1338system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id 1339system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id 1340system.l2c.tags.tag_accesses 25998619 # Number of tag accesses 1341system.l2c.tags.data_accesses 25998619 # Number of data accesses 1342system.l2c.ReadReq_hits::cpu0.inst 687419 # number of ReadReq hits 1343system.l2c.ReadReq_hits::cpu0.data 668122 # number of ReadReq hits 1344system.l2c.ReadReq_hits::cpu1.inst 318193 # number of ReadReq hits 1345system.l2c.ReadReq_hits::cpu1.data 105248 # number of ReadReq hits 1346system.l2c.ReadReq_hits::total 1778982 # number of ReadReq hits 1347system.l2c.Writeback_hits::writebacks 793794 # number of Writeback hits 1348system.l2c.Writeback_hits::total 793794 # number of Writeback hits 1349system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits 1350system.l2c.UpgradeReq_hits::cpu1.data 544 # number of UpgradeReq hits 1351system.l2c.UpgradeReq_hits::total 726 # number of UpgradeReq hits 1352system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits 1353system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits 1354system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits 1355system.l2c.ReadExReq_hits::cpu0.data 129870 # number of ReadExReq hits 1356system.l2c.ReadExReq_hits::cpu1.data 42509 # number of ReadExReq hits 1357system.l2c.ReadExReq_hits::total 172379 # number of ReadExReq hits 1358system.l2c.demand_hits::cpu0.inst 687419 # number of demand (read+write) hits 1359system.l2c.demand_hits::cpu0.data 797992 # number of demand (read+write) hits 1360system.l2c.demand_hits::cpu1.inst 318193 # number of demand (read+write) hits 1361system.l2c.demand_hits::cpu1.data 147757 # number of demand (read+write) hits 1362system.l2c.demand_hits::total 1951361 # number of demand (read+write) hits 1363system.l2c.overall_hits::cpu0.inst 687419 # number of overall hits 1364system.l2c.overall_hits::cpu0.data 797992 # number of overall hits 1365system.l2c.overall_hits::cpu1.inst 318193 # number of overall hits 1366system.l2c.overall_hits::cpu1.data 147757 # number of overall hits 1367system.l2c.overall_hits::total 1951361 # number of overall hits 1368system.l2c.ReadReq_misses::cpu0.inst 12865 # number of ReadReq misses 1369system.l2c.ReadReq_misses::cpu0.data 271552 # number of ReadReq misses 1370system.l2c.ReadReq_misses::cpu1.inst 660 # number of ReadReq misses 1371system.l2c.ReadReq_misses::cpu1.data 293 # number of ReadReq misses 1372system.l2c.ReadReq_misses::total 285370 # number of ReadReq misses 1373system.l2c.UpgradeReq_misses::cpu0.data 2959 # number of UpgradeReq misses 1374system.l2c.UpgradeReq_misses::cpu1.data 1779 # number of UpgradeReq misses 1375system.l2c.UpgradeReq_misses::total 4738 # number of UpgradeReq misses 1376system.l2c.SCUpgradeReq_misses::cpu0.data 894 # number of SCUpgradeReq misses 1377system.l2c.SCUpgradeReq_misses::cpu1.data 916 # number of SCUpgradeReq misses 1378system.l2c.SCUpgradeReq_misses::total 1810 # number of SCUpgradeReq misses 1379system.l2c.ReadExReq_misses::cpu0.data 117973 # number of ReadExReq misses 1380system.l2c.ReadExReq_misses::cpu1.data 5779 # number of ReadExReq misses 1381system.l2c.ReadExReq_misses::total 123752 # number of ReadExReq misses 1382system.l2c.demand_misses::cpu0.inst 12865 # number of demand (read+write) misses 1383system.l2c.demand_misses::cpu0.data 389525 # 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mshr miss rate for SCUpgradeReq accesses 1577system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475999 # mshr miss rate for ReadExReq accesses 1578system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119678 # mshr miss rate for ReadExReq accesses 1579system.l2c.ReadExReq_mshr_miss_rate::total 0.417896 # mshr miss rate for ReadExReq accesses 1580system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for demand accesses 1581system.l2c.demand_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for demand accesses 1582system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for demand accesses 1583system.l2c.demand_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for demand accesses 1584system.l2c.demand_mshr_miss_rate::total 0.173317 # mshr miss rate for demand accesses 1585system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018367 # mshr miss rate for overall accesses 1586system.l2c.overall_mshr_miss_rate::cpu0.data 0.328016 # mshr miss rate for overall accesses 1587system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002045 # mshr miss rate for overall accesses 1588system.l2c.overall_mshr_miss_rate::cpu1.data 0.039472 # mshr miss rate for overall accesses 1589system.l2c.overall_mshr_miss_rate::total 0.173317 # mshr miss rate for overall accesses 1590system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average ReadReq mshr miss latency 1591system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52556.207467 # average ReadReq mshr miss latency 1592system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average ReadReq mshr miss latency 1593system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 58242.320819 # average ReadReq mshr miss latency 1594system.l2c.ReadReq_avg_mshr_miss_latency::total 52950.882923 # average ReadReq mshr miss latency 1595system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.381548 # average UpgradeReq mshr miss latency 1596system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.588533 # average UpgradeReq mshr miss latency 1597system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.562896 # average UpgradeReq mshr miss latency 1598system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.675615 # average SCUpgradeReq mshr miss latency 1599system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.192140 # average SCUpgradeReq mshr miss latency 1600system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.309392 # average SCUpgradeReq mshr miss latency 1601system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56475.322591 # average ReadExReq mshr miss latency 1602system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61281.194151 # average ReadExReq mshr miss latency 1603system.l2c.ReadExReq_avg_mshr_miss_latency::total 56699.748311 # average ReadExReq mshr miss latency 1604system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency 1605system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency 1606system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency 1607system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency 1608system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency 1609system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency 1610system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency 1611system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency 1612system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency 1613system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency 1614system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1615system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1616system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1617system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1618system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1619system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1620system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1621system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1622system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1623system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1624system.membus.trans_dist::ReadReq 292732 # Transaction distribution 1625system.membus.trans_dist::ReadResp 292732 # Transaction distribution 1626system.membus.trans_dist::WriteReq 14079 # Transaction distribution 1627system.membus.trans_dist::WriteResp 14079 # Transaction distribution 1628system.membus.trans_dist::Writeback 121224 # Transaction distribution 1629system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1630system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 1631system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution 1632system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution 1633system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution 1634system.membus.trans_dist::ReadExReq 124094 # Transaction distribution 1635system.membus.trans_dist::ReadExResp 123249 # Transaction distribution 1636system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) 1637system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes) 1638system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes) 1639system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) 1640system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) 1641system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes) 1642system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) 1643system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes) 1644system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes) 1645system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) 1646system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) 1647system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes) 1648system.membus.snoops 22113 # Total snoops (count) 1649system.membus.snoop_fanout::samples 600297 # Request fanout histogram 1650system.membus.snoop_fanout::mean 1 # Request fanout histogram 1651system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1652system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1653system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1654system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram 1655system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1656system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1657system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1658system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1659system.membus.snoop_fanout::total 600297 # Request fanout histogram 1660system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks) 1661system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1662system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks) 1663system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1664system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks) 1665system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 1666system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) 1667system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1668system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution 1669system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution 1670system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution 1671system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution 1672system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution 1673system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 1674system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution 1675system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution 1676system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution 1677system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution 1678system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution 1679system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes) 1680system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes) 1681system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes) 1682system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes) 1683system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes) 1684system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes) 1685system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes) 1686system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes) 1687system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes) 1688system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes) 1689system.toL2Bus.snoops 99450 # Total snoops (count) 1690system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram 1691system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram 1692system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram 1693system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1694system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1695system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1696system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1697system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram 1698system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram 1699system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1700system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1701system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1702system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram 1703system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks) 1704system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1705system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) 1706system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1707system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks) 1708system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1709system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks) 1710system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) 1711system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks) 1712system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) 1713system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks) 1714system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1715system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1716system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1717system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1718system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1719system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1720system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1721system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1722system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1723system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1724system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1725system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1726system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1727system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1728system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1729system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1730system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1731system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1732system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1733system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1734system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1735system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1736system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1737system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1738system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1739system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1740system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1741system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1742system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1743system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1744system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1745system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
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| 1738 1739---------- End Simulation Statistics ---------- | 1746 1747---------- End Simulation Statistics ---------- |