| stats.txt (10433:821cbe4a183b) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.961827 # Number of seconds simulated 4sim_ticks 1961826628500 # Number of ticks simulated 5final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.961827 # Number of seconds simulated 4sim_ticks 1961826628500 # Number of ticks simulated 5final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 855480 # Simulator instruction rate (inst/s) 8host_op_rate 855480 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27561784483 # Simulator tick rate (ticks/s) 10host_mem_usage 318220 # Number of bytes of host memory used 11host_seconds 71.18 # Real time elapsed on the host | 7host_inst_rate 1248737 # Simulator instruction rate (inst/s) 8host_op_rate 1248737 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40231703865 # Simulator tick rate (ticks/s) 10host_mem_usage 312404 # Number of bytes of host memory used 11host_seconds 48.76 # Real time elapsed on the host |
| 12sim_insts 60892387 # Number of instructions simulated 13sim_ops 60892387 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory --- 703 unchanged lines hidden (view full) --- 723system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.iocache.blocked::no_targets 0 # number of cycles access was blocked 725system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.iocache.fast_writes 41552 # number of fast writes performed 728system.iocache.cache_copies 0 # number of cache copies performed 729system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 730system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses | 12sim_insts 60892387 # Number of instructions simulated 13sim_ops 60892387 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory --- 703 unchanged lines hidden (view full) --- 723system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.iocache.blocked::no_targets 0 # number of cycles access was blocked 725system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.iocache.fast_writes 41552 # number of fast writes performed 728system.iocache.cache_copies 0 # number of cache copies performed 729system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 730system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses |
| 731system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 732system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses | |
| 733system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses 734system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 735system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses 736system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses 737system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles 738system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles 739system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2501404806 # number of WriteInvalidateReq MSHR miss cycles 740system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2501404806 # number of WriteInvalidateReq MSHR miss cycles 741system.iocache.demand_mshr_miss_latency::tsunami.ide 12199383 # number of demand (read+write) MSHR miss cycles 742system.iocache.demand_mshr_miss_latency::total 12199383 # number of demand (read+write) MSHR miss cycles 743system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 # number of overall MSHR miss cycles 744system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles 745system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 746system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 731system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses 732system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 733system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses 734system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses 735system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles 736system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles 737system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2501404806 # number of WriteInvalidateReq MSHR miss cycles 738system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2501404806 # number of WriteInvalidateReq MSHR miss cycles 739system.iocache.demand_mshr_miss_latency::tsunami.ide 12199383 # number of demand (read+write) MSHR miss cycles 740system.iocache.demand_mshr_miss_latency::total 12199383 # number of demand (read+write) MSHR miss cycles 741system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 # number of overall MSHR miss cycles 742system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles 743system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 744system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 747system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 748system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses | |
| 749system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 750system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 751system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 752system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 753system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency 754system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency | 745system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 746system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 747system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 748system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 749system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency 750system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency |
| 755system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049 # average WriteInvalidateReq mshr miss latency 756system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049 # average WriteInvalidateReq mshr miss latency | 751system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency 752system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 757system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency 758system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency 759system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency 760system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency 761system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 762system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 763system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 764system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 979 unchanged lines hidden --- | 753system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency 754system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency 755system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency 756system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency 757system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 758system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 759system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 760system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 979 unchanged lines hidden --- |