| stats.txt (10220:9eab5efc02e8) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.962822 # Number of seconds simulated 4sim_ticks 1962822184500 # Number of ticks simulated 5final_tick 1962822184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.962815 # Number of seconds simulated 4sim_ticks 1962815218500 # Number of ticks simulated 5final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 916137 # Simulator instruction rate (inst/s) 8host_op_rate 916137 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 30287148246 # Simulator tick rate (ticks/s) 10host_mem_usage 346744 # Number of bytes of host memory used 11host_seconds 64.81 # Real time elapsed on the host 12sim_insts 59372170 # Number of instructions simulated 13sim_ops 59372170 # Number of ops (including micro ops) simulated | 7host_inst_rate 1506000 # Simulator instruction rate (inst/s) 8host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49787604582 # Simulator tick rate (ticks/s) 10host_mem_usage 317424 # Number of bytes of host memory used 11host_seconds 39.42 # Real time elapsed on the host 12sim_insts 59372159 # Number of instructions simulated 13sim_ops 59372159 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.inst 724800 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24150336 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 138496 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 1080640 # Number of bytes read from this memory 21system.physmem.bytes_read::total 28743616 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 724800 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 138496 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 863296 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7747520 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7747520 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 11325 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 377349 # Number of read requests responded to by this memory 29system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 2164 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 16885 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 449119 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 121055 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 121055 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 369264 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12303884 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::tsunami.ide 1349763 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 70560 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 550554 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 14644024 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 369264 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 70560 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 439824 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3947133 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3947133 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3947133 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 369264 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12303884 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::tsunami.ide 1349763 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 70560 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 550554 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 449119 # Number of read requests accepted 54system.physmem.writeReqs 121055 # Number of write requests accepted 55system.physmem.readBursts 449119 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 121055 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 28736320 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7746176 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 28743616 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7747520 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory 26system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory 30system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory 35system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s) 49system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.readReqs 408000 # Number of read requests accepted 57system.physmem.writeReqs 121085 # Number of write requests accepted 58system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue 59system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue 60system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM 61system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue 62system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM 63system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side 64system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side 65system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue |
| 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write | 66system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 67system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write |
| 65system.physmem.perBankRdBursts::0 28065 # Per bank write bursts 66system.physmem.perBankRdBursts::1 28141 # Per bank write bursts 67system.physmem.perBankRdBursts::2 27986 # Per bank write bursts 68system.physmem.perBankRdBursts::3 28553 # Per bank write bursts 69system.physmem.perBankRdBursts::4 28160 # Per bank write bursts 70system.physmem.perBankRdBursts::5 27775 # Per bank write bursts 71system.physmem.perBankRdBursts::6 27616 # Per bank write bursts 72system.physmem.perBankRdBursts::7 27528 # Per bank write bursts 73system.physmem.perBankRdBursts::8 27559 # Per bank write bursts 74system.physmem.perBankRdBursts::9 27974 # Per bank write bursts 75system.physmem.perBankRdBursts::10 27981 # Per bank write bursts 76system.physmem.perBankRdBursts::11 28021 # Per bank write bursts 77system.physmem.perBankRdBursts::12 28612 # Per bank write bursts 78system.physmem.perBankRdBursts::13 28738 # Per bank write bursts 79system.physmem.perBankRdBursts::14 28459 # Per bank write bursts 80system.physmem.perBankRdBursts::15 27837 # Per bank write bursts | 68system.physmem.perBankRdBursts::0 25223 # Per bank write bursts 69system.physmem.perBankRdBursts::1 25569 # Per bank write bursts 70system.physmem.perBankRdBursts::2 25254 # Per bank write bursts 71system.physmem.perBankRdBursts::3 25702 # Per bank write bursts 72system.physmem.perBankRdBursts::4 25695 # Per bank write bursts 73system.physmem.perBankRdBursts::5 25237 # Per bank write bursts 74system.physmem.perBankRdBursts::6 25154 # Per bank write bursts 75system.physmem.perBankRdBursts::7 25289 # Per bank write bursts 76system.physmem.perBankRdBursts::8 25197 # Per bank write bursts 77system.physmem.perBankRdBursts::9 25673 # Per bank write bursts 78system.physmem.perBankRdBursts::10 25761 # Per bank write bursts 79system.physmem.perBankRdBursts::11 25821 # Per bank write bursts 80system.physmem.perBankRdBursts::12 25887 # Per bank write bursts 81system.physmem.perBankRdBursts::13 25811 # Per bank write bursts 82system.physmem.perBankRdBursts::14 25568 # Per bank write bursts 83system.physmem.perBankRdBursts::15 24971 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::0 7862 # Per bank write bursts | 84system.physmem.perBankWrBursts::0 7862 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::1 7636 # Per bank write bursts | 85system.physmem.perBankWrBursts::1 7635 # Per bank write bursts |
| 83system.physmem.perBankWrBursts::2 7481 # Per bank write bursts | 86system.physmem.perBankWrBursts::2 7481 # Per bank write bursts |
| 84system.physmem.perBankWrBursts::3 8065 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7619 # Per bank write bursts | 87system.physmem.perBankWrBursts::3 8078 # Per bank write bursts 88system.physmem.perBankWrBursts::4 7635 # Per bank write bursts |
| 86system.physmem.perBankWrBursts::5 7244 # Per bank write bursts | 89system.physmem.perBankWrBursts::5 7244 # Per bank write bursts |
| 87system.physmem.perBankWrBursts::6 7159 # Per bank write bursts 88system.physmem.perBankWrBursts::7 6941 # Per bank write bursts | 90system.physmem.perBankWrBursts::6 7160 # Per bank write bursts 91system.physmem.perBankWrBursts::7 6937 # Per bank write bursts |
| 89system.physmem.perBankWrBursts::8 6882 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7297 # Per bank write bursts | 92system.physmem.perBankWrBursts::8 6882 # Per bank write bursts 93system.physmem.perBankWrBursts::9 7297 # Per bank write bursts |
| 91system.physmem.perBankWrBursts::10 7427 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7400 # Per bank write bursts | 94system.physmem.perBankWrBursts::10 7429 # Per bank write bursts 95system.physmem.perBankWrBursts::11 7398 # Per bank write bursts |
| 93system.physmem.perBankWrBursts::12 8124 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8265 # Per bank write bursts | 96system.physmem.perBankWrBursts::12 8124 # Per bank write bursts 97system.physmem.perBankWrBursts::13 8265 # Per bank write bursts |
| 95system.physmem.perBankWrBursts::14 8168 # Per bank write bursts | 98system.physmem.perBankWrBursts::14 8169 # Per bank write bursts |
| 96system.physmem.perBankWrBursts::15 7464 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 99system.physmem.perBankWrBursts::15 7464 # Per bank write bursts 100system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 98system.physmem.numWrRetry 8 # Number of times write queue was full causing retry 99system.physmem.totGap 1962815073500 # Total gap between requests | 101system.physmem.numWrRetry 6 # Number of times write queue was full causing retry 102system.physmem.totGap 1962808109000 # Total gap between requests |
| 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) | 103system.physmem.readPktSize::0 0 # Read request sizes (log2) 104system.physmem.readPktSize::1 0 # Read request sizes (log2) 105system.physmem.readPktSize::2 0 # Read request sizes (log2) 106system.physmem.readPktSize::3 0 # Read request sizes (log2) 107system.physmem.readPktSize::4 0 # Read request sizes (log2) 108system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 106system.physmem.readPktSize::6 449119 # Read request sizes (log2) | 109system.physmem.readPktSize::6 408000 # Read request sizes (log2) |
| 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) | 110system.physmem.writePktSize::0 0 # Write request sizes (log2) 111system.physmem.writePktSize::1 0 # Write request sizes (log2) 112system.physmem.writePktSize::2 0 # Write request sizes (log2) 113system.physmem.writePktSize::3 0 # Write request sizes (log2) 114system.physmem.writePktSize::4 0 # Write request sizes (log2) 115system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 113system.physmem.writePktSize::6 121055 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 407912 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 1721 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 2712 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1276 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1995 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 4350 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 3947 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 2533 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 2190 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 2125 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 2091 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1613 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 1879 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 2087 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 1205 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 975 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 896 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see | 116system.physmem.writePktSize::6 121085 # Write request sizes (log2) 117system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 138system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 156system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::15 1425 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 1547 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 4875 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 4920 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 4927 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 4931 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 4933 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 5043 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 5216 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 5300 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 5467 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 5674 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 5678 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 5762 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 5841 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 5977 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 5938 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 6015 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 879 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 923 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 879 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 937 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 961 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 1045 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 1159 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 1188 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 1167 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 1240 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 1400 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 1637 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 1890 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 2102 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 1946 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 1888 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 1710 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 1689 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 1830 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 1638 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 806 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 68642 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 531.489409 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 323.678439 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 416.279001 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 15609 22.74% 22.74% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 11929 17.38% 40.12% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5150 7.50% 47.62% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3087 4.50% 52.12% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 3390 4.94% 57.06% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 1779 2.59% 59.65% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1473 2.15% 61.79% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1315 1.92% 63.71% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 24910 36.29% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 68642 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 7087 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 63.355581 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 1920.089024 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-4095 7082 99.93% 99.93% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::4096-8191 1 0.01% 99.94% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::40960-45055 1 0.01% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-61439 1 0.01% 99.97% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::73728-77823 1 0.01% 99.99% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::122880-126975 1 0.01% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::total 7087 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 7087 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 17.078312 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 16.846071 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 3.814192 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16 5314 74.98% 74.98% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::17 115 1.62% 76.61% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::18 1264 17.84% 94.44% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::19 37 0.52% 94.96% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::20 12 0.17% 95.13% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::21 12 0.17% 95.30% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::22 26 0.37% 95.67% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::23 96 1.35% 97.02% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::24 18 0.25% 97.28% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::25 39 0.55% 97.83% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::26 16 0.23% 98.05% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::27 10 0.14% 98.19% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::28 12 0.17% 98.36% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::29 8 0.11% 98.48% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::30 4 0.06% 98.53% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::31 15 0.21% 98.74% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::32 3 0.04% 98.79% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::34 4 0.06% 98.84% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::35 2 0.03% 98.87% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::36 1 0.01% 98.89% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::37 3 0.04% 98.93% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::38 2 0.03% 98.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::39 10 0.14% 99.10% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::40 6 0.08% 99.18% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::41 6 0.08% 99.27% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::43 2 0.03% 99.32% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::44 2 0.03% 99.35% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::45 4 0.06% 99.41% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::47 10 0.14% 99.56% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48 2 0.03% 99.59% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::50 2 0.03% 99.62% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::55 1 0.01% 99.63% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::56 9 0.13% 99.76% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::57 14 0.20% 99.96% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::total 7087 # Writes before turning the bus around for reads 276system.physmem.totQLat 7297703000 # Total ticks spent queuing 277system.physmem.totMemAccLat 15716546750 # Total ticks spent from burst creation until serviced by the DRAM 278system.physmem.totBusLat 2245025000 # Total ticks spent in databus transfers 279system.physmem.avgQLat 16253.06 # Average queueing delay per DRAM burst | 164system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::19 6272 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::20 7040 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::21 7344 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::22 8568 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::24 8887 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::25 8584 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::26 8726 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::27 7185 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::28 6736 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::29 5915 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::30 5652 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::31 5640 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::32 5632 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::35 178 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::37 172 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::38 158 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::46 119 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::59 55 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see 213system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation 227system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes 235system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes 236system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes 237system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::132-135 2 0.04% 99.52% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::140-143 5 0.09% 99.71% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::144-147 8 0.15% 99.85% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::160-163 2 0.04% 99.93% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads 278system.physmem.totQLat 2167934250 # Total ticks spent queuing 279system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM 280system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers 281system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst |
| 280system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 282system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 281system.physmem.avgMemAccLat 35003.06 # Average memory access latency per DRAM burst 282system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s | 283system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst 284system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s |
| 283system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s | 285system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s |
| 284system.physmem.avgRdBWSys 14.64 # Average system read bandwidth in MiByte/s | 286system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s |
| 285system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s 286system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 287system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s 288system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 287system.physmem.busUtil 0.15 # Data bus utilization in percentage 288system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads | 289system.physmem.busUtil 0.13 # Data bus utilization in percentage 290system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads |
| 289system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 291system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 290system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 291system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing 292system.physmem.readRowHits 403892 # Number of row buffer hits during reads 293system.physmem.writeRowHits 97505 # Number of row buffer hits during writes 294system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads 295system.physmem.writeRowHitRate 80.55 # Row buffer hit rate for writes 296system.physmem.avgGap 3442484.35 # Average gap between requests 297system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined 298system.physmem.memoryStateTime::IDLE 1840580762750 # Time in different power states 299system.physmem.memoryStateTime::REF 65542880000 # Time in different power states | 292system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 293system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing 294system.physmem.readRowHits 365758 # Number of row buffer hits during reads 295system.physmem.writeRowHits 97091 # Number of row buffer hits during writes 296system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads 297system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes 298system.physmem.avgGap 3709816.21 # Average gap between requests 299system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined 300system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states 301system.physmem.memoryStateTime::REF 65542620000 # Time in different power states |
| 300system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 302system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 301system.physmem.memoryStateTime::ACT 56696821000 # Time in different power states | 303system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states |
| 302system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 304system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 303system.membus.throughput 18645480 # Throughput (bytes/s) 304system.membus.trans_dist::ReadReq 292657 # Transaction distribution 305system.membus.trans_dist::ReadResp 292657 # Transaction distribution | 305system.membus.throughput 17291736 # Throughput (bytes/s) 306system.membus.trans_dist::ReadReq 292660 # Transaction distribution 307system.membus.trans_dist::ReadResp 292660 # Transaction distribution |
| 306system.membus.trans_dist::WriteReq 12414 # Transaction distribution 307system.membus.trans_dist::WriteResp 12414 # Transaction distribution | 308system.membus.trans_dist::WriteReq 12414 # Transaction distribution 309system.membus.trans_dist::WriteResp 12414 # Transaction distribution |
| 308system.membus.trans_dist::Writeback 121055 # Transaction distribution 309system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution 310system.membus.trans_dist::SCUpgradeReq 1018 # Transaction distribution | 310system.membus.trans_dist::Writeback 79533 # Transaction distribution 311system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 312system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 313system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution 314system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution |
| 311system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution | 315system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution |
| 312system.membus.trans_dist::ReadExReq 164356 # Transaction distribution 313system.membus.trans_dist::ReadExResp 164254 # Transaction distribution | 316system.membus.trans_dist::ReadExReq 122803 # Transaction distribution 317system.membus.trans_dist::ReadExResp 122701 # Transaction distribution |
| 314system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes) | 318system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes) |
| 315system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904273 # Packet count per connected master and slave (bytes) 316system.membus.pkt_count_system.l2c.mem_side::total 943501 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) 319system.membus.pkt_count::total 1068148 # Packet count per connected master and slave (bytes) | 319system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes) 320system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes) 321system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes) 322system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes) 323system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes) |
| 320system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes) | 324system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes) |
| 321system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31184320 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.l2c.mem_side::total 31253058 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) 324system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) 325system.membus.tot_pkt_size::total 36559874 # Cumulative packet size per connected master and slave (bytes) 326system.membus.data_through_bus 36559874 # Total data (bytes) 327system.membus.snoop_data_through_bus 37888 # Total snoop data (bytes) 328system.membus.reqLayer0.occupancy 39221000 # Layer occupancy (ticks) | 325system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31201152 # Cumulative packet size per connected master and slave (bytes) 326system.membus.tot_pkt_size_system.l2c.mem_side::total 31269890 # Cumulative packet size per connected master and slave (bytes) 327system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) 328system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) 329system.membus.tot_pkt_size::total 33930178 # Cumulative packet size per connected master and slave (bytes) 330system.membus.data_through_bus 33930178 # Total data (bytes) 331system.membus.snoop_data_through_bus 10304 # Total snoop data (bytes) 332system.membus.reqLayer0.occupancy 39224500 # Layer occupancy (ticks) |
| 329system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 333system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 330system.membus.reqLayer1.occupancy 1574833000 # Layer occupancy (ticks) | 334system.membus.reqLayer1.occupancy 1533573250 # Layer occupancy (ticks) |
| 331system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 335system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 332system.membus.respLayer1.occupancy 3826410374 # Layer occupancy (ticks) | 336system.membus.respLayer1.occupancy 3826483141 # Layer occupancy (ticks) |
| 333system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 337system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 334system.membus.respLayer2.occupancy 376647250 # Layer occupancy (ticks) | 338system.membus.respLayer2.occupancy 43139750 # Layer occupancy (ticks) |
| 335system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 336system.cpu_clk_domain.clock 500 # Clock period in ticks | 339system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 340system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 337system.l2c.tags.replacements 342221 # number of replacements 338system.l2c.tags.tagsinuse 65256.412579 # Cycle average of tags in use 339system.l2c.tags.total_refs 2544259 # Total number of references to valid blocks. 340system.l2c.tags.sampled_refs 407367 # Sample count of references to valid blocks. 341system.l2c.tags.avg_refs 6.245619 # Average number of references to valid blocks. | 341system.l2c.tags.replacements 342222 # number of replacements 342system.l2c.tags.tagsinuse 65256.426750 # Cycle average of tags in use 343system.l2c.tags.total_refs 2542307 # Total number of references to valid blocks. 344system.l2c.tags.sampled_refs 407368 # Sample count of references to valid blocks. 345system.l2c.tags.avg_refs 6.240812 # Average number of references to valid blocks. |
| 342system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit. | 346system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit. |
| 343system.l2c.tags.occ_blocks::writebacks 55518.574788 # Average occupied blocks per requestor 344system.l2c.tags.occ_blocks::cpu0.inst 3744.543964 # Average occupied blocks per requestor 345system.l2c.tags.occ_blocks::cpu0.data 4299.514442 # Average occupied blocks per requestor 346system.l2c.tags.occ_blocks::cpu1.inst 1171.756098 # Average occupied blocks per requestor 347system.l2c.tags.occ_blocks::cpu1.data 522.023286 # Average occupied blocks per requestor 348system.l2c.tags.occ_percent::writebacks 0.847146 # Average percentage of cache occupancy 349system.l2c.tags.occ_percent::cpu0.inst 0.057137 # Average percentage of cache occupancy 350system.l2c.tags.occ_percent::cpu0.data 0.065605 # Average percentage of cache occupancy 351system.l2c.tags.occ_percent::cpu1.inst 0.017880 # Average percentage of cache occupancy | 347system.l2c.tags.occ_blocks::writebacks 55518.260732 # Average occupied blocks per requestor 348system.l2c.tags.occ_blocks::cpu0.inst 3744.767678 # Average occupied blocks per requestor 349system.l2c.tags.occ_blocks::cpu0.data 4299.632317 # Average occupied blocks per requestor 350system.l2c.tags.occ_blocks::cpu1.inst 1171.746225 # Average occupied blocks per requestor 351system.l2c.tags.occ_blocks::cpu1.data 522.019798 # Average occupied blocks per requestor 352system.l2c.tags.occ_percent::writebacks 0.847141 # Average percentage of cache occupancy 353system.l2c.tags.occ_percent::cpu0.inst 0.057141 # Average percentage of cache occupancy 354system.l2c.tags.occ_percent::cpu0.data 0.065607 # Average percentage of cache occupancy 355system.l2c.tags.occ_percent::cpu1.inst 0.017879 # Average percentage of cache occupancy |
| 352system.l2c.tags.occ_percent::cpu1.data 0.007965 # Average percentage of cache occupancy 353system.l2c.tags.occ_percent::total 0.995734 # Average percentage of cache occupancy 354system.l2c.tags.occ_task_id_blocks::1024 65146 # Occupied blocks per task id | 356system.l2c.tags.occ_percent::cpu1.data 0.007965 # Average percentage of cache occupancy 357system.l2c.tags.occ_percent::total 0.995734 # Average percentage of cache occupancy 358system.l2c.tags.occ_task_id_blocks::1024 65146 # Occupied blocks per task id |
| 355system.l2c.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 356system.l2c.tags.age_task_id_blocks_1024::1 752 # Occupied blocks per task id | 359system.l2c.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 360system.l2c.tags.age_task_id_blocks_1024::1 748 # Occupied blocks per task id |
| 357system.l2c.tags.age_task_id_blocks_1024::2 5288 # Occupied blocks per task id | 361system.l2c.tags.age_task_id_blocks_1024::2 5288 # Occupied blocks per task id |
| 358system.l2c.tags.age_task_id_blocks_1024::3 7256 # Occupied blocks per task id 359system.l2c.tags.age_task_id_blocks_1024::4 51736 # Occupied blocks per task id | 362system.l2c.tags.age_task_id_blocks_1024::3 7253 # Occupied blocks per task id 363system.l2c.tags.age_task_id_blocks_1024::4 51739 # Occupied blocks per task id |
| 360system.l2c.tags.occ_task_id_percent::1024 0.994049 # Percentage of cache occupancy per task id | 364system.l2c.tags.occ_task_id_percent::1024 0.994049 # Percentage of cache occupancy per task id |
| 361system.l2c.tags.tag_accesses 26948745 # Number of tag accesses 362system.l2c.tags.data_accesses 26948745 # Number of data accesses 363system.l2c.ReadReq_hits::cpu0.inst 527962 # number of ReadReq hits 364system.l2c.ReadReq_hits::cpu0.data 377923 # number of ReadReq hits 365system.l2c.ReadReq_hits::cpu1.inst 461443 # number of ReadReq hits 366system.l2c.ReadReq_hits::cpu1.data 449896 # number of ReadReq hits 367system.l2c.ReadReq_hits::total 1817224 # number of ReadReq hits 368system.l2c.Writeback_hits::writebacks 850135 # number of Writeback hits 369system.l2c.Writeback_hits::total 850135 # number of Writeback hits 370system.l2c.UpgradeReq_hits::cpu0.data 136 # number of UpgradeReq hits | 365system.l2c.tags.tag_accesses 26946350 # Number of tag accesses 366system.l2c.tags.data_accesses 26946350 # Number of data accesses 367system.l2c.ReadReq_hits::cpu0.inst 527823 # number of ReadReq hits 368system.l2c.ReadReq_hits::cpu0.data 377901 # number of ReadReq hits 369system.l2c.ReadReq_hits::cpu1.inst 461413 # number of ReadReq hits 370system.l2c.ReadReq_hits::cpu1.data 449863 # number of ReadReq hits 371system.l2c.ReadReq_hits::total 1817000 # number of ReadReq hits 372system.l2c.Writeback_hits::writebacks 850078 # number of Writeback hits 373system.l2c.Writeback_hits::total 850078 # number of Writeback hits 374system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits |
| 371system.l2c.UpgradeReq_hits::cpu1.data 70 # number of UpgradeReq hits | 375system.l2c.UpgradeReq_hits::cpu1.data 70 # number of UpgradeReq hits |
| 372system.l2c.UpgradeReq_hits::total 206 # number of UpgradeReq hits 373system.l2c.SCUpgradeReq_hits::cpu0.data 24 # number of SCUpgradeReq hits 374system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits 375system.l2c.SCUpgradeReq_hits::total 44 # number of SCUpgradeReq hits 376system.l2c.ReadExReq_hits::cpu0.data 113466 # number of ReadExReq hits 377system.l2c.ReadExReq_hits::cpu1.data 85009 # number of ReadExReq hits 378system.l2c.ReadExReq_hits::total 198475 # number of ReadExReq hits 379system.l2c.demand_hits::cpu0.inst 527962 # number of demand (read+write) hits 380system.l2c.demand_hits::cpu0.data 491389 # number of demand (read+write) hits 381system.l2c.demand_hits::cpu1.inst 461443 # number of demand (read+write) hits 382system.l2c.demand_hits::cpu1.data 534905 # number of demand (read+write) hits 383system.l2c.demand_hits::total 2015699 # number of demand (read+write) hits 384system.l2c.overall_hits::cpu0.inst 527962 # number of overall hits 385system.l2c.overall_hits::cpu0.data 491389 # number of overall hits 386system.l2c.overall_hits::cpu1.inst 461443 # number of overall hits 387system.l2c.overall_hits::cpu1.data 534905 # number of overall hits 388system.l2c.overall_hits::total 2015699 # number of overall hits 389system.l2c.ReadReq_misses::cpu0.inst 11328 # number of ReadReq misses 390system.l2c.ReadReq_misses::cpu0.data 270740 # number of ReadReq misses 391system.l2c.ReadReq_misses::cpu1.inst 2172 # number of ReadReq misses | 376system.l2c.UpgradeReq_hits::total 205 # number of UpgradeReq hits 377system.l2c.SCUpgradeReq_hits::cpu0.data 25 # number of SCUpgradeReq hits 378system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits 379system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits 380system.l2c.ReadExReq_hits::cpu0.data 113452 # number of ReadExReq hits 381system.l2c.ReadExReq_hits::cpu1.data 85004 # number of ReadExReq hits 382system.l2c.ReadExReq_hits::total 198456 # number of ReadExReq hits 383system.l2c.demand_hits::cpu0.inst 527823 # number of demand (read+write) hits 384system.l2c.demand_hits::cpu0.data 491353 # number of demand (read+write) hits 385system.l2c.demand_hits::cpu1.inst 461413 # number of demand (read+write) hits 386system.l2c.demand_hits::cpu1.data 534867 # number of demand (read+write) hits 387system.l2c.demand_hits::total 2015456 # number of demand (read+write) hits 388system.l2c.overall_hits::cpu0.inst 527823 # number of overall hits 389system.l2c.overall_hits::cpu0.data 491353 # number of overall hits 390system.l2c.overall_hits::cpu1.inst 461413 # number of overall hits 391system.l2c.overall_hits::cpu1.data 534867 # number of overall hits 392system.l2c.overall_hits::total 2015456 # number of overall hits 393system.l2c.ReadReq_misses::cpu0.inst 11331 # number of ReadReq misses 394system.l2c.ReadReq_misses::cpu0.data 270739 # number of ReadReq misses 395system.l2c.ReadReq_misses::cpu1.inst 2173 # number of ReadReq misses |
| 392system.l2c.ReadReq_misses::cpu1.data 1052 # number of ReadReq misses | 396system.l2c.ReadReq_misses::cpu1.data 1052 # number of ReadReq misses |
| 393system.l2c.ReadReq_misses::total 285292 # number of ReadReq misses | 397system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses |
| 394system.l2c.UpgradeReq_misses::cpu0.data 2603 # number of UpgradeReq misses | 398system.l2c.UpgradeReq_misses::cpu0.data 2603 # number of UpgradeReq misses |
| 395system.l2c.UpgradeReq_misses::cpu1.data 468 # number of UpgradeReq misses 396system.l2c.UpgradeReq_misses::total 3071 # number of UpgradeReq misses | 399system.l2c.UpgradeReq_misses::cpu1.data 469 # number of UpgradeReq misses 400system.l2c.UpgradeReq_misses::total 3072 # number of UpgradeReq misses |
| 397system.l2c.SCUpgradeReq_misses::cpu0.data 62 # number of SCUpgradeReq misses 398system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses 399system.l2c.SCUpgradeReq_misses::total 142 # number of SCUpgradeReq misses 400system.l2c.ReadExReq_misses::cpu0.data 107000 # number of ReadExReq misses | 401system.l2c.SCUpgradeReq_misses::cpu0.data 62 # number of SCUpgradeReq misses 402system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses 403system.l2c.SCUpgradeReq_misses::total 142 # number of SCUpgradeReq misses 404system.l2c.ReadExReq_misses::cpu0.data 107000 # number of ReadExReq misses |
| 401system.l2c.ReadExReq_misses::cpu1.data 15849 # number of ReadExReq misses 402system.l2c.ReadExReq_misses::total 122849 # number of ReadExReq misses 403system.l2c.demand_misses::cpu0.inst 11328 # number of demand (read+write) misses 404system.l2c.demand_misses::cpu0.data 377740 # number of demand (read+write) misses 405system.l2c.demand_misses::cpu1.inst 2172 # number of demand (read+write) misses 406system.l2c.demand_misses::cpu1.data 16901 # number of demand (read+write) misses 407system.l2c.demand_misses::total 408141 # number of demand (read+write) misses 408system.l2c.overall_misses::cpu0.inst 11328 # number of overall misses 409system.l2c.overall_misses::cpu0.data 377740 # number of overall misses 410system.l2c.overall_misses::cpu1.inst 2172 # number of overall misses 411system.l2c.overall_misses::cpu1.data 16901 # number of overall misses 412system.l2c.overall_misses::total 408141 # number of overall misses 413system.l2c.ReadReq_miss_latency::cpu0.inst 833297996 # number of ReadReq miss cycles 414system.l2c.ReadReq_miss_latency::cpu0.data 17596590486 # number of ReadReq miss cycles 415system.l2c.ReadReq_miss_latency::cpu1.inst 160787750 # number of ReadReq miss cycles 416system.l2c.ReadReq_miss_latency::cpu1.data 79756250 # number of ReadReq miss cycles 417system.l2c.ReadReq_miss_latency::total 18670432482 # number of ReadReq miss cycles 418system.l2c.UpgradeReq_miss_latency::cpu0.data 706471 # number of UpgradeReq miss cycles 419system.l2c.UpgradeReq_miss_latency::cpu1.data 350485 # number of UpgradeReq miss cycles 420system.l2c.UpgradeReq_miss_latency::total 1056956 # number of UpgradeReq miss cycles 421system.l2c.SCUpgradeReq_miss_latency::cpu0.data 162493 # number of SCUpgradeReq miss cycles 422system.l2c.SCUpgradeReq_miss_latency::cpu1.data 92496 # number of SCUpgradeReq miss cycles 423system.l2c.SCUpgradeReq_miss_latency::total 254989 # number of SCUpgradeReq miss cycles 424system.l2c.ReadExReq_miss_latency::cpu0.data 7343044869 # number of ReadExReq miss cycles 425system.l2c.ReadExReq_miss_latency::cpu1.data 1158336734 # number of ReadExReq miss cycles 426system.l2c.ReadExReq_miss_latency::total 8501381603 # number of ReadExReq miss cycles 427system.l2c.demand_miss_latency::cpu0.inst 833297996 # number of demand (read+write) miss cycles 428system.l2c.demand_miss_latency::cpu0.data 24939635355 # number of demand (read+write) miss cycles 429system.l2c.demand_miss_latency::cpu1.inst 160787750 # number of demand (read+write) miss cycles 430system.l2c.demand_miss_latency::cpu1.data 1238092984 # number of demand (read+write) miss cycles 431system.l2c.demand_miss_latency::total 27171814085 # number of demand (read+write) miss cycles 432system.l2c.overall_miss_latency::cpu0.inst 833297996 # number of overall miss cycles 433system.l2c.overall_miss_latency::cpu0.data 24939635355 # number of overall miss cycles 434system.l2c.overall_miss_latency::cpu1.inst 160787750 # number of overall miss cycles 435system.l2c.overall_miss_latency::cpu1.data 1238092984 # number of overall miss cycles 436system.l2c.overall_miss_latency::total 27171814085 # number of overall miss cycles 437system.l2c.ReadReq_accesses::cpu0.inst 539290 # number of ReadReq accesses(hits+misses) 438system.l2c.ReadReq_accesses::cpu0.data 648663 # number of ReadReq accesses(hits+misses) 439system.l2c.ReadReq_accesses::cpu1.inst 463615 # number of ReadReq accesses(hits+misses) 440system.l2c.ReadReq_accesses::cpu1.data 450948 # number of ReadReq accesses(hits+misses) 441system.l2c.ReadReq_accesses::total 2102516 # number of ReadReq accesses(hits+misses) 442system.l2c.Writeback_accesses::writebacks 850135 # number of Writeback accesses(hits+misses) 443system.l2c.Writeback_accesses::total 850135 # number of Writeback accesses(hits+misses) 444system.l2c.UpgradeReq_accesses::cpu0.data 2739 # number of UpgradeReq accesses(hits+misses) 445system.l2c.UpgradeReq_accesses::cpu1.data 538 # number of UpgradeReq accesses(hits+misses) | 405system.l2c.ReadExReq_misses::cpu1.data 15847 # number of ReadExReq misses 406system.l2c.ReadExReq_misses::total 122847 # number of ReadExReq misses 407system.l2c.demand_misses::cpu0.inst 11331 # number of demand (read+write) misses 408system.l2c.demand_misses::cpu0.data 377739 # number of demand (read+write) misses 409system.l2c.demand_misses::cpu1.inst 2173 # number of demand (read+write) misses 410system.l2c.demand_misses::cpu1.data 16899 # number of demand (read+write) misses 411system.l2c.demand_misses::total 408142 # number of demand (read+write) misses 412system.l2c.overall_misses::cpu0.inst 11331 # number of overall misses 413system.l2c.overall_misses::cpu0.data 377739 # number of overall misses 414system.l2c.overall_misses::cpu1.inst 2173 # number of overall misses 415system.l2c.overall_misses::cpu1.data 16899 # number of overall misses 416system.l2c.overall_misses::total 408142 # number of overall misses 417system.l2c.ReadReq_miss_latency::cpu0.inst 827161250 # number of ReadReq miss cycles 418system.l2c.ReadReq_miss_latency::cpu0.data 17596749000 # number of ReadReq miss cycles 419system.l2c.ReadReq_miss_latency::cpu1.inst 162190250 # number of ReadReq miss cycles 420system.l2c.ReadReq_miss_latency::cpu1.data 79449000 # number of ReadReq miss cycles 421system.l2c.ReadReq_miss_latency::total 18665549500 # number of ReadReq miss cycles 422system.l2c.UpgradeReq_miss_latency::cpu0.data 700470 # number of UpgradeReq miss cycles 423system.l2c.UpgradeReq_miss_latency::cpu1.data 348985 # number of UpgradeReq miss cycles 424system.l2c.UpgradeReq_miss_latency::total 1049455 # number of UpgradeReq miss cycles 425system.l2c.SCUpgradeReq_miss_latency::cpu0.data 162993 # number of SCUpgradeReq miss cycles 426system.l2c.SCUpgradeReq_miss_latency::cpu1.data 93496 # number of SCUpgradeReq miss cycles 427system.l2c.SCUpgradeReq_miss_latency::total 256489 # number of SCUpgradeReq miss cycles 428system.l2c.ReadExReq_miss_latency::cpu0.data 7343632619 # number of ReadExReq miss cycles 429system.l2c.ReadExReq_miss_latency::cpu1.data 1157201235 # number of ReadExReq miss cycles 430system.l2c.ReadExReq_miss_latency::total 8500833854 # number of ReadExReq miss cycles 431system.l2c.demand_miss_latency::cpu0.inst 827161250 # number of demand (read+write) miss cycles 432system.l2c.demand_miss_latency::cpu0.data 24940381619 # number of demand (read+write) miss cycles 433system.l2c.demand_miss_latency::cpu1.inst 162190250 # number of demand (read+write) miss cycles 434system.l2c.demand_miss_latency::cpu1.data 1236650235 # number of demand (read+write) miss cycles 435system.l2c.demand_miss_latency::total 27166383354 # number of demand (read+write) miss cycles 436system.l2c.overall_miss_latency::cpu0.inst 827161250 # number of overall miss cycles 437system.l2c.overall_miss_latency::cpu0.data 24940381619 # number of overall miss cycles 438system.l2c.overall_miss_latency::cpu1.inst 162190250 # number of overall miss cycles 439system.l2c.overall_miss_latency::cpu1.data 1236650235 # number of overall miss cycles 440system.l2c.overall_miss_latency::total 27166383354 # number of overall miss cycles 441system.l2c.ReadReq_accesses::cpu0.inst 539154 # number of ReadReq accesses(hits+misses) 442system.l2c.ReadReq_accesses::cpu0.data 648640 # number of ReadReq accesses(hits+misses) 443system.l2c.ReadReq_accesses::cpu1.inst 463586 # number of ReadReq accesses(hits+misses) 444system.l2c.ReadReq_accesses::cpu1.data 450915 # number of ReadReq accesses(hits+misses) 445system.l2c.ReadReq_accesses::total 2102295 # number of ReadReq accesses(hits+misses) 446system.l2c.Writeback_accesses::writebacks 850078 # number of Writeback accesses(hits+misses) 447system.l2c.Writeback_accesses::total 850078 # number of Writeback accesses(hits+misses) 448system.l2c.UpgradeReq_accesses::cpu0.data 2738 # number of UpgradeReq accesses(hits+misses) 449system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses) |
| 446system.l2c.UpgradeReq_accesses::total 3277 # number of UpgradeReq accesses(hits+misses) | 450system.l2c.UpgradeReq_accesses::total 3277 # number of UpgradeReq accesses(hits+misses) |
| 447system.l2c.SCUpgradeReq_accesses::cpu0.data 86 # number of SCUpgradeReq accesses(hits+misses) 448system.l2c.SCUpgradeReq_accesses::cpu1.data 100 # number of SCUpgradeReq accesses(hits+misses) 449system.l2c.SCUpgradeReq_accesses::total 186 # number of SCUpgradeReq accesses(hits+misses) 450system.l2c.ReadExReq_accesses::cpu0.data 220466 # number of ReadExReq accesses(hits+misses) 451system.l2c.ReadExReq_accesses::cpu1.data 100858 # number of ReadExReq accesses(hits+misses) 452system.l2c.ReadExReq_accesses::total 321324 # number of ReadExReq accesses(hits+misses) 453system.l2c.demand_accesses::cpu0.inst 539290 # number of demand (read+write) accesses 454system.l2c.demand_accesses::cpu0.data 869129 # number of demand (read+write) accesses 455system.l2c.demand_accesses::cpu1.inst 463615 # number of demand (read+write) accesses 456system.l2c.demand_accesses::cpu1.data 551806 # number of demand (read+write) accesses 457system.l2c.demand_accesses::total 2423840 # number of demand (read+write) accesses 458system.l2c.overall_accesses::cpu0.inst 539290 # number of overall (read+write) accesses 459system.l2c.overall_accesses::cpu0.data 869129 # number of overall (read+write) accesses 460system.l2c.overall_accesses::cpu1.inst 463615 # number of overall (read+write) accesses 461system.l2c.overall_accesses::cpu1.data 551806 # number of overall (read+write) accesses 462system.l2c.overall_accesses::total 2423840 # number of overall (read+write) accesses 463system.l2c.ReadReq_miss_rate::cpu0.inst 0.021005 # miss rate for ReadReq accesses 464system.l2c.ReadReq_miss_rate::cpu0.data 0.417382 # miss rate for ReadReq accesses 465system.l2c.ReadReq_miss_rate::cpu1.inst 0.004685 # miss rate for ReadReq accesses | 451system.l2c.SCUpgradeReq_accesses::cpu0.data 87 # number of SCUpgradeReq accesses(hits+misses) 452system.l2c.SCUpgradeReq_accesses::cpu1.data 101 # number of SCUpgradeReq accesses(hits+misses) 453system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) 454system.l2c.ReadExReq_accesses::cpu0.data 220452 # number of ReadExReq accesses(hits+misses) 455system.l2c.ReadExReq_accesses::cpu1.data 100851 # number of ReadExReq accesses(hits+misses) 456system.l2c.ReadExReq_accesses::total 321303 # number of ReadExReq accesses(hits+misses) 457system.l2c.demand_accesses::cpu0.inst 539154 # number of demand (read+write) accesses 458system.l2c.demand_accesses::cpu0.data 869092 # number of demand (read+write) accesses 459system.l2c.demand_accesses::cpu1.inst 463586 # number of demand (read+write) accesses 460system.l2c.demand_accesses::cpu1.data 551766 # number of demand (read+write) accesses 461system.l2c.demand_accesses::total 2423598 # number of demand (read+write) accesses 462system.l2c.overall_accesses::cpu0.inst 539154 # number of overall (read+write) accesses 463system.l2c.overall_accesses::cpu0.data 869092 # number of overall (read+write) accesses 464system.l2c.overall_accesses::cpu1.inst 463586 # number of overall (read+write) accesses 465system.l2c.overall_accesses::cpu1.data 551766 # number of overall (read+write) accesses 466system.l2c.overall_accesses::total 2423598 # number of overall (read+write) accesses 467system.l2c.ReadReq_miss_rate::cpu0.inst 0.021016 # miss rate for ReadReq accesses 468system.l2c.ReadReq_miss_rate::cpu0.data 0.417395 # miss rate for ReadReq accesses 469system.l2c.ReadReq_miss_rate::cpu1.inst 0.004687 # miss rate for ReadReq accesses |
| 466system.l2c.ReadReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadReq accesses | 470system.l2c.ReadReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadReq accesses |
| 467system.l2c.ReadReq_miss_rate::total 0.135691 # miss rate for ReadReq accesses 468system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950347 # miss rate for UpgradeReq accesses 469system.l2c.UpgradeReq_miss_rate::cpu1.data 0.869888 # miss rate for UpgradeReq accesses 470system.l2c.UpgradeReq_miss_rate::total 0.937138 # miss rate for UpgradeReq accesses 471system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.720930 # miss rate for SCUpgradeReq accesses 472system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.800000 # miss rate for SCUpgradeReq accesses 473system.l2c.SCUpgradeReq_miss_rate::total 0.763441 # miss rate for SCUpgradeReq accesses 474system.l2c.ReadExReq_miss_rate::cpu0.data 0.485336 # miss rate for ReadExReq accesses 475system.l2c.ReadExReq_miss_rate::cpu1.data 0.157142 # miss rate for ReadExReq accesses 476system.l2c.ReadExReq_miss_rate::total 0.382321 # miss rate for ReadExReq accesses 477system.l2c.demand_miss_rate::cpu0.inst 0.021005 # miss rate for demand accesses 478system.l2c.demand_miss_rate::cpu0.data 0.434619 # miss rate for demand accesses 479system.l2c.demand_miss_rate::cpu1.inst 0.004685 # miss rate for demand accesses 480system.l2c.demand_miss_rate::cpu1.data 0.030629 # miss rate for demand accesses 481system.l2c.demand_miss_rate::total 0.168386 # miss rate for demand accesses 482system.l2c.overall_miss_rate::cpu0.inst 0.021005 # miss rate for overall accesses 483system.l2c.overall_miss_rate::cpu0.data 0.434619 # miss rate for overall accesses 484system.l2c.overall_miss_rate::cpu1.inst 0.004685 # miss rate for overall accesses 485system.l2c.overall_miss_rate::cpu1.data 0.030629 # miss rate for overall accesses 486system.l2c.overall_miss_rate::total 0.168386 # miss rate for overall accesses 487system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73560.910664 # average ReadReq miss latency 488system.l2c.ReadReq_avg_miss_latency::cpu0.data 64994.424488 # average ReadReq miss latency 489system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74027.509208 # average ReadReq miss latency 490system.l2c.ReadReq_avg_miss_latency::cpu1.data 75813.925856 # average ReadReq miss latency 491system.l2c.ReadReq_avg_miss_latency::total 65443.238794 # average ReadReq miss latency 492system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 271.406454 # average UpgradeReq miss latency 493system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 748.899573 # average UpgradeReq miss latency 494system.l2c.UpgradeReq_avg_miss_latency::total 344.173233 # average UpgradeReq miss latency 495system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2620.854839 # average SCUpgradeReq miss latency 496system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1156.200000 # average SCUpgradeReq miss latency 497system.l2c.SCUpgradeReq_avg_miss_latency::total 1795.697183 # average SCUpgradeReq miss latency 498system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68626.587561 # average ReadExReq miss latency 499system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73085.793047 # average ReadExReq miss latency 500system.l2c.ReadExReq_avg_miss_latency::total 69201.878754 # average ReadExReq miss latency 501system.l2c.demand_avg_miss_latency::cpu0.inst 73560.910664 # average overall miss latency 502system.l2c.demand_avg_miss_latency::cpu0.data 66023.284150 # average overall miss latency 503system.l2c.demand_avg_miss_latency::cpu1.inst 74027.509208 # average overall miss latency 504system.l2c.demand_avg_miss_latency::cpu1.data 73255.605230 # average overall miss latency 505system.l2c.demand_avg_miss_latency::total 66574.576151 # average overall miss latency 506system.l2c.overall_avg_miss_latency::cpu0.inst 73560.910664 # average overall miss latency 507system.l2c.overall_avg_miss_latency::cpu0.data 66023.284150 # average overall miss latency 508system.l2c.overall_avg_miss_latency::cpu1.inst 74027.509208 # average overall miss latency 509system.l2c.overall_avg_miss_latency::cpu1.data 73255.605230 # average overall miss latency 510system.l2c.overall_avg_miss_latency::total 66574.576151 # average overall miss latency | 471system.l2c.ReadReq_miss_rate::total 0.135706 # miss rate for ReadReq accesses 472system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950694 # miss rate for UpgradeReq accesses 473system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870130 # miss rate for UpgradeReq accesses 474system.l2c.UpgradeReq_miss_rate::total 0.937443 # miss rate for UpgradeReq accesses 475system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.712644 # miss rate for SCUpgradeReq accesses 476system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.792079 # miss rate for SCUpgradeReq accesses 477system.l2c.SCUpgradeReq_miss_rate::total 0.755319 # miss rate for SCUpgradeReq accesses 478system.l2c.ReadExReq_miss_rate::cpu0.data 0.485366 # miss rate for ReadExReq accesses 479system.l2c.ReadExReq_miss_rate::cpu1.data 0.157133 # miss rate for ReadExReq accesses 480system.l2c.ReadExReq_miss_rate::total 0.382340 # miss rate for ReadExReq accesses 481system.l2c.demand_miss_rate::cpu0.inst 0.021016 # miss rate for demand accesses 482system.l2c.demand_miss_rate::cpu0.data 0.434636 # miss rate for demand accesses 483system.l2c.demand_miss_rate::cpu1.inst 0.004687 # miss rate for demand accesses 484system.l2c.demand_miss_rate::cpu1.data 0.030627 # miss rate for demand accesses 485system.l2c.demand_miss_rate::total 0.168403 # miss rate for demand accesses 486system.l2c.overall_miss_rate::cpu0.inst 0.021016 # miss rate for overall accesses 487system.l2c.overall_miss_rate::cpu0.data 0.434636 # miss rate for overall accesses 488system.l2c.overall_miss_rate::cpu1.inst 0.004687 # miss rate for overall accesses 489system.l2c.overall_miss_rate::cpu1.data 0.030627 # miss rate for overall accesses 490system.l2c.overall_miss_rate::total 0.168403 # miss rate for overall accesses 491system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72999.845556 # average ReadReq miss latency 492system.l2c.ReadReq_avg_miss_latency::cpu0.data 64995.250038 # average ReadReq miss latency 493system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74638.863323 # average ReadReq miss latency 494system.l2c.ReadReq_avg_miss_latency::cpu1.data 75521.863118 # average ReadReq miss latency 495system.l2c.ReadReq_avg_miss_latency::total 65425.435076 # average ReadReq miss latency 496system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 269.101037 # average UpgradeReq miss latency 497system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 744.104478 # average UpgradeReq miss latency 498system.l2c.UpgradeReq_avg_miss_latency::total 341.619466 # average UpgradeReq miss latency 499system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2628.919355 # average SCUpgradeReq miss latency 500system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1168.700000 # average SCUpgradeReq miss latency 501system.l2c.SCUpgradeReq_avg_miss_latency::total 1806.260563 # average SCUpgradeReq miss latency 502system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68632.080551 # average ReadExReq miss latency 503system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73023.363097 # average ReadExReq miss latency 504system.l2c.ReadExReq_avg_miss_latency::total 69198.546599 # average ReadExReq miss latency 505system.l2c.demand_avg_miss_latency::cpu0.inst 72999.845556 # average overall miss latency 506system.l2c.demand_avg_miss_latency::cpu0.data 66025.434543 # average overall miss latency 507system.l2c.demand_avg_miss_latency::cpu1.inst 74638.863323 # average overall miss latency 508system.l2c.demand_avg_miss_latency::cpu1.data 73178.900231 # average overall miss latency 509system.l2c.demand_avg_miss_latency::total 66561.107051 # average overall miss latency 510system.l2c.overall_avg_miss_latency::cpu0.inst 72999.845556 # average overall miss latency 511system.l2c.overall_avg_miss_latency::cpu0.data 66025.434543 # average overall miss latency 512system.l2c.overall_avg_miss_latency::cpu1.inst 74638.863323 # average overall miss latency 513system.l2c.overall_avg_miss_latency::cpu1.data 73178.900231 # average overall miss latency 514system.l2c.overall_avg_miss_latency::total 66561.107051 # average overall miss latency |
| 511system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 512system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 513system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 514system.l2c.blocked::no_targets 0 # number of cycles access was blocked 515system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 516system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 517system.l2c.fast_writes 0 # number of fast writes performed 518system.l2c.cache_copies 0 # number of cache copies performed | 515system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 518system.l2c.blocked::no_targets 0 # number of cycles access was blocked 519system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.l2c.fast_writes 0 # number of fast writes performed 522system.l2c.cache_copies 0 # number of cache copies performed |
| 519system.l2c.writebacks::writebacks 79532 # number of writebacks 520system.l2c.writebacks::total 79532 # number of writebacks | 523system.l2c.writebacks::writebacks 79533 # number of writebacks 524system.l2c.writebacks::total 79533 # number of writebacks |
| 521system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits 522system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits 523system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 524system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 525system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 526system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 527system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 528system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 529system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits | 525system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits 526system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits 527system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 528system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 529system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits 530system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 531system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 532system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits 533system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits |
| 530system.l2c.ReadReq_mshr_misses::cpu0.inst 11325 # number of ReadReq MSHR misses 531system.l2c.ReadReq_mshr_misses::cpu0.data 270740 # number of ReadReq MSHR misses 532system.l2c.ReadReq_mshr_misses::cpu1.inst 2164 # number of ReadReq MSHR misses | 534system.l2c.ReadReq_mshr_misses::cpu0.inst 11328 # number of ReadReq MSHR misses 535system.l2c.ReadReq_mshr_misses::cpu0.data 270739 # number of ReadReq MSHR misses 536system.l2c.ReadReq_mshr_misses::cpu1.inst 2165 # number of ReadReq MSHR misses |
| 533system.l2c.ReadReq_mshr_misses::cpu1.data 1052 # number of ReadReq MSHR misses | 537system.l2c.ReadReq_mshr_misses::cpu1.data 1052 # number of ReadReq MSHR misses |
| 534system.l2c.ReadReq_mshr_misses::total 285281 # number of ReadReq MSHR misses | 538system.l2c.ReadReq_mshr_misses::total 285284 # number of ReadReq MSHR misses |
| 535system.l2c.UpgradeReq_mshr_misses::cpu0.data 2603 # number of UpgradeReq MSHR misses | 539system.l2c.UpgradeReq_mshr_misses::cpu0.data 2603 # number of UpgradeReq MSHR misses |
| 536system.l2c.UpgradeReq_mshr_misses::cpu1.data 468 # number of UpgradeReq MSHR misses 537system.l2c.UpgradeReq_mshr_misses::total 3071 # number of UpgradeReq MSHR misses | 540system.l2c.UpgradeReq_mshr_misses::cpu1.data 469 # number of UpgradeReq MSHR misses 541system.l2c.UpgradeReq_mshr_misses::total 3072 # number of UpgradeReq MSHR misses |
| 538system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 62 # number of SCUpgradeReq MSHR misses 539system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 80 # number of SCUpgradeReq MSHR misses 540system.l2c.SCUpgradeReq_mshr_misses::total 142 # number of SCUpgradeReq MSHR misses 541system.l2c.ReadExReq_mshr_misses::cpu0.data 107000 # number of ReadExReq MSHR misses | 542system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 62 # number of SCUpgradeReq MSHR misses 543system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 80 # number of SCUpgradeReq MSHR misses 544system.l2c.SCUpgradeReq_mshr_misses::total 142 # number of SCUpgradeReq MSHR misses 545system.l2c.ReadExReq_mshr_misses::cpu0.data 107000 # number of ReadExReq MSHR misses |
| 542system.l2c.ReadExReq_mshr_misses::cpu1.data 15849 # number of ReadExReq MSHR misses 543system.l2c.ReadExReq_mshr_misses::total 122849 # number of ReadExReq MSHR misses 544system.l2c.demand_mshr_misses::cpu0.inst 11325 # number of demand (read+write) MSHR misses 545system.l2c.demand_mshr_misses::cpu0.data 377740 # number of demand (read+write) MSHR misses 546system.l2c.demand_mshr_misses::cpu1.inst 2164 # number of demand (read+write) MSHR misses 547system.l2c.demand_mshr_misses::cpu1.data 16901 # number of demand (read+write) MSHR misses 548system.l2c.demand_mshr_misses::total 408130 # number of demand (read+write) MSHR misses 549system.l2c.overall_mshr_misses::cpu0.inst 11325 # number of overall MSHR misses 550system.l2c.overall_mshr_misses::cpu0.data 377740 # number of overall MSHR misses 551system.l2c.overall_mshr_misses::cpu1.inst 2164 # number of overall MSHR misses 552system.l2c.overall_mshr_misses::cpu1.data 16901 # number of overall MSHR misses 553system.l2c.overall_mshr_misses::total 408130 # number of overall MSHR misses 554system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 689008754 # number of ReadReq MSHR miss cycles 555system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14211795014 # number of ReadReq MSHR miss cycles 556system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 132703500 # number of ReadReq MSHR miss cycles 557system.l2c.ReadReq_mshr_miss_latency::cpu1.data 66581750 # number of ReadReq MSHR miss cycles 558system.l2c.ReadReq_mshr_miss_latency::total 15100089018 # number of ReadReq MSHR miss cycles 559system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26041101 # number of UpgradeReq MSHR miss cycles 560system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4800968 # number of UpgradeReq MSHR miss cycles 561system.l2c.UpgradeReq_mshr_miss_latency::total 30842069 # number of UpgradeReq MSHR miss cycles | 546system.l2c.ReadExReq_mshr_misses::cpu1.data 15847 # number of ReadExReq MSHR misses 547system.l2c.ReadExReq_mshr_misses::total 122847 # number of ReadExReq MSHR misses 548system.l2c.demand_mshr_misses::cpu0.inst 11328 # number of demand (read+write) MSHR misses 549system.l2c.demand_mshr_misses::cpu0.data 377739 # number of demand (read+write) MSHR misses 550system.l2c.demand_mshr_misses::cpu1.inst 2165 # number of demand (read+write) MSHR misses 551system.l2c.demand_mshr_misses::cpu1.data 16899 # number of demand (read+write) MSHR misses 552system.l2c.demand_mshr_misses::total 408131 # number of demand (read+write) MSHR misses 553system.l2c.overall_mshr_misses::cpu0.inst 11328 # number of overall MSHR misses 554system.l2c.overall_mshr_misses::cpu0.data 377739 # number of overall MSHR misses 555system.l2c.overall_mshr_misses::cpu1.inst 2165 # number of overall MSHR misses 556system.l2c.overall_mshr_misses::cpu1.data 16899 # number of overall MSHR misses 557system.l2c.overall_mshr_misses::total 408131 # number of overall MSHR misses 558system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 682834500 # number of ReadReq MSHR miss cycles 559system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14211900500 # number of ReadReq MSHR miss cycles 560system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 134094500 # number of ReadReq MSHR miss cycles 561system.l2c.ReadReq_mshr_miss_latency::cpu1.data 66276000 # number of ReadReq MSHR miss cycles 562system.l2c.ReadReq_mshr_miss_latency::total 15095105500 # number of ReadReq MSHR miss cycles 563system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26034602 # number of UpgradeReq MSHR miss cycles 564system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4690469 # number of UpgradeReq MSHR miss cycles 565system.l2c.UpgradeReq_mshr_miss_latency::total 30725071 # number of UpgradeReq MSHR miss cycles |
| 562system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 620062 # number of SCUpgradeReq MSHR miss cycles 563system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 800080 # number of SCUpgradeReq MSHR miss cycles 564system.l2c.SCUpgradeReq_mshr_miss_latency::total 1420142 # number of SCUpgradeReq MSHR miss cycles | 566system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 620062 # number of SCUpgradeReq MSHR miss cycles 567system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 800080 # number of SCUpgradeReq MSHR miss cycles 568system.l2c.SCUpgradeReq_mshr_miss_latency::total 1420142 # number of SCUpgradeReq MSHR miss cycles |
| 565system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5999010131 # number of ReadExReq MSHR miss cycles 566system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 959576266 # number of ReadExReq MSHR miss cycles 567system.l2c.ReadExReq_mshr_miss_latency::total 6958586397 # number of ReadExReq MSHR miss cycles 568system.l2c.demand_mshr_miss_latency::cpu0.inst 689008754 # number of demand (read+write) MSHR miss cycles 569system.l2c.demand_mshr_miss_latency::cpu0.data 20210805145 # number of demand (read+write) MSHR miss cycles 570system.l2c.demand_mshr_miss_latency::cpu1.inst 132703500 # number of demand (read+write) MSHR miss cycles 571system.l2c.demand_mshr_miss_latency::cpu1.data 1026158016 # number of demand (read+write) MSHR miss cycles 572system.l2c.demand_mshr_miss_latency::total 22058675415 # number of demand (read+write) MSHR miss cycles 573system.l2c.overall_mshr_miss_latency::cpu0.inst 689008754 # number of overall MSHR miss cycles 574system.l2c.overall_mshr_miss_latency::cpu0.data 20210805145 # number of overall MSHR miss cycles 575system.l2c.overall_mshr_miss_latency::cpu1.inst 132703500 # number of overall MSHR miss cycles 576system.l2c.overall_mshr_miss_latency::cpu1.data 1026158016 # number of overall MSHR miss cycles 577system.l2c.overall_mshr_miss_latency::total 22058675415 # number of overall MSHR miss cycles 578system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 941946500 # number of ReadReq MSHR uncacheable cycles | 569system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5999575381 # number of ReadExReq MSHR miss cycles 570system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958453765 # number of ReadExReq MSHR miss cycles 571system.l2c.ReadExReq_mshr_miss_latency::total 6958029146 # number of ReadExReq MSHR miss cycles 572system.l2c.demand_mshr_miss_latency::cpu0.inst 682834500 # number of demand (read+write) MSHR miss cycles 573system.l2c.demand_mshr_miss_latency::cpu0.data 20211475881 # number of demand (read+write) MSHR miss cycles 574system.l2c.demand_mshr_miss_latency::cpu1.inst 134094500 # number of demand (read+write) MSHR miss cycles 575system.l2c.demand_mshr_miss_latency::cpu1.data 1024729765 # number of demand (read+write) MSHR miss cycles 576system.l2c.demand_mshr_miss_latency::total 22053134646 # number of demand (read+write) MSHR miss cycles 577system.l2c.overall_mshr_miss_latency::cpu0.inst 682834500 # number of overall MSHR miss cycles 578system.l2c.overall_mshr_miss_latency::cpu0.data 20211475881 # number of overall MSHR miss cycles 579system.l2c.overall_mshr_miss_latency::cpu1.inst 134094500 # number of overall MSHR miss cycles 580system.l2c.overall_mshr_miss_latency::cpu1.data 1024729765 # number of overall MSHR miss cycles 581system.l2c.overall_mshr_miss_latency::total 22053134646 # number of overall MSHR miss cycles 582system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 941946000 # number of ReadReq MSHR uncacheable cycles |
| 579system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 449028500 # number of ReadReq MSHR uncacheable cycles | 583system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 449028500 # number of ReadReq MSHR uncacheable cycles |
| 580system.l2c.ReadReq_mshr_uncacheable_latency::total 1390975000 # number of ReadReq MSHR uncacheable cycles 581system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1618779500 # number of WriteReq MSHR uncacheable cycles 582system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 858260500 # number of WriteReq MSHR uncacheable cycles 583system.l2c.WriteReq_mshr_uncacheable_latency::total 2477040000 # number of WriteReq MSHR uncacheable cycles 584system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2560726000 # number of overall MSHR uncacheable cycles 585system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1307289000 # number of overall MSHR uncacheable cycles 586system.l2c.overall_mshr_uncacheable_latency::total 3868015000 # number of overall MSHR uncacheable cycles 587system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.021000 # mshr miss rate for ReadReq accesses 588system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.417382 # mshr miss rate for ReadReq accesses 589system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004668 # mshr miss rate for ReadReq accesses | 584system.l2c.ReadReq_mshr_uncacheable_latency::total 1390974500 # number of ReadReq MSHR uncacheable cycles 585system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1618783500 # number of WriteReq MSHR uncacheable cycles 586system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 858261500 # number of WriteReq MSHR uncacheable cycles 587system.l2c.WriteReq_mshr_uncacheable_latency::total 2477045000 # number of WriteReq MSHR uncacheable cycles 588system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2560729500 # number of overall MSHR uncacheable cycles 589system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1307290000 # number of overall MSHR uncacheable cycles 590system.l2c.overall_mshr_uncacheable_latency::total 3868019500 # number of overall MSHR uncacheable cycles 591system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for ReadReq accesses 592system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.417395 # mshr miss rate for ReadReq accesses 593system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for ReadReq accesses |
| 590system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadReq accesses | 594system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadReq accesses |
| 591system.l2c.ReadReq_mshr_miss_rate::total 0.135686 # mshr miss rate for ReadReq accesses 592system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.950347 # mshr miss rate for UpgradeReq accesses 593system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.869888 # mshr miss rate for UpgradeReq accesses 594system.l2c.UpgradeReq_mshr_miss_rate::total 0.937138 # mshr miss rate for UpgradeReq accesses 595system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.720930 # mshr miss rate for SCUpgradeReq accesses 596system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SCUpgradeReq accesses 597system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.763441 # mshr miss rate for SCUpgradeReq accesses 598system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.485336 # mshr miss rate for ReadExReq accesses 599system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.157142 # mshr miss rate for ReadExReq accesses 600system.l2c.ReadExReq_mshr_miss_rate::total 0.382321 # mshr miss rate for ReadExReq accesses 601system.l2c.demand_mshr_miss_rate::cpu0.inst 0.021000 # mshr miss rate for demand accesses 602system.l2c.demand_mshr_miss_rate::cpu0.data 0.434619 # mshr miss rate for demand accesses 603system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004668 # mshr miss rate for demand accesses 604system.l2c.demand_mshr_miss_rate::cpu1.data 0.030629 # mshr miss rate for demand accesses 605system.l2c.demand_mshr_miss_rate::total 0.168382 # mshr miss rate for demand accesses 606system.l2c.overall_mshr_miss_rate::cpu0.inst 0.021000 # mshr miss rate for overall accesses 607system.l2c.overall_mshr_miss_rate::cpu0.data 0.434619 # mshr miss rate for overall accesses 608system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004668 # mshr miss rate for overall accesses 609system.l2c.overall_mshr_miss_rate::cpu1.data 0.030629 # mshr miss rate for overall accesses 610system.l2c.overall_mshr_miss_rate::total 0.168382 # mshr miss rate for overall accesses 611system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average ReadReq mshr miss latency 612system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.409744 # average ReadReq mshr miss latency 613system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average ReadReq mshr miss latency 614system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63290.636882 # average ReadReq mshr miss latency 615system.l2c.ReadReq_avg_mshr_miss_latency::total 52930.580789 # average ReadReq mshr miss latency 616system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.264695 # average UpgradeReq mshr miss latency 617system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10258.478632 # average UpgradeReq mshr miss latency 618system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10043.005210 # average UpgradeReq mshr miss latency | 595system.l2c.ReadReq_mshr_miss_rate::total 0.135701 # mshr miss rate for ReadReq accesses 596system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.950694 # mshr miss rate for UpgradeReq accesses 597system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870130 # mshr miss rate for UpgradeReq accesses 598system.l2c.UpgradeReq_mshr_miss_rate::total 0.937443 # mshr miss rate for UpgradeReq accesses 599system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.712644 # mshr miss rate for SCUpgradeReq accesses 600system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.792079 # mshr miss rate for SCUpgradeReq accesses 601system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755319 # mshr miss rate for SCUpgradeReq accesses 602system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.485366 # mshr miss rate for ReadExReq accesses 603system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.157133 # mshr miss rate for ReadExReq accesses 604system.l2c.ReadExReq_mshr_miss_rate::total 0.382340 # mshr miss rate for ReadExReq accesses 605system.l2c.demand_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for demand accesses 606system.l2c.demand_mshr_miss_rate::cpu0.data 0.434636 # mshr miss rate for demand accesses 607system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for demand accesses 608system.l2c.demand_mshr_miss_rate::cpu1.data 0.030627 # mshr miss rate for demand accesses 609system.l2c.demand_mshr_miss_rate::total 0.168399 # mshr miss rate for demand accesses 610system.l2c.overall_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for overall accesses 611system.l2c.overall_mshr_miss_rate::cpu0.data 0.434636 # mshr miss rate for overall accesses 612system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for overall accesses 613system.l2c.overall_mshr_miss_rate::cpu1.data 0.030627 # mshr miss rate for overall accesses 614system.l2c.overall_mshr_miss_rate::total 0.168399 # mshr miss rate for overall accesses 615system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average ReadReq mshr miss latency 616system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.993252 # average ReadReq mshr miss latency 617system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average ReadReq mshr miss latency 618system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63000 # average ReadReq mshr miss latency 619system.l2c.ReadReq_avg_mshr_miss_latency::total 52912.555559 # average ReadReq mshr miss latency 620system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001.767960 # average UpgradeReq mshr miss latency 621system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency 622system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.650716 # average UpgradeReq mshr miss latency |
| 619system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency 620system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency 621system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 623system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency 624system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency 625system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 622system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56065.515243 # average ReadExReq mshr miss latency 623system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60544.909206 # average ReadExReq mshr miss latency 624system.l2c.ReadExReq_avg_mshr_miss_latency::total 56643.410992 # average ReadExReq mshr miss latency 625system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency 626system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency 627system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency 628system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency 629system.l2c.demand_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency 630system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency 631system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency 632system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency 633system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency 634system.l2c.overall_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency | 626system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56070.797953 # average ReadExReq mshr miss latency 627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60481.716729 # average ReadExReq mshr miss latency 628system.l2c.ReadExReq_avg_mshr_miss_latency::total 56639.797032 # average ReadExReq mshr miss latency 629system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency 630system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency 631system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency 632system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency 633system.l2c.demand_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency 634system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency 635system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency 636system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency 637system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency 638system.l2c.overall_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency |
| 635system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 636system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 637system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 638system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 639system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 640system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 641system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 642system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 643system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 644system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 645system.iocache.tags.replacements 41699 # number of replacements | 639system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 640system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 641system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 642system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 643system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 644system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 645system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 646system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 647system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 648system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 649system.iocache.tags.replacements 41699 # number of replacements |
| 646system.iocache.tags.tagsinuse 0.570023 # Cycle average of tags in use | 650system.iocache.tags.tagsinuse 0.569942 # Cycle average of tags in use |
| 647system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 648system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 649system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 651system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 652system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. 653system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 650system.iocache.tags.warmup_cycle 1756486423000 # Cycle when the warmup percentage was hit. 651system.iocache.tags.occ_blocks::tsunami.ide 0.570023 # Average occupied blocks per requestor 652system.iocache.tags.occ_percent::tsunami.ide 0.035626 # Average percentage of cache occupancy 653system.iocache.tags.occ_percent::total 0.035626 # Average percentage of cache occupancy | 654system.iocache.tags.warmup_cycle 1756486320000 # Cycle when the warmup percentage was hit. 655system.iocache.tags.occ_blocks::tsunami.ide 0.569942 # Average occupied blocks per requestor 656system.iocache.tags.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy 657system.iocache.tags.occ_percent::total 0.035621 # Average percentage of cache occupancy |
| 654system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 655system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 656system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 657system.iocache.tags.tag_accesses 375552 # Number of tag accesses 658system.iocache.tags.data_accesses 375552 # Number of data accesses | 658system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 659system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 660system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 661system.iocache.tags.tag_accesses 375552 # Number of tag accesses 662system.iocache.tags.data_accesses 375552 # Number of data accesses |
| 663system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 664system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits |
|
| 659system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 660system.iocache.ReadReq_misses::total 176 # number of ReadReq misses | 665system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses 666system.iocache.ReadReq_misses::total 176 # number of ReadReq misses |
| 661system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 662system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 663system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses 664system.iocache.demand_misses::total 41728 # number of demand (read+write) misses 665system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses 666system.iocache.overall_misses::total 41728 # number of overall misses 667system.iocache.ReadReq_miss_latency::tsunami.ide 21474883 # number of ReadReq miss cycles 668system.iocache.ReadReq_miss_latency::total 21474883 # number of ReadReq miss cycles 669system.iocache.WriteReq_miss_latency::tsunami.ide 12370994210 # number of WriteReq miss cycles 670system.iocache.WriteReq_miss_latency::total 12370994210 # number of WriteReq miss cycles 671system.iocache.demand_miss_latency::tsunami.ide 12392469093 # number of demand (read+write) miss cycles 672system.iocache.demand_miss_latency::total 12392469093 # number of demand (read+write) miss cycles 673system.iocache.overall_miss_latency::tsunami.ide 12392469093 # number of overall miss cycles 674system.iocache.overall_miss_latency::total 12392469093 # number of overall miss cycles | 667system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses 668system.iocache.demand_misses::total 176 # number of demand (read+write) misses 669system.iocache.overall_misses::tsunami.ide 176 # number of overall misses 670system.iocache.overall_misses::total 176 # number of overall misses 671system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles 672system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles 673system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles 674system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles 675system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles 676system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles |
| 675system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 676system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) | 677system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) 678system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) |
| 677system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 678system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 679system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses 680system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses 681system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses 682system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses | 679system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 680system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 681system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses 682system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses 683system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses 684system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses |
| 683system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 684system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 685system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 686system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 685system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 686system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses | |
| 687system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 688system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 689system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 690system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 687system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 688system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 689system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 690system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 691system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122016.380682 # average ReadReq miss latency 692system.iocache.ReadReq_avg_miss_latency::total 122016.380682 # average ReadReq miss latency 693system.iocache.WriteReq_avg_miss_latency::tsunami.ide 297723.195273 # average WriteReq miss latency 694system.iocache.WriteReq_avg_miss_latency::total 297723.195273 # average WriteReq miss latency 695system.iocache.demand_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency 696system.iocache.demand_avg_miss_latency::total 296982.100580 # average overall miss latency 697system.iocache.overall_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency 698system.iocache.overall_avg_miss_latency::total 296982.100580 # average overall miss latency 699system.iocache.blocked_cycles::no_mshrs 362942 # number of cycles access was blocked | 691system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency 692system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency 693system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency 694system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency 695system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency 696system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency 697system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 700system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 698system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 701system.iocache.blocked::no_mshrs 28216 # number of cycles access was blocked | 699system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 702system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 700system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 703system.iocache.avg_blocked_cycles::no_mshrs 12.862986 # average number of cycles each access was blocked | 701system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 704system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 702system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 705system.iocache.fast_writes 0 # number of fast writes performed | 703system.iocache.fast_writes 41552 # number of fast writes performed |
| 706system.iocache.cache_copies 0 # number of cache copies performed | 704system.iocache.cache_copies 0 # number of cache copies performed |
| 707system.iocache.writebacks::writebacks 41523 # number of writebacks 708system.iocache.writebacks::total 41523 # number of writebacks | |
| 709system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 710system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses | 705system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses 706system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses |
| 711system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 712system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 713system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses 714system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses 715system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses 716system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses 717system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321883 # number of ReadReq MSHR miss cycles 718system.iocache.ReadReq_mshr_miss_latency::total 12321883 # number of ReadReq MSHR miss cycles 719system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10208100710 # number of WriteReq MSHR miss cycles 720system.iocache.WriteReq_mshr_miss_latency::total 10208100710 # number of WriteReq MSHR miss cycles 721system.iocache.demand_mshr_miss_latency::tsunami.ide 10220422593 # number of demand (read+write) MSHR miss cycles 722system.iocache.demand_mshr_miss_latency::total 10220422593 # number of demand (read+write) MSHR miss cycles 723system.iocache.overall_mshr_miss_latency::tsunami.ide 10220422593 # number of overall MSHR miss cycles 724system.iocache.overall_mshr_miss_latency::total 10220422593 # number of overall MSHR miss cycles | 707system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses 708system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses 709system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses 710system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses 711system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses 712system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses 713system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles 714system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles 715system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2504351556 # number of WriteInvalidateReq MSHR miss cycles 716system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2504351556 # number of WriteInvalidateReq MSHR miss cycles 717system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles 718system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles 719system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles 720system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles |
| 725system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 726system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 721system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 722system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 727system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 728system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses | 723system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses 724system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
| 729system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 730system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 731system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 732system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 725system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 726system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 727system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 728system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 733system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70010.698864 # average ReadReq mshr miss latency 734system.iocache.ReadReq_avg_mshr_miss_latency::total 70010.698864 # average ReadReq mshr miss latency 735system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 245670.502262 # average WriteReq mshr miss latency 736system.iocache.WriteReq_avg_mshr_miss_latency::total 245670.502262 # average WriteReq mshr miss latency 737system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency 738system.iocache.demand_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency 739system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency 740system.iocache.overall_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency | 729system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency 730system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency 731system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency 732system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency 733system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency 734system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency 735system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency 736system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency |
| 741system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 742system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 743system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 744system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 745system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 746system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 747system.disk0.dma_write_txs 395 # Number of DMA write transactions. 748system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 749system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 750system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 751system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 752system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 753system.disk2.dma_write_txs 1 # Number of DMA write transactions. 754system.cpu0.dtb.fetch_hits 0 # ITB hits 755system.cpu0.dtb.fetch_misses 0 # ITB misses 756system.cpu0.dtb.fetch_acv 0 # ITB acv 757system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 737system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 738system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 739system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 740system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 741system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 742system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 743system.disk0.dma_write_txs 395 # Number of DMA write transactions. 744system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 745system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 746system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 747system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 748system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 749system.disk2.dma_write_txs 1 # Number of DMA write transactions. 750system.cpu0.dtb.fetch_hits 0 # ITB hits 751system.cpu0.dtb.fetch_misses 0 # ITB misses 752system.cpu0.dtb.fetch_acv 0 # ITB acv 753system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 758system.cpu0.dtb.read_hits 6067358 # DTB read hits | 754system.cpu0.dtb.read_hits 6067147 # DTB read hits |
| 759system.cpu0.dtb.read_misses 7765 # DTB read misses 760system.cpu0.dtb.read_acv 210 # DTB read access violations 761system.cpu0.dtb.read_accesses 524069 # DTB read accesses | 755system.cpu0.dtb.read_misses 7765 # DTB read misses 756system.cpu0.dtb.read_acv 210 # DTB read access violations 757system.cpu0.dtb.read_accesses 524069 # DTB read accesses |
| 762system.cpu0.dtb.write_hits 4265662 # DTB write hits | 758system.cpu0.dtb.write_hits 4265547 # DTB write hits |
| 763system.cpu0.dtb.write_misses 910 # DTB write misses 764system.cpu0.dtb.write_acv 133 # DTB write access violations 765system.cpu0.dtb.write_accesses 202595 # DTB write accesses | 759system.cpu0.dtb.write_misses 910 # DTB write misses 760system.cpu0.dtb.write_acv 133 # DTB write access violations 761system.cpu0.dtb.write_accesses 202595 # DTB write accesses |
| 766system.cpu0.dtb.data_hits 10333020 # DTB hits | 762system.cpu0.dtb.data_hits 10332694 # DTB hits |
| 767system.cpu0.dtb.data_misses 8675 # DTB misses 768system.cpu0.dtb.data_acv 343 # DTB access violations 769system.cpu0.dtb.data_accesses 726664 # DTB accesses | 763system.cpu0.dtb.data_misses 8675 # DTB misses 764system.cpu0.dtb.data_acv 343 # DTB access violations 765system.cpu0.dtb.data_accesses 726664 # DTB accesses |
| 770system.cpu0.itb.fetch_hits 3354842 # ITB hits | 766system.cpu0.itb.fetch_hits 3354719 # ITB hits |
| 771system.cpu0.itb.fetch_misses 3984 # ITB misses 772system.cpu0.itb.fetch_acv 184 # ITB acv | 767system.cpu0.itb.fetch_misses 3984 # ITB misses 768system.cpu0.itb.fetch_acv 184 # ITB acv |
| 773system.cpu0.itb.fetch_accesses 3358826 # ITB accesses | 769system.cpu0.itb.fetch_accesses 3358703 # ITB accesses |
| 774system.cpu0.itb.read_hits 0 # DTB read hits 775system.cpu0.itb.read_misses 0 # DTB read misses 776system.cpu0.itb.read_acv 0 # DTB read access violations 777system.cpu0.itb.read_accesses 0 # DTB read accesses 778system.cpu0.itb.write_hits 0 # DTB write hits 779system.cpu0.itb.write_misses 0 # DTB write misses 780system.cpu0.itb.write_acv 0 # DTB write access violations 781system.cpu0.itb.write_accesses 0 # DTB write accesses 782system.cpu0.itb.data_hits 0 # DTB hits 783system.cpu0.itb.data_misses 0 # DTB misses 784system.cpu0.itb.data_acv 0 # DTB access violations 785system.cpu0.itb.data_accesses 0 # DTB accesses | 770system.cpu0.itb.read_hits 0 # DTB read hits 771system.cpu0.itb.read_misses 0 # DTB read misses 772system.cpu0.itb.read_acv 0 # DTB read access violations 773system.cpu0.itb.read_accesses 0 # DTB read accesses 774system.cpu0.itb.write_hits 0 # DTB write hits 775system.cpu0.itb.write_misses 0 # DTB write misses 776system.cpu0.itb.write_acv 0 # DTB write access violations 777system.cpu0.itb.write_accesses 0 # DTB write accesses 778system.cpu0.itb.data_hits 0 # DTB hits 779system.cpu0.itb.data_misses 0 # DTB misses 780system.cpu0.itb.data_acv 0 # DTB access violations 781system.cpu0.itb.data_accesses 0 # DTB accesses |
| 786system.cpu0.numCycles 3925644369 # number of cpu cycles simulated | 782system.cpu0.numCycles 3925630437 # number of cpu cycles simulated |
| 787system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 788system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 783system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 784system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 789system.cpu0.committedInsts 38276564 # Number of instructions committed 790system.cpu0.committedOps 38276564 # Number of ops (including micro ops) committed 791system.cpu0.num_int_alu_accesses 35596868 # Number of integer alu accesses 792system.cpu0.num_fp_alu_accesses 153627 # Number of float alu accesses 793system.cpu0.num_func_calls 936507 # number of times a function call or return occured 794system.cpu0.num_conditional_control_insts 4464991 # number of instructions that are conditional controls 795system.cpu0.num_int_insts 35596868 # number of integer instructions 796system.cpu0.num_fp_insts 153627 # number of float instructions 797system.cpu0.num_int_register_reads 48919002 # number of times the integer registers were read 798system.cpu0.num_int_register_writes 26532177 # number of times the integer registers were written 799system.cpu0.num_fp_register_reads 75066 # number of times the floating registers were read 800system.cpu0.num_fp_register_writes 75978 # number of times the floating registers were written 801system.cpu0.num_mem_refs 10366198 # number of memory refs 802system.cpu0.num_load_insts 6090760 # Number of load instructions 803system.cpu0.num_store_insts 4275438 # Number of store instructions 804system.cpu0.num_idle_cycles 3742234246.498094 # Number of idle cycles 805system.cpu0.num_busy_cycles 183410122.501907 # Number of busy cycles 806system.cpu0.not_idle_fraction 0.046721 # Percentage of non-idle cycles 807system.cpu0.idle_fraction 0.953279 # Percentage of idle cycles 808system.cpu0.Branches 5694814 # Number of branches fetched 809system.cpu0.op_class::No_OpClass 2096369 5.48% 5.48% # Class of executed instruction 810system.cpu0.op_class::IntAlu 24995370 65.29% 70.76% # Class of executed instruction 811system.cpu0.op_class::IntMult 39322 0.10% 70.86% # Class of executed instruction 812system.cpu0.op_class::IntDiv 0 0.00% 70.86% # Class of executed instruction 813system.cpu0.op_class::FloatAdd 12602 0.03% 70.90% # Class of executed instruction | 785system.cpu0.committedInsts 38276405 # Number of instructions committed 786system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed 787system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses 788system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses 789system.cpu0.num_func_calls 936479 # number of times a function call or return occured 790system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls 791system.cpu0.num_int_insts 35596815 # number of integer instructions 792system.cpu0.num_fp_insts 153493 # number of float instructions 793system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read 794system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written 795system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read 796system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written 797system.cpu0.num_mem_refs 10365856 # number of memory refs 798system.cpu0.num_load_insts 6090539 # Number of load instructions 799system.cpu0.num_store_insts 4275317 # Number of store instructions 800system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles 801system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles 802system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles 803system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles 804system.cpu0.Branches 5694884 # Number of branches fetched 805system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction 806system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction 807system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction 808system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction 809system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction |
| 814system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction 815system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction 816system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction 817system.cpu0.op_class::FloatDiv 1883 0.00% 70.90% # Class of executed instruction 818system.cpu0.op_class::FloatSqrt 0 0.00% 70.90% # Class of executed instruction 819system.cpu0.op_class::SimdAdd 0 0.00% 70.90% # Class of executed instruction 820system.cpu0.op_class::SimdAddAcc 0 0.00% 70.90% # Class of executed instruction 821system.cpu0.op_class::SimdAlu 0 0.00% 70.90% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 831system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.90% # Class of executed instruction 832system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.90% # Class of executed instruction 833system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.90% # Class of executed instruction 834system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.90% # Class of executed instruction 835system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Class of executed instruction 836system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction 837system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction 838system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction | 810system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction 811system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction 812system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction 813system.cpu0.op_class::FloatDiv 1883 0.00% 70.90% # Class of executed instruction 814system.cpu0.op_class::FloatSqrt 0 0.00% 70.90% # Class of executed instruction 815system.cpu0.op_class::SimdAdd 0 0.00% 70.90% # Class of executed instruction 816system.cpu0.op_class::SimdAddAcc 0 0.00% 70.90% # Class of executed instruction 817system.cpu0.op_class::SimdAlu 0 0.00% 70.90% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 827system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.90% # Class of executed instruction 828system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.90% # Class of executed instruction 829system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.90% # Class of executed instruction 830system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.90% # Class of executed instruction 831system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Class of executed instruction 832system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction 833system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction 834system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction |
| 839system.cpu0.op_class::MemRead 6233117 16.28% 87.18% # Class of executed instruction 840system.cpu0.op_class::MemWrite 4280683 11.18% 98.36% # Class of executed instruction 841system.cpu0.op_class::IprAccess 626236 1.64% 100.00% # Class of executed instruction | 835system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction 836system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction 837system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction |
| 842system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 838system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 843system.cpu0.op_class::total 38285582 # Class of executed instruction | 839system.cpu0.op_class::total 38285423 # Class of executed instruction |
| 844system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 840system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 845system.cpu0.kern.inst.quiesce 4866 # number of quiesce instructions executed 846system.cpu0.kern.inst.hwrei 138364 # number of hwrei instructions executed 847system.cpu0.kern.ipl_count::0 44810 38.76% 38.76% # number of times we switched to this ipl | 841system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed 842system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed 843system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl |
| 848system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl 849system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl 850system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl | 844system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl 845system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl 846system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl |
| 851system.cpu0.kern.ipl_count::31 68668 59.40% 100.00% # number of times we switched to this ipl 852system.cpu0.kern.ipl_count::total 115600 # number of times we switched to this ipl 853system.cpu0.kern.ipl_good::0 44285 48.84% 48.84% # number of times we switched to this ipl from a different ipl | 847system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl 848system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl 849system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl |
| 854system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl 855system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl 856system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl | 850system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl 851system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl 852system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl |
| 857system.cpu0.kern.ipl_good::31 44269 48.82% 100.00% # number of times we switched to this ipl from a different ipl 858system.cpu0.kern.ipl_good::total 90676 # number of times we switched to this ipl from a different ipl 859system.cpu0.kern.ipl_ticks::0 1909704051500 97.29% 97.29% # number of cycles we spent at this ipl 860system.cpu0.kern.ipl_ticks::21 94854000 0.00% 97.30% # number of cycles we spent at this ipl 861system.cpu0.kern.ipl_ticks::22 764030500 0.04% 97.34% # number of cycles we spent at this ipl | 853system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl 854system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl 855system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl 856system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl 857system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl |
| 862system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl | 858system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl |
| 863system.cpu0.kern.ipl_ticks::31 52245891000 2.66% 100.00% # number of cycles we spent at this ipl 864system.cpu0.kern.ipl_ticks::total 1962821412500 # number of cycles we spent at this ipl 865system.cpu0.kern.ipl_used::0 0.988284 # fraction of swpipl calls that actually changed the ipl | 859system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl 860system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl 861system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl |
| 866system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 867system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 868system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 862system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 863system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 864system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 869system.cpu0.kern.ipl_used::31 0.644682 # fraction of swpipl calls that actually changed the ipl | 865system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl |
| 870system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl 871system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 872system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 873system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 874system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 875system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 876system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 877system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed --- 20 unchanged lines hidden (view full) --- 898system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 899system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 900system.cpu0.kern.syscall::total 234 # number of syscalls executed 901system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 902system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # number of callpals executed 903system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 904system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 905system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed | 866system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl 867system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 868system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 869system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 870system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 871system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 872system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 873system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed --- 20 unchanged lines hidden (view full) --- 894system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 895system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 896system.cpu0.kern.syscall::total 234 # number of syscalls executed 897system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 898system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # number of callpals executed 899system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed 900system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed 901system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed |
| 906system.cpu0.kern.callpal::swpctx 2218 1.80% 1.88% # number of callpals executed | 902system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed |
| 907system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed 908system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed | 903system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed 904system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed |
| 909system.cpu0.kern.callpal::swpipl 109461 88.95% 90.88% # number of callpals executed | 905system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed |
| 910system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed 911system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed 912system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed 913system.cpu0.kern.callpal::rdusp 9 0.01% 96.30% # number of callpals executed 914system.cpu0.kern.callpal::whami 2 0.00% 96.30% # number of callpals executed 915system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed 916system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed 917system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed | 906system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed 907system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed 908system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed 909system.cpu0.kern.callpal::rdusp 9 0.01% 96.30% # number of callpals executed 910system.cpu0.kern.callpal::whami 2 0.00% 96.30% # number of callpals executed 911system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed 912system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed 913system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed |
| 918system.cpu0.kern.callpal::total 123054 # number of callpals executed 919system.cpu0.kern.mode_switch::kernel 5726 # number of protection mode switches 920system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches | 914system.cpu0.kern.callpal::total 123047 # number of callpals executed 915system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches 916system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches |
| 921system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 917system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 922system.cpu0.kern.mode_good::kernel 1370 923system.cpu0.kern.mode_good::user 1371 | 918system.cpu0.kern.mode_good::kernel 1371 919system.cpu0.kern.mode_good::user 1372 |
| 924system.cpu0.kern.mode_good::idle 0 | 920system.cpu0.kern.mode_good::idle 0 |
| 925system.cpu0.kern.mode_switch_good::kernel 0.239260 # fraction of useful protection mode switches | 921system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches |
| 926system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 927system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 922system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 923system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 928system.cpu0.kern.mode_switch_good::total 0.386220 # fraction of useful protection mode switches 929system.cpu0.kern.mode_ticks::kernel 1959031016000 99.81% 99.81% # number of ticks spent at the given mode 930system.cpu0.kern.mode_ticks::user 3790392000 0.19% 100.00% # number of ticks spent at the given mode | 924system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches 925system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode 926system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode |
| 931system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 927system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 932system.cpu0.kern.swap_context 2219 # number of times the context was actually changed | 928system.cpu0.kern.swap_context 2217 # number of times the context was actually changed |
| 933system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 934system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 935system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 936system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 937system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 938system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 939system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 940system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 956system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 957system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 958system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 959system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 960system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 961system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 962system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 963system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 929system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 930system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 931system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 932system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 933system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 934system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 935system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 936system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 952system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 953system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 954system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 955system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 956system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 957system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 958system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 959system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 964system.toL2Bus.throughput 108070579 # Throughput (bytes/s) 965system.toL2Bus.trans_dist::ReadReq 2148343 # Transaction distribution 966system.toL2Bus.trans_dist::ReadResp 2148328 # Transaction distribution | 960system.toL2Bus.throughput 109416622 # Throughput (bytes/s) 961system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution 962system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution |
| 967system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution 968system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution | 963system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution 964system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution |
| 969system.toL2Bus.trans_dist::Writeback 850135 # Transaction distribution 970system.toL2Bus.trans_dist::UpgradeReq 4614 # Transaction distribution 971system.toL2Bus.trans_dist::SCUpgradeReq 1062 # Transaction distribution 972system.toL2Bus.trans_dist::UpgradeResp 5676 # Transaction distribution 973system.toL2Bus.trans_dist::ReadExReq 363639 # Transaction distribution 974system.toL2Bus.trans_dist::ReadExResp 322090 # Transaction distribution 975system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078600 # Packet count per connected master and slave (bytes) 976system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181406 # Packet count per connected master and slave (bytes) 977system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927231 # Packet count per connected master and slave (bytes) 978system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598323 # Packet count per connected master and slave (bytes) 979system.toL2Bus.pkt_count::total 5785560 # Packet count per connected master and slave (bytes) 980system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34514560 # Cumulative packet size per connected master and slave (bytes) 981system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81611821 # Cumulative packet size per connected master and slave (bytes) 982system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29671360 # Cumulative packet size per connected master and slave (bytes) 983system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63815893 # Cumulative packet size per connected master and slave (bytes) 984system.toL2Bus.tot_pkt_size::total 209613634 # Cumulative packet size per connected master and slave (bytes) 985system.toL2Bus.data_through_bus 209603138 # Total data (bytes) 986system.toL2Bus.snoop_data_through_bus 2520192 # Total snoop data (bytes) 987system.toL2Bus.reqLayer0.occupancy 5075991989 # Layer occupancy (ticks) | 965system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution 966system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution 967system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution 968system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution 969system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution 970system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution 971system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution 972system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes) 973system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes) 974system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes) 975system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes) 976system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes) 977system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes) 978system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes) 979system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes) 980system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes) 981system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes) 982system.toL2Bus.data_through_bus 209584002 # Total data (bytes) 983system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes) 984system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks) |
| 988system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) | 985system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) |
| 989system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) | 986system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) |
| 990system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 987system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 991system.toL2Bus.respLayer0.occupancy 2429088500 # Layer occupancy (ticks) | 988system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks) |
| 992system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 989system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 993system.toL2Bus.respLayer1.occupancy 4030648808 # Layer occupancy (ticks) | 990system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks) |
| 994system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) | 991system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 995system.toL2Bus.respLayer2.occupancy 2086694241 # Layer occupancy (ticks) | 992system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks) |
| 996system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) | 993system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 997system.toL2Bus.respLayer3.occupancy 2646669064 # Layer occupancy (ticks) | 994system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks) |
| 998system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) | 995system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) |
| 999system.iobus.throughput 1391043 # Throughput (bytes/s) | 996system.iobus.throughput 1391048 # Throughput (bytes/s) |
| 1000system.iobus.trans_dist::ReadReq 7376 # Transaction distribution 1001system.iobus.trans_dist::ReadResp 7376 # Transaction distribution 1002system.iobus.trans_dist::WriteReq 53966 # Transaction distribution 1003system.iobus.trans_dist::WriteResp 53966 # Transaction distribution 1004system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10614 # Packet count per connected master and slave (bytes) 1005system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 484 # Packet count per connected master and slave (bytes) 1006system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1007system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 43 unchanged lines hidden (view full) --- 1051system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1052system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1053system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1054system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1055system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1056system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1057system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1058system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 997system.iobus.trans_dist::ReadReq 7376 # Transaction distribution 998system.iobus.trans_dist::ReadResp 7376 # Transaction distribution 999system.iobus.trans_dist::WriteReq 53966 # Transaction distribution 1000system.iobus.trans_dist::WriteResp 53966 # Transaction distribution 1001system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10614 # Packet count per connected master and slave (bytes) 1002system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 484 # Packet count per connected master and slave (bytes) 1003system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) --- 43 unchanged lines hidden (view full) --- 1048system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1049system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1050system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1051system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1052system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1053system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1054system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1055system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1059system.iobus.reqLayer29.occupancy 380139843 # Layer occupancy (ticks) | 1056system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks) |
| 1060system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1061system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1062system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1063system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks) 1064system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1057system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1058system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1059system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 1060system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks) 1061system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1065system.iobus.respLayer1.occupancy 43231750 # Layer occupancy (ticks) | 1062system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks) |
| 1066system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1063system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1067system.cpu0.icache.tags.replacements 538677 # number of replacements 1068system.cpu0.icache.tags.tagsinuse 508.393435 # Cycle average of tags in use 1069system.cpu0.icache.tags.total_refs 37746273 # Total number of references to valid blocks. 1070system.cpu0.icache.tags.sampled_refs 539189 # Sample count of references to valid blocks. 1071system.cpu0.icache.tags.avg_refs 70.005644 # Average number of references to valid blocks. | 1064system.cpu0.icache.tags.replacements 538541 # number of replacements 1065system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use 1066system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks. 1067system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks. 1068system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks. |
| 1072system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. | 1069system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. |
| 1073system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393435 # Average occupied blocks per requestor | 1070system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor |
| 1074system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy 1075system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy 1076system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1077system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1078system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 1079system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id 1080system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 1081system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1071system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy 1072system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy 1073system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1074system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1075system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 1076system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id 1077system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id 1078system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1082system.cpu0.icache.tags.tag_accesses 38824893 # Number of tag accesses 1083system.cpu0.icache.tags.data_accesses 38824893 # Number of data accesses 1084system.cpu0.icache.ReadReq_hits::cpu0.inst 37746273 # number of ReadReq hits 1085system.cpu0.icache.ReadReq_hits::total 37746273 # number of ReadReq hits 1086system.cpu0.icache.demand_hits::cpu0.inst 37746273 # number of demand (read+write) hits 1087system.cpu0.icache.demand_hits::total 37746273 # number of demand (read+write) hits 1088system.cpu0.icache.overall_hits::cpu0.inst 37746273 # number of overall hits 1089system.cpu0.icache.overall_hits::total 37746273 # number of overall hits 1090system.cpu0.icache.ReadReq_misses::cpu0.inst 539310 # number of ReadReq misses 1091system.cpu0.icache.ReadReq_misses::total 539310 # number of ReadReq misses 1092system.cpu0.icache.demand_misses::cpu0.inst 539310 # number of demand (read+write) misses 1093system.cpu0.icache.demand_misses::total 539310 # number of demand (read+write) misses 1094system.cpu0.icache.overall_misses::cpu0.inst 539310 # number of overall misses 1095system.cpu0.icache.overall_misses::total 539310 # number of overall misses 1096system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7764312000 # number of ReadReq miss cycles 1097system.cpu0.icache.ReadReq_miss_latency::total 7764312000 # number of ReadReq miss cycles 1098system.cpu0.icache.demand_miss_latency::cpu0.inst 7764312000 # number of demand (read+write) miss cycles 1099system.cpu0.icache.demand_miss_latency::total 7764312000 # number of demand (read+write) miss cycles 1100system.cpu0.icache.overall_miss_latency::cpu0.inst 7764312000 # number of overall miss cycles 1101system.cpu0.icache.overall_miss_latency::total 7764312000 # number of overall miss cycles 1102system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285583 # number of ReadReq accesses(hits+misses) 1103system.cpu0.icache.ReadReq_accesses::total 38285583 # number of ReadReq accesses(hits+misses) 1104system.cpu0.icache.demand_accesses::cpu0.inst 38285583 # number of demand (read+write) accesses 1105system.cpu0.icache.demand_accesses::total 38285583 # number of demand (read+write) accesses 1106system.cpu0.icache.overall_accesses::cpu0.inst 38285583 # number of overall (read+write) accesses 1107system.cpu0.icache.overall_accesses::total 38285583 # number of overall (read+write) accesses 1108system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014087 # miss rate for ReadReq accesses 1109system.cpu0.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses 1110system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014087 # miss rate for demand accesses 1111system.cpu0.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses 1112system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014087 # miss rate for overall accesses 1113system.cpu0.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses 1114system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14396.751405 # average ReadReq miss latency 1115system.cpu0.icache.ReadReq_avg_miss_latency::total 14396.751405 # average ReadReq miss latency 1116system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14396.751405 # average overall miss latency 1117system.cpu0.icache.demand_avg_miss_latency::total 14396.751405 # average overall miss latency 1118system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14396.751405 # average overall miss latency 1119system.cpu0.icache.overall_avg_miss_latency::total 14396.751405 # average overall miss latency | 1079system.cpu0.icache.tags.tag_accesses 38824598 # Number of tag accesses 1080system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses 1081system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits 1082system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits 1083system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits 1084system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits 1085system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits 1086system.cpu0.icache.overall_hits::total 37746250 # number of overall hits 1087system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses 1088system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses 1089system.cpu0.icache.demand_misses::cpu0.inst 539174 # number of demand (read+write) misses 1090system.cpu0.icache.demand_misses::total 539174 # number of demand (read+write) misses 1091system.cpu0.icache.overall_misses::cpu0.inst 539174 # number of overall misses 1092system.cpu0.icache.overall_misses::total 539174 # number of overall misses 1093system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7756302744 # number of ReadReq miss cycles 1094system.cpu0.icache.ReadReq_miss_latency::total 7756302744 # number of ReadReq miss cycles 1095system.cpu0.icache.demand_miss_latency::cpu0.inst 7756302744 # number of demand (read+write) miss cycles 1096system.cpu0.icache.demand_miss_latency::total 7756302744 # number of demand (read+write) miss cycles 1097system.cpu0.icache.overall_miss_latency::cpu0.inst 7756302744 # number of overall miss cycles 1098system.cpu0.icache.overall_miss_latency::total 7756302744 # number of overall miss cycles 1099system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285424 # number of ReadReq accesses(hits+misses) 1100system.cpu0.icache.ReadReq_accesses::total 38285424 # number of ReadReq accesses(hits+misses) 1101system.cpu0.icache.demand_accesses::cpu0.inst 38285424 # number of demand (read+write) accesses 1102system.cpu0.icache.demand_accesses::total 38285424 # number of demand (read+write) accesses 1103system.cpu0.icache.overall_accesses::cpu0.inst 38285424 # number of overall (read+write) accesses 1104system.cpu0.icache.overall_accesses::total 38285424 # number of overall (read+write) accesses 1105system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014083 # miss rate for ReadReq accesses 1106system.cpu0.icache.ReadReq_miss_rate::total 0.014083 # miss rate for ReadReq accesses 1107system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014083 # miss rate for demand accesses 1108system.cpu0.icache.demand_miss_rate::total 0.014083 # miss rate for demand accesses 1109system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014083 # miss rate for overall accesses 1110system.cpu0.icache.overall_miss_rate::total 0.014083 # miss rate for overall accesses 1111system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14385.528130 # average ReadReq miss latency 1112system.cpu0.icache.ReadReq_avg_miss_latency::total 14385.528130 # average ReadReq miss latency 1113system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency 1114system.cpu0.icache.demand_avg_miss_latency::total 14385.528130 # average overall miss latency 1115system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency 1116system.cpu0.icache.overall_avg_miss_latency::total 14385.528130 # average overall miss latency |
| 1120system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1121system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1122system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1123system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1124system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1125system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1126system.cpu0.icache.fast_writes 0 # number of fast writes performed 1127system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1117system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1118system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1119system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1120system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1121system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1122system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1123system.cpu0.icache.fast_writes 0 # number of fast writes performed 1124system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1128system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539310 # number of ReadReq MSHR misses 1129system.cpu0.icache.ReadReq_mshr_misses::total 539310 # number of ReadReq MSHR misses 1130system.cpu0.icache.demand_mshr_misses::cpu0.inst 539310 # number of demand (read+write) MSHR misses 1131system.cpu0.icache.demand_mshr_misses::total 539310 # number of demand (read+write) MSHR misses 1132system.cpu0.icache.overall_mshr_misses::cpu0.inst 539310 # number of overall MSHR misses 1133system.cpu0.icache.overall_mshr_misses::total 539310 # number of overall MSHR misses 1134system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6681305000 # number of ReadReq MSHR miss cycles 1135system.cpu0.icache.ReadReq_mshr_miss_latency::total 6681305000 # number of ReadReq MSHR miss cycles 1136system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6681305000 # number of demand (read+write) MSHR miss cycles 1137system.cpu0.icache.demand_mshr_miss_latency::total 6681305000 # number of demand (read+write) MSHR miss cycles 1138system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6681305000 # number of overall MSHR miss cycles 1139system.cpu0.icache.overall_mshr_miss_latency::total 6681305000 # number of overall MSHR miss cycles 1140system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for ReadReq accesses 1141system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses 1142system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for demand accesses 1143system.cpu0.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses 1144system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for overall accesses 1145system.cpu0.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses 1146system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average ReadReq mshr miss latency 1147system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12388.616936 # average ReadReq mshr miss latency 1148system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average overall mshr miss latency 1149system.cpu0.icache.demand_avg_mshr_miss_latency::total 12388.616936 # average overall mshr miss latency 1150system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average overall mshr miss latency 1151system.cpu0.icache.overall_avg_mshr_miss_latency::total 12388.616936 # average overall mshr miss latency | 1125system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539174 # number of ReadReq MSHR misses 1126system.cpu0.icache.ReadReq_mshr_misses::total 539174 # number of ReadReq MSHR misses 1127system.cpu0.icache.demand_mshr_misses::cpu0.inst 539174 # number of demand (read+write) MSHR misses 1128system.cpu0.icache.demand_mshr_misses::total 539174 # number of demand (read+write) MSHR misses 1129system.cpu0.icache.overall_mshr_misses::cpu0.inst 539174 # number of overall MSHR misses 1130system.cpu0.icache.overall_mshr_misses::total 539174 # number of overall MSHR misses 1131system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6673548256 # number of ReadReq MSHR miss cycles 1132system.cpu0.icache.ReadReq_mshr_miss_latency::total 6673548256 # number of ReadReq MSHR miss cycles 1133system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6673548256 # number of demand (read+write) MSHR miss cycles 1134system.cpu0.icache.demand_mshr_miss_latency::total 6673548256 # number of demand (read+write) MSHR miss cycles 1135system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6673548256 # number of overall MSHR miss cycles 1136system.cpu0.icache.overall_mshr_miss_latency::total 6673548256 # number of overall MSHR miss cycles 1137system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for ReadReq accesses 1138system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014083 # mshr miss rate for ReadReq accesses 1139system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for demand accesses 1140system.cpu0.icache.demand_mshr_miss_rate::total 0.014083 # mshr miss rate for demand accesses 1141system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for overall accesses 1142system.cpu0.icache.overall_mshr_miss_rate::total 0.014083 # mshr miss rate for overall accesses 1143system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average ReadReq mshr miss latency 1144system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12377.355466 # average ReadReq mshr miss latency 1145system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency 1146system.cpu0.icache.demand_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency 1147system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency 1148system.cpu0.icache.overall_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency |
| 1152system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1149system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1153system.cpu0.dcache.tags.replacements 871224 # number of replacements 1154system.cpu0.dcache.tags.tagsinuse 481.747613 # Cycle average of tags in use 1155system.cpu0.dcache.tags.total_refs 9466123 # Total number of references to valid blocks. 1156system.cpu0.dcache.tags.sampled_refs 871736 # Sample count of references to valid blocks. 1157system.cpu0.dcache.tags.avg_refs 10.858933 # Average number of references to valid blocks. | 1150system.cpu0.dcache.tags.replacements 871192 # number of replacements 1151system.cpu0.dcache.tags.tagsinuse 481.742326 # Cycle average of tags in use 1152system.cpu0.dcache.tags.total_refs 9465806 # Total number of references to valid blocks. 1153system.cpu0.dcache.tags.sampled_refs 871704 # Sample count of references to valid blocks. 1154system.cpu0.dcache.tags.avg_refs 10.858968 # Average number of references to valid blocks. |
| 1158system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. | 1155system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. |
| 1159system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.747613 # Average occupied blocks per requestor 1160system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940913 # Average percentage of cache occupancy 1161system.cpu0.dcache.tags.occ_percent::total 0.940913 # Average percentage of cache occupancy | 1156system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.742326 # Average occupied blocks per requestor 1157system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940903 # Average percentage of cache occupancy 1158system.cpu0.dcache.tags.occ_percent::total 0.940903 # Average percentage of cache occupancy |
| 1162system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1159system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1163system.cpu0.dcache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 1164system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id | 1160system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 1161system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id |
| 1165system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 1166system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1162system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 1163system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1167system.cpu0.dcache.tags.tag_accesses 42234072 # Number of tag accesses 1168system.cpu0.dcache.tags.data_accesses 42234072 # Number of data accesses 1169system.cpu0.dcache.ReadReq_hits::cpu0.data 5299987 # number of ReadReq hits 1170system.cpu0.dcache.ReadReq_hits::total 5299987 # number of ReadReq hits 1171system.cpu0.dcache.WriteReq_hits::cpu0.data 3905819 # number of WriteReq hits 1172system.cpu0.dcache.WriteReq_hits::total 3905819 # number of WriteReq hits 1173system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124795 # number of LoadLockedReq hits 1174system.cpu0.dcache.LoadLockedReq_hits::total 124795 # number of LoadLockedReq hits 1175system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131586 # number of StoreCondReq hits 1176system.cpu0.dcache.StoreCondReq_hits::total 131586 # number of StoreCondReq hits 1177system.cpu0.dcache.demand_hits::cpu0.data 9205806 # number of demand (read+write) hits 1178system.cpu0.dcache.demand_hits::total 9205806 # number of demand (read+write) hits 1179system.cpu0.dcache.overall_hits::cpu0.data 9205806 # number of overall hits 1180system.cpu0.dcache.overall_hits::total 9205806 # number of overall hits 1181system.cpu0.dcache.ReadReq_misses::cpu0.data 645326 # number of ReadReq misses 1182system.cpu0.dcache.ReadReq_misses::total 645326 # number of ReadReq misses 1183system.cpu0.dcache.WriteReq_misses::cpu0.data 224198 # number of WriteReq misses 1184system.cpu0.dcache.WriteReq_misses::total 224198 # number of WriteReq misses 1185system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7833 # number of LoadLockedReq misses 1186system.cpu0.dcache.LoadLockedReq_misses::total 7833 # number of LoadLockedReq misses 1187system.cpu0.dcache.StoreCondReq_misses::cpu0.data 495 # number of StoreCondReq misses 1188system.cpu0.dcache.StoreCondReq_misses::total 495 # number of StoreCondReq misses 1189system.cpu0.dcache.demand_misses::cpu0.data 869524 # number of demand (read+write) misses 1190system.cpu0.dcache.demand_misses::total 869524 # number of demand (read+write) misses 1191system.cpu0.dcache.overall_misses::cpu0.data 869524 # number of overall misses 1192system.cpu0.dcache.overall_misses::total 869524 # number of overall misses 1193system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374169264 # number of ReadReq miss cycles 1194system.cpu0.dcache.ReadReq_miss_latency::total 23374169264 # number of ReadReq miss cycles 1195system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262123232 # number of WriteReq miss cycles 1196system.cpu0.dcache.WriteReq_miss_latency::total 9262123232 # number of WriteReq miss cycles 1197system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102899750 # number of LoadLockedReq miss cycles 1198system.cpu0.dcache.LoadLockedReq_miss_latency::total 102899750 # number of LoadLockedReq miss cycles 1199system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3567062 # number of StoreCondReq miss cycles 1200system.cpu0.dcache.StoreCondReq_miss_latency::total 3567062 # number of StoreCondReq miss cycles 1201system.cpu0.dcache.demand_miss_latency::cpu0.data 32636292496 # number of demand (read+write) miss cycles 1202system.cpu0.dcache.demand_miss_latency::total 32636292496 # number of demand (read+write) miss cycles 1203system.cpu0.dcache.overall_miss_latency::cpu0.data 32636292496 # number of overall miss cycles 1204system.cpu0.dcache.overall_miss_latency::total 32636292496 # number of overall miss cycles 1205system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945313 # number of ReadReq accesses(hits+misses) 1206system.cpu0.dcache.ReadReq_accesses::total 5945313 # number of ReadReq accesses(hits+misses) 1207system.cpu0.dcache.WriteReq_accesses::cpu0.data 4130017 # number of WriteReq accesses(hits+misses) 1208system.cpu0.dcache.WriteReq_accesses::total 4130017 # number of WriteReq accesses(hits+misses) 1209system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132628 # number of LoadLockedReq accesses(hits+misses) 1210system.cpu0.dcache.LoadLockedReq_accesses::total 132628 # number of LoadLockedReq accesses(hits+misses) 1211system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132081 # number of StoreCondReq accesses(hits+misses) 1212system.cpu0.dcache.StoreCondReq_accesses::total 132081 # number of StoreCondReq accesses(hits+misses) 1213system.cpu0.dcache.demand_accesses::cpu0.data 10075330 # number of demand (read+write) accesses 1214system.cpu0.dcache.demand_accesses::total 10075330 # number of demand (read+write) accesses 1215system.cpu0.dcache.overall_accesses::cpu0.data 10075330 # number of overall (read+write) accesses 1216system.cpu0.dcache.overall_accesses::total 10075330 # number of overall (read+write) accesses 1217system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108544 # miss rate for ReadReq accesses 1218system.cpu0.dcache.ReadReq_miss_rate::total 0.108544 # miss rate for ReadReq accesses 1219system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054285 # miss rate for WriteReq accesses 1220system.cpu0.dcache.WriteReq_miss_rate::total 0.054285 # miss rate for WriteReq accesses 1221system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059060 # miss rate for LoadLockedReq accesses 1222system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059060 # miss rate for LoadLockedReq accesses 1223system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003748 # miss rate for StoreCondReq accesses 1224system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003748 # miss rate for StoreCondReq accesses 1225system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086302 # miss rate for demand accesses 1226system.cpu0.dcache.demand_miss_rate::total 0.086302 # miss rate for demand accesses 1227system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086302 # miss rate for overall accesses 1228system.cpu0.dcache.overall_miss_rate::total 0.086302 # miss rate for overall accesses 1229system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36220.715211 # average ReadReq miss latency 1230system.cpu0.dcache.ReadReq_avg_miss_latency::total 36220.715211 # average ReadReq miss latency 1231system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41312.247353 # average WriteReq miss latency 1232system.cpu0.dcache.WriteReq_avg_miss_latency::total 41312.247353 # average WriteReq miss latency 1233system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13136.697306 # average LoadLockedReq miss latency 1234system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13136.697306 # average LoadLockedReq miss latency 1235system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7206.185859 # average StoreCondReq miss latency 1236system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7206.185859 # average StoreCondReq miss latency 1237system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37533.515459 # average overall miss latency 1238system.cpu0.dcache.demand_avg_miss_latency::total 37533.515459 # average overall miss latency 1239system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37533.515459 # average overall miss latency 1240system.cpu0.dcache.overall_avg_miss_latency::total 37533.515459 # average overall miss latency | 1164system.cpu0.dcache.tags.tag_accesses 42232679 # Number of tag accesses 1165system.cpu0.dcache.tags.data_accesses 42232679 # Number of data accesses 1166system.cpu0.dcache.ReadReq_hits::cpu0.data 5299779 # number of ReadReq hits 1167system.cpu0.dcache.ReadReq_hits::total 5299779 # number of ReadReq hits 1168system.cpu0.dcache.WriteReq_hits::cpu0.data 3905718 # number of WriteReq hits 1169system.cpu0.dcache.WriteReq_hits::total 3905718 # number of WriteReq hits 1170system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124794 # number of LoadLockedReq hits 1171system.cpu0.dcache.LoadLockedReq_hits::total 124794 # number of LoadLockedReq hits 1172system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131579 # number of StoreCondReq hits 1173system.cpu0.dcache.StoreCondReq_hits::total 131579 # number of StoreCondReq hits 1174system.cpu0.dcache.demand_hits::cpu0.data 9205497 # number of demand (read+write) hits 1175system.cpu0.dcache.demand_hits::total 9205497 # number of demand (read+write) hits 1176system.cpu0.dcache.overall_hits::cpu0.data 9205497 # number of overall hits 1177system.cpu0.dcache.overall_hits::total 9205497 # number of overall hits 1178system.cpu0.dcache.ReadReq_misses::cpu0.data 645318 # number of ReadReq misses 1179system.cpu0.dcache.ReadReq_misses::total 645318 # number of ReadReq misses 1180system.cpu0.dcache.WriteReq_misses::cpu0.data 224183 # number of WriteReq misses 1181system.cpu0.dcache.WriteReq_misses::total 224183 # number of WriteReq misses 1182system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7829 # number of LoadLockedReq misses 1183system.cpu0.dcache.LoadLockedReq_misses::total 7829 # number of LoadLockedReq misses 1184system.cpu0.dcache.StoreCondReq_misses::cpu0.data 497 # number of StoreCondReq misses 1185system.cpu0.dcache.StoreCondReq_misses::total 497 # number of StoreCondReq misses 1186system.cpu0.dcache.demand_misses::cpu0.data 869501 # number of demand (read+write) misses 1187system.cpu0.dcache.demand_misses::total 869501 # number of demand (read+write) misses 1188system.cpu0.dcache.overall_misses::cpu0.data 869501 # number of overall misses 1189system.cpu0.dcache.overall_misses::total 869501 # number of overall misses 1190system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374202500 # number of ReadReq miss cycles 1191system.cpu0.dcache.ReadReq_miss_latency::total 23374202500 # number of ReadReq miss cycles 1192system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262527483 # number of WriteReq miss cycles 1193system.cpu0.dcache.WriteReq_miss_latency::total 9262527483 # number of WriteReq miss cycles 1194system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102834500 # number of LoadLockedReq miss cycles 1195system.cpu0.dcache.LoadLockedReq_miss_latency::total 102834500 # number of LoadLockedReq miss cycles 1196system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3584562 # number of StoreCondReq miss cycles 1197system.cpu0.dcache.StoreCondReq_miss_latency::total 3584562 # number of StoreCondReq miss cycles 1198system.cpu0.dcache.demand_miss_latency::cpu0.data 32636729983 # number of demand (read+write) miss cycles 1199system.cpu0.dcache.demand_miss_latency::total 32636729983 # number of demand (read+write) miss cycles 1200system.cpu0.dcache.overall_miss_latency::cpu0.data 32636729983 # number of overall miss cycles 1201system.cpu0.dcache.overall_miss_latency::total 32636729983 # number of overall miss cycles 1202system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945097 # number of ReadReq accesses(hits+misses) 1203system.cpu0.dcache.ReadReq_accesses::total 5945097 # number of ReadReq accesses(hits+misses) 1204system.cpu0.dcache.WriteReq_accesses::cpu0.data 4129901 # number of WriteReq accesses(hits+misses) 1205system.cpu0.dcache.WriteReq_accesses::total 4129901 # number of WriteReq accesses(hits+misses) 1206system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132623 # number of LoadLockedReq accesses(hits+misses) 1207system.cpu0.dcache.LoadLockedReq_accesses::total 132623 # number of LoadLockedReq accesses(hits+misses) 1208system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132076 # number of StoreCondReq accesses(hits+misses) 1209system.cpu0.dcache.StoreCondReq_accesses::total 132076 # number of StoreCondReq accesses(hits+misses) 1210system.cpu0.dcache.demand_accesses::cpu0.data 10074998 # number of demand (read+write) accesses 1211system.cpu0.dcache.demand_accesses::total 10074998 # number of demand (read+write) accesses 1212system.cpu0.dcache.overall_accesses::cpu0.data 10074998 # number of overall (read+write) accesses 1213system.cpu0.dcache.overall_accesses::total 10074998 # number of overall (read+write) accesses 1214system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108546 # miss rate for ReadReq accesses 1215system.cpu0.dcache.ReadReq_miss_rate::total 0.108546 # miss rate for ReadReq accesses 1216system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054283 # miss rate for WriteReq accesses 1217system.cpu0.dcache.WriteReq_miss_rate::total 0.054283 # miss rate for WriteReq accesses 1218system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059032 # miss rate for LoadLockedReq accesses 1219system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059032 # miss rate for LoadLockedReq accesses 1220system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003763 # miss rate for StoreCondReq accesses 1221system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003763 # miss rate for StoreCondReq accesses 1222system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086303 # miss rate for demand accesses 1223system.cpu0.dcache.demand_miss_rate::total 0.086303 # miss rate for demand accesses 1224system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086303 # miss rate for overall accesses 1225system.cpu0.dcache.overall_miss_rate::total 0.086303 # miss rate for overall accesses 1226system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742 # average ReadReq miss latency 1227system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742 # average ReadReq miss latency 1228system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758 # average WriteReq miss latency 1229system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758 # average WriteReq miss latency 1230system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722 # average LoadLockedReq miss latency 1231system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722 # average LoadLockedReq miss latency 1232system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7212.398390 # average StoreCondReq miss latency 1233system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7212.398390 # average StoreCondReq miss latency 1234system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency 1235system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441 # average overall miss latency 1236system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency 1237system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency |
| 1241system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1242system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1243system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1244system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1245system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1246system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1247system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1248system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1238system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1239system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1240system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1241system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1242system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1243system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1244system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1245system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1249system.cpu0.dcache.writebacks::writebacks 405192 # number of writebacks 1250system.cpu0.dcache.writebacks::total 405192 # number of writebacks 1251system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645326 # number of ReadReq MSHR misses 1252system.cpu0.dcache.ReadReq_mshr_misses::total 645326 # number of ReadReq MSHR misses 1253system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224198 # number of WriteReq MSHR misses 1254system.cpu0.dcache.WriteReq_mshr_misses::total 224198 # number of WriteReq MSHR misses 1255system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7833 # number of LoadLockedReq MSHR misses 1256system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7833 # number of LoadLockedReq MSHR misses 1257system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 495 # number of StoreCondReq MSHR misses 1258system.cpu0.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses 1259system.cpu0.dcache.demand_mshr_misses::cpu0.data 869524 # number of demand (read+write) MSHR misses 1260system.cpu0.dcache.demand_mshr_misses::total 869524 # number of demand (read+write) MSHR misses 1261system.cpu0.dcache.overall_mshr_misses::cpu0.data 869524 # number of overall MSHR misses 1262system.cpu0.dcache.overall_mshr_misses::total 869524 # number of overall MSHR misses 1263system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958342736 # number of ReadReq MSHR miss cycles 1264system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958342736 # number of ReadReq MSHR miss cycles 1265system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8764766768 # number of WriteReq MSHR miss cycles 1266system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8764766768 # number of WriteReq MSHR miss cycles 1267system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87220250 # number of LoadLockedReq MSHR miss cycles 1268system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87220250 # number of LoadLockedReq MSHR miss cycles 1269system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2576938 # number of StoreCondReq MSHR miss cycles 1270system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2576938 # number of StoreCondReq MSHR miss cycles 1271system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723109504 # number of demand (read+write) MSHR miss cycles 1272system.cpu0.dcache.demand_mshr_miss_latency::total 30723109504 # number of demand (read+write) MSHR miss cycles 1273system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723109504 # number of overall MSHR miss cycles 1274system.cpu0.dcache.overall_mshr_miss_latency::total 30723109504 # number of overall MSHR miss cycles 1275system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004924500 # number of ReadReq MSHR uncacheable cycles 1276system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004924500 # number of ReadReq MSHR uncacheable cycles 1277system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718153000 # number of WriteReq MSHR uncacheable cycles 1278system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718153000 # number of WriteReq MSHR uncacheable cycles 1279system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723077500 # number of overall MSHR uncacheable cycles 1280system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723077500 # number of overall MSHR uncacheable cycles 1281system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108544 # mshr miss rate for ReadReq accesses 1282system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108544 # mshr miss rate for ReadReq accesses 1283system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054285 # mshr miss rate for WriteReq accesses 1284system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054285 # mshr miss rate for WriteReq accesses 1285system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059060 # mshr miss rate for LoadLockedReq accesses 1286system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059060 # mshr miss rate for LoadLockedReq accesses 1287system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003748 # mshr miss rate for StoreCondReq accesses 1288system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003748 # mshr miss rate for StoreCondReq accesses 1289system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for demand accesses 1290system.cpu0.dcache.demand_mshr_miss_rate::total 0.086302 # mshr miss rate for demand accesses 1291system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for overall accesses 1292system.cpu0.dcache.overall_mshr_miss_rate::total 0.086302 # mshr miss rate for overall accesses 1293system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34026.744213 # average ReadReq mshr miss latency 1294system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34026.744213 # average ReadReq mshr miss latency 1295system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39093.866886 # average WriteReq mshr miss latency 1296system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39093.866886 # average WriteReq mshr miss latency 1297system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11134.973829 # average LoadLockedReq mshr miss latency 1298system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11134.973829 # average LoadLockedReq mshr miss latency 1299system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5205.935354 # average StoreCondReq mshr miss latency 1300system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5205.935354 # average StoreCondReq mshr miss latency 1301system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency 1302system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency 1303system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency 1304system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency | 1246system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks 1247system.cpu0.dcache.writebacks::total 405151 # number of writebacks 1248system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses 1249system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses 1250system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses 1251system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses 1252system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses 1253system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses 1254system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses 1255system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses 1256system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses 1257system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses 1258system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses 1259system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses 1260system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles 1261system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles 1262system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles 1263system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles 1264system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles 1265system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles 1266system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles 1267system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles 1268system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles 1269system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles 1270system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles 1271system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles 1272system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles 1273system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles 1274system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles 1275system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles 1276system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles 1277system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles 1278system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses 1279system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses 1280system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses 1281system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses 1282system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses 1283system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses 1284system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses 1285system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses 1286system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses 1287system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses 1288system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses 1289system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses 1290system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency 1291system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency 1292system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency 1293system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency 1294system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency 1295system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency 1296system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency 1297system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency 1298system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency 1299system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency 1300system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency 1301system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency |
| 1305system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1306system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1307system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1308system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1309system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1310system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1311system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1312system.cpu1.dtb.fetch_hits 0 # ITB hits 1313system.cpu1.dtb.fetch_misses 0 # ITB misses 1314system.cpu1.dtb.fetch_acv 0 # ITB acv 1315system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1302system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1303system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1304system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1305system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1306system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1307system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1308system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1309system.cpu1.dtb.fetch_hits 0 # ITB hits 1310system.cpu1.dtb.fetch_misses 0 # ITB misses 1311system.cpu1.dtb.fetch_acv 0 # ITB acv 1312system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1316system.cpu1.dtb.read_hits 3617105 # DTB read hits | 1313system.cpu1.dtb.read_hits 3617054 # DTB read hits |
| 1317system.cpu1.dtb.read_misses 2620 # DTB read misses 1318system.cpu1.dtb.read_acv 0 # DTB read access violations 1319system.cpu1.dtb.read_accesses 205337 # DTB read accesses | 1314system.cpu1.dtb.read_misses 2620 # DTB read misses 1315system.cpu1.dtb.read_acv 0 # DTB read access violations 1316system.cpu1.dtb.read_accesses 205337 # DTB read accesses |
| 1320system.cpu1.dtb.write_hits 2433899 # DTB write hits | 1317system.cpu1.dtb.write_hits 2433875 # DTB write hits |
| 1321system.cpu1.dtb.write_misses 235 # DTB write misses 1322system.cpu1.dtb.write_acv 24 # DTB write access violations 1323system.cpu1.dtb.write_accesses 89739 # DTB write accesses | 1318system.cpu1.dtb.write_misses 235 # DTB write misses 1319system.cpu1.dtb.write_acv 24 # DTB write access violations 1320system.cpu1.dtb.write_accesses 89739 # DTB write accesses |
| 1324system.cpu1.dtb.data_hits 6051004 # DTB hits | 1321system.cpu1.dtb.data_hits 6050929 # DTB hits |
| 1325system.cpu1.dtb.data_misses 2855 # DTB misses 1326system.cpu1.dtb.data_acv 24 # DTB access violations 1327system.cpu1.dtb.data_accesses 295076 # DTB accesses | 1322system.cpu1.dtb.data_misses 2855 # DTB misses 1323system.cpu1.dtb.data_acv 24 # DTB access violations 1324system.cpu1.dtb.data_accesses 295076 # DTB accesses |
| 1328system.cpu1.itb.fetch_hits 1988116 # ITB hits | 1325system.cpu1.itb.fetch_hits 1988100 # ITB hits |
| 1329system.cpu1.itb.fetch_misses 1064 # ITB misses 1330system.cpu1.itb.fetch_acv 0 # ITB acv | 1326system.cpu1.itb.fetch_misses 1064 # ITB misses 1327system.cpu1.itb.fetch_acv 0 # ITB acv |
| 1331system.cpu1.itb.fetch_accesses 1989180 # ITB accesses | 1328system.cpu1.itb.fetch_accesses 1989164 # ITB accesses |
| 1332system.cpu1.itb.read_hits 0 # DTB read hits 1333system.cpu1.itb.read_misses 0 # DTB read misses 1334system.cpu1.itb.read_acv 0 # DTB read access violations 1335system.cpu1.itb.read_accesses 0 # DTB read accesses 1336system.cpu1.itb.write_hits 0 # DTB write hits 1337system.cpu1.itb.write_misses 0 # DTB write misses 1338system.cpu1.itb.write_acv 0 # DTB write access violations 1339system.cpu1.itb.write_accesses 0 # DTB write accesses 1340system.cpu1.itb.data_hits 0 # DTB hits 1341system.cpu1.itb.data_misses 0 # DTB misses 1342system.cpu1.itb.data_acv 0 # DTB access violations 1343system.cpu1.itb.data_accesses 0 # DTB accesses | 1329system.cpu1.itb.read_hits 0 # DTB read hits 1330system.cpu1.itb.read_misses 0 # DTB read misses 1331system.cpu1.itb.read_acv 0 # DTB read access violations 1332system.cpu1.itb.read_accesses 0 # DTB read accesses 1333system.cpu1.itb.write_hits 0 # DTB write hits 1334system.cpu1.itb.write_misses 0 # DTB write misses 1335system.cpu1.itb.write_acv 0 # DTB write access violations 1336system.cpu1.itb.write_accesses 0 # DTB write accesses 1337system.cpu1.itb.data_hits 0 # DTB hits 1338system.cpu1.itb.data_misses 0 # DTB misses 1339system.cpu1.itb.data_acv 0 # DTB access violations 1340system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1344system.cpu1.numCycles 3923841481 # number of cpu cycles simulated | 1341system.cpu1.numCycles 3923841470 # number of cpu cycles simulated |
| 1345system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1346system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1342system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1343system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1347system.cpu1.committedInsts 21095606 # Number of instructions committed 1348system.cpu1.committedOps 21095606 # Number of ops (including micro ops) committed 1349system.cpu1.num_int_alu_accesses 19410796 # Number of integer alu accesses | 1344system.cpu1.committedInsts 21095754 # Number of instructions committed 1345system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed 1346system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses |
| 1350system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses | 1347system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses |
| 1351system.cpu1.num_func_calls 648522 # number of times a function call or return occured 1352system.cpu1.num_conditional_control_insts 2286515 # number of instructions that are conditional controls 1353system.cpu1.num_int_insts 19410796 # number of integer instructions | 1348system.cpu1.num_func_calls 648514 # number of times a function call or return occured 1349system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls 1350system.cpu1.num_int_insts 19410964 # number of integer instructions |
| 1354system.cpu1.num_fp_insts 175175 # number of float instructions | 1351system.cpu1.num_fp_insts 175175 # number of float instructions |
| 1355system.cpu1.num_int_register_reads 26519930 # number of times the integer registers were read 1356system.cpu1.num_int_register_writes 14289781 # number of times the integer registers were written | 1352system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read 1353system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written |
| 1357system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read 1358system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written | 1354system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read 1355system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written |
| 1359system.cpu1.num_mem_refs 6073244 # number of memory refs 1360system.cpu1.num_load_insts 3630952 # Number of load instructions 1361system.cpu1.num_store_insts 2442292 # Number of store instructions 1362system.cpu1.num_idle_cycles 3837671905.347151 # Number of idle cycles 1363system.cpu1.num_busy_cycles 86169575.652849 # Number of busy cycles 1364system.cpu1.not_idle_fraction 0.021961 # Percentage of non-idle cycles 1365system.cpu1.idle_fraction 0.978039 # Percentage of idle cycles 1366system.cpu1.Branches 3164985 # Number of branches fetched 1367system.cpu1.op_class::No_OpClass 1250072 5.92% 5.92% # Class of executed instruction 1368system.cpu1.op_class::IntAlu 13187049 62.50% 68.43% # Class of executed instruction 1369system.cpu1.op_class::IntMult 30193 0.14% 68.57% # Class of executed instruction | 1356system.cpu1.num_mem_refs 6073169 # number of memory refs 1357system.cpu1.num_load_insts 3630901 # Number of load instructions 1358system.cpu1.num_store_insts 2442268 # Number of store instructions 1359system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles 1360system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles 1361system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles 1362system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles 1363system.cpu1.Branches 3165037 # Number of branches fetched 1364system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction 1365system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction 1366system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction |
| 1370system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction | 1367system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction |
| 1371system.cpu1.op_class::FloatAdd 13163 0.06% 68.63% # Class of executed instruction | 1368system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction |
| 1372system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction 1373system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction 1374system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction 1375system.cpu1.op_class::FloatDiv 1759 0.01% 68.64% # Class of executed instruction 1376system.cpu1.op_class::FloatSqrt 0 0.00% 68.64% # Class of executed instruction 1377system.cpu1.op_class::SimdAdd 0 0.00% 68.64% # Class of executed instruction 1378system.cpu1.op_class::SimdAddAcc 0 0.00% 68.64% # Class of executed instruction 1379system.cpu1.op_class::SimdAlu 0 0.00% 68.64% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 1389system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.64% # Class of executed instruction 1390system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.64% # Class of executed instruction 1391system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.64% # Class of executed instruction 1392system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.64% # Class of executed instruction 1393system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Class of executed instruction 1394system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction 1395system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction 1396system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction | 1369system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction 1370system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction 1371system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction 1372system.cpu1.op_class::FloatDiv 1759 0.01% 68.64% # Class of executed instruction 1373system.cpu1.op_class::FloatSqrt 0 0.00% 68.64% # Class of executed instruction 1374system.cpu1.op_class::SimdAdd 0 0.00% 68.64% # Class of executed instruction 1375system.cpu1.op_class::SimdAddAcc 0 0.00% 68.64% # Class of executed instruction 1376system.cpu1.op_class::SimdAlu 0 0.00% 68.64% # Class of executed instruction --- 9 unchanged lines hidden (view full) --- 1386system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.64% # Class of executed instruction 1387system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.64% # Class of executed instruction 1388system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.64% # Class of executed instruction 1389system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.64% # Class of executed instruction 1390system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Class of executed instruction 1391system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction 1392system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction 1393system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction |
| 1397system.cpu1.op_class::MemRead 3726131 17.66% 86.30% # Class of executed instruction 1398system.cpu1.op_class::MemWrite 2443312 11.58% 97.88% # Class of executed instruction 1399system.cpu1.op_class::IprAccess 446806 2.12% 100.00% # Class of executed instruction | 1394system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction 1395system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction 1396system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction |
| 1400system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1397system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1401system.cpu1.op_class::total 21098485 # Class of executed instruction | 1398system.cpu1.op_class::total 21098633 # Class of executed instruction |
| 1402system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1403system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed | 1399system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1400system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed |
| 1404system.cpu1.kern.inst.hwrei 100735 # number of hwrei instructions executed 1405system.cpu1.kern.ipl_count::0 37219 40.29% 40.29% # number of times we switched to this ipl | 1401system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed 1402system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl |
| 1406system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl 1407system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl | 1403system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl 1404system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl |
| 1408system.cpu1.kern.ipl_count::31 53109 57.49% 100.00% # number of times we switched to this ipl 1409system.cpu1.kern.ipl_count::total 92384 # number of times we switched to this ipl 1410system.cpu1.kern.ipl_good::0 36367 48.68% 48.68% # number of times we switched to this ipl from a different ipl | 1405system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl 1406system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl 1407system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl |
| 1411system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl 1412system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl | 1408system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl 1409system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl |
| 1413system.cpu1.kern.ipl_good::31 36281 48.57% 100.00% # number of times we switched to this ipl from a different ipl 1414system.cpu1.kern.ipl_good::total 74704 # number of times we switched to this ipl from a different ipl 1415system.cpu1.kern.ipl_ticks::0 1906656399000 97.18% 97.18% # number of cycles we spent at this ipl 1416system.cpu1.kern.ipl_ticks::22 706249000 0.04% 97.22% # number of cycles we spent at this ipl | 1410system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl 1411system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl 1412system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl 1413system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl |
| 1417system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl | 1414system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl |
| 1418system.cpu1.kern.ipl_ticks::31 54498695500 2.78% 100.00% # number of cycles we spent at this ipl 1419system.cpu1.kern.ipl_ticks::total 1961920710500 # number of cycles we spent at this ipl | 1415system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl 1416system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl |
| 1420system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl 1421system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1422system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1417system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl 1418system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1419system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1423system.cpu1.kern.ipl_used::31 0.683142 # fraction of swpipl calls that actually changed the ipl 1424system.cpu1.kern.ipl_used::total 0.808625 # fraction of swpipl calls that actually changed the ipl | 1420system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl 1421system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl |
| 1425system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 1426system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 1427system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 1428system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 1429system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 1430system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 1431system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 1432system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed --- 5 unchanged lines hidden (view full) --- 1438system.cpu1.kern.syscall::total 92 # number of syscalls executed 1439system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1440system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed 1441system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed 1442system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed 1443system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed 1444system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed 1445system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed | 1422system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 1423system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 1424system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 1425system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 1426system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 1427system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 1428system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 1429system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed --- 5 unchanged lines hidden (view full) --- 1435system.cpu1.kern.syscall::total 92 # number of syscalls executed 1436system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1437system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed 1438system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed 1439system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed 1440system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed 1441system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed 1442system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed |
| 1446system.cpu1.kern.callpal::swpipl 87061 91.90% 94.06% # number of callpals executed | 1443system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed |
| 1447system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed 1448system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed 1449system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed 1450system.cpu1.kern.callpal::whami 3 0.00% 96.38% # number of callpals executed 1451system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # number of callpals executed 1452system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed 1453system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed 1454system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1444system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed 1445system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed 1446system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed 1447system.cpu1.kern.callpal::whami 3 0.00% 96.38% # number of callpals executed 1448system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # number of callpals executed 1449system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed 1450system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed 1451system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1455system.cpu1.kern.callpal::total 94734 # number of callpals executed | 1452system.cpu1.kern.callpal::total 94732 # number of callpals executed |
| 1456system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches | 1453system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches |
| 1457system.cpu1.kern.mode_switch::user 366 # number of protection mode switches | 1454system.cpu1.kern.mode_switch::user 367 # number of protection mode switches |
| 1458system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches | 1455system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches |
| 1459system.cpu1.kern.mode_good::kernel 414 1460system.cpu1.kern.mode_good::user 366 | 1456system.cpu1.kern.mode_good::kernel 415 1457system.cpu1.kern.mode_good::user 367 |
| 1461system.cpu1.kern.mode_good::idle 48 | 1458system.cpu1.kern.mode_good::idle 48 |
| 1462system.cpu1.kern.mode_switch_good::kernel 0.171429 # fraction of useful protection mode switches | 1459system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches |
| 1463system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1464system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches | 1460system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1461system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches |
| 1465system.cpu1.kern.mode_switch_good::total 0.171856 # fraction of useful protection mode switches 1466system.cpu1.kern.mode_ticks::kernel 65780447000 3.35% 3.35% # number of ticks spent at the given mode 1467system.cpu1.kern.mode_ticks::user 1486717000 0.08% 3.43% # number of ticks spent at the given mode 1468system.cpu1.kern.mode_ticks::idle 1893764152500 96.57% 100.00% # number of ticks spent at the given mode | 1462system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches 1463system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode 1464system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode 1465system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode |
| 1469system.cpu1.kern.swap_context 2021 # number of times the context was actually changed | 1466system.cpu1.kern.swap_context 2021 # number of times the context was actually changed |
| 1470system.cpu1.icache.tags.replacements 463064 # number of replacements 1471system.cpu1.icache.tags.tagsinuse 500.061225 # Cycle average of tags in use 1472system.cpu1.icache.tags.total_refs 20634869 # Total number of references to valid blocks. 1473system.cpu1.icache.tags.sampled_refs 463576 # Sample count of references to valid blocks. 1474system.cpu1.icache.tags.avg_refs 44.512376 # Average number of references to valid blocks. | 1467system.cpu1.icache.tags.replacements 463035 # number of replacements 1468system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use 1469system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks. 1470system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks. 1471system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks. |
| 1475system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit. | 1472system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit. |
| 1476system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061225 # Average occupied blocks per requestor | 1473system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor |
| 1477system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy 1478system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy 1479system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1480system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 1481system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id 1482system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1474system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy 1475system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy 1476system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1477system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id 1478system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id 1479system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1483system.cpu1.icache.tags.tag_accesses 21562101 # Number of tag accesses 1484system.cpu1.icache.tags.data_accesses 21562101 # Number of data accesses 1485system.cpu1.icache.ReadReq_hits::cpu1.inst 20634869 # number of ReadReq hits 1486system.cpu1.icache.ReadReq_hits::total 20634869 # number of ReadReq hits 1487system.cpu1.icache.demand_hits::cpu1.inst 20634869 # number of demand (read+write) hits 1488system.cpu1.icache.demand_hits::total 20634869 # number of demand (read+write) hits 1489system.cpu1.icache.overall_hits::cpu1.inst 20634869 # number of overall hits 1490system.cpu1.icache.overall_hits::total 20634869 # number of overall hits 1491system.cpu1.icache.ReadReq_misses::cpu1.inst 463616 # number of ReadReq misses 1492system.cpu1.icache.ReadReq_misses::total 463616 # number of ReadReq misses 1493system.cpu1.icache.demand_misses::cpu1.inst 463616 # number of demand (read+write) misses 1494system.cpu1.icache.demand_misses::total 463616 # number of demand (read+write) misses 1495system.cpu1.icache.overall_misses::cpu1.inst 463616 # number of overall misses 1496system.cpu1.icache.overall_misses::total 463616 # number of overall misses 1497system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6201828741 # number of ReadReq miss cycles 1498system.cpu1.icache.ReadReq_miss_latency::total 6201828741 # number of ReadReq miss cycles 1499system.cpu1.icache.demand_miss_latency::cpu1.inst 6201828741 # number of demand (read+write) miss cycles 1500system.cpu1.icache.demand_miss_latency::total 6201828741 # number of demand (read+write) miss cycles 1501system.cpu1.icache.overall_miss_latency::cpu1.inst 6201828741 # number of overall miss cycles 1502system.cpu1.icache.overall_miss_latency::total 6201828741 # number of overall miss cycles 1503system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098485 # number of ReadReq accesses(hits+misses) 1504system.cpu1.icache.ReadReq_accesses::total 21098485 # number of ReadReq accesses(hits+misses) 1505system.cpu1.icache.demand_accesses::cpu1.inst 21098485 # number of demand (read+write) accesses 1506system.cpu1.icache.demand_accesses::total 21098485 # number of demand (read+write) accesses 1507system.cpu1.icache.overall_accesses::cpu1.inst 21098485 # number of overall (read+write) accesses 1508system.cpu1.icache.overall_accesses::total 21098485 # number of overall (read+write) accesses 1509system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021974 # miss rate for ReadReq accesses 1510system.cpu1.icache.ReadReq_miss_rate::total 0.021974 # miss rate for ReadReq accesses 1511system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021974 # miss rate for demand accesses 1512system.cpu1.icache.demand_miss_rate::total 0.021974 # miss rate for demand accesses 1513system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021974 # miss rate for overall accesses 1514system.cpu1.icache.overall_miss_rate::total 0.021974 # miss rate for overall accesses 1515system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13377.080905 # average ReadReq miss latency 1516system.cpu1.icache.ReadReq_avg_miss_latency::total 13377.080905 # average ReadReq miss latency 1517system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency 1518system.cpu1.icache.demand_avg_miss_latency::total 13377.080905 # average overall miss latency 1519system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency 1520system.cpu1.icache.overall_avg_miss_latency::total 13377.080905 # average overall miss latency | 1480system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses 1481system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses 1482system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits 1483system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits 1484system.cpu1.icache.demand_hits::cpu1.inst 20635046 # number of demand (read+write) hits 1485system.cpu1.icache.demand_hits::total 20635046 # number of demand (read+write) hits 1486system.cpu1.icache.overall_hits::cpu1.inst 20635046 # number of overall hits 1487system.cpu1.icache.overall_hits::total 20635046 # number of overall hits 1488system.cpu1.icache.ReadReq_misses::cpu1.inst 463587 # number of ReadReq misses 1489system.cpu1.icache.ReadReq_misses::total 463587 # number of ReadReq misses 1490system.cpu1.icache.demand_misses::cpu1.inst 463587 # number of demand (read+write) misses 1491system.cpu1.icache.demand_misses::total 463587 # number of demand (read+write) misses 1492system.cpu1.icache.overall_misses::cpu1.inst 463587 # number of overall misses 1493system.cpu1.icache.overall_misses::total 463587 # number of overall misses 1494system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6202855739 # number of ReadReq miss cycles 1495system.cpu1.icache.ReadReq_miss_latency::total 6202855739 # number of ReadReq miss cycles 1496system.cpu1.icache.demand_miss_latency::cpu1.inst 6202855739 # number of demand (read+write) miss cycles 1497system.cpu1.icache.demand_miss_latency::total 6202855739 # number of demand (read+write) miss cycles 1498system.cpu1.icache.overall_miss_latency::cpu1.inst 6202855739 # number of overall miss cycles 1499system.cpu1.icache.overall_miss_latency::total 6202855739 # number of overall miss cycles 1500system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098633 # number of ReadReq accesses(hits+misses) 1501system.cpu1.icache.ReadReq_accesses::total 21098633 # number of ReadReq accesses(hits+misses) 1502system.cpu1.icache.demand_accesses::cpu1.inst 21098633 # number of demand (read+write) accesses 1503system.cpu1.icache.demand_accesses::total 21098633 # number of demand (read+write) accesses 1504system.cpu1.icache.overall_accesses::cpu1.inst 21098633 # number of overall (read+write) accesses 1505system.cpu1.icache.overall_accesses::total 21098633 # number of overall (read+write) accesses 1506system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021972 # miss rate for ReadReq accesses 1507system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses 1508system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021972 # miss rate for demand accesses 1509system.cpu1.icache.demand_miss_rate::total 0.021972 # miss rate for demand accesses 1510system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021972 # miss rate for overall accesses 1511system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses 1512system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047 # average ReadReq miss latency 1513system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency 1514system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency 1515system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency 1516system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency 1517system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency |
| 1521system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1522system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1523system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1524system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1525system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1526system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1527system.cpu1.icache.fast_writes 0 # number of fast writes performed 1528system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1518system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1519system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1520system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1521system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1522system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1523system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1524system.cpu1.icache.fast_writes 0 # number of fast writes performed 1525system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1529system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463616 # number of ReadReq MSHR misses 1530system.cpu1.icache.ReadReq_mshr_misses::total 463616 # number of ReadReq MSHR misses 1531system.cpu1.icache.demand_mshr_misses::cpu1.inst 463616 # number of demand (read+write) MSHR misses 1532system.cpu1.icache.demand_mshr_misses::total 463616 # number of demand (read+write) MSHR misses 1533system.cpu1.icache.overall_mshr_misses::cpu1.inst 463616 # number of overall MSHR misses 1534system.cpu1.icache.overall_mshr_misses::total 463616 # number of overall MSHR misses 1535system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5273752259 # number of ReadReq MSHR miss cycles 1536system.cpu1.icache.ReadReq_mshr_miss_latency::total 5273752259 # number of ReadReq MSHR miss cycles 1537system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5273752259 # number of demand (read+write) MSHR miss cycles 1538system.cpu1.icache.demand_mshr_miss_latency::total 5273752259 # number of demand (read+write) MSHR miss cycles 1539system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5273752259 # number of overall MSHR miss cycles 1540system.cpu1.icache.overall_mshr_miss_latency::total 5273752259 # number of overall MSHR miss cycles 1541system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for ReadReq accesses 1542system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021974 # mshr miss rate for ReadReq accesses 1543system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for demand accesses 1544system.cpu1.icache.demand_mshr_miss_rate::total 0.021974 # mshr miss rate for demand accesses 1545system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for overall accesses 1546system.cpu1.icache.overall_mshr_miss_rate::total 0.021974 # mshr miss rate for overall accesses 1547system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average ReadReq mshr miss latency 1548system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11375.259394 # average ReadReq mshr miss latency 1549system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency 1550system.cpu1.icache.demand_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency 1551system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency 1552system.cpu1.icache.overall_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency | 1526system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses 1527system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses 1528system.cpu1.icache.demand_mshr_misses::cpu1.inst 463587 # number of demand (read+write) MSHR misses 1529system.cpu1.icache.demand_mshr_misses::total 463587 # number of demand (read+write) MSHR misses 1530system.cpu1.icache.overall_mshr_misses::cpu1.inst 463587 # number of overall MSHR misses 1531system.cpu1.icache.overall_mshr_misses::total 463587 # number of overall MSHR misses 1532system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5274833261 # number of ReadReq MSHR miss cycles 1533system.cpu1.icache.ReadReq_mshr_miss_latency::total 5274833261 # number of ReadReq MSHR miss cycles 1534system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles 1535system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles 1536system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles 1537system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles 1538system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for ReadReq accesses 1539system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses 1540system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses 1541system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses 1542system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses 1543system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses 1544system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency 1545system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency 1546system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency 1547system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency 1548system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency 1549system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency |
| 1553system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1550system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1554system.cpu1.dcache.tags.replacements 581734 # number of replacements 1555system.cpu1.dcache.tags.tagsinuse 492.027113 # Cycle average of tags in use 1556system.cpu1.dcache.tags.total_refs 5462976 # Total number of references to valid blocks. 1557system.cpu1.dcache.tags.sampled_refs 582077 # Sample count of references to valid blocks. 1558system.cpu1.dcache.tags.avg_refs 9.385315 # Average number of references to valid blocks. | 1551system.cpu1.dcache.tags.replacements 581700 # number of replacements 1552system.cpu1.dcache.tags.tagsinuse 492.027042 # Cycle average of tags in use 1553system.cpu1.dcache.tags.total_refs 5462019 # Total number of references to valid blocks. 1554system.cpu1.dcache.tags.sampled_refs 582040 # Sample count of references to valid blocks. 1555system.cpu1.dcache.tags.avg_refs 9.384267 # Average number of references to valid blocks. |
| 1559system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit. | 1556system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit. |
| 1560system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027113 # Average occupied blocks per requestor | 1557system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027042 # Average occupied blocks per requestor |
| 1561system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy 1562system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy | 1558system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy 1559system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy |
| 1563system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id 1564system.cpu1.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id 1565system.cpu1.dcache.tags.age_task_id_blocks_1024::3 300 # Occupied blocks per task id 1566system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id 1567system.cpu1.dcache.tags.tag_accesses 24828652 # Number of tag accesses 1568system.cpu1.dcache.tags.data_accesses 24828652 # Number of data accesses 1569system.cpu1.dcache.ReadReq_hits::cpu1.data 3080166 # number of ReadReq hits 1570system.cpu1.dcache.ReadReq_hits::total 3080166 # number of ReadReq hits 1571system.cpu1.dcache.WriteReq_hits::cpu1.data 2260006 # number of WriteReq hits 1572system.cpu1.dcache.WriteReq_hits::total 2260006 # number of WriteReq hits 1573system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60928 # number of LoadLockedReq hits 1574system.cpu1.dcache.LoadLockedReq_hits::total 60928 # number of LoadLockedReq hits 1575system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71558 # number of StoreCondReq hits 1576system.cpu1.dcache.StoreCondReq_hits::total 71558 # number of StoreCondReq hits 1577system.cpu1.dcache.demand_hits::cpu1.data 5340172 # number of demand (read+write) hits 1578system.cpu1.dcache.demand_hits::total 5340172 # number of demand (read+write) hits 1579system.cpu1.dcache.overall_hits::cpu1.data 5340172 # number of overall hits 1580system.cpu1.dcache.overall_hits::total 5340172 # number of overall hits 1581system.cpu1.dcache.ReadReq_misses::cpu1.data 473210 # number of ReadReq misses 1582system.cpu1.dcache.ReadReq_misses::total 473210 # number of ReadReq misses 1583system.cpu1.dcache.WriteReq_misses::cpu1.data 102503 # number of WriteReq misses 1584system.cpu1.dcache.WriteReq_misses::total 102503 # number of WriteReq misses 1585system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11672 # number of LoadLockedReq misses 1586system.cpu1.dcache.LoadLockedReq_misses::total 11672 # number of LoadLockedReq misses 1587system.cpu1.dcache.StoreCondReq_misses::cpu1.data 567 # number of StoreCondReq misses 1588system.cpu1.dcache.StoreCondReq_misses::total 567 # number of StoreCondReq misses 1589system.cpu1.dcache.demand_misses::cpu1.data 575713 # number of demand (read+write) misses 1590system.cpu1.dcache.demand_misses::total 575713 # number of demand (read+write) misses 1591system.cpu1.dcache.overall_misses::cpu1.data 575713 # number of overall misses 1592system.cpu1.dcache.overall_misses::total 575713 # number of overall misses 1593system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938920500 # number of ReadReq miss cycles 1594system.cpu1.dcache.ReadReq_miss_latency::total 5938920500 # number of ReadReq miss cycles 1595system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2340100234 # number of WriteReq miss cycles 1596system.cpu1.dcache.WriteReq_miss_latency::total 2340100234 # number of WriteReq miss cycles 1597system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149905750 # number of LoadLockedReq miss cycles 1598system.cpu1.dcache.LoadLockedReq_miss_latency::total 149905750 # number of LoadLockedReq miss cycles 1599system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4163080 # number of StoreCondReq miss cycles 1600system.cpu1.dcache.StoreCondReq_miss_latency::total 4163080 # number of StoreCondReq miss cycles 1601system.cpu1.dcache.demand_miss_latency::cpu1.data 8279020734 # number of demand (read+write) miss cycles 1602system.cpu1.dcache.demand_miss_latency::total 8279020734 # number of demand (read+write) miss cycles 1603system.cpu1.dcache.overall_miss_latency::cpu1.data 8279020734 # number of overall miss cycles 1604system.cpu1.dcache.overall_miss_latency::total 8279020734 # number of overall miss cycles 1605system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553376 # number of ReadReq accesses(hits+misses) 1606system.cpu1.dcache.ReadReq_accesses::total 3553376 # number of ReadReq accesses(hits+misses) 1607system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362509 # number of WriteReq accesses(hits+misses) 1608system.cpu1.dcache.WriteReq_accesses::total 2362509 # number of WriteReq accesses(hits+misses) 1609system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72600 # number of LoadLockedReq accesses(hits+misses) 1610system.cpu1.dcache.LoadLockedReq_accesses::total 72600 # number of LoadLockedReq accesses(hits+misses) 1611system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72125 # number of StoreCondReq accesses(hits+misses) 1612system.cpu1.dcache.StoreCondReq_accesses::total 72125 # number of StoreCondReq accesses(hits+misses) 1613system.cpu1.dcache.demand_accesses::cpu1.data 5915885 # number of demand (read+write) accesses 1614system.cpu1.dcache.demand_accesses::total 5915885 # number of demand (read+write) accesses 1615system.cpu1.dcache.overall_accesses::cpu1.data 5915885 # number of overall (read+write) accesses 1616system.cpu1.dcache.overall_accesses::total 5915885 # number of overall (read+write) accesses 1617system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133172 # miss rate for ReadReq accesses 1618system.cpu1.dcache.ReadReq_miss_rate::total 0.133172 # miss rate for ReadReq accesses | 1560system.cpu1.dcache.tags.occ_task_id_blocks::1024 340 # Occupied blocks per task id 1561system.cpu1.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 1562system.cpu1.dcache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id 1563system.cpu1.dcache.tags.occ_task_id_percent::1024 0.664062 # Percentage of cache occupancy per task id 1564system.cpu1.dcache.tags.tag_accesses 24828314 # Number of tag accesses 1565system.cpu1.dcache.tags.data_accesses 24828314 # Number of data accesses 1566system.cpu1.dcache.ReadReq_hits::cpu1.data 3080149 # number of ReadReq hits 1567system.cpu1.dcache.ReadReq_hits::total 3080149 # number of ReadReq hits 1568system.cpu1.dcache.WriteReq_hits::cpu1.data 2259986 # number of WriteReq hits 1569system.cpu1.dcache.WriteReq_hits::total 2259986 # number of WriteReq hits 1570system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60927 # number of LoadLockedReq hits 1571system.cpu1.dcache.LoadLockedReq_hits::total 60927 # number of LoadLockedReq hits 1572system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71555 # number of StoreCondReq hits 1573system.cpu1.dcache.StoreCondReq_hits::total 71555 # number of StoreCondReq hits 1574system.cpu1.dcache.demand_hits::cpu1.data 5340135 # number of demand (read+write) hits 1575system.cpu1.dcache.demand_hits::total 5340135 # number of demand (read+write) hits 1576system.cpu1.dcache.overall_hits::cpu1.data 5340135 # number of overall hits 1577system.cpu1.dcache.overall_hits::total 5340135 # number of overall hits 1578system.cpu1.dcache.ReadReq_misses::cpu1.data 473178 # number of ReadReq misses 1579system.cpu1.dcache.ReadReq_misses::total 473178 # number of ReadReq misses 1580system.cpu1.dcache.WriteReq_misses::cpu1.data 102501 # number of WriteReq misses 1581system.cpu1.dcache.WriteReq_misses::total 102501 # number of WriteReq misses 1582system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11671 # number of LoadLockedReq misses 1583system.cpu1.dcache.LoadLockedReq_misses::total 11671 # number of LoadLockedReq misses 1584system.cpu1.dcache.StoreCondReq_misses::cpu1.data 568 # number of StoreCondReq misses 1585system.cpu1.dcache.StoreCondReq_misses::total 568 # number of StoreCondReq misses 1586system.cpu1.dcache.demand_misses::cpu1.data 575679 # number of demand (read+write) misses 1587system.cpu1.dcache.demand_misses::total 575679 # number of demand (read+write) misses 1588system.cpu1.dcache.overall_misses::cpu1.data 575679 # number of overall misses 1589system.cpu1.dcache.overall_misses::total 575679 # number of overall misses 1590system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938208750 # number of ReadReq miss cycles 1591system.cpu1.dcache.ReadReq_miss_latency::total 5938208750 # number of ReadReq miss cycles 1592system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2338814234 # number of WriteReq miss cycles 1593system.cpu1.dcache.WriteReq_miss_latency::total 2338814234 # number of WriteReq miss cycles 1594system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149892750 # number of LoadLockedReq miss cycles 1595system.cpu1.dcache.LoadLockedReq_miss_latency::total 149892750 # number of LoadLockedReq miss cycles 1596system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4181580 # number of StoreCondReq miss cycles 1597system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles 1598system.cpu1.dcache.demand_miss_latency::cpu1.data 8277022984 # number of demand (read+write) miss cycles 1599system.cpu1.dcache.demand_miss_latency::total 8277022984 # number of demand (read+write) miss cycles 1600system.cpu1.dcache.overall_miss_latency::cpu1.data 8277022984 # number of overall miss cycles 1601system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles 1602system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses) 1603system.cpu1.dcache.ReadReq_accesses::total 3553327 # number of ReadReq accesses(hits+misses) 1604system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362487 # number of WriteReq accesses(hits+misses) 1605system.cpu1.dcache.WriteReq_accesses::total 2362487 # number of WriteReq accesses(hits+misses) 1606system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72598 # number of LoadLockedReq accesses(hits+misses) 1607system.cpu1.dcache.LoadLockedReq_accesses::total 72598 # number of LoadLockedReq accesses(hits+misses) 1608system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72123 # number of StoreCondReq accesses(hits+misses) 1609system.cpu1.dcache.StoreCondReq_accesses::total 72123 # number of StoreCondReq accesses(hits+misses) 1610system.cpu1.dcache.demand_accesses::cpu1.data 5915814 # number of demand (read+write) accesses 1611system.cpu1.dcache.demand_accesses::total 5915814 # number of demand (read+write) accesses 1612system.cpu1.dcache.overall_accesses::cpu1.data 5915814 # number of overall (read+write) accesses 1613system.cpu1.dcache.overall_accesses::total 5915814 # number of overall (read+write) accesses 1614system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133165 # miss rate for ReadReq accesses 1615system.cpu1.dcache.ReadReq_miss_rate::total 0.133165 # miss rate for ReadReq accesses |
| 1619system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses 1620system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses | 1616system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses 1617system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses |
| 1621system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160771 # miss rate for LoadLockedReq accesses 1622system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160771 # miss rate for LoadLockedReq accesses 1623system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007861 # miss rate for StoreCondReq accesses 1624system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007861 # miss rate for StoreCondReq accesses 1625system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097316 # miss rate for demand accesses 1626system.cpu1.dcache.demand_miss_rate::total 0.097316 # miss rate for demand accesses 1627system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097316 # miss rate for overall accesses 1628system.cpu1.dcache.overall_miss_rate::total 0.097316 # miss rate for overall accesses 1629system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12550.285286 # average ReadReq miss latency 1630system.cpu1.dcache.ReadReq_avg_miss_latency::total 12550.285286 # average ReadReq miss latency 1631system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22829.578003 # average WriteReq miss latency 1632system.cpu1.dcache.WriteReq_avg_miss_latency::total 22829.578003 # average WriteReq miss latency 1633system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.193112 # average LoadLockedReq miss latency 1634system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.193112 # average LoadLockedReq miss latency 1635system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.292769 # average StoreCondReq miss latency 1636system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.292769 # average StoreCondReq miss latency 1637system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14380.465152 # average overall miss latency 1638system.cpu1.dcache.demand_avg_miss_latency::total 14380.465152 # average overall miss latency 1639system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14380.465152 # average overall miss latency 1640system.cpu1.dcache.overall_avg_miss_latency::total 14380.465152 # average overall miss latency | 1618system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160762 # miss rate for LoadLockedReq accesses 1619system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160762 # miss rate for LoadLockedReq accesses 1620system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007875 # miss rate for StoreCondReq accesses 1621system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007875 # miss rate for StoreCondReq accesses 1622system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097312 # miss rate for demand accesses 1623system.cpu1.dcache.demand_miss_rate::total 0.097312 # miss rate for demand accesses 1624system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097312 # miss rate for overall accesses 1625system.cpu1.dcache.overall_miss_rate::total 0.097312 # miss rate for overall accesses 1626system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency 1627system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency 1628system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22817.477234 # average WriteReq miss latency 1629system.cpu1.dcache.WriteReq_avg_miss_latency::total 22817.477234 # average WriteReq miss latency 1630system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.179676 # average LoadLockedReq miss latency 1631system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.179676 # average LoadLockedReq miss latency 1632system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.936620 # average StoreCondReq miss latency 1633system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.936620 # average StoreCondReq miss latency 1634system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency 1635system.cpu1.dcache.demand_avg_miss_latency::total 14377.844222 # average overall miss latency 1636system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency 1637system.cpu1.dcache.overall_avg_miss_latency::total 14377.844222 # average overall miss latency |
| 1641system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1642system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1643system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1644system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1645system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1646system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1647system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1648system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1638system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1639system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1640system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1641system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1642system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1643system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1644system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1645system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1649system.cpu1.dcache.writebacks::writebacks 444943 # number of writebacks 1650system.cpu1.dcache.writebacks::total 444943 # number of writebacks 1651system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473210 # number of ReadReq MSHR misses 1652system.cpu1.dcache.ReadReq_mshr_misses::total 473210 # number of ReadReq MSHR misses 1653system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102503 # number of WriteReq MSHR misses 1654system.cpu1.dcache.WriteReq_mshr_misses::total 102503 # number of WriteReq MSHR misses 1655system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11672 # number of LoadLockedReq MSHR misses 1656system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11672 # number of LoadLockedReq MSHR misses 1657system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 567 # number of StoreCondReq MSHR misses 1658system.cpu1.dcache.StoreCondReq_mshr_misses::total 567 # number of StoreCondReq MSHR misses 1659system.cpu1.dcache.demand_mshr_misses::cpu1.data 575713 # number of demand (read+write) MSHR misses 1660system.cpu1.dcache.demand_mshr_misses::total 575713 # number of demand (read+write) MSHR misses 1661system.cpu1.dcache.overall_mshr_misses::cpu1.data 575713 # number of overall MSHR misses 1662system.cpu1.dcache.overall_mshr_misses::total 575713 # number of overall MSHR misses 1663system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4992146500 # number of ReadReq MSHR miss cycles 1664system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4992146500 # number of ReadReq MSHR miss cycles 1665system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2128603766 # number of WriteReq MSHR miss cycles 1666system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2128603766 # number of WriteReq MSHR miss cycles 1667system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126561250 # number of LoadLockedReq MSHR miss cycles 1668system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126561250 # number of LoadLockedReq MSHR miss cycles 1669system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3028920 # number of StoreCondReq MSHR miss cycles 1670system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3028920 # number of StoreCondReq MSHR miss cycles 1671system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7120750266 # number of demand (read+write) MSHR miss cycles 1672system.cpu1.dcache.demand_mshr_miss_latency::total 7120750266 # number of demand (read+write) MSHR miss cycles 1673system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7120750266 # number of overall MSHR miss cycles 1674system.cpu1.dcache.overall_mshr_miss_latency::total 7120750266 # number of overall MSHR miss cycles | 1646system.cpu1.dcache.writebacks::writebacks 444927 # number of writebacks 1647system.cpu1.dcache.writebacks::total 444927 # number of writebacks 1648system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473178 # number of ReadReq MSHR misses 1649system.cpu1.dcache.ReadReq_mshr_misses::total 473178 # number of ReadReq MSHR misses 1650system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102501 # number of WriteReq MSHR misses 1651system.cpu1.dcache.WriteReq_mshr_misses::total 102501 # number of WriteReq MSHR misses 1652system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11671 # number of LoadLockedReq MSHR misses 1653system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11671 # number of LoadLockedReq MSHR misses 1654system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 568 # number of StoreCondReq MSHR misses 1655system.cpu1.dcache.StoreCondReq_mshr_misses::total 568 # number of StoreCondReq MSHR misses 1656system.cpu1.dcache.demand_mshr_misses::cpu1.data 575679 # number of demand (read+write) MSHR misses 1657system.cpu1.dcache.demand_mshr_misses::total 575679 # number of demand (read+write) MSHR misses 1658system.cpu1.dcache.overall_mshr_misses::cpu1.data 575679 # number of overall MSHR misses 1659system.cpu1.dcache.overall_mshr_misses::total 575679 # number of overall MSHR misses 1660system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4991497250 # number of ReadReq MSHR miss cycles 1661system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4991497250 # number of ReadReq MSHR miss cycles 1662system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2127317766 # number of WriteReq MSHR miss cycles 1663system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2127317766 # number of WriteReq MSHR miss cycles 1664system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126550250 # number of LoadLockedReq MSHR miss cycles 1665system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles 1666system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3045420 # number of StoreCondReq MSHR miss cycles 1667system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3045420 # number of StoreCondReq MSHR miss cycles 1668system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7118815016 # number of demand (read+write) MSHR miss cycles 1669system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles 1670system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7118815016 # number of overall MSHR miss cycles 1671system.cpu1.dcache.overall_mshr_miss_latency::total 7118815016 # number of overall MSHR miss cycles |
| 1675system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles 1676system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles | 1672system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles 1673system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles |
| 1677system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907861000 # number of WriteReq MSHR uncacheable cycles 1678system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907861000 # number of WriteReq MSHR uncacheable cycles 1679system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387519500 # number of overall MSHR uncacheable cycles 1680system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387519500 # number of overall MSHR uncacheable cycles 1681system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133172 # mshr miss rate for ReadReq accesses 1682system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133172 # mshr miss rate for ReadReq accesses | 1674system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907862000 # number of WriteReq MSHR uncacheable cycles 1675system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907862000 # number of WriteReq MSHR uncacheable cycles 1676system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387520500 # number of overall MSHR uncacheable cycles 1677system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387520500 # number of overall MSHR uncacheable cycles 1678system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133165 # mshr miss rate for ReadReq accesses 1679system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133165 # mshr miss rate for ReadReq accesses |
| 1683system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses 1684system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses | 1680system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses 1681system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses |
| 1685system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160771 # mshr miss rate for LoadLockedReq accesses 1686system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160771 # mshr miss rate for LoadLockedReq accesses 1687system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007861 # mshr miss rate for StoreCondReq accesses 1688system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007861 # mshr miss rate for StoreCondReq accesses 1689system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for demand accesses 1690system.cpu1.dcache.demand_mshr_miss_rate::total 0.097316 # mshr miss rate for demand accesses 1691system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for overall accesses 1692system.cpu1.dcache.overall_mshr_miss_rate::total 0.097316 # mshr miss rate for overall accesses 1693system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10549.537203 # average ReadReq mshr miss latency 1694system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10549.537203 # average ReadReq mshr miss latency 1695system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20766.258217 # average WriteReq mshr miss latency 1696system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20766.258217 # average WriteReq mshr miss latency 1697system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.150274 # average LoadLockedReq mshr miss latency 1698system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.150274 # average LoadLockedReq mshr miss latency 1699system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.010582 # average StoreCondReq mshr miss latency 1700system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.010582 # average StoreCondReq mshr miss latency 1701system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency 1702system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency 1703system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency 1704system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency | 1682system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160762 # mshr miss rate for LoadLockedReq accesses 1683system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses 1684system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007875 # mshr miss rate for StoreCondReq accesses 1685system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007875 # mshr miss rate for StoreCondReq accesses 1686system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for demand accesses 1687system.cpu1.dcache.demand_mshr_miss_rate::total 0.097312 # mshr miss rate for demand accesses 1688system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for overall accesses 1689system.cpu1.dcache.overall_mshr_miss_rate::total 0.097312 # mshr miss rate for overall accesses 1690system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540 # average ReadReq mshr miss latency 1691system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency 1692system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189 # average WriteReq mshr miss latency 1693system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency 1694system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835 # average LoadLockedReq mshr miss latency 1695system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency 1696system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency 1697system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency 1698system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency 1699system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency 1700system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency 1701system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency |
| 1705system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1706system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1707system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1708system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1709system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1710system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1711system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1712 1713---------- End Simulation Statistics ---------- | 1702system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1703system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1704system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1705system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1706system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1707system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1708system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1709 1710---------- End Simulation Statistics ---------- |