| stats.txt (10063:9595c7a1d837) | stats.txt (10148:4574d5882066) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.960910 # Number of seconds simulated 4sim_ticks 1960909874500 # Number of ticks simulated 5final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.961814 # Number of seconds simulated 4sim_ticks 1961813569500 # Number of ticks simulated 5final_tick 1961813569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1305982 # Simulator instruction rate (inst/s) 8host_op_rate 1305981 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 42027651646 # Simulator tick rate (ticks/s) 10host_mem_usage 309852 # Number of bytes of host memory used 11host_seconds 46.66 # Real time elapsed on the host 12sim_insts 60933947 # Number of instructions simulated 13sim_ops 60933947 # Number of ops (including micro ops) simulated | 7host_inst_rate 1769979 # Simulator instruction rate (inst/s) 8host_op_rate 1769979 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57024152249 # Simulator tick rate (ticks/s) 10host_mem_usage 311592 # Number of bytes of host memory used 11host_seconds 34.40 # Real time elapsed on the host 12sim_insts 60892925 # Number of instructions simulated 13sim_ops 60892925 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory 21system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory 29system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 449082 # Number of read requests accepted 54system.physmem.writeReqs 120995 # Number of write requests accepted 55system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.bytes_read::cpu0.inst 833088 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24884096 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 31936 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 337152 # Number of bytes read from this memory 21system.physmem.bytes_read::total 28737152 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 833088 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7735232 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7735232 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 13017 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 388814 # Number of read requests responded to by this memory 29system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 499 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 5268 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 449018 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120863 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120863 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 424652 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12684231 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::tsunami.ide 1351240 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 16279 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 171857 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 14648258 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 424652 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 16279 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 440931 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3942899 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3942899 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3942899 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 424652 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12684231 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::tsunami.ide 1351240 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 16279 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 171857 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 449018 # Number of read requests accepted 54system.physmem.writeReqs 120863 # Number of write requests accepted 55system.physmem.readBursts 449018 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 120863 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 28729600 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7733952 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 28737152 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7735232 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue |
| 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 64system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 28167 # Per bank write bursts 66system.physmem.perBankRdBursts::1 28459 # Per bank write bursts 67system.physmem.perBankRdBursts::2 28057 # Per bank write bursts 68system.physmem.perBankRdBursts::3 27664 # Per bank write bursts 69system.physmem.perBankRdBursts::4 27762 # Per bank write bursts 70system.physmem.perBankRdBursts::5 27793 # Per bank write bursts 71system.physmem.perBankRdBursts::6 28259 # Per bank write bursts 72system.physmem.perBankRdBursts::7 27872 # Per bank write bursts 73system.physmem.perBankRdBursts::8 28083 # Per bank write bursts 74system.physmem.perBankRdBursts::9 27730 # Per bank write bursts 75system.physmem.perBankRdBursts::10 27672 # Per bank write bursts 76system.physmem.perBankRdBursts::11 28135 # Per bank write bursts 77system.physmem.perBankRdBursts::12 28179 # Per bank write bursts 78system.physmem.perBankRdBursts::13 28505 # Per bank write bursts 79system.physmem.perBankRdBursts::14 28654 # Per bank write bursts 80system.physmem.perBankRdBursts::15 28035 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7928 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7868 # Per bank write bursts 83system.physmem.perBankWrBursts::2 7543 # Per bank write bursts 84system.physmem.perBankWrBursts::3 7157 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7275 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7314 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7747 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7251 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7322 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7110 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7099 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7523 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7681 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8141 # Per bank write bursts 95system.physmem.perBankWrBursts::14 8335 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7684 # Per bank write bursts | 64system.physmem.neitherReadNorWriteReqs 6983 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 28166 # Per bank write bursts 66system.physmem.perBankRdBursts::1 28350 # Per bank write bursts 67system.physmem.perBankRdBursts::2 28054 # Per bank write bursts 68system.physmem.perBankRdBursts::3 27500 # Per bank write bursts 69system.physmem.perBankRdBursts::4 27615 # Per bank write bursts 70system.physmem.perBankRdBursts::5 27605 # Per bank write bursts 71system.physmem.perBankRdBursts::6 28127 # Per bank write bursts 72system.physmem.perBankRdBursts::7 27851 # Per bank write bursts 73system.physmem.perBankRdBursts::8 28176 # Per bank write bursts 74system.physmem.perBankRdBursts::9 27723 # Per bank write bursts 75system.physmem.perBankRdBursts::10 27750 # Per bank write bursts 76system.physmem.perBankRdBursts::11 28018 # Per bank write bursts 77system.physmem.perBankRdBursts::12 28330 # Per bank write bursts 78system.physmem.perBankRdBursts::13 28694 # Per bank write bursts 79system.physmem.perBankRdBursts::14 28891 # Per bank write bursts 80system.physmem.perBankRdBursts::15 28050 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7929 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7797 # Per bank write bursts 83system.physmem.perBankWrBursts::2 7545 # Per bank write bursts 84system.physmem.perBankWrBursts::3 7029 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7135 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7129 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7643 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7252 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7395 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7084 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7104 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7401 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7833 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8315 # Per bank write bursts 95system.physmem.perBankWrBursts::14 8551 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7701 # Per bank write bursts |
| 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 98system.physmem.numWrRetry 11 # Number of times write queue was full causing retry 99system.physmem.totGap 1960902862500 # Total gap between requests | 98system.physmem.numWrRetry 12 # Number of times write queue was full causing retry 99system.physmem.totGap 1961806557500 # Total gap between requests |
| 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) | 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 106system.physmem.readPktSize::6 449082 # Read request sizes (log2) | 106system.physmem.readPktSize::6 449018 # Read request sizes (log2) |
| 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) | 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 113system.physmem.writePktSize::6 120995 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see | 113system.physmem.writePktSize::6 120863 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 407987 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 1708 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 1544 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1052 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1160 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 4326 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 3779 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 3770 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 3964 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 2524 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 2113 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 2058 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1914 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1871 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1569 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 1543 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 1513 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 1527 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 1719 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 1248 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see |
| 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 146system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 5185 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 5982 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 6055 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 6054 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 6099 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 6134 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 5025 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 4966 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 4953 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 232 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 20 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see 178system.physmem.bytesPerActivate::samples 49380 # Bytes accessed per row activation 179system.physmem.bytesPerActivate::mean 738.726934 # Bytes accessed per row activation 180system.physmem.bytesPerActivate::gmean 222.746795 # Bytes accessed per row activation 181system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation 182system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1984-1987 64 0.13% 90.71% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2048-2051 84 0.17% 90.88% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2112-2115 51 0.10% 90.99% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2176-2179 54 0.11% 91.10% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2240-2243 70 0.14% 91.24% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2304-2307 45 0.09% 91.33% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2368-2371 72 0.15% 91.47% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2432-2435 49 0.10% 91.57% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2496-2499 40 0.08% 91.65% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2560-2563 72 0.15% 91.80% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2624-2627 42 0.09% 91.89% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2688-2691 45 0.09% 91.98% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2752-2755 69 0.14% 92.12% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::2816-2819 44 0.09% 92.21% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::2880-2883 64 0.13% 92.33% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::2944-2947 43 0.09% 92.42% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.51% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3072-3075 76 0.15% 92.66% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3136-3139 39 0.08% 92.74% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3200-3203 46 0.09% 92.83% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3264-3267 67 0.14% 92.97% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3328-3331 46 0.09% 93.06% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3392-3395 66 0.13% 93.20% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3456-3459 46 0.09% 93.29% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3520-3523 37 0.07% 93.36% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3584-3587 72 0.15% 93.51% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3648-3651 38 0.08% 93.59% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3712-3715 42 0.09% 93.67% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3776-3779 69 0.14% 93.81% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3840-3843 43 0.09% 93.90% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3904-3907 64 0.13% 94.03% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::3968-3971 42 0.09% 94.11% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4032-4035 41 0.08% 94.20% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4096-4099 74 0.15% 94.35% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4160-4163 37 0.07% 94.42% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4224-4227 43 0.09% 94.51% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4288-4291 66 0.13% 94.64% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4352-4355 46 0.09% 94.73% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4416-4419 64 0.13% 94.86% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4480-4483 43 0.09% 94.95% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4544-4547 37 0.07% 95.03% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4608-4611 404 0.82% 95.84% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4672-4675 34 0.07% 95.91% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4736-4739 44 0.09% 96.00% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4800-4803 36 0.07% 96.08% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4864-4867 44 0.09% 96.16% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4928-4931 34 0.07% 96.23% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::4992-4995 44 0.09% 96.32% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5056-5059 33 0.07% 96.39% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5120-5123 41 0.08% 96.47% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5184-5187 51 0.10% 96.58% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5248-5251 44 0.09% 96.66% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5312-5315 32 0.06% 96.73% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5376-5379 40 0.08% 96.81% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5440-5443 37 0.07% 96.89% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5504-5507 43 0.09% 96.97% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5568-5571 35 0.07% 97.04% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5632-5635 40 0.08% 97.12% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::5696-5699 33 0.07% 97.19% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::5760-5763 47 0.10% 97.29% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::5824-5827 34 0.07% 97.36% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::5888-5891 43 0.09% 97.44% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::5952-5955 35 0.07% 97.51% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6016-6019 44 0.09% 97.60% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6080-6083 34 0.07% 97.67% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6144-6147 44 0.09% 97.76% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6208-6211 38 0.08% 97.84% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6272-6275 42 0.09% 97.92% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6336-6339 35 0.07% 97.99% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6400-6403 43 0.09% 98.08% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6464-6467 32 0.06% 98.14% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6528-6531 40 0.08% 98.23% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::6592-6595 37 0.07% 98.30% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::6656-6659 41 0.08% 98.38% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6720-6723 32 0.06% 98.45% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6784-6787 431 0.87% 99.32% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.32% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.33% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7168-7171 10 0.02% 99.35% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.35% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.35% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.36% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7616-7619 3 0.01% 99.36% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.36% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.37% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.37% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.37% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.37% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.39% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.39% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.40% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.40% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.40% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.41% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.41% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.41% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::9088-9091 3 0.01% 99.42% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.42% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.42% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.42% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.43% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.43% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.43% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.43% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.44% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.44% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.45% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.45% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::11520-11523 2 0.00% 99.45% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.46% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.46% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.46% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.46% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::12288-12291 2 0.00% 99.47% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::12352-12355 3 0.01% 99.47% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.48% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.48% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::12672-12675 3 0.01% 99.48% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.49% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.49% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.49% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.49% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.50% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.50% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.50% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.51% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.51% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.52% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.52% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation 363system.physmem.totQLat 6346588750 # Total ticks spent queuing 364system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM 365system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers 366system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks 367system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst 368system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst | 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1574 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 1864 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 2356 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 4659 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 4719 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 4730 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 4812 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 4815 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 4859 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 6368 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 5252 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 5405 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 6934 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 5634 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 5860 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 5888 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 5671 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 1116 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 1056 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 1045 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 1090 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 1047 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 1031 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 1187 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 1508 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 1614 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 1739 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 1832 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 1868 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 1782 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 1877 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 1859 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 1827 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 1847 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 1717 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 1501 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 1291 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 437 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 293 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 48187 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 641.951066 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 418.430190 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 422.843508 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 8213 17.04% 17.04% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 7073 14.68% 31.72% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 2891 6.00% 37.72% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 1720 3.57% 41.29% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 1328 2.76% 44.05% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 906 1.88% 45.93% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 669 1.39% 47.32% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 536 1.11% 48.43% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 24851 51.57% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 48187 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 6896 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 65.095418 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2542.617511 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 6893 99.96% 99.96% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6896 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6896 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 17.523637 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 17.253710 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 3.981541 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16 4466 64.76% 64.76% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::17 342 4.96% 69.72% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::18 377 5.47% 75.19% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::19 1323 19.19% 94.37% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20 32 0.46% 94.84% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::21 16 0.23% 95.07% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::22 12 0.17% 95.24% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::23 22 0.32% 95.56% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::24 43 0.62% 96.19% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::25 30 0.44% 96.62% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::26 27 0.39% 97.01% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::27 32 0.46% 97.48% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::28 29 0.42% 97.90% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::29 31 0.45% 98.35% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::30 6 0.09% 98.43% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::31 8 0.12% 98.55% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::32 10 0.15% 98.69% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::33 3 0.04% 98.74% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::34 4 0.06% 98.80% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::35 4 0.06% 98.85% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::37 3 0.04% 98.90% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::38 3 0.04% 98.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::39 5 0.07% 99.01% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::40 3 0.04% 99.06% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::41 2 0.03% 99.09% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::42 2 0.03% 99.12% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::43 3 0.04% 99.16% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::45 3 0.04% 99.20% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::46 6 0.09% 99.29% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::47 12 0.17% 99.46% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::48 5 0.07% 99.54% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::49 7 0.10% 99.64% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::50 4 0.06% 99.70% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::51 3 0.04% 99.74% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::52 5 0.07% 99.81% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::53 6 0.09% 99.90% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::55 1 0.01% 99.91% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::56 2 0.03% 99.94% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::57 1 0.01% 99.96% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::total 6896 # Writes before turning the bus around for reads 277system.physmem.totQLat 7845433250 # Total ticks spent queuing 278system.physmem.totMemAccLat 16453873250 # Total ticks spent from burst creation until serviced by the DRAM 279system.physmem.totBusLat 2244500000 # Total ticks spent in databus transfers 280system.physmem.totBankLat 6363940000 # Total ticks spent accessing banks 281system.physmem.avgQLat 17477.02 # Average queueing delay per DRAM burst 282system.physmem.avgBankLat 14176.74 # Average bank access latency per DRAM burst |
| 369system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 283system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 370system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst 371system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s 372system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s 373system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s 374system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s | 284system.physmem.avgMemAccLat 36653.76 # Average memory access latency per DRAM burst 285system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s 286system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s 287system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s 288system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s |
| 375system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 376system.physmem.busUtil 0.15 # Data bus utilization in percentage 377system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 378system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes | 289system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 290system.physmem.busUtil 0.15 # Data bus utilization in percentage 291system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads 292system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 379system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing 380system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing 381system.physmem.readRowHits 424775 # Number of row buffer hits during reads 382system.physmem.writeRowHits 95849 # Number of row buffer hits during writes 383system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads 384system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes 385system.physmem.avgGap 3439715.80 # Average gap between requests 386system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined 387system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state 388system.membus.throughput 18666756 # Throughput (bytes/s) 389system.membus.trans_dist::ReadReq 292805 # Transaction distribution 390system.membus.trans_dist::ReadResp 292805 # Transaction distribution 391system.membus.trans_dist::WriteReq 14109 # Transaction distribution 392system.membus.trans_dist::WriteResp 14109 # Transaction distribution 393system.membus.trans_dist::Writeback 120995 # Transaction distribution 394system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution 395system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution 396system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution 397system.membus.trans_dist::ReadExReq 164894 # Transaction distribution 398system.membus.trans_dist::ReadExResp 164048 # Transaction distribution 399system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes) 400system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes) 401system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes) 402system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes) 403system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes) 404system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes) 405system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes) 406system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes) 407system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes) 408system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes) 409system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes) 410system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes) 411system.membus.data_through_bus 36567218 # Total data (bytes) 412system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes) 413system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks) | 293system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 294system.physmem.avgWrQLen 26.52 # Average write queue length when enqueuing 295system.physmem.readRowHits 403422 # Number of row buffer hits during reads 296system.physmem.writeRowHits 97436 # Number of row buffer hits during writes 297system.physmem.readRowHitRate 89.87 # Row buffer hit rate for reads 298system.physmem.writeRowHitRate 80.62 # Row buffer hit rate for writes 299system.physmem.avgGap 3442484.58 # Average gap between requests 300system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined 301system.physmem.prechargeAllPercent 0.55 # Percentage of time for which DRAM has all the banks in precharge state 302system.membus.throughput 18651494 # Throughput (bytes/s) 303system.membus.trans_dist::ReadReq 292756 # Transaction distribution 304system.membus.trans_dist::ReadResp 292756 # Transaction distribution 305system.membus.trans_dist::WriteReq 14067 # Transaction distribution 306system.membus.trans_dist::WriteResp 14067 # Transaction distribution 307system.membus.trans_dist::Writeback 120863 # Transaction distribution 308system.membus.trans_dist::UpgradeReq 16150 # Transaction distribution 309system.membus.trans_dist::SCUpgradeReq 11271 # Transaction distribution 310system.membus.trans_dist::UpgradeResp 6986 # Transaction distribution 311system.membus.trans_dist::ReadExReq 164854 # Transaction distribution 312system.membus.trans_dist::ReadExResp 164030 # Transaction distribution 313system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) 314system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930030 # Packet count per connected master and slave (bytes) 315system.membus.pkt_count_system.l2c.mem_side::total 972562 # Packet count per connected master and slave (bytes) 316system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count::total 1097228 # Packet count per connected master and slave (bytes) 319system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) 320system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31164224 # Cumulative packet size per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.l2c.mem_side::total 31246178 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) 324system.membus.tot_pkt_size::total 36554338 # Cumulative packet size per connected master and slave (bytes) 325system.membus.data_through_bus 36554338 # Total data (bytes) 326system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) 327system.membus.reqLayer0.occupancy 43154000 # Layer occupancy (ticks) |
| 414system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 328system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 415system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks) | 329system.membus.reqLayer1.occupancy 1578633000 # Layer occupancy (ticks) |
| 416system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) | 330system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) |
| 417system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks) | 331system.membus.respLayer1.occupancy 3834132000 # Layer occupancy (ticks) |
| 418system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 332system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 419system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks) | 333system.membus.respLayer2.occupancy 376702000 # Layer occupancy (ticks) |
| 420system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 421system.cpu_clk_domain.clock 500 # Clock period in ticks | 334system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 335system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 422system.l2c.tags.replacements 342160 # number of replacements 423system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use 424system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks. 425system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks. 426system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks. 427system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit. 428system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor 429system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor 430system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor 431system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor 432system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor 433system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy 434system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy 435system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy 436system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy 437system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy 438system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy | 336system.l2c.tags.replacements 342098 # number of replacements 337system.l2c.tags.tagsinuse 65220.106735 # Cycle average of tags in use 338system.l2c.tags.total_refs 2445213 # Total number of references to valid blocks. 339system.l2c.tags.sampled_refs 407285 # Sample count of references to valid blocks. 340system.l2c.tags.avg_refs 6.003690 # Average number of references to valid blocks. 341system.l2c.tags.warmup_cycle 8658635750 # Cycle when the warmup percentage was hit. 342system.l2c.tags.occ_blocks::writebacks 55273.758884 # Average occupied blocks per requestor 343system.l2c.tags.occ_blocks::cpu0.inst 4807.212496 # Average occupied blocks per requestor 344system.l2c.tags.occ_blocks::cpu0.data 4935.163888 # Average occupied blocks per requestor 345system.l2c.tags.occ_blocks::cpu1.inst 160.761256 # Average occupied blocks per requestor 346system.l2c.tags.occ_blocks::cpu1.data 43.210211 # Average occupied blocks per requestor 347system.l2c.tags.occ_percent::writebacks 0.843411 # Average percentage of cache occupancy 348system.l2c.tags.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy 349system.l2c.tags.occ_percent::cpu0.data 0.075305 # Average percentage of cache occupancy 350system.l2c.tags.occ_percent::cpu1.inst 0.002453 # Average percentage of cache occupancy 351system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy 352system.l2c.tags.occ_percent::total 0.995180 # Average percentage of cache occupancy |
| 439system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id 440system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id | 353system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id 354system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id |
| 441system.l2c.tags.age_task_id_blocks_1024::1 761 # Occupied blocks per task id 442system.l2c.tags.age_task_id_blocks_1024::2 5186 # Occupied blocks per task id 443system.l2c.tags.age_task_id_blocks_1024::3 7242 # Occupied blocks per task id 444system.l2c.tags.age_task_id_blocks_1024::4 51881 # Occupied blocks per task id | 355system.l2c.tags.age_task_id_blocks_1024::1 784 # Occupied blocks per task id 356system.l2c.tags.age_task_id_blocks_1024::2 5254 # Occupied blocks per task id 357system.l2c.tags.age_task_id_blocks_1024::3 7171 # Occupied blocks per task id 358system.l2c.tags.age_task_id_blocks_1024::4 51861 # Occupied blocks per task id |
| 445system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id | 359system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id |
| 446system.l2c.tags.tag_accesses 25932224 # Number of tag accesses 447system.l2c.tags.data_accesses 25932224 # Number of data accesses 448system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits 449system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits 450system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits 451system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits 452system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits 453system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits 454system.l2c.Writeback_hits::total 791641 # number of Writeback hits 455system.l2c.UpgradeReq_hits::cpu0.data 180 # number of UpgradeReq hits 456system.l2c.UpgradeReq_hits::cpu1.data 539 # number of UpgradeReq hits 457system.l2c.UpgradeReq_hits::total 719 # number of UpgradeReq hits 458system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits 459system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits 460system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits 461system.l2c.ReadExReq_hits::cpu0.data 129054 # number of ReadExReq hits 462system.l2c.ReadExReq_hits::cpu1.data 42974 # number of ReadExReq hits 463system.l2c.ReadExReq_hits::total 172028 # number of ReadExReq hits 464system.l2c.demand_hits::cpu0.inst 684719 # number of demand (read+write) hits 465system.l2c.demand_hits::cpu0.data 793579 # number of demand (read+write) hits 466system.l2c.demand_hits::cpu1.inst 317383 # number of demand (read+write) hits 467system.l2c.demand_hits::cpu1.data 150404 # number of demand (read+write) hits 468system.l2c.demand_hits::total 1946085 # number of demand (read+write) hits 469system.l2c.overall_hits::cpu0.inst 684719 # number of overall hits 470system.l2c.overall_hits::cpu0.data 793579 # number of overall hits 471system.l2c.overall_hits::cpu1.inst 317383 # number of overall hits 472system.l2c.overall_hits::cpu1.data 150404 # number of overall hits 473system.l2c.overall_hits::total 1946085 # number of overall hits 474system.l2c.ReadReq_misses::cpu0.inst 13026 # number of ReadReq misses 475system.l2c.ReadReq_misses::cpu0.data 271672 # number of ReadReq misses 476system.l2c.ReadReq_misses::cpu1.inst 503 # number of ReadReq misses 477system.l2c.ReadReq_misses::cpu1.data 242 # number of ReadReq misses 478system.l2c.ReadReq_misses::total 285443 # number of ReadReq misses 479system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses 480system.l2c.UpgradeReq_misses::cpu1.data 1793 # number of UpgradeReq misses 481system.l2c.UpgradeReq_misses::total 4742 # number of UpgradeReq misses 482system.l2c.SCUpgradeReq_misses::cpu0.data 919 # number of SCUpgradeReq misses 483system.l2c.SCUpgradeReq_misses::cpu1.data 927 # number of SCUpgradeReq misses 484system.l2c.SCUpgradeReq_misses::total 1846 # number of SCUpgradeReq misses 485system.l2c.ReadExReq_misses::cpu0.data 117950 # number of ReadExReq misses 486system.l2c.ReadExReq_misses::cpu1.data 5055 # number of ReadExReq misses 487system.l2c.ReadExReq_misses::total 123005 # number of ReadExReq misses 488system.l2c.demand_misses::cpu0.inst 13026 # number of demand (read+write) misses 489system.l2c.demand_misses::cpu0.data 389622 # number of demand (read+write) misses 490system.l2c.demand_misses::cpu1.inst 503 # number of demand (read+write) misses 491system.l2c.demand_misses::cpu1.data 5297 # number of demand (read+write) misses 492system.l2c.demand_misses::total 408448 # number of demand (read+write) misses 493system.l2c.overall_misses::cpu0.inst 13026 # number of overall misses 494system.l2c.overall_misses::cpu0.data 389622 # number of overall misses 495system.l2c.overall_misses::cpu1.inst 503 # number of overall misses 496system.l2c.overall_misses::cpu1.data 5297 # number of overall misses 497system.l2c.overall_misses::total 408448 # number of overall misses 498system.l2c.ReadReq_miss_latency::cpu0.inst 997409492 # number of ReadReq miss cycles 499system.l2c.ReadReq_miss_latency::cpu0.data 17552881248 # number of ReadReq miss cycles 500system.l2c.ReadReq_miss_latency::cpu1.inst 35450000 # number of ReadReq miss cycles 501system.l2c.ReadReq_miss_latency::cpu1.data 19470500 # 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number of overall miss cycles 518system.l2c.overall_miss_latency::cpu0.data 25817866500 # number of overall miss cycles 519system.l2c.overall_miss_latency::cpu1.inst 35450000 # number of overall miss cycles 520system.l2c.overall_miss_latency::cpu1.data 406671989 # number of overall miss cycles 521system.l2c.overall_miss_latency::total 27257397981 # number of overall miss cycles 522system.l2c.ReadReq_accesses::cpu0.inst 697745 # number of ReadReq accesses(hits+misses) 523system.l2c.ReadReq_accesses::cpu0.data 936197 # number of ReadReq accesses(hits+misses) 524system.l2c.ReadReq_accesses::cpu1.inst 317886 # number of ReadReq accesses(hits+misses) 525system.l2c.ReadReq_accesses::cpu1.data 107672 # number of ReadReq accesses(hits+misses) 526system.l2c.ReadReq_accesses::total 2059500 # number of ReadReq accesses(hits+misses) 527system.l2c.Writeback_accesses::writebacks 791641 # number of Writeback accesses(hits+misses) 528system.l2c.Writeback_accesses::total 791641 # number of Writeback accesses(hits+misses) 529system.l2c.UpgradeReq_accesses::cpu0.data 3129 # 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miss rate for ReadReq accesses 553system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942474 # miss rate for UpgradeReq accesses 554system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768868 # miss rate for UpgradeReq accesses 555system.l2c.UpgradeReq_miss_rate::total 0.868339 # miss rate for UpgradeReq accesses 556system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.960293 # miss rate for SCUpgradeReq accesses 557system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.977848 # miss rate for SCUpgradeReq accesses 558system.l2c.SCUpgradeReq_miss_rate::total 0.969029 # miss rate for SCUpgradeReq accesses 559system.l2c.ReadExReq_miss_rate::cpu0.data 0.477523 # miss rate for ReadExReq accesses 560system.l2c.ReadExReq_miss_rate::cpu1.data 0.105249 # miss rate for ReadExReq accesses 561system.l2c.ReadExReq_miss_rate::total 0.416919 # miss rate for ReadExReq accesses 562system.l2c.demand_miss_rate::cpu0.inst 0.018669 # miss rate for demand accesses 563system.l2c.demand_miss_rate::cpu0.data 0.329295 # miss rate for demand accesses 564system.l2c.demand_miss_rate::cpu1.inst 0.001582 # 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| 604system.l2c.writebacks::writebacks 79475 # number of writebacks 605system.l2c.writebacks::total 79475 # number of writebacks | 518system.l2c.writebacks::writebacks 79343 # number of writebacks 519system.l2c.writebacks::total 79343 # number of writebacks |
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number of demand (read+write) MSHR miss cycles 572system.l2c.overall_mshr_miss_latency::cpu0.inst 793128009 # number of overall MSHR miss cycles 573system.l2c.overall_mshr_miss_latency::cpu0.data 20892906747 # number of overall MSHR miss cycles 574system.l2c.overall_mshr_miss_latency::cpu1.inst 30990750 # number of overall MSHR miss cycles 575system.l2c.overall_mshr_miss_latency::cpu1.data 315042011 # number of overall MSHR miss cycles 576system.l2c.overall_mshr_miss_latency::total 22032067517 # number of overall MSHR miss cycles 577system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373162000 # number of ReadReq MSHR uncacheable cycles 578system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17619500 # number of ReadReq MSHR uncacheable cycles 579system.l2c.ReadReq_mshr_uncacheable_latency::total 1390781500 # number of ReadReq MSHR uncacheable cycles 580system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2149958500 # number of WriteReq MSHR uncacheable cycles 581system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674822000 # 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average ReadReq mshr miss latency 614system.l2c.ReadReq_avg_mshr_miss_latency::total 53053.913569 # average ReadReq mshr miss latency 615system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.674797 # average UpgradeReq mshr miss latency 616system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency 617system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.161868 # average UpgradeReq mshr miss latency |
| 704system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency 705system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency 706system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 618system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency 619system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency 620system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 707system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57507.611259 # average ReadExReq mshr miss latency 708system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63969.537290 # average ReadExReq mshr miss latency 709system.l2c.ReadExReq_avg_mshr_miss_latency::total 57773.169863 # average ReadExReq mshr miss latency 710system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average overall mshr miss latency 711system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53742.138534 # average overall mshr miss latency 712system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency 713system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency 714system.l2c.demand_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency 715system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average overall mshr miss latency 716system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53742.138534 # average overall mshr miss latency 717system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency 718system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency 719system.l2c.overall_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency | 621system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55884.310050 # average ReadExReq mshr miss latency 622system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59621.283419 # average ReadExReq mshr miss latency 623system.l2c.ReadExReq_avg_mshr_miss_latency::total 56037.522980 # average ReadExReq mshr miss latency 624system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency 625system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency 626system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency 627system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency 628system.l2c.demand_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency 629system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency 630system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency 631system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency 632system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency 633system.l2c.overall_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency |
| 720system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 721system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 722system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 723system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 724system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 725system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 726system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 727system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 728system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 729system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 730system.iocache.tags.replacements 41694 # number of replacements | 634system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 635system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 636system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 637system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 638system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 639system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 640system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 641system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 642system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 643system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 644system.iocache.tags.replacements 41694 # number of replacements |
| 731system.iocache.tags.tagsinuse 0.570482 # Cycle average of tags in use | 645system.iocache.tags.tagsinuse 0.569649 # Cycle average of tags in use |
| 732system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 733system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. 734system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 646system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 647system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. 648system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 735system.iocache.tags.warmup_cycle 1754531382000 # Cycle when the warmup percentage was hit. 736system.iocache.tags.occ_blocks::tsunami.ide 0.570482 # Average occupied blocks per requestor 737system.iocache.tags.occ_percent::tsunami.ide 0.035655 # Average percentage of cache occupancy 738system.iocache.tags.occ_percent::total 0.035655 # Average percentage of cache occupancy | 649system.iocache.tags.warmup_cycle 1755503918000 # Cycle when the warmup percentage was hit. 650system.iocache.tags.occ_blocks::tsunami.ide 0.569649 # Average occupied blocks per requestor 651system.iocache.tags.occ_percent::tsunami.ide 0.035603 # Average percentage of cache occupancy 652system.iocache.tags.occ_percent::total 0.035603 # Average percentage of cache occupancy |
| 739system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 740system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 741system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 742system.iocache.tags.tag_accesses 375534 # Number of tag accesses 743system.iocache.tags.data_accesses 375534 # Number of data accesses 744system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 745system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 746system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 747system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 748system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 749system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 750system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 751system.iocache.overall_misses::total 41726 # number of overall misses | 653system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 654system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 655system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 656system.iocache.tags.tag_accesses 375534 # Number of tag accesses 657system.iocache.tags.data_accesses 375534 # Number of data accesses 658system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 659system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 660system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 661system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 662system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 663system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 664system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 665system.iocache.overall_misses::total 41726 # number of overall misses |
| 752system.iocache.ReadReq_miss_latency::tsunami.ide 21249133 # number of ReadReq miss cycles 753system.iocache.ReadReq_miss_latency::total 21249133 # number of ReadReq miss cycles 754system.iocache.WriteReq_miss_latency::tsunami.ide 12966402814 # number of WriteReq miss cycles 755system.iocache.WriteReq_miss_latency::total 12966402814 # number of WriteReq miss cycles 756system.iocache.demand_miss_latency::tsunami.ide 12987651947 # number of demand (read+write) miss cycles 757system.iocache.demand_miss_latency::total 12987651947 # number of demand (read+write) miss cycles 758system.iocache.overall_miss_latency::tsunami.ide 12987651947 # number of overall miss cycles 759system.iocache.overall_miss_latency::total 12987651947 # number of overall miss cycles | 666system.iocache.ReadReq_miss_latency::tsunami.ide 21248883 # number of ReadReq miss cycles 667system.iocache.ReadReq_miss_latency::total 21248883 # number of ReadReq miss cycles 668system.iocache.WriteReq_miss_latency::tsunami.ide 13129991411 # number of WriteReq miss cycles 669system.iocache.WriteReq_miss_latency::total 13129991411 # number of WriteReq miss cycles 670system.iocache.demand_miss_latency::tsunami.ide 13151240294 # number of demand (read+write) miss cycles 671system.iocache.demand_miss_latency::total 13151240294 # number of demand (read+write) miss cycles 672system.iocache.overall_miss_latency::tsunami.ide 13151240294 # number of overall miss cycles 673system.iocache.overall_miss_latency::total 13151240294 # number of overall miss cycles |
| 760system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 761system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 762system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 763system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 764system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 765system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 766system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 767system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 768system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 769system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 770system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 771system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 772system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 773system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 774system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 775system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 674system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 675system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 676system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 677system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 678system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 679system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 680system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 681system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 682system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 683system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 684system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 685system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 686system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 687system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 688system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 689system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 776system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023 # average ReadReq miss latency 777system.iocache.ReadReq_avg_miss_latency::total 122121.454023 # average ReadReq miss latency 778system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839 # average WriteReq miss latency 779system.iocache.WriteReq_avg_miss_latency::total 312052.435839 # average WriteReq miss latency 780system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency 781system.iocache.demand_avg_miss_latency::total 311260.411901 # average overall miss latency 782system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency 783system.iocache.overall_avg_miss_latency::total 311260.411901 # average overall miss latency 784system.iocache.blocked_cycles::no_mshrs 401197 # number of cycles access was blocked | 690system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241 # average ReadReq miss latency 691system.iocache.ReadReq_avg_miss_latency::total 122120.017241 # average ReadReq miss latency 692system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684 # average WriteReq miss latency 693system.iocache.WriteReq_avg_miss_latency::total 315989.396684 # average WriteReq miss latency 694system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency 695system.iocache.demand_avg_miss_latency::total 315180.949384 # average overall miss latency 696system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency 697system.iocache.overall_avg_miss_latency::total 315180.949384 # average overall miss latency 698system.iocache.blocked_cycles::no_mshrs 388544 # number of cycles access was blocked |
| 785system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 699system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 786system.iocache.blocked::no_mshrs 28980 # number of cycles access was blocked | 700system.iocache.blocked::no_mshrs 28481 # number of cycles access was blocked |
| 787system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 701system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 788system.iocache.avg_blocked_cycles::no_mshrs 13.843927 # average number of cycles each access was blocked | 702system.iocache.avg_blocked_cycles::no_mshrs 13.642218 # average number of cycles each access was blocked |
| 789system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 790system.iocache.fast_writes 0 # number of fast writes performed 791system.iocache.cache_copies 0 # number of cache copies performed 792system.iocache.writebacks::writebacks 41520 # number of writebacks 793system.iocache.writebacks::total 41520 # number of writebacks 794system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 795system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 796system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 797system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 798system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses 799system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses 800system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses 801system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses | 703system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 704system.iocache.fast_writes 0 # number of fast writes performed 705system.iocache.cache_copies 0 # number of cache copies performed 706system.iocache.writebacks::writebacks 41520 # number of writebacks 707system.iocache.writebacks::total 41520 # number of writebacks 708system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 709system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 710system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 711system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 712system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses 713system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses 714system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses 715system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses |
| 802system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12200133 # number of ReadReq MSHR miss cycles 803system.iocache.ReadReq_mshr_miss_latency::total 12200133 # number of ReadReq MSHR miss cycles 804system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10804136814 # number of WriteReq MSHR miss cycles 805system.iocache.WriteReq_mshr_miss_latency::total 10804136814 # number of WriteReq MSHR miss cycles 806system.iocache.demand_mshr_miss_latency::tsunami.ide 10816336947 # number of demand (read+write) MSHR miss cycles 807system.iocache.demand_mshr_miss_latency::total 10816336947 # number of demand (read+write) MSHR miss cycles 808system.iocache.overall_mshr_miss_latency::tsunami.ide 10816336947 # number of overall MSHR miss cycles 809system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles | 716system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199883 # number of ReadReq MSHR miss cycles 717system.iocache.ReadReq_mshr_miss_latency::total 12199883 # number of ReadReq MSHR miss cycles 718system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10966952411 # number of WriteReq MSHR miss cycles 719system.iocache.WriteReq_mshr_miss_latency::total 10966952411 # number of WriteReq MSHR miss cycles 720system.iocache.demand_mshr_miss_latency::tsunami.ide 10979152294 # number of demand (read+write) MSHR miss cycles 721system.iocache.demand_mshr_miss_latency::total 10979152294 # number of demand (read+write) MSHR miss cycles 722system.iocache.overall_mshr_miss_latency::tsunami.ide 10979152294 # number of overall MSHR miss cycles 723system.iocache.overall_mshr_miss_latency::total 10979152294 # number of overall MSHR miss cycles |
| 810system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 811system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 812system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 813system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 814system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 815system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 816system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 817system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 724system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 725system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 726system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 727system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 728system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 729system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 730system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 731system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 818system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency 819system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency 820system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency 821system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency 822system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency 823system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency 824system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency 825system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency | 732system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115 # average ReadReq mshr miss latency 733system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115 # average ReadReq mshr miss latency 734system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036 # average WriteReq mshr miss latency 735system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036 # average WriteReq mshr miss latency 736system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency 737system.iocache.demand_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency 738system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency 739system.iocache.overall_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency |
| 826system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 827system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 828system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 829system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 830system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 831system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 832system.disk0.dma_write_txs 395 # Number of DMA write transactions. 833system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 834system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 835system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 836system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 837system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 838system.disk2.dma_write_txs 1 # Number of DMA write transactions. 839system.cpu0.dtb.fetch_hits 0 # ITB hits 840system.cpu0.dtb.fetch_misses 0 # ITB misses 841system.cpu0.dtb.fetch_acv 0 # ITB acv 842system.cpu0.dtb.fetch_accesses 0 # ITB accesses | 740system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 741system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 742system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 743system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 744system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 745system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 746system.disk0.dma_write_txs 395 # Number of DMA write transactions. 747system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 748system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 749system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 750system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 751system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 752system.disk2.dma_write_txs 1 # Number of DMA write transactions. 753system.cpu0.dtb.fetch_hits 0 # ITB hits 754system.cpu0.dtb.fetch_misses 0 # ITB misses 755system.cpu0.dtb.fetch_acv 0 # ITB acv 756system.cpu0.dtb.fetch_accesses 0 # ITB accesses |
| 843system.cpu0.dtb.read_hits 7532654 # DTB read hits 844system.cpu0.dtb.read_misses 7812 # DTB read misses | 757system.cpu0.dtb.read_hits 7562587 # DTB read hits 758system.cpu0.dtb.read_misses 7765 # DTB read misses |
| 845system.cpu0.dtb.read_acv 210 # DTB read access violations | 759system.cpu0.dtb.read_acv 210 # DTB read access violations |
| 846system.cpu0.dtb.read_accesses 524694 # DTB read accesses 847system.cpu0.dtb.write_hits 5120278 # DTB write hits 848system.cpu0.dtb.write_misses 919 # DTB write misses 849system.cpu0.dtb.write_acv 139 # DTB write access violations 850system.cpu0.dtb.write_accesses 202960 # DTB write accesses 851system.cpu0.dtb.data_hits 12652932 # DTB hits 852system.cpu0.dtb.data_misses 8731 # DTB misses 853system.cpu0.dtb.data_acv 349 # DTB access violations 854system.cpu0.dtb.data_accesses 727654 # DTB accesses 855system.cpu0.itb.fetch_hits 3655515 # ITB hits 856system.cpu0.itb.fetch_misses 4023 # ITB misses | 760system.cpu0.dtb.read_accesses 524069 # DTB read accesses 761system.cpu0.dtb.write_hits 5147352 # DTB write hits 762system.cpu0.dtb.write_misses 910 # DTB write misses 763system.cpu0.dtb.write_acv 133 # DTB write access violations 764system.cpu0.dtb.write_accesses 202595 # DTB write accesses 765system.cpu0.dtb.data_hits 12709939 # DTB hits 766system.cpu0.dtb.data_misses 8675 # DTB misses 767system.cpu0.dtb.data_acv 343 # DTB access violations 768system.cpu0.dtb.data_accesses 726664 # DTB accesses 769system.cpu0.itb.fetch_hits 3660806 # ITB hits 770system.cpu0.itb.fetch_misses 3984 # ITB misses |
| 857system.cpu0.itb.fetch_acv 184 # ITB acv | 771system.cpu0.itb.fetch_acv 184 # ITB acv |
| 858system.cpu0.itb.fetch_accesses 3659538 # ITB accesses | 772system.cpu0.itb.fetch_accesses 3664790 # ITB accesses |
| 859system.cpu0.itb.read_hits 0 # DTB read hits 860system.cpu0.itb.read_misses 0 # DTB read misses 861system.cpu0.itb.read_acv 0 # DTB read access violations 862system.cpu0.itb.read_accesses 0 # DTB read accesses 863system.cpu0.itb.write_hits 0 # DTB write hits 864system.cpu0.itb.write_misses 0 # DTB write misses 865system.cpu0.itb.write_acv 0 # DTB write access violations 866system.cpu0.itb.write_accesses 0 # DTB write accesses 867system.cpu0.itb.data_hits 0 # DTB hits 868system.cpu0.itb.data_misses 0 # DTB misses 869system.cpu0.itb.data_acv 0 # DTB access violations 870system.cpu0.itb.data_accesses 0 # DTB accesses | 773system.cpu0.itb.read_hits 0 # DTB read hits 774system.cpu0.itb.read_misses 0 # DTB read misses 775system.cpu0.itb.read_acv 0 # DTB read access violations 776system.cpu0.itb.read_accesses 0 # DTB read accesses 777system.cpu0.itb.write_hits 0 # DTB write hits 778system.cpu0.itb.write_misses 0 # DTB write misses 779system.cpu0.itb.write_acv 0 # DTB write access violations 780system.cpu0.itb.write_accesses 0 # DTB write accesses 781system.cpu0.itb.data_hits 0 # DTB hits 782system.cpu0.itb.data_misses 0 # DTB misses 783system.cpu0.itb.data_acv 0 # DTB access violations 784system.cpu0.itb.data_accesses 0 # DTB accesses |
| 871system.cpu0.numCycles 3921819749 # number of cpu cycles simulated | 785system.cpu0.numCycles 3923627139 # number of cpu cycles simulated |
| 872system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 873system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 786system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 787system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 874system.cpu0.committedInsts 47983654 # Number of instructions committed 875system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed 876system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses 877system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses 878system.cpu0.num_func_calls 1203620 # number of times a function call or return occured 879system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls 880system.cpu0.num_int_insts 44515044 # number of integer instructions 881system.cpu0.num_fp_insts 211401 # number of float instructions 882system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read 883system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written 884system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read 885system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written 886system.cpu0.num_mem_refs 12694028 # number of memory refs 887system.cpu0.num_load_insts 7560495 # Number of load instructions 888system.cpu0.num_store_insts 5133533 # Number of store instructions 889system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles 890system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles 891system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles 892system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles 893system.cpu0.Branches 7227606 # Number of branches fetched | 788system.cpu0.committedInsts 48127942 # Number of instructions committed 789system.cpu0.committedOps 48127942 # Number of ops (including micro ops) committed 790system.cpu0.num_int_alu_accesses 44644072 # Number of integer alu accesses 791system.cpu0.num_fp_alu_accesses 213646 # Number of float alu accesses 792system.cpu0.num_func_calls 1209779 # number of times a function call or return occured 793system.cpu0.num_conditional_control_insts 5646914 # number of instructions that are conditional controls 794system.cpu0.num_int_insts 44644072 # number of integer instructions 795system.cpu0.num_fp_insts 213646 # number of float instructions 796system.cpu0.num_int_register_reads 61387929 # number of times the integer registers were read 797system.cpu0.num_int_register_writes 33243119 # number of times the integer registers were written 798system.cpu0.num_fp_register_reads 104403 # number of times the floating registers were read 799system.cpu0.num_fp_register_writes 106204 # number of times the floating registers were written 800system.cpu0.num_mem_refs 12751056 # number of memory refs 801system.cpu0.num_load_insts 7590434 # Number of load instructions 802system.cpu0.num_store_insts 5160622 # Number of store instructions 803system.cpu0.num_idle_cycles 3699531471.998114 # Number of idle cycles 804system.cpu0.num_busy_cycles 224095667.001886 # Number of busy cycles 805system.cpu0.not_idle_fraction 0.057114 # Percentage of non-idle cycles 806system.cpu0.idle_fraction 0.942886 # Percentage of idle cycles 807system.cpu0.Branches 7246727 # Number of branches fetched |
| 894system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 808system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 895system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed 896system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed 897system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl 898system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl 899system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl 900system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl 901system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl 902system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl 903system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl | 809system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed 810system.cpu0.kern.inst.hwrei 166332 # number of hwrei instructions executed 811system.cpu0.kern.ipl_count::0 57240 40.25% 40.25% # number of times we switched to this ipl 812system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl 813system.cpu0.kern.ipl_count::22 1974 1.39% 41.73% # number of times we switched to this ipl 814system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl 815system.cpu0.kern.ipl_count::31 82451 57.97% 100.00% # number of times we switched to this ipl 816system.cpu0.kern.ipl_count::total 142220 # number of times we switched to this ipl 817system.cpu0.kern.ipl_good::0 56707 49.09% 49.09% # number of times we switched to this ipl from a different ipl |
| 904system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl | 818system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl |
| 905system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl 906system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl 907system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl 908system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl 909system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl 910system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl 911system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl 912system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl 913system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl 914system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl 915system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl | 819system.cpu0.kern.ipl_good::22 1974 1.71% 50.91% # number of times we switched to this ipl from a different ipl 820system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl 821system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl 822system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl 823system.cpu0.kern.ipl_ticks::0 1902164041000 96.96% 96.96% # number of cycles we spent at this ipl 824system.cpu0.kern.ipl_ticks::21 95225000 0.00% 96.96% # number of cycles we spent at this ipl 825system.cpu0.kern.ipl_ticks::22 767277500 0.04% 97.00% # number of cycles we spent at this ipl 826system.cpu0.kern.ipl_ticks::30 314374500 0.02% 97.02% # number of cycles we spent at this ipl 827system.cpu0.kern.ipl_ticks::31 58471894000 2.98% 100.00% # number of cycles we spent at this ipl 828system.cpu0.kern.ipl_ticks::total 1961812812000 # number of cycles we spent at this ipl 829system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl |
| 916system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 917system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 918system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 830system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 831system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 832system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 919system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl 920system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl | 833system.cpu0.kern.ipl_used::31 0.682624 # fraction of swpipl calls that actually changed the ipl 834system.cpu0.kern.ipl_used::total 0.812256 # fraction of swpipl calls that actually changed the ipl |
| 921system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 922system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 923system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 924system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 925system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 926system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 927system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 928system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 944system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 945system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 946system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 947system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 948system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 949system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 950system.cpu0.kern.syscall::total 234 # number of syscalls executed 951system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 835system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed 836system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed 837system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed 838system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed 839system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed 840system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed 841system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed 842system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed --- 15 unchanged lines hidden (view full) --- 858system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed 859system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed 860system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed 861system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed 862system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed 863system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed 864system.cpu0.kern.syscall::total 234 # number of syscalls executed 865system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 952system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed 953system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed 954system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed 955system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed 956system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed 957system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed 958system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 959system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed 960system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed 961system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed 962system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed 963system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed 964system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed 965system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed 966system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed | 866system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed 867system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 868system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 869system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed 870system.cpu0.kern.callpal::swpctx 3107 2.06% 2.40% # number of callpals executed 871system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 872system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed 873system.cpu0.kern.callpal::swpipl 135267 89.81% 92.25% # number of callpals executed 874system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed 875system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed 876system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed 877system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed 878system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed 879system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed 880system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed |
| 967system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed | 881system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed |
| 968system.cpu0.kern.callpal::total 149515 # number of callpals executed 969system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches 970system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches | 882system.cpu0.kern.callpal::total 150615 # number of callpals executed 883system.cpu0.kern.mode_switch::kernel 7022 # number of protection mode switches 884system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches |
| 971system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches | 885system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches |
| 972system.cpu0.kern.mode_good::kernel 1377 973system.cpu0.kern.mode_good::user 1378 | 886system.cpu0.kern.mode_good::kernel 1371 887system.cpu0.kern.mode_good::user 1372 |
| 974system.cpu0.kern.mode_good::idle 0 | 888system.cpu0.kern.mode_good::idle 0 |
| 975system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches | 889system.cpu0.kern.mode_switch_good::kernel 0.195244 # fraction of useful protection mode switches |
| 976system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 977system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 890system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 891system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 978system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches 979system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode 980system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode | 892system.cpu0.kern.mode_switch_good::total 0.326781 # fraction of useful protection mode switches 893system.cpu0.kern.mode_ticks::kernel 1958041026500 99.81% 99.81% # number of ticks spent at the given mode 894system.cpu0.kern.mode_ticks::user 3771781000 0.19% 100.00% # number of ticks spent at the given mode |
| 981system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode | 895system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode |
| 982system.cpu0.kern.swap_context 3091 # number of times the context was actually changed | 896system.cpu0.kern.swap_context 3108 # number of times the context was actually changed |
| 983system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 984system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 985system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 986system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 987system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 988system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 989system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 990system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1006system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1007system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1008system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1009system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1010system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1011system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1012system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1013system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 897system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 898system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 899system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 900system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 901system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 902system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 903system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 904system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 920system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 921system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 922system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 923system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 924system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 925system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 926system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 927system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 1014system.toL2Bus.throughput 103937669 # Throughput (bytes/s) 1015system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution 1016system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution 1017system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution 1018system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution 1019system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution 1020system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution 1021system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution 1022system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution 1023system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution 1024system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution 1025system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes) 1026system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes) 1027system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes) 1028system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes) 1029system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes) 1030system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes) 1031system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes) 1032system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes) 1033system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes) 1034system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes) 1035system.toL2Bus.data_through_bus 201437426 # Total data (bytes) 1036system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes) 1037system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks) | 928system.toL2Bus.throughput 103965077 # Throughput (bytes/s) 929system.toL2Bus.trans_dist::ReadReq 2102306 # Transaction distribution 930system.toL2Bus.trans_dist::ReadResp 2102291 # Transaction distribution 931system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution 932system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution 933system.toL2Bus.trans_dist::Writeback 792911 # Transaction distribution 934system.toL2Bus.trans_dist::UpgradeReq 16363 # Transaction distribution 935system.toL2Bus.trans_dist::SCUpgradeReq 11335 # Transaction distribution 936system.toL2Bus.trans_dist::UpgradeResp 27698 # Transaction distribution 937system.toL2Bus.trans_dist::ReadExReq 339143 # Transaction distribution 938system.toL2Bus.trans_dist::ReadExResp 297593 # Transaction distribution 939system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407788 # Packet count per connected master and slave (bytes) 940system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134857 # Packet count per connected master and slave (bytes) 941system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624045 # Packet count per connected master and slave (bytes) 942system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452421 # Packet count per connected master and slave (bytes) 943system.toL2Bus.pkt_count::total 5619111 # Packet count per connected master and slave (bytes) 944system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45048576 # Cumulative packet size per connected master and slave (bytes) 945system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120057312 # Cumulative packet size per connected master and slave (bytes) 946system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19969408 # Cumulative packet size per connected master and slave (bytes) 947system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16548674 # Cumulative packet size per connected master and slave (bytes) 948system.toL2Bus.tot_pkt_size::total 201623970 # Cumulative packet size per connected master and slave (bytes) 949system.toL2Bus.data_through_bus 201613666 # Total data (bytes) 950system.toL2Bus.snoop_data_through_bus 2346432 # Total snoop data (bytes) 951system.toL2Bus.reqLayer0.occupancy 4795947858 # Layer occupancy (ticks) |
| 1038system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1039system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) 1040system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 952system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 953system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) 954system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1041system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks) | 955system.toL2Bus.respLayer0.occupancy 3170057255 # Layer occupancy (ticks) |
| 1042system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) | 956system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) |
| 1043system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks) | 957system.toL2Bus.respLayer1.occupancy 5536383084 # Layer occupancy (ticks) |
| 1044system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) | 958system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) |
| 1045system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks) | 959system.toL2Bus.respLayer2.occupancy 1404201241 # Layer occupancy (ticks) |
| 1046system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) | 960system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 1047system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks) | 961system.toL2Bus.respLayer3.occupancy 776393157 # Layer occupancy (ticks) |
| 1048system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 962system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1049system.iobus.throughput 1399302 # Throughput (bytes/s) | 963system.iobus.throughput 1398487 # Throughput (bytes/s) |
| 1050system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1051system.iobus.trans_dist::ReadResp 7373 # Transaction distribution | 964system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 965system.iobus.trans_dist::ReadResp 7373 # Transaction distribution |
| 1052system.iobus.trans_dist::WriteReq 55661 # Transaction distribution 1053system.iobus.trans_dist::WriteResp 55661 # Transaction distribution 1054system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes) | 966system.iobus.trans_dist::WriteReq 55619 # Transaction distribution 967system.iobus.trans_dist::WriteResp 55619 # Transaction distribution 968system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) |
| 1055system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) 1056system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1057system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1058system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1059system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1060system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1061system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1062system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 1063system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1064system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 1065system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 969system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) 970system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 971system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 972system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 973system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 974system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 975system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 976system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 977system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 978system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 979system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 1066system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes) | 980system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) |
| 1067system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 1068system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) | 981system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 982system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) |
| 1069system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes) 1070system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes) | 983system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) 984system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) |
| 1071system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) 1072system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1073system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1074system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1075system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1076system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1077system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1078system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 1079system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1080system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 1081system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 985system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) 986system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 987system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 988system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 989system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 990system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 991system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 992system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 993system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 994system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 995system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1082system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes) | 996system.iobus.tot_pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) |
| 1083system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 1084system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) | 997system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 998system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) |
| 1085system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes) 1086system.iobus.data_through_bus 2743906 # Total data (bytes) 1087system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks) | 999system.iobus.tot_pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) 1000system.iobus.data_through_bus 2743570 # Total data (bytes) 1001system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) |
| 1088system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1089system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) 1090system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1091system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1092system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1093system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1094system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1095system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1101system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1102system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1103system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1104system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1105system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1106system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1107system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1108system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1002system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1003system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) 1004system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1005system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 1006system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1007system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 1008system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1009system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1015system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 1016system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1017system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 1018system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1019system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 1020system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1021system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 1022system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1109system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks) | 1023system.iobus.reqLayer29.occupancy 380082294 # Layer occupancy (ticks) |
| 1110system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1111system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1112system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) | 1024system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 1025system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 1026system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) |
| 1113system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks) | 1027system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) |
| 1114system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1028system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1115system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks) | 1029system.iobus.respLayer1.occupancy 43185000 # Layer occupancy (ticks) |
| 1116system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1030system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1117system.cpu0.icache.tags.replacements 697136 # number of replacements 1118system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use 1119system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks. 1120system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks. 1121system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks. 1122system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit. 1123system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor 1124system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy 1125system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy | 1031system.cpu0.icache.tags.replacements 703274 # number of replacements 1032system.cpu0.icache.tags.tagsinuse 508.380970 # Cycle average of tags in use 1033system.cpu0.icache.tags.total_refs 47433057 # Total number of references to valid blocks. 1034system.cpu0.icache.tags.sampled_refs 703786 # Sample count of references to valid blocks. 1035system.cpu0.icache.tags.avg_refs 67.396989 # Average number of references to valid blocks. 1036system.cpu0.icache.tags.warmup_cycle 40278267250 # Cycle when the warmup percentage was hit. 1037system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.380970 # Average occupied blocks per requestor 1038system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992932 # Average percentage of cache occupancy 1039system.cpu0.icache.tags.occ_percent::total 0.992932 # Average percentage of cache occupancy |
| 1126system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1127system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 1128system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id | 1040system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1041system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 1042system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id |
| 1129system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id 1130system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id | 1043system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id 1044system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id |
| 1131system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1045system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1132system.cpu0.icache.tags.tag_accesses 48690501 # Number of tag accesses 1133system.cpu0.icache.tags.data_accesses 48690501 # Number of data accesses 1134system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits 1135system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits 1136system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits 1137system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits 1138system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits 1139system.cpu0.icache.overall_hits::total 47294969 # number of overall hits 1140system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses 1141system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses 1142system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses 1143system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses 1144system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses 1145system.cpu0.icache.overall_misses::total 697766 # number of overall misses 1146system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles 1147system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles 1148system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles 1149system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles 1150system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles 1151system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles 1152system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses) 1153system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses) 1154system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses 1155system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses 1156system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses 1157system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses 1158system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses 1159system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses 1160system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses 1161system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses 1162system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses 1163system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses 1164system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency 1165system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency 1166system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency 1167system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency 1168system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency 1169system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency | 1046system.cpu0.icache.tags.tag_accesses 48840865 # Number of tag accesses 1047system.cpu0.icache.tags.data_accesses 48840865 # Number of data accesses 1048system.cpu0.icache.ReadReq_hits::cpu0.inst 47433057 # number of ReadReq hits 1049system.cpu0.icache.ReadReq_hits::total 47433057 # number of ReadReq hits 1050system.cpu0.icache.demand_hits::cpu0.inst 47433057 # number of demand (read+write) hits 1051system.cpu0.icache.demand_hits::total 47433057 # number of demand (read+write) hits 1052system.cpu0.icache.overall_hits::cpu0.inst 47433057 # number of overall hits 1053system.cpu0.icache.overall_hits::total 47433057 # number of overall hits 1054system.cpu0.icache.ReadReq_misses::cpu0.inst 703904 # number of ReadReq misses 1055system.cpu0.icache.ReadReq_misses::total 703904 # number of ReadReq misses 1056system.cpu0.icache.demand_misses::cpu0.inst 703904 # number of demand (read+write) misses 1057system.cpu0.icache.demand_misses::total 703904 # number of demand (read+write) misses 1058system.cpu0.icache.overall_misses::cpu0.inst 703904 # number of overall misses 1059system.cpu0.icache.overall_misses::total 703904 # number of overall misses 1060system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10025783755 # number of ReadReq miss cycles 1061system.cpu0.icache.ReadReq_miss_latency::total 10025783755 # number of ReadReq miss cycles 1062system.cpu0.icache.demand_miss_latency::cpu0.inst 10025783755 # number of demand (read+write) miss cycles 1063system.cpu0.icache.demand_miss_latency::total 10025783755 # number of demand (read+write) miss cycles 1064system.cpu0.icache.overall_miss_latency::cpu0.inst 10025783755 # number of overall miss cycles 1065system.cpu0.icache.overall_miss_latency::total 10025783755 # number of overall miss cycles 1066system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136961 # number of ReadReq accesses(hits+misses) 1067system.cpu0.icache.ReadReq_accesses::total 48136961 # number of ReadReq accesses(hits+misses) 1068system.cpu0.icache.demand_accesses::cpu0.inst 48136961 # number of demand (read+write) accesses 1069system.cpu0.icache.demand_accesses::total 48136961 # number of demand (read+write) accesses 1070system.cpu0.icache.overall_accesses::cpu0.inst 48136961 # number of overall (read+write) accesses 1071system.cpu0.icache.overall_accesses::total 48136961 # number of overall (read+write) accesses 1072system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014623 # miss rate for ReadReq accesses 1073system.cpu0.icache.ReadReq_miss_rate::total 0.014623 # miss rate for ReadReq accesses 1074system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014623 # miss rate for demand accesses 1075system.cpu0.icache.demand_miss_rate::total 0.014623 # miss rate for demand accesses 1076system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014623 # miss rate for overall accesses 1077system.cpu0.icache.overall_miss_rate::total 0.014623 # miss rate for overall accesses 1078system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14243.112349 # average ReadReq miss latency 1079system.cpu0.icache.ReadReq_avg_miss_latency::total 14243.112349 # average ReadReq miss latency 1080system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency 1081system.cpu0.icache.demand_avg_miss_latency::total 14243.112349 # average overall miss latency 1082system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency 1083system.cpu0.icache.overall_avg_miss_latency::total 14243.112349 # average overall miss latency |
| 1170system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1171system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1172system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1173system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1174system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1175system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1176system.cpu0.icache.fast_writes 0 # number of fast writes performed 1177system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1084system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1085system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1086system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1087system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1088system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1089system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1090system.cpu0.icache.fast_writes 0 # number of fast writes performed 1091system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1178system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697766 # number of ReadReq MSHR misses 1179system.cpu0.icache.ReadReq_mshr_misses::total 697766 # number of ReadReq MSHR misses 1180system.cpu0.icache.demand_mshr_misses::cpu0.inst 697766 # number of demand (read+write) MSHR misses 1181system.cpu0.icache.demand_mshr_misses::total 697766 # number of demand (read+write) MSHR misses 1182system.cpu0.icache.overall_mshr_misses::cpu0.inst 697766 # number of overall MSHR misses 1183system.cpu0.icache.overall_mshr_misses::total 697766 # number of overall MSHR misses 1184system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8583721995 # number of ReadReq MSHR miss cycles 1185system.cpu0.icache.ReadReq_mshr_miss_latency::total 8583721995 # number of ReadReq MSHR miss cycles 1186system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8583721995 # number of demand (read+write) MSHR miss cycles 1187system.cpu0.icache.demand_mshr_miss_latency::total 8583721995 # number of demand (read+write) MSHR miss cycles 1188system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8583721995 # number of overall MSHR miss cycles 1189system.cpu0.icache.overall_mshr_miss_latency::total 8583721995 # number of overall MSHR miss cycles 1190system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for ReadReq accesses 1191system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses 1192system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for demand accesses 1193system.cpu0.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses 1194system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for overall accesses 1195system.cpu0.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses 1196system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average ReadReq mshr miss latency 1197system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12301.720054 # average ReadReq mshr miss latency 1198system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency 1199system.cpu0.icache.demand_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency 1200system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency 1201system.cpu0.icache.overall_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency | 1092system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703904 # number of ReadReq MSHR misses 1093system.cpu0.icache.ReadReq_mshr_misses::total 703904 # number of ReadReq MSHR misses 1094system.cpu0.icache.demand_mshr_misses::cpu0.inst 703904 # number of demand (read+write) MSHR misses 1095system.cpu0.icache.demand_mshr_misses::total 703904 # number of demand (read+write) MSHR misses 1096system.cpu0.icache.overall_mshr_misses::cpu0.inst 703904 # number of overall MSHR misses 1097system.cpu0.icache.overall_mshr_misses::total 703904 # number of overall MSHR misses 1098system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8612997245 # number of ReadReq MSHR miss cycles 1099system.cpu0.icache.ReadReq_mshr_miss_latency::total 8612997245 # number of ReadReq MSHR miss cycles 1100system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8612997245 # number of demand (read+write) MSHR miss cycles 1101system.cpu0.icache.demand_mshr_miss_latency::total 8612997245 # number of demand (read+write) MSHR miss cycles 1102system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8612997245 # number of overall MSHR miss cycles 1103system.cpu0.icache.overall_mshr_miss_latency::total 8612997245 # number of overall MSHR miss cycles 1104system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for ReadReq accesses 1105system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014623 # mshr miss rate for ReadReq accesses 1106system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for demand accesses 1107system.cpu0.icache.demand_mshr_miss_rate::total 0.014623 # mshr miss rate for demand accesses 1108system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for overall accesses 1109system.cpu0.icache.overall_mshr_miss_rate::total 0.014623 # mshr miss rate for overall accesses 1110system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average ReadReq mshr miss latency 1111system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12236.039638 # average ReadReq mshr miss latency 1112system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency 1113system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency 1114system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency 1115system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency |
| 1202system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1116system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1203system.cpu0.dcache.tags.replacements 1186229 # number of replacements 1204system.cpu0.dcache.tags.tagsinuse 505.271614 # Cycle average of tags in use 1205system.cpu0.dcache.tags.total_refs 11460994 # Total number of references to valid blocks. 1206system.cpu0.dcache.tags.sampled_refs 1186741 # Sample count of references to valid blocks. 1207system.cpu0.dcache.tags.avg_refs 9.657536 # Average number of references to valid blocks. 1208system.cpu0.dcache.tags.warmup_cycle 107902250 # Cycle when the warmup percentage was hit. 1209system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # Average occupied blocks per requestor 1210system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986859 # Average percentage of cache occupancy 1211system.cpu0.dcache.tags.occ_percent::total 0.986859 # Average percentage of cache occupancy | 1117system.cpu0.dcache.tags.replacements 1191290 # number of replacements 1118system.cpu0.dcache.tags.tagsinuse 505.228160 # Cycle average of tags in use 1119system.cpu0.dcache.tags.total_refs 11513399 # Total number of references to valid blocks. 1120system.cpu0.dcache.tags.sampled_refs 1191802 # Sample count of references to valid blocks. 1121system.cpu0.dcache.tags.avg_refs 9.660496 # Average number of references to valid blocks. 1122system.cpu0.dcache.tags.warmup_cycle 108508250 # Cycle when the warmup percentage was hit. 1123system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.228160 # Average occupied blocks per requestor 1124system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986774 # Average percentage of cache occupancy 1125system.cpu0.dcache.tags.occ_percent::total 0.986774 # Average percentage of cache occupancy |
| 1212system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1213system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 1214system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 1215system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1216system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1126system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1127system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 1128system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 1129system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 1130system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1217system.cpu0.dcache.tags.tag_accesses 51851796 # Number of tag accesses 1218system.cpu0.dcache.tags.data_accesses 51851796 # Number of data accesses 1219system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits 1220system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits 1221system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits 1222system.cpu0.dcache.WriteReq_hits::total 4706856 # number of WriteReq hits 1223system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140512 # number of LoadLockedReq hits 1224system.cpu0.dcache.LoadLockedReq_hits::total 140512 # number of LoadLockedReq hits 1225system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148003 # number of StoreCondReq hits 1226system.cpu0.dcache.StoreCondReq_hits::total 148003 # number of StoreCondReq hits 1227system.cpu0.dcache.demand_hits::cpu0.data 11158591 # number of demand (read+write) hits 1228system.cpu0.dcache.demand_hits::total 11158591 # number of demand (read+write) hits 1229system.cpu0.dcache.overall_hits::cpu0.data 11158591 # number of overall hits 1230system.cpu0.dcache.overall_hits::total 11158591 # number of overall hits 1231system.cpu0.dcache.ReadReq_misses::cpu0.data 939483 # number of ReadReq misses 1232system.cpu0.dcache.ReadReq_misses::total 939483 # number of ReadReq misses 1233system.cpu0.dcache.WriteReq_misses::cpu0.data 256736 # number of WriteReq misses 1234system.cpu0.dcache.WriteReq_misses::total 256736 # number of WriteReq misses 1235system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13633 # number of LoadLockedReq misses 1236system.cpu0.dcache.LoadLockedReq_misses::total 13633 # number of LoadLockedReq misses 1237system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5600 # number of StoreCondReq misses 1238system.cpu0.dcache.StoreCondReq_misses::total 5600 # number of StoreCondReq misses 1239system.cpu0.dcache.demand_misses::cpu0.data 1196219 # number of demand (read+write) misses 1240system.cpu0.dcache.demand_misses::total 1196219 # number of demand (read+write) misses 1241system.cpu0.dcache.overall_misses::cpu0.data 1196219 # number of overall misses 1242system.cpu0.dcache.overall_misses::total 1196219 # number of overall misses 1243system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27076055500 # number of ReadReq miss cycles 1244system.cpu0.dcache.ReadReq_miss_latency::total 27076055500 # number of ReadReq miss cycles 1245system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10459807694 # number of WriteReq miss cycles 1246system.cpu0.dcache.WriteReq_miss_latency::total 10459807694 # number of WriteReq miss cycles 1247system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148332750 # number of LoadLockedReq miss cycles 1248system.cpu0.dcache.LoadLockedReq_miss_latency::total 148332750 # number of LoadLockedReq miss cycles 1249system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43345419 # number of StoreCondReq miss cycles 1250system.cpu0.dcache.StoreCondReq_miss_latency::total 43345419 # number of StoreCondReq miss cycles 1251system.cpu0.dcache.demand_miss_latency::cpu0.data 37535863194 # number of demand (read+write) miss cycles 1252system.cpu0.dcache.demand_miss_latency::total 37535863194 # number of demand (read+write) miss cycles 1253system.cpu0.dcache.overall_miss_latency::cpu0.data 37535863194 # number of overall miss cycles 1254system.cpu0.dcache.overall_miss_latency::total 37535863194 # number of overall miss cycles 1255system.cpu0.dcache.ReadReq_accesses::cpu0.data 7391218 # number of ReadReq accesses(hits+misses) 1256system.cpu0.dcache.ReadReq_accesses::total 7391218 # number of ReadReq accesses(hits+misses) 1257system.cpu0.dcache.WriteReq_accesses::cpu0.data 4963592 # number of WriteReq accesses(hits+misses) 1258system.cpu0.dcache.WriteReq_accesses::total 4963592 # number of WriteReq accesses(hits+misses) 1259system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154145 # number of LoadLockedReq accesses(hits+misses) 1260system.cpu0.dcache.LoadLockedReq_accesses::total 154145 # number of LoadLockedReq accesses(hits+misses) 1261system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153603 # number of StoreCondReq accesses(hits+misses) 1262system.cpu0.dcache.StoreCondReq_accesses::total 153603 # number of StoreCondReq accesses(hits+misses) 1263system.cpu0.dcache.demand_accesses::cpu0.data 12354810 # number of demand (read+write) accesses 1264system.cpu0.dcache.demand_accesses::total 12354810 # number of demand (read+write) accesses 1265system.cpu0.dcache.overall_accesses::cpu0.data 12354810 # number of overall (read+write) accesses 1266system.cpu0.dcache.overall_accesses::total 12354810 # number of overall (read+write) accesses 1267system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127108 # miss rate for ReadReq accesses 1268system.cpu0.dcache.ReadReq_miss_rate::total 0.127108 # miss rate for ReadReq accesses 1269system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051724 # miss rate for WriteReq accesses 1270system.cpu0.dcache.WriteReq_miss_rate::total 0.051724 # miss rate for WriteReq accesses 1271system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088443 # miss rate for LoadLockedReq accesses 1272system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088443 # miss rate for LoadLockedReq accesses 1273system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036458 # miss rate for StoreCondReq accesses 1274system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036458 # miss rate for StoreCondReq accesses 1275system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096822 # miss rate for demand accesses 1276system.cpu0.dcache.demand_miss_rate::total 0.096822 # miss rate for demand accesses 1277system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096822 # miss rate for overall accesses 1278system.cpu0.dcache.overall_miss_rate::total 0.096822 # miss rate for overall accesses 1279system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28820.165453 # average ReadReq miss latency 1280system.cpu0.dcache.ReadReq_avg_miss_latency::total 28820.165453 # average ReadReq miss latency 1281system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40741.492015 # average WriteReq miss latency 1282system.cpu0.dcache.WriteReq_avg_miss_latency::total 40741.492015 # average WriteReq miss latency 1283system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10880.418837 # average LoadLockedReq miss latency 1284system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10880.418837 # average LoadLockedReq miss latency 1285system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7740.253393 # average StoreCondReq miss latency 1286system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7740.253393 # average StoreCondReq miss latency 1287system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency 1288system.cpu0.dcache.demand_avg_miss_latency::total 31378.755223 # average overall miss latency 1289system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency 1290system.cpu0.dcache.overall_avg_miss_latency::total 31378.755223 # average overall miss latency | 1131system.cpu0.dcache.tags.tag_accesses 52084916 # Number of tag accesses 1132system.cpu0.dcache.tags.data_accesses 52084916 # Number of data accesses 1133system.cpu0.dcache.ReadReq_hits::cpu0.data 6477391 # number of ReadReq hits 1134system.cpu0.dcache.ReadReq_hits::total 6477391 # number of ReadReq hits 1135system.cpu0.dcache.WriteReq_hits::cpu0.data 4731575 # number of WriteReq hits 1136system.cpu0.dcache.WriteReq_hits::total 4731575 # number of WriteReq hits 1137system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141550 # number of LoadLockedReq hits 1138system.cpu0.dcache.LoadLockedReq_hits::total 141550 # number of LoadLockedReq hits 1139system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149263 # number of StoreCondReq hits 1140system.cpu0.dcache.StoreCondReq_hits::total 149263 # number of StoreCondReq hits 1141system.cpu0.dcache.demand_hits::cpu0.data 11208966 # number of demand (read+write) hits 1142system.cpu0.dcache.demand_hits::total 11208966 # number of demand (read+write) hits 1143system.cpu0.dcache.overall_hits::cpu0.data 11208966 # number of overall hits 1144system.cpu0.dcache.overall_hits::total 11208966 # number of overall hits 1145system.cpu0.dcache.ReadReq_misses::cpu0.data 942691 # number of ReadReq misses 1146system.cpu0.dcache.ReadReq_misses::total 942691 # number of ReadReq misses 1147system.cpu0.dcache.WriteReq_misses::cpu0.data 258024 # number of WriteReq misses 1148system.cpu0.dcache.WriteReq_misses::total 258024 # number of WriteReq misses 1149system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13717 # number of LoadLockedReq misses 1150system.cpu0.dcache.LoadLockedReq_misses::total 13717 # number of LoadLockedReq misses 1151system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses 1152system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses 1153system.cpu0.dcache.demand_misses::cpu0.data 1200715 # number of demand (read+write) misses 1154system.cpu0.dcache.demand_misses::total 1200715 # number of demand (read+write) misses 1155system.cpu0.dcache.overall_misses::cpu0.data 1200715 # number of overall misses 1156system.cpu0.dcache.overall_misses::total 1200715 # number of overall misses 1157system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27259981257 # number of ReadReq miss cycles 1158system.cpu0.dcache.ReadReq_miss_latency::total 27259981257 # number of ReadReq miss cycles 1159system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10282729939 # number of WriteReq miss cycles 1160system.cpu0.dcache.WriteReq_miss_latency::total 10282729939 # number of WriteReq miss cycles 1161system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150891500 # number of LoadLockedReq miss cycles 1162system.cpu0.dcache.LoadLockedReq_miss_latency::total 150891500 # number of LoadLockedReq miss cycles 1163system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41989388 # number of StoreCondReq miss cycles 1164system.cpu0.dcache.StoreCondReq_miss_latency::total 41989388 # number of StoreCondReq miss cycles 1165system.cpu0.dcache.demand_miss_latency::cpu0.data 37542711196 # number of demand (read+write) miss cycles 1166system.cpu0.dcache.demand_miss_latency::total 37542711196 # number of demand (read+write) miss cycles 1167system.cpu0.dcache.overall_miss_latency::cpu0.data 37542711196 # number of overall miss cycles 1168system.cpu0.dcache.overall_miss_latency::total 37542711196 # number of overall miss cycles 1169system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420082 # number of ReadReq accesses(hits+misses) 1170system.cpu0.dcache.ReadReq_accesses::total 7420082 # number of ReadReq accesses(hits+misses) 1171system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989599 # number of WriteReq accesses(hits+misses) 1172system.cpu0.dcache.WriteReq_accesses::total 4989599 # number of WriteReq accesses(hits+misses) 1173system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155267 # number of LoadLockedReq accesses(hits+misses) 1174system.cpu0.dcache.LoadLockedReq_accesses::total 155267 # number of LoadLockedReq accesses(hits+misses) 1175system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154715 # number of StoreCondReq accesses(hits+misses) 1176system.cpu0.dcache.StoreCondReq_accesses::total 154715 # number of StoreCondReq accesses(hits+misses) 1177system.cpu0.dcache.demand_accesses::cpu0.data 12409681 # number of demand (read+write) accesses 1178system.cpu0.dcache.demand_accesses::total 12409681 # number of demand (read+write) accesses 1179system.cpu0.dcache.overall_accesses::cpu0.data 12409681 # number of overall (read+write) accesses 1180system.cpu0.dcache.overall_accesses::total 12409681 # number of overall (read+write) accesses 1181system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127046 # miss rate for ReadReq accesses 1182system.cpu0.dcache.ReadReq_miss_rate::total 0.127046 # miss rate for ReadReq accesses 1183system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051712 # miss rate for WriteReq accesses 1184system.cpu0.dcache.WriteReq_miss_rate::total 0.051712 # miss rate for WriteReq accesses 1185system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088345 # miss rate for LoadLockedReq accesses 1186system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088345 # miss rate for LoadLockedReq accesses 1187system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035239 # miss rate for StoreCondReq accesses 1188system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035239 # miss rate for StoreCondReq accesses 1189system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096756 # miss rate for demand accesses 1190system.cpu0.dcache.demand_miss_rate::total 0.096756 # miss rate for demand accesses 1191system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096756 # miss rate for overall accesses 1192system.cpu0.dcache.overall_miss_rate::total 0.096756 # miss rate for overall accesses 1193system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894 # average ReadReq miss latency 1194system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894 # average ReadReq miss latency 1195system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252 # average WriteReq miss latency 1196system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252 # average WriteReq miss latency 1197system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060 # average LoadLockedReq miss latency 1198system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060 # average LoadLockedReq miss latency 1199system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7701.648569 # average StoreCondReq miss latency 1200system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7701.648569 # average StoreCondReq miss latency 1201system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency 1202system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765 # average overall miss latency 1203system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency 1204system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765 # average overall miss latency |
| 1291system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1292system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1293system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1294system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1295system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1296system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1297system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1298system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 1205system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1206system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1207system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1208system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1209system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1210system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1211system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1212system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1299system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks 1300system.cpu0.dcache.writebacks::total 682519 # number of writebacks 1301system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses 1302system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses 1303system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses 1304system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses 1305system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses 1306system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses 1307system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses 1308system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses 1309system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses 1310system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses 1311system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses 1312system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses 1313system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles 1314system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles 1315system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles 1316system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles 1317system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles 1318system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles 1319system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles 1320system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles 1321system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 1322system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1323system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles 1324system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles 1325system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles 1326system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles | 1213system.cpu0.dcache.writebacks::writebacks 686471 # number of writebacks 1214system.cpu0.dcache.writebacks::total 686471 # number of writebacks 1215system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942691 # number of ReadReq MSHR misses 1216system.cpu0.dcache.ReadReq_mshr_misses::total 942691 # number of ReadReq MSHR misses 1217system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258024 # number of WriteReq MSHR misses 1218system.cpu0.dcache.WriteReq_mshr_misses::total 258024 # number of WriteReq MSHR misses 1219system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13717 # number of LoadLockedReq MSHR misses 1220system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13717 # number of LoadLockedReq MSHR misses 1221system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses 1222system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses 1223system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200715 # number of demand (read+write) MSHR misses 1224system.cpu0.dcache.demand_mshr_misses::total 1200715 # number of demand (read+write) MSHR misses 1225system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200715 # number of overall MSHR misses 1226system.cpu0.dcache.overall_mshr_misses::total 1200715 # number of overall MSHR misses 1227system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25249299743 # number of ReadReq MSHR miss cycles 1228system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25249299743 # number of ReadReq MSHR miss cycles 1229system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9714288061 # number of WriteReq MSHR miss cycles 1230system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9714288061 # number of WriteReq MSHR miss cycles 1231system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 123443500 # number of LoadLockedReq MSHR miss cycles 1232system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 123443500 # number of LoadLockedReq MSHR miss cycles 1233system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31083612 # number of StoreCondReq MSHR miss cycles 1234system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31083612 # number of StoreCondReq MSHR miss cycles 1235system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34963587804 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.dcache.demand_mshr_miss_latency::total 34963587804 # number of demand (read+write) MSHR miss cycles 1237system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34963587804 # number of overall MSHR miss cycles 1238system.cpu0.dcache.overall_mshr_miss_latency::total 34963587804 # number of overall MSHR miss cycles |
| 1327system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles 1328system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles | 1239system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles 1240system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles |
| 1329system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles 1330system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles 1331system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles 1332system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles 1333system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses 1334system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses 1335system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses 1336system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses 1337system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses 1338system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses 1339system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses 1340system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses 1341system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses 1342system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses 1343system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses 1344system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses 1345system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency 1346system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency 1347system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency 1348system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency 1349system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency 1350system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency 1351system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency 1352system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency 1353system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1354system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1355system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency 1356system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency 1357system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency 1358system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency | 1241system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2280051500 # number of WriteReq MSHR uncacheable cycles 1242system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2280051500 # number of WriteReq MSHR uncacheable cycles 1243system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3745653500 # number of overall MSHR uncacheable cycles 1244system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3745653500 # number of overall MSHR uncacheable cycles 1245system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127046 # mshr miss rate for ReadReq accesses 1246system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127046 # mshr miss rate for ReadReq accesses 1247system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051712 # mshr miss rate for WriteReq accesses 1248system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051712 # mshr miss rate for WriteReq accesses 1249system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088345 # mshr miss rate for LoadLockedReq accesses 1250system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088345 # mshr miss rate for LoadLockedReq accesses 1251system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035239 # mshr miss rate for StoreCondReq accesses 1252system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035239 # mshr miss rate for StoreCondReq accesses 1253system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for demand accesses 1254system.cpu0.dcache.demand_mshr_miss_rate::total 0.096756 # mshr miss rate for demand accesses 1255system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for overall accesses 1256system.cpu0.dcache.overall_mshr_miss_rate::total 0.096756 # mshr miss rate for overall accesses 1257system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26784.280048 # average ReadReq mshr miss latency 1258system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26784.280048 # average ReadReq mshr miss latency 1259system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37648.777094 # average WriteReq mshr miss latency 1260system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37648.777094 # average WriteReq mshr miss latency 1261system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8999.307429 # average LoadLockedReq mshr miss latency 1262system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8999.307429 # average LoadLockedReq mshr miss latency 1263system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5701.322817 # average StoreCondReq mshr miss latency 1264system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5701.322817 # average StoreCondReq mshr miss latency 1265system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency 1266system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency 1267system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency 1268system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency |
| 1359system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1360system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1361system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1362system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1363system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1364system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1365system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1366system.cpu1.dtb.fetch_hits 0 # ITB hits 1367system.cpu1.dtb.fetch_misses 0 # ITB misses 1368system.cpu1.dtb.fetch_acv 0 # ITB acv 1369system.cpu1.dtb.fetch_accesses 0 # ITB accesses | 1269system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1270system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1271system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1272system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1273system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1274system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1275system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1276system.cpu1.dtb.fetch_hits 0 # ITB hits 1277system.cpu1.dtb.fetch_misses 0 # ITB misses 1278system.cpu1.dtb.fetch_acv 0 # ITB acv 1279system.cpu1.dtb.fetch_accesses 0 # ITB accesses |
| 1370system.cpu1.dtb.read_hits 2383442 # DTB read hits | 1280system.cpu1.dtb.read_hits 2348422 # DTB read hits |
| 1371system.cpu1.dtb.read_misses 2620 # DTB read misses 1372system.cpu1.dtb.read_acv 0 # DTB read access violations 1373system.cpu1.dtb.read_accesses 205337 # DTB read accesses | 1281system.cpu1.dtb.read_misses 2620 # DTB read misses 1282system.cpu1.dtb.read_acv 0 # DTB read access violations 1283system.cpu1.dtb.read_accesses 205337 # DTB read accesses |
| 1374system.cpu1.dtb.write_hits 1706844 # DTB write hits | 1284system.cpu1.dtb.write_hits 1677006 # DTB write hits |
| 1375system.cpu1.dtb.write_misses 235 # DTB write misses 1376system.cpu1.dtb.write_acv 24 # DTB write access violations 1377system.cpu1.dtb.write_accesses 89739 # DTB write accesses | 1285system.cpu1.dtb.write_misses 235 # DTB write misses 1286system.cpu1.dtb.write_acv 24 # DTB write access violations 1287system.cpu1.dtb.write_accesses 89739 # DTB write accesses |
| 1378system.cpu1.dtb.data_hits 4090286 # DTB hits | 1288system.cpu1.dtb.data_hits 4025428 # DTB hits |
| 1379system.cpu1.dtb.data_misses 2855 # DTB misses 1380system.cpu1.dtb.data_acv 24 # DTB access violations 1381system.cpu1.dtb.data_accesses 295076 # DTB accesses | 1289system.cpu1.dtb.data_misses 2855 # DTB misses 1290system.cpu1.dtb.data_acv 24 # DTB access violations 1291system.cpu1.dtb.data_accesses 295076 # DTB accesses |
| 1382system.cpu1.itb.fetch_hits 1814139 # ITB hits | 1292system.cpu1.itb.fetch_hits 1801062 # ITB hits |
| 1383system.cpu1.itb.fetch_misses 1064 # ITB misses 1384system.cpu1.itb.fetch_acv 0 # ITB acv | 1293system.cpu1.itb.fetch_misses 1064 # ITB misses 1294system.cpu1.itb.fetch_acv 0 # ITB acv |
| 1385system.cpu1.itb.fetch_accesses 1815203 # ITB accesses | 1295system.cpu1.itb.fetch_accesses 1802126 # ITB accesses |
| 1386system.cpu1.itb.read_hits 0 # DTB read hits 1387system.cpu1.itb.read_misses 0 # DTB read misses 1388system.cpu1.itb.read_acv 0 # DTB read access violations 1389system.cpu1.itb.read_accesses 0 # DTB read accesses 1390system.cpu1.itb.write_hits 0 # DTB write hits 1391system.cpu1.itb.write_misses 0 # DTB write misses 1392system.cpu1.itb.write_acv 0 # DTB write access violations 1393system.cpu1.itb.write_accesses 0 # DTB write accesses 1394system.cpu1.itb.data_hits 0 # DTB hits 1395system.cpu1.itb.data_misses 0 # DTB misses 1396system.cpu1.itb.data_acv 0 # DTB access violations 1397system.cpu1.itb.data_accesses 0 # DTB accesses | 1296system.cpu1.itb.read_hits 0 # DTB read hits 1297system.cpu1.itb.read_misses 0 # DTB read misses 1298system.cpu1.itb.read_acv 0 # DTB read access violations 1299system.cpu1.itb.read_accesses 0 # DTB read accesses 1300system.cpu1.itb.write_hits 0 # DTB write hits 1301system.cpu1.itb.write_misses 0 # DTB write misses 1302system.cpu1.itb.write_acv 0 # DTB write access violations 1303system.cpu1.itb.write_accesses 0 # DTB write accesses 1304system.cpu1.itb.data_hits 0 # DTB hits 1305system.cpu1.itb.data_misses 0 # DTB misses 1306system.cpu1.itb.data_acv 0 # DTB access violations 1307system.cpu1.itb.data_accesses 0 # DTB accesses |
| 1398system.cpu1.numCycles 3919927793 # number of cpu cycles simulated | 1308system.cpu1.numCycles 3921881188 # number of cpu cycles simulated |
| 1399system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1400system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1309system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1310system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1401system.cpu1.committedInsts 12950293 # Number of instructions committed 1402system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed 1403system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses 1404system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses 1405system.cpu1.num_func_calls 410658 # number of times a function call or return occured 1406system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls 1407system.cpu1.num_int_insts 11929999 # number of integer instructions 1408system.cpu1.num_fp_insts 174217 # number of float instructions 1409system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read 1410system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written 1411system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read 1412system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written 1413system.cpu1.num_mem_refs 4113222 # number of memory refs 1414system.cpu1.num_load_insts 2397194 # Number of load instructions 1415system.cpu1.num_store_insts 1716028 # Number of store instructions 1416system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles 1417system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles 1418system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles 1419system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles 1420system.cpu1.Branches 1846576 # Number of branches fetched | 1311system.cpu1.committedInsts 12764983 # Number of instructions committed 1312system.cpu1.committedOps 12764983 # Number of ops (including micro ops) committed 1313system.cpu1.num_int_alu_accesses 11763372 # Number of integer alu accesses 1314system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses 1315system.cpu1.num_func_calls 404056 # number of times a function call or return occured 1316system.cpu1.num_conditional_control_insts 1265589 # number of instructions that are conditional controls 1317system.cpu1.num_int_insts 11763372 # number of integer instructions 1318system.cpu1.num_fp_insts 170364 # number of float instructions 1319system.cpu1.num_int_register_reads 16177579 # number of times the integer registers were read 1320system.cpu1.num_int_register_writes 8656447 # number of times the integer registers were written 1321system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read 1322system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written 1323system.cpu1.num_mem_refs 4047975 # number of memory refs 1324system.cpu1.num_load_insts 2361944 # Number of load instructions 1325system.cpu1.num_store_insts 1686031 # Number of store instructions 1326system.cpu1.num_idle_cycles 3873256564.808130 # Number of idle cycles 1327system.cpu1.num_busy_cycles 48624623.191870 # Number of busy cycles 1328system.cpu1.not_idle_fraction 0.012398 # Percentage of non-idle cycles 1329system.cpu1.idle_fraction 0.987602 # Percentage of idle cycles 1330system.cpu1.Branches 1821589 # Number of branches fetched |
| 1421system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1331system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1422system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed 1423system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed 1424system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl 1425system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl 1426system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl 1427system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl 1428system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl 1429system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl 1430system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl 1431system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl 1432system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl 1433system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl 1434system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl 1435system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl 1436system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl 1437system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl 1438system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl 1439system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl | 1332system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed 1333system.cpu1.kern.inst.hwrei 77081 # number of hwrei instructions executed 1334system.cpu1.kern.ipl_count::0 26132 38.19% 38.19% # number of times we switched to this ipl 1335system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl 1336system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl 1337system.cpu1.kern.ipl_count::31 39821 58.19% 100.00% # number of times we switched to this ipl 1338system.cpu1.kern.ipl_count::total 68428 # number of times we switched to this ipl 1339system.cpu1.kern.ipl_good::0 25288 48.13% 48.13% # number of times we switched to this ipl from a different ipl 1340system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl 1341system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl 1342system.cpu1.kern.ipl_good::31 24782 47.16% 100.00% # number of times we switched to this ipl from a different ipl 1343system.cpu1.kern.ipl_good::total 52545 # number of times we switched to this ipl from a different ipl 1344system.cpu1.kern.ipl_ticks::0 1909614205500 97.38% 97.38% # number of cycles we spent at this ipl 1345system.cpu1.kern.ipl_ticks::22 700881500 0.04% 97.42% # number of cycles we spent at this ipl 1346system.cpu1.kern.ipl_ticks::30 353850000 0.02% 97.44% # number of cycles we spent at this ipl 1347system.cpu1.kern.ipl_ticks::31 50271627000 2.56% 100.00% # number of cycles we spent at this ipl 1348system.cpu1.kern.ipl_ticks::total 1960940564000 # number of cycles we spent at this ipl 1349system.cpu1.kern.ipl_used::0 0.967702 # fraction of swpipl calls that actually changed the ipl |
| 1440system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1441system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl | 1350system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1351system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl |
| 1442system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl 1443system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl | 1352system.cpu1.kern.ipl_used::31 0.622335 # fraction of swpipl calls that actually changed the ipl 1353system.cpu1.kern.ipl_used::total 0.767887 # fraction of swpipl calls that actually changed the ipl |
| 1444system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 1445system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 1446system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 1447system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 1448system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 1449system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 1450system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 1451system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 1452system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 1453system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 1454system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 1455system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 1456system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 1457system.cpu1.kern.syscall::total 92 # number of syscalls executed 1458system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed | 1354system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed 1355system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed 1356system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed 1357system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed 1358system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed 1359system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed 1360system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed 1361system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed 1362system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed 1363system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed 1364system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed 1365system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed 1366system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed 1367system.cpu1.kern.syscall::total 92 # number of syscalls executed 1368system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed |
| 1459system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed 1460system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed 1461system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed 1462system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed 1463system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed 1464system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed 1465system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed 1466system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed 1467system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed 1468system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed 1469system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed 1470system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed | 1369system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed 1370system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed 1371system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed 1372system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed 1373system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed 1374system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed 1375system.cpu1.kern.callpal::swpipl 62267 88.12% 91.51% # number of callpals executed 1376system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed 1377system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed 1378system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed 1379system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed 1380system.cpu1.kern.callpal::rti 3685 5.22% 99.77% # number of callpals executed |
| 1471system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed 1472system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed 1473system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed | 1381system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed 1382system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed 1383system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed |
| 1474system.cpu1.kern.callpal::total 71838 # number of callpals executed 1475system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches | 1384system.cpu1.kern.callpal::total 70661 # number of callpals executed 1385system.cpu1.kern.mode_switch::kernel 1917 # number of protection mode switches |
| 1476system.cpu1.kern.mode_switch::user 368 # number of protection mode switches | 1386system.cpu1.kern.mode_switch::user 368 # number of protection mode switches |
| 1477system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches 1478system.cpu1.kern.mode_good::kernel 809 | 1387system.cpu1.kern.mode_switch::idle 2889 # number of protection mode switches 1388system.cpu1.kern.mode_good::kernel 798 |
| 1479system.cpu1.kern.mode_good::user 368 | 1389system.cpu1.kern.mode_good::user 368 |
| 1480system.cpu1.kern.mode_good::idle 441 1481system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches | 1390system.cpu1.kern.mode_good::idle 430 1391system.cpu1.kern.mode_switch_good::kernel 0.416275 # fraction of useful protection mode switches |
| 1482system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 1392system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 1483system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches 1484system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches 1485system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode 1486system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode 1487system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode 1488system.cpu1.kern.swap_context 2002 # number of times the context was actually changed 1489system.cpu1.icache.tags.replacements 317336 # number of replacements 1490system.cpu1.icache.tags.tagsinuse 446.450379 # Cycle average of tags in use 1491system.cpu1.icache.tags.total_refs 12635285 # Total number of references to valid blocks. 1492system.cpu1.icache.tags.sampled_refs 317847 # Sample count of references to valid blocks. 1493system.cpu1.icache.tags.avg_refs 39.752727 # Average number of references to valid blocks. 1494system.cpu1.icache.tags.warmup_cycle 1958987590000 # Cycle when the warmup percentage was hit. 1495system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.450379 # Average occupied blocks per requestor 1496system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871973 # Average percentage of cache occupancy 1497system.cpu1.icache.tags.occ_percent::total 0.871973 # Average percentage of cache occupancy | 1393system.cpu1.kern.mode_switch_good::idle 0.148840 # fraction of useful protection mode switches 1394system.cpu1.kern.mode_switch_good::total 0.308465 # fraction of useful protection mode switches 1395system.cpu1.kern.mode_ticks::kernel 17543884000 0.90% 0.90% # number of ticks spent at the given mode 1396system.cpu1.kern.mode_ticks::user 1484004500 0.08% 0.97% # number of ticks spent at the given mode 1397system.cpu1.kern.mode_ticks::idle 1941017048000 99.03% 100.00% # number of ticks spent at the given mode 1398system.cpu1.kern.swap_context 1956 # number of times the context was actually changed 1399system.cpu1.icache.tags.replacements 311472 # number of replacements 1400system.cpu1.icache.tags.tagsinuse 449.263709 # Cycle average of tags in use 1401system.cpu1.icache.tags.total_refs 12455839 # Total number of references to valid blocks. 1402system.cpu1.icache.tags.sampled_refs 311983 # Sample count of references to valid blocks. 1403system.cpu1.icache.tags.avg_refs 39.924736 # Average number of references to valid blocks. 1404system.cpu1.icache.tags.warmup_cycle 1960006992500 # Cycle when the warmup percentage was hit. 1405system.cpu1.icache.tags.occ_blocks::cpu1.inst 449.263709 # Average occupied blocks per requestor 1406system.cpu1.icache.tags.occ_percent::cpu1.inst 0.877468 # Average percentage of cache occupancy 1407system.cpu1.icache.tags.occ_percent::total 0.877468 # Average percentage of cache occupancy |
| 1498system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id | 1408system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id |
| 1499system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 1500system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id | 1409system.cpu1.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id 1410system.cpu1.icache.tags.age_task_id_blocks_1024::3 437 # Occupied blocks per task id |
| 1501system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 1411system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 1502system.cpu1.icache.tags.tag_accesses 13271059 # Number of tag accesses 1503system.cpu1.icache.tags.data_accesses 13271059 # Number of data accesses 1504system.cpu1.icache.ReadReq_hits::cpu1.inst 12635285 # number of ReadReq hits 1505system.cpu1.icache.ReadReq_hits::total 12635285 # number of ReadReq hits 1506system.cpu1.icache.demand_hits::cpu1.inst 12635285 # number of demand (read+write) hits 1507system.cpu1.icache.demand_hits::total 12635285 # number of demand (read+write) hits 1508system.cpu1.icache.overall_hits::cpu1.inst 12635285 # number of overall hits 1509system.cpu1.icache.overall_hits::total 12635285 # number of overall hits 1510system.cpu1.icache.ReadReq_misses::cpu1.inst 317887 # number of ReadReq misses 1511system.cpu1.icache.ReadReq_misses::total 317887 # number of ReadReq misses 1512system.cpu1.icache.demand_misses::cpu1.inst 317887 # number of demand (read+write) misses 1513system.cpu1.icache.demand_misses::total 317887 # number of demand (read+write) misses 1514system.cpu1.icache.overall_misses::cpu1.inst 317887 # number of overall misses 1515system.cpu1.icache.overall_misses::total 317887 # number of overall misses 1516system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4180819492 # number of ReadReq miss cycles 1517system.cpu1.icache.ReadReq_miss_latency::total 4180819492 # number of ReadReq miss cycles 1518system.cpu1.icache.demand_miss_latency::cpu1.inst 4180819492 # number of demand (read+write) miss cycles 1519system.cpu1.icache.demand_miss_latency::total 4180819492 # number of demand (read+write) miss cycles 1520system.cpu1.icache.overall_miss_latency::cpu1.inst 4180819492 # number of overall miss cycles 1521system.cpu1.icache.overall_miss_latency::total 4180819492 # number of overall miss cycles 1522system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953172 # number of ReadReq accesses(hits+misses) 1523system.cpu1.icache.ReadReq_accesses::total 12953172 # number of ReadReq accesses(hits+misses) 1524system.cpu1.icache.demand_accesses::cpu1.inst 12953172 # number of demand (read+write) accesses 1525system.cpu1.icache.demand_accesses::total 12953172 # number of demand (read+write) accesses 1526system.cpu1.icache.overall_accesses::cpu1.inst 12953172 # number of overall (read+write) accesses 1527system.cpu1.icache.overall_accesses::total 12953172 # number of overall (read+write) accesses 1528system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024541 # miss rate for ReadReq accesses 1529system.cpu1.icache.ReadReq_miss_rate::total 0.024541 # miss rate for ReadReq accesses 1530system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024541 # miss rate for demand accesses 1531system.cpu1.icache.demand_miss_rate::total 0.024541 # miss rate for demand accesses 1532system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024541 # miss rate for overall accesses 1533system.cpu1.icache.overall_miss_rate::total 0.024541 # miss rate for overall accesses 1534system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13151.904582 # average ReadReq miss latency 1535system.cpu1.icache.ReadReq_avg_miss_latency::total 13151.904582 # average ReadReq miss latency 1536system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency 1537system.cpu1.icache.demand_avg_miss_latency::total 13151.904582 # average overall miss latency 1538system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency 1539system.cpu1.icache.overall_avg_miss_latency::total 13151.904582 # average overall miss latency | 1412system.cpu1.icache.tags.tag_accesses 13079885 # Number of tag accesses 1413system.cpu1.icache.tags.data_accesses 13079885 # Number of data accesses 1414system.cpu1.icache.ReadReq_hits::cpu1.inst 12455839 # number of ReadReq hits 1415system.cpu1.icache.ReadReq_hits::total 12455839 # number of ReadReq hits 1416system.cpu1.icache.demand_hits::cpu1.inst 12455839 # number of demand (read+write) hits 1417system.cpu1.icache.demand_hits::total 12455839 # number of demand (read+write) hits 1418system.cpu1.icache.overall_hits::cpu1.inst 12455839 # number of overall hits 1419system.cpu1.icache.overall_hits::total 12455839 # number of overall hits 1420system.cpu1.icache.ReadReq_misses::cpu1.inst 312023 # number of ReadReq misses 1421system.cpu1.icache.ReadReq_misses::total 312023 # number of ReadReq misses 1422system.cpu1.icache.demand_misses::cpu1.inst 312023 # number of demand (read+write) misses 1423system.cpu1.icache.demand_misses::total 312023 # number of demand (read+write) misses 1424system.cpu1.icache.overall_misses::cpu1.inst 312023 # number of overall misses 1425system.cpu1.icache.overall_misses::total 312023 # number of overall misses 1426system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4106650741 # number of ReadReq miss cycles 1427system.cpu1.icache.ReadReq_miss_latency::total 4106650741 # number of ReadReq miss cycles 1428system.cpu1.icache.demand_miss_latency::cpu1.inst 4106650741 # number of demand (read+write) miss cycles 1429system.cpu1.icache.demand_miss_latency::total 4106650741 # number of demand (read+write) miss cycles 1430system.cpu1.icache.overall_miss_latency::cpu1.inst 4106650741 # number of overall miss cycles 1431system.cpu1.icache.overall_miss_latency::total 4106650741 # number of overall miss cycles 1432system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767862 # number of ReadReq accesses(hits+misses) 1433system.cpu1.icache.ReadReq_accesses::total 12767862 # number of ReadReq accesses(hits+misses) 1434system.cpu1.icache.demand_accesses::cpu1.inst 12767862 # number of demand (read+write) accesses 1435system.cpu1.icache.demand_accesses::total 12767862 # number of demand (read+write) accesses 1436system.cpu1.icache.overall_accesses::cpu1.inst 12767862 # number of overall (read+write) accesses 1437system.cpu1.icache.overall_accesses::total 12767862 # number of overall (read+write) accesses 1438system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024438 # miss rate for ReadReq accesses 1439system.cpu1.icache.ReadReq_miss_rate::total 0.024438 # miss rate for ReadReq accesses 1440system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024438 # miss rate for demand accesses 1441system.cpu1.icache.demand_miss_rate::total 0.024438 # miss rate for demand accesses 1442system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024438 # miss rate for overall accesses 1443system.cpu1.icache.overall_miss_rate::total 0.024438 # miss rate for overall accesses 1444system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889 # average ReadReq miss latency 1445system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889 # average ReadReq miss latency 1446system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency 1447system.cpu1.icache.demand_avg_miss_latency::total 13161.371889 # average overall miss latency 1448system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency 1449system.cpu1.icache.overall_avg_miss_latency::total 13161.371889 # average overall miss latency |
| 1540system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1541system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1542system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1543system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1544system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1545system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1546system.cpu1.icache.fast_writes 0 # number of fast writes performed 1547system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1450system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1451system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1452system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1453system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1454system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1455system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1456system.cpu1.icache.fast_writes 0 # number of fast writes performed 1457system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1548system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317887 # number of ReadReq MSHR misses 1549system.cpu1.icache.ReadReq_mshr_misses::total 317887 # number of ReadReq MSHR misses 1550system.cpu1.icache.demand_mshr_misses::cpu1.inst 317887 # number of demand (read+write) MSHR misses 1551system.cpu1.icache.demand_mshr_misses::total 317887 # number of demand (read+write) MSHR misses 1552system.cpu1.icache.overall_mshr_misses::cpu1.inst 317887 # number of overall MSHR misses 1553system.cpu1.icache.overall_mshr_misses::total 317887 # number of overall MSHR misses 1554system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3544847508 # number of ReadReq MSHR miss cycles 1555system.cpu1.icache.ReadReq_mshr_miss_latency::total 3544847508 # number of ReadReq MSHR miss cycles 1556system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3544847508 # number of demand (read+write) MSHR miss cycles 1557system.cpu1.icache.demand_mshr_miss_latency::total 3544847508 # number of demand (read+write) MSHR miss cycles 1558system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3544847508 # number of overall MSHR miss cycles 1559system.cpu1.icache.overall_mshr_miss_latency::total 3544847508 # number of overall MSHR miss cycles 1560system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for ReadReq accesses 1561system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024541 # mshr miss rate for ReadReq accesses 1562system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for demand accesses 1563system.cpu1.icache.demand_mshr_miss_rate::total 0.024541 # mshr miss rate for demand accesses 1564system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for overall accesses 1565system.cpu1.icache.overall_mshr_miss_rate::total 0.024541 # mshr miss rate for overall accesses 1566system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average ReadReq mshr miss latency 1567system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11151.281770 # average ReadReq mshr miss latency 1568system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency 1569system.cpu1.icache.demand_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency 1570system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency 1571system.cpu1.icache.overall_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency | 1458system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312023 # number of ReadReq MSHR misses 1459system.cpu1.icache.ReadReq_mshr_misses::total 312023 # number of ReadReq MSHR misses 1460system.cpu1.icache.demand_mshr_misses::cpu1.inst 312023 # number of demand (read+write) MSHR misses 1461system.cpu1.icache.demand_mshr_misses::total 312023 # number of demand (read+write) MSHR misses 1462system.cpu1.icache.overall_mshr_misses::cpu1.inst 312023 # number of overall MSHR misses 1463system.cpu1.icache.overall_mshr_misses::total 312023 # number of overall MSHR misses 1464system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3482409259 # number of ReadReq MSHR miss cycles 1465system.cpu1.icache.ReadReq_mshr_miss_latency::total 3482409259 # number of ReadReq MSHR miss cycles 1466system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3482409259 # number of demand (read+write) MSHR miss cycles 1467system.cpu1.icache.demand_mshr_miss_latency::total 3482409259 # number of demand (read+write) MSHR miss cycles 1468system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3482409259 # number of overall MSHR miss cycles 1469system.cpu1.icache.overall_mshr_miss_latency::total 3482409259 # number of overall MSHR miss cycles 1470system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for ReadReq accesses 1471system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024438 # mshr miss rate for ReadReq accesses 1472system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for demand accesses 1473system.cpu1.icache.demand_mshr_miss_rate::total 0.024438 # mshr miss rate for demand accesses 1474system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for overall accesses 1475system.cpu1.icache.overall_mshr_miss_rate::total 0.024438 # mshr miss rate for overall accesses 1476system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average ReadReq mshr miss latency 1477system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11160.745391 # average ReadReq mshr miss latency 1478system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency 1479system.cpu1.icache.demand_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency 1480system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency 1481system.cpu1.icache.overall_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency |
| 1572system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1482system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1573system.cpu1.dcache.tags.replacements 158764 # number of replacements 1574system.cpu1.dcache.tags.tagsinuse 485.752776 # Cycle average of tags in use 1575system.cpu1.dcache.tags.total_refs 3916687 # Total number of references to valid blocks. 1576system.cpu1.dcache.tags.sampled_refs 159090 # Sample count of references to valid blocks. 1577system.cpu1.dcache.tags.avg_refs 24.619316 # Average number of references to valid blocks. 1578system.cpu1.dcache.tags.warmup_cycle 67802253000 # Cycle when the warmup percentage was hit. 1579system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.752776 # Average occupied blocks per requestor 1580system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948736 # Average percentage of cache occupancy 1581system.cpu1.dcache.tags.occ_percent::total 0.948736 # Average percentage of cache occupancy 1582system.cpu1.dcache.tags.occ_task_id_blocks::1024 326 # Occupied blocks per task id 1583system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id 1584system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id 1585system.cpu1.dcache.tags.occ_task_id_percent::1024 0.636719 # Percentage of cache occupancy per task id 1586system.cpu1.dcache.tags.tag_accesses 16587420 # Number of tag accesses 1587system.cpu1.dcache.tags.data_accesses 16587420 # Number of data accesses 1588system.cpu1.dcache.ReadReq_hits::cpu1.data 2220669 # number of ReadReq hits 1589system.cpu1.dcache.ReadReq_hits::total 2220669 # number of ReadReq hits 1590system.cpu1.dcache.WriteReq_hits::cpu1.data 1595283 # number of WriteReq hits 1591system.cpu1.dcache.WriteReq_hits::total 1595283 # number of WriteReq hits 1592system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48031 # number of LoadLockedReq hits 1593system.cpu1.dcache.LoadLockedReq_hits::total 48031 # number of LoadLockedReq hits 1594system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50613 # number of StoreCondReq hits 1595system.cpu1.dcache.StoreCondReq_hits::total 50613 # number of StoreCondReq hits 1596system.cpu1.dcache.demand_hits::cpu1.data 3815952 # number of demand (read+write) hits 1597system.cpu1.dcache.demand_hits::total 3815952 # number of demand (read+write) hits 1598system.cpu1.dcache.overall_hits::cpu1.data 3815952 # number of overall hits 1599system.cpu1.dcache.overall_hits::total 3815952 # number of overall hits 1600system.cpu1.dcache.ReadReq_misses::cpu1.data 116704 # number of ReadReq misses 1601system.cpu1.dcache.ReadReq_misses::total 116704 # number of ReadReq misses 1602system.cpu1.dcache.WriteReq_misses::cpu1.data 56889 # number of WriteReq misses 1603system.cpu1.dcache.WriteReq_misses::total 56889 # number of WriteReq misses 1604system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9081 # number of LoadLockedReq misses 1605system.cpu1.dcache.LoadLockedReq_misses::total 9081 # number of LoadLockedReq misses 1606system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6019 # number of StoreCondReq misses 1607system.cpu1.dcache.StoreCondReq_misses::total 6019 # number of StoreCondReq misses 1608system.cpu1.dcache.demand_misses::cpu1.data 173593 # number of demand (read+write) misses 1609system.cpu1.dcache.demand_misses::total 173593 # number of demand (read+write) misses 1610system.cpu1.dcache.overall_misses::cpu1.data 173593 # number of overall misses 1611system.cpu1.dcache.overall_misses::total 173593 # number of overall misses 1612system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1411486000 # number of ReadReq miss cycles 1613system.cpu1.dcache.ReadReq_miss_latency::total 1411486000 # number of ReadReq miss cycles 1614system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1044020804 # number of WriteReq miss cycles 1615system.cpu1.dcache.WriteReq_miss_latency::total 1044020804 # number of WriteReq miss cycles 1616system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82357000 # number of LoadLockedReq miss cycles 1617system.cpu1.dcache.LoadLockedReq_miss_latency::total 82357000 # number of LoadLockedReq miss cycles 1618system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44184927 # number of StoreCondReq miss cycles 1619system.cpu1.dcache.StoreCondReq_miss_latency::total 44184927 # number of StoreCondReq miss cycles 1620system.cpu1.dcache.demand_miss_latency::cpu1.data 2455506804 # number of demand (read+write) miss cycles 1621system.cpu1.dcache.demand_miss_latency::total 2455506804 # number of demand (read+write) miss cycles 1622system.cpu1.dcache.overall_miss_latency::cpu1.data 2455506804 # number of overall miss cycles 1623system.cpu1.dcache.overall_miss_latency::total 2455506804 # number of overall miss cycles 1624system.cpu1.dcache.ReadReq_accesses::cpu1.data 2337373 # number of ReadReq accesses(hits+misses) 1625system.cpu1.dcache.ReadReq_accesses::total 2337373 # number of ReadReq accesses(hits+misses) 1626system.cpu1.dcache.WriteReq_accesses::cpu1.data 1652172 # number of WriteReq accesses(hits+misses) 1627system.cpu1.dcache.WriteReq_accesses::total 1652172 # number of WriteReq accesses(hits+misses) 1628system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57112 # number of LoadLockedReq accesses(hits+misses) 1629system.cpu1.dcache.LoadLockedReq_accesses::total 57112 # number of LoadLockedReq accesses(hits+misses) 1630system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56632 # number of StoreCondReq accesses(hits+misses) 1631system.cpu1.dcache.StoreCondReq_accesses::total 56632 # number of StoreCondReq accesses(hits+misses) 1632system.cpu1.dcache.demand_accesses::cpu1.data 3989545 # number of demand (read+write) accesses 1633system.cpu1.dcache.demand_accesses::total 3989545 # number of demand (read+write) accesses 1634system.cpu1.dcache.overall_accesses::cpu1.data 3989545 # number of overall (read+write) accesses 1635system.cpu1.dcache.overall_accesses::total 3989545 # number of overall (read+write) accesses 1636system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049930 # miss rate for ReadReq accesses 1637system.cpu1.dcache.ReadReq_miss_rate::total 0.049930 # miss rate for ReadReq accesses 1638system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034433 # miss rate for WriteReq accesses 1639system.cpu1.dcache.WriteReq_miss_rate::total 0.034433 # miss rate for WriteReq accesses 1640system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159003 # miss rate for LoadLockedReq accesses 1641system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159003 # miss rate for LoadLockedReq accesses 1642system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106283 # miss rate for StoreCondReq accesses 1643system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106283 # miss rate for StoreCondReq accesses 1644system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043512 # miss rate for demand accesses 1645system.cpu1.dcache.demand_miss_rate::total 0.043512 # miss rate for demand accesses 1646system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043512 # miss rate for overall accesses 1647system.cpu1.dcache.overall_miss_rate::total 0.043512 # miss rate for overall accesses 1648system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12094.581163 # average ReadReq miss latency 1649system.cpu1.dcache.ReadReq_avg_miss_latency::total 12094.581163 # average ReadReq miss latency 1650system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18351.892352 # average WriteReq miss latency 1651system.cpu1.dcache.WriteReq_avg_miss_latency::total 18351.892352 # average WriteReq miss latency 1652system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9069.155379 # average LoadLockedReq miss latency 1653system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9069.155379 # average LoadLockedReq miss latency 1654system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7340.908290 # average StoreCondReq miss latency 1655system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7340.908290 # average StoreCondReq miss latency 1656system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency 1657system.cpu1.dcache.demand_avg_miss_latency::total 14145.194818 # average overall miss latency 1658system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency 1659system.cpu1.dcache.overall_avg_miss_latency::total 14145.194818 # average overall miss latency | 1483system.cpu1.dcache.tags.replacements 155135 # number of replacements 1484system.cpu1.dcache.tags.tagsinuse 486.308895 # Cycle average of tags in use 1485system.cpu1.dcache.tags.total_refs 3855441 # Total number of references to valid blocks. 1486system.cpu1.dcache.tags.sampled_refs 155464 # Sample count of references to valid blocks. 1487system.cpu1.dcache.tags.avg_refs 24.799574 # Average number of references to valid blocks. 1488system.cpu1.dcache.tags.warmup_cycle 1048852146500 # Cycle when the warmup percentage was hit. 1489system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308895 # Average occupied blocks per requestor 1490system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949822 # Average percentage of cache occupancy 1491system.cpu1.dcache.tags.occ_percent::total 0.949822 # Average percentage of cache occupancy 1492system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id 1493system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 1494system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id 1495system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id 1496system.cpu1.dcache.tags.tag_accesses 16322717 # Number of tag accesses 1497system.cpu1.dcache.tags.data_accesses 16322717 # Number of data accesses 1498system.cpu1.dcache.ReadReq_hits::cpu1.data 2189668 # number of ReadReq hits 1499system.cpu1.dcache.ReadReq_hits::total 2189668 # number of ReadReq hits 1500system.cpu1.dcache.WriteReq_hits::cpu1.data 1567568 # number of WriteReq hits 1501system.cpu1.dcache.WriteReq_hits::total 1567568 # number of WriteReq hits 1502system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46969 # number of LoadLockedReq hits 1503system.cpu1.dcache.LoadLockedReq_hits::total 46969 # number of LoadLockedReq hits 1504system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49480 # number of StoreCondReq hits 1505system.cpu1.dcache.StoreCondReq_hits::total 49480 # number of StoreCondReq hits 1506system.cpu1.dcache.demand_hits::cpu1.data 3757236 # number of demand (read+write) hits 1507system.cpu1.dcache.demand_hits::total 3757236 # number of demand (read+write) hits 1508system.cpu1.dcache.overall_hits::cpu1.data 3757236 # number of overall hits 1509system.cpu1.dcache.overall_hits::total 3757236 # number of overall hits 1510system.cpu1.dcache.ReadReq_misses::cpu1.data 113735 # number of ReadReq misses 1511system.cpu1.dcache.ReadReq_misses::total 113735 # number of ReadReq misses 1512system.cpu1.dcache.WriteReq_misses::cpu1.data 55930 # number of WriteReq misses 1513system.cpu1.dcache.WriteReq_misses::total 55930 # number of WriteReq misses 1514system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8863 # number of LoadLockedReq misses 1515system.cpu1.dcache.LoadLockedReq_misses::total 8863 # number of LoadLockedReq misses 1516system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5883 # number of StoreCondReq misses 1517system.cpu1.dcache.StoreCondReq_misses::total 5883 # number of StoreCondReq misses 1518system.cpu1.dcache.demand_misses::cpu1.data 169665 # number of demand (read+write) misses 1519system.cpu1.dcache.demand_misses::total 169665 # number of demand (read+write) misses 1520system.cpu1.dcache.overall_misses::cpu1.data 169665 # number of overall misses 1521system.cpu1.dcache.overall_misses::total 169665 # number of overall misses 1522system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1371834000 # number of ReadReq miss cycles 1523system.cpu1.dcache.ReadReq_miss_latency::total 1371834000 # number of ReadReq miss cycles 1524system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1009197248 # number of WriteReq miss cycles 1525system.cpu1.dcache.WriteReq_miss_latency::total 1009197248 # number of WriteReq miss cycles 1526system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80472000 # number of LoadLockedReq miss cycles 1527system.cpu1.dcache.LoadLockedReq_miss_latency::total 80472000 # number of LoadLockedReq miss cycles 1528system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43306909 # number of StoreCondReq miss cycles 1529system.cpu1.dcache.StoreCondReq_miss_latency::total 43306909 # number of StoreCondReq miss cycles 1530system.cpu1.dcache.demand_miss_latency::cpu1.data 2381031248 # number of demand (read+write) miss cycles 1531system.cpu1.dcache.demand_miss_latency::total 2381031248 # number of demand (read+write) miss cycles 1532system.cpu1.dcache.overall_miss_latency::cpu1.data 2381031248 # number of overall miss cycles 1533system.cpu1.dcache.overall_miss_latency::total 2381031248 # number of overall miss cycles 1534system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303403 # number of ReadReq accesses(hits+misses) 1535system.cpu1.dcache.ReadReq_accesses::total 2303403 # number of ReadReq accesses(hits+misses) 1536system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623498 # number of WriteReq accesses(hits+misses) 1537system.cpu1.dcache.WriteReq_accesses::total 1623498 # number of WriteReq accesses(hits+misses) 1538system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55832 # number of LoadLockedReq accesses(hits+misses) 1539system.cpu1.dcache.LoadLockedReq_accesses::total 55832 # number of LoadLockedReq accesses(hits+misses) 1540system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55363 # number of StoreCondReq accesses(hits+misses) 1541system.cpu1.dcache.StoreCondReq_accesses::total 55363 # number of StoreCondReq accesses(hits+misses) 1542system.cpu1.dcache.demand_accesses::cpu1.data 3926901 # number of demand (read+write) accesses 1543system.cpu1.dcache.demand_accesses::total 3926901 # number of demand (read+write) accesses 1544system.cpu1.dcache.overall_accesses::cpu1.data 3926901 # number of overall (read+write) accesses 1545system.cpu1.dcache.overall_accesses::total 3926901 # number of overall (read+write) accesses 1546system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049377 # miss rate for ReadReq accesses 1547system.cpu1.dcache.ReadReq_miss_rate::total 0.049377 # miss rate for ReadReq accesses 1548system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034450 # miss rate for WriteReq accesses 1549system.cpu1.dcache.WriteReq_miss_rate::total 0.034450 # miss rate for WriteReq accesses 1550system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158744 # miss rate for LoadLockedReq accesses 1551system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158744 # miss rate for LoadLockedReq accesses 1552system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106262 # miss rate for StoreCondReq accesses 1553system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106262 # miss rate for StoreCondReq accesses 1554system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043206 # miss rate for demand accesses 1555system.cpu1.dcache.demand_miss_rate::total 0.043206 # miss rate for demand accesses 1556system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043206 # miss rate for overall accesses 1557system.cpu1.dcache.overall_miss_rate::total 0.043206 # miss rate for overall accesses 1558system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.669671 # average ReadReq miss latency 1559system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.669671 # average ReadReq miss latency 1560system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18043.934347 # average WriteReq miss latency 1561system.cpu1.dcache.WriteReq_avg_miss_latency::total 18043.934347 # average WriteReq miss latency 1562system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9079.544172 # average LoadLockedReq miss latency 1563system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9079.544172 # average LoadLockedReq miss latency 1564system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.364780 # average StoreCondReq miss latency 1565system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.364780 # average StoreCondReq miss latency 1566system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency 1567system.cpu1.dcache.demand_avg_miss_latency::total 14033.720850 # average overall miss latency 1568system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency 1569system.cpu1.dcache.overall_avg_miss_latency::total 14033.720850 # average overall miss latency |
| 1660system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1661system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1662system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1663system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1664system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1665system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1666system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1667system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1570system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1571system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1572system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1573system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1574system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1575system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1576system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1577system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1668system.cpu1.dcache.writebacks::writebacks 109122 # number of writebacks 1669system.cpu1.dcache.writebacks::total 109122 # number of writebacks 1670system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116704 # number of ReadReq MSHR misses 1671system.cpu1.dcache.ReadReq_mshr_misses::total 116704 # number of ReadReq MSHR misses 1672system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 56889 # number of WriteReq MSHR misses 1673system.cpu1.dcache.WriteReq_mshr_misses::total 56889 # number of WriteReq MSHR misses 1674system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9081 # number of LoadLockedReq MSHR misses 1675system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9081 # number of LoadLockedReq MSHR misses 1676system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6019 # number of StoreCondReq MSHR misses 1677system.cpu1.dcache.StoreCondReq_mshr_misses::total 6019 # number of StoreCondReq MSHR misses 1678system.cpu1.dcache.demand_mshr_misses::cpu1.data 173593 # number of demand (read+write) MSHR misses 1679system.cpu1.dcache.demand_mshr_misses::total 173593 # number of demand (read+write) MSHR misses 1680system.cpu1.dcache.overall_mshr_misses::cpu1.data 173593 # number of overall MSHR misses 1681system.cpu1.dcache.overall_mshr_misses::total 173593 # number of overall MSHR misses 1682system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1178000000 # number of ReadReq MSHR miss cycles 1683system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1178000000 # number of ReadReq MSHR miss cycles 1684system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 927938196 # number of WriteReq MSHR miss cycles 1685system.cpu1.dcache.WriteReq_mshr_miss_latency::total 927938196 # number of WriteReq MSHR miss cycles 1686system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64195000 # number of LoadLockedReq MSHR miss cycles 1687system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64195000 # number of LoadLockedReq MSHR miss cycles 1688system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32145073 # number of StoreCondReq MSHR miss cycles 1689system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32145073 # number of StoreCondReq MSHR miss cycles 1690system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2105938196 # number of demand (read+write) MSHR miss cycles 1691system.cpu1.dcache.demand_mshr_miss_latency::total 2105938196 # number of demand (read+write) MSHR miss cycles 1692system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2105938196 # number of overall MSHR miss cycles 1693system.cpu1.dcache.overall_mshr_miss_latency::total 2105938196 # number of overall MSHR miss cycles 1694system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776000 # number of ReadReq MSHR uncacheable cycles 1695system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776000 # number of ReadReq MSHR uncacheable cycles 1696system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718207000 # number of WriteReq MSHR uncacheable cycles 1697system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles 1698system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles 1699system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles 1700system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses 1701system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses 1702system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses 1703system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses 1704system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses 1705system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses 1706system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses 1707system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses 1708system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses 1709system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses 1710system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses 1711system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses 1712system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency 1713system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency 1714system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency 1715system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency 1716system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency 1717system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency 1718system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency 1719system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency 1720system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency 1721system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency 1722system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency 1723system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency | 1578system.cpu1.dcache.writebacks::writebacks 106440 # number of writebacks 1579system.cpu1.dcache.writebacks::total 106440 # number of writebacks 1580system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113735 # number of ReadReq MSHR misses 1581system.cpu1.dcache.ReadReq_mshr_misses::total 113735 # number of ReadReq MSHR misses 1582system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55930 # number of WriteReq MSHR misses 1583system.cpu1.dcache.WriteReq_mshr_misses::total 55930 # number of WriteReq MSHR misses 1584system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8863 # number of LoadLockedReq MSHR misses 1585system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8863 # number of LoadLockedReq MSHR misses 1586system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5883 # number of StoreCondReq MSHR misses 1587system.cpu1.dcache.StoreCondReq_mshr_misses::total 5883 # number of StoreCondReq MSHR misses 1588system.cpu1.dcache.demand_mshr_misses::cpu1.data 169665 # number of demand (read+write) MSHR misses 1589system.cpu1.dcache.demand_mshr_misses::total 169665 # number of demand (read+write) MSHR misses 1590system.cpu1.dcache.overall_mshr_misses::cpu1.data 169665 # number of overall MSHR misses 1591system.cpu1.dcache.overall_mshr_misses::total 169665 # number of overall MSHR misses 1592system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144290000 # number of ReadReq MSHR miss cycles 1593system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144290000 # number of ReadReq MSHR miss cycles 1594system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 895105752 # number of WriteReq MSHR miss cycles 1595system.cpu1.dcache.WriteReq_mshr_miss_latency::total 895105752 # number of WriteReq MSHR miss cycles 1596system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62746000 # number of LoadLockedReq MSHR miss cycles 1597system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62746000 # number of LoadLockedReq MSHR miss cycles 1598system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31539091 # number of StoreCondReq MSHR miss cycles 1599system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31539091 # number of StoreCondReq MSHR miss cycles 1600system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2039395752 # number of demand (read+write) MSHR miss cycles 1601system.cpu1.dcache.demand_mshr_miss_latency::total 2039395752 # number of demand (read+write) MSHR miss cycles 1602system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2039395752 # number of overall MSHR miss cycles 1603system.cpu1.dcache.overall_mshr_miss_latency::total 2039395752 # number of overall MSHR miss cycles 1604system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776500 # number of ReadReq MSHR uncacheable cycles 1605system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776500 # number of ReadReq MSHR uncacheable cycles 1606system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713537000 # number of WriteReq MSHR uncacheable cycles 1607system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713537000 # number of WriteReq MSHR uncacheable cycles 1608system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732313500 # number of overall MSHR uncacheable cycles 1609system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732313500 # number of overall MSHR uncacheable cycles 1610system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049377 # mshr miss rate for ReadReq accesses 1611system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049377 # mshr miss rate for ReadReq accesses 1612system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034450 # mshr miss rate for WriteReq accesses 1613system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034450 # mshr miss rate for WriteReq accesses 1614system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158744 # mshr miss rate for LoadLockedReq accesses 1615system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158744 # mshr miss rate for LoadLockedReq accesses 1616system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106262 # mshr miss rate for StoreCondReq accesses 1617system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106262 # mshr miss rate for StoreCondReq accesses 1618system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for demand accesses 1619system.cpu1.dcache.demand_mshr_miss_rate::total 0.043206 # mshr miss rate for demand accesses 1620system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for overall accesses 1621system.cpu1.dcache.overall_mshr_miss_rate::total 0.043206 # mshr miss rate for overall accesses 1622system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035 # average ReadReq mshr miss latency 1623system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035 # average ReadReq mshr miss latency 1624system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331 # average WriteReq mshr miss latency 1625system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331 # average WriteReq mshr miss latency 1626system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.544172 # average LoadLockedReq mshr miss latency 1627system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.544172 # average LoadLockedReq mshr miss latency 1628system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.055754 # average StoreCondReq mshr miss latency 1629system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.055754 # average StoreCondReq mshr miss latency 1630system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency 1631system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency 1632system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency 1633system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency |
| 1724system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1725system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1726system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1727system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1728system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1729system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1730system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1731 1732---------- End Simulation Statistics ---------- | 1634system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1635system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1636system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1637system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1638system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1639system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1640system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1641 1642---------- End Simulation Statistics ---------- |