3,5c3,5
< sim_seconds 1.961837 # Number of seconds simulated
< sim_ticks 1961837389000 # Number of ticks simulated
< final_tick 1961837389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.960910 # Number of seconds simulated
> sim_ticks 1960909874500 # Number of ticks simulated
> final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,14c7,14
< host_inst_rate 1325125 # Simulator instruction rate (inst/s)
< host_op_rate 1325124 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 42668778131 # Simulator tick rate (ticks/s)
< host_mem_usage 308960 # Number of bytes of host memory used
< host_seconds 45.98 # Real time elapsed on the host
< sim_insts 60926932 # Number of instructions simulated
< sim_ops 60926932 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu0.inst 833280 # Number of bytes read from this memory
---
> host_inst_rate 787846 # Simulator instruction rate (inst/s)
> host_op_rate 787845 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 25353578812 # Simulator tick rate (ticks/s)
> host_mem_usage 353976 # Number of bytes of host memory used
> host_seconds 77.34 # Real time elapsed on the host
> sim_insts 60933947 # Number of instructions simulated
> sim_ops 60933947 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory
16c16
< system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
---
> system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory
18,20c18,20
< system.physmem.bytes_read::cpu1.data 338432 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28741376 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 833280 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory
22,25c22,25
< system.physmem.bytes_inst_read::total 864960 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7742464 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7742464 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 13020 # Number of read requests responded to by this memory
---
> system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory
27c27
< system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory
29,60c29,60
< system.physmem.num_reads::cpu1.data 5288 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 449084 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 120976 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 120976 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 424745 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 12685610 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1351223 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 16148 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 172508 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 14650234 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 424745 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 16148 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 440893 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3946537 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3946537 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3946537 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 424745 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 12685610 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1351223 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 16148 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 172508 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 18596771 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 449084 # Number of read requests accepted
< system.physmem.writeReqs 120976 # Number of write requests accepted
< system.physmem.readBursts 449084 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 120976 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 28737920 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 3456 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7741568 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 28741376 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7742464 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 54 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 449082 # Number of read requests accepted
> system.physmem.writeReqs 120995 # Number of write requests accepted
> system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue
62c62
< system.physmem.neitherReadNorWriteReqs 7077 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write
64,66c64,66
< system.physmem.perBankRdBursts::1 28458 # Per bank write bursts
< system.physmem.perBankRdBursts::2 28055 # Per bank write bursts
< system.physmem.perBankRdBursts::3 27665 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 28459 # Per bank write bursts
> system.physmem.perBankRdBursts::2 28057 # Per bank write bursts
> system.physmem.perBankRdBursts::3 27664 # Per bank write bursts
68,73c68,73
< system.physmem.perBankRdBursts::5 27792 # Per bank write bursts
< system.physmem.perBankRdBursts::6 28261 # Per bank write bursts
< system.physmem.perBankRdBursts::7 27879 # Per bank write bursts
< system.physmem.perBankRdBursts::8 28077 # Per bank write bursts
< system.physmem.perBankRdBursts::9 27735 # Per bank write bursts
< system.physmem.perBankRdBursts::10 27671 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 27793 # Per bank write bursts
> system.physmem.perBankRdBursts::6 28259 # Per bank write bursts
> system.physmem.perBankRdBursts::7 27872 # Per bank write bursts
> system.physmem.perBankRdBursts::8 28083 # Per bank write bursts
> system.physmem.perBankRdBursts::9 27730 # Per bank write bursts
> system.physmem.perBankRdBursts::10 27672 # Per bank write bursts
75c75
< system.physmem.perBankRdBursts::12 28173 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 28179 # Per bank write bursts
77,81c77,81
< system.physmem.perBankRdBursts::14 28655 # Per bank write bursts
< system.physmem.perBankRdBursts::15 28040 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7931 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7869 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7539 # Per bank write bursts
---
> system.physmem.perBankRdBursts::14 28654 # Per bank write bursts
> system.physmem.perBankRdBursts::15 28035 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7928 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7868 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7543 # Per bank write bursts
84,89c84,89
< system.physmem.perBankWrBursts::5 7313 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7748 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7258 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7316 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7114 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7078 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 7314 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7747 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7251 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7322 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7110 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7099 # Per bank write bursts
91c91
< system.physmem.perBankWrBursts::12 7676 # Per bank write bursts
---
> system.physmem.perBankWrBursts::12 7681 # Per bank write bursts
93,94c93,94
< system.physmem.perBankWrBursts::14 8336 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7688 # Per bank write bursts
---
> system.physmem.perBankWrBursts::14 8335 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7684 # Per bank write bursts
96,97c96,97
< system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
< system.physmem.totGap 1961830378000 # Total gap between requests
---
> system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
> system.physmem.totGap 1960902862500 # Total gap between requests
104c104
< system.physmem.readPktSize::6 449084 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 449082 # Read request sizes (log2)
111,129c111,129
< system.physmem.writePktSize::6 120976 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 409885 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 10531 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 5358 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 2695 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 2315 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2316 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 1356 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 1333 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 1333 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 1442 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1324 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1276 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1111 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 977 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 963 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 963 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 961 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 960 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 120995 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see
131,132c131,132
< system.physmem.rdQLenPdf::19 961 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
144,169c144,169
< system.physmem.wrQLenPdf::0 4884 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 4909 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4919 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 5610 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 6333 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5791 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5851 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5968 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 6087 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 6069 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 6113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 6155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4975 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4963 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 216 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 45 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 25 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5982 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 6055 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 6054 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 6099 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 6134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5025 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4966 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4953 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see
171,291c171,291
< system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 24 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 49252 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 740.628604 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 223.502021 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 1737.958624 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-67 17638 35.81% 35.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-131 7255 14.73% 50.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-195 4934 10.02% 60.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-259 2938 5.97% 66.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-323 1843 3.74% 70.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-387 1471 2.99% 73.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-451 1137 2.31% 75.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-515 871 1.77% 77.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-579 749 1.52% 78.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-643 678 1.38% 80.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-707 696 1.41% 81.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-771 441 0.90% 82.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-835 346 0.70% 83.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-899 295 0.60% 83.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-963 325 0.66% 84.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1027 366 0.74% 85.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1091 215 0.44% 85.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1155 196 0.40% 86.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1219 200 0.41% 86.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1283 126 0.26% 86.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1347 182 0.37% 87.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1411 862 1.75% 88.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1475 228 0.46% 89.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1539 113 0.23% 89.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1603 126 0.26% 89.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1667 100 0.20% 90.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1731 86 0.17% 90.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1795 47 0.10% 90.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1859 73 0.15% 90.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1923 75 0.15% 90.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-1987 79 0.16% 90.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2051 32 0.06% 90.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2115 84 0.17% 90.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2179 62 0.13% 91.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2243 61 0.12% 91.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2307 26 0.05% 91.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2371 60 0.12% 91.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2435 59 0.12% 91.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2499 68 0.14% 91.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2563 29 0.06% 91.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2627 67 0.14% 91.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2691 63 0.13% 91.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2755 57 0.12% 92.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2819 25 0.05% 92.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2883 61 0.12% 92.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2947 59 0.12% 92.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3011 69 0.14% 92.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3075 25 0.05% 92.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3139 65 0.13% 92.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3200-3203 58 0.12% 92.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3267 65 0.13% 92.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328-3331 25 0.05% 93.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3395 59 0.12% 93.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3459 53 0.11% 93.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520-3523 71 0.14% 93.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3587 22 0.04% 93.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3651 70 0.14% 93.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3712-3715 53 0.11% 93.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3779 60 0.12% 93.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3843 27 0.05% 93.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3907 61 0.12% 93.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3968-3971 53 0.11% 94.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4035 63 0.13% 94.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4099 34 0.07% 94.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4160-4163 63 0.13% 94.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4227 57 0.12% 94.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288-4291 62 0.13% 94.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4352-4355 28 0.06% 94.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4419 58 0.12% 94.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4480-4483 54 0.11% 94.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4544-4547 66 0.13% 95.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4608-4611 361 0.73% 95.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4672-4675 57 0.12% 95.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4736-4739 23 0.05% 95.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4800-4803 53 0.11% 96.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4864-4867 23 0.05% 96.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928-4931 58 0.12% 96.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4992-4995 23 0.05% 96.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5056-5059 51 0.10% 96.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5120-5123 22 0.04% 96.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5184-5187 54 0.11% 96.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5248-5251 39 0.08% 96.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5312-5315 55 0.11% 96.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5376-5379 21 0.04% 96.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5440-5443 55 0.11% 96.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5504-5507 27 0.05% 96.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5568-5571 50 0.10% 97.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632-5635 22 0.04% 97.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5696-5699 54 0.11% 97.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5760-5763 25 0.05% 97.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5824-5827 53 0.11% 97.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5888-5891 22 0.04% 97.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5952-5955 52 0.11% 97.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6016-6019 23 0.05% 97.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6080-6083 54 0.11% 97.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6147 23 0.05% 97.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6208-6211 52 0.11% 97.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6272-6275 23 0.05% 97.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6336-6339 54 0.11% 97.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6400-6403 23 0.05% 98.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6464-6467 53 0.11% 98.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6528-6531 23 0.05% 98.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6592-6595 55 0.11% 98.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6656-6659 26 0.05% 98.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6720-6723 57 0.12% 98.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6784-6787 421 0.85% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6851 1 0.00% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7171 12 0.02% 99.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7360-7363 2 0.00% 99.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.35% # Bytes accessed per row activation
---
> system.physmem.wrQLenPdf::27 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 49380 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 738.726934 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 222.746795 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1987 64 0.13% 90.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2051 84 0.17% 90.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2115 51 0.10% 90.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2179 54 0.11% 91.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2243 70 0.14% 91.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2307 45 0.09% 91.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2371 72 0.15% 91.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2435 49 0.10% 91.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2499 40 0.08% 91.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2563 72 0.15% 91.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2627 42 0.09% 91.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2691 45 0.09% 91.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2755 69 0.14% 92.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2819 44 0.09% 92.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2883 64 0.13% 92.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2947 43 0.09% 92.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3075 76 0.15% 92.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3139 39 0.08% 92.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3203 46 0.09% 92.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3267 67 0.14% 92.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3331 46 0.09% 93.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3395 66 0.13% 93.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3459 46 0.09% 93.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3523 37 0.07% 93.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3587 72 0.15% 93.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3651 38 0.08% 93.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712-3715 42 0.09% 93.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3779 69 0.14% 93.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3843 43 0.09% 93.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3907 64 0.13% 94.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968-3971 42 0.09% 94.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4035 41 0.08% 94.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4099 74 0.15% 94.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4160-4163 37 0.07% 94.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4227 43 0.09% 94.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288-4291 66 0.13% 94.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352-4355 46 0.09% 94.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4419 64 0.13% 94.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480-4483 43 0.09% 94.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4547 37 0.07% 95.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608-4611 404 0.82% 95.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4672-4675 34 0.07% 95.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736-4739 44 0.09% 96.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4803 36 0.07% 96.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864-4867 44 0.09% 96.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928-4931 34 0.07% 96.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992-4995 44 0.09% 96.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056-5059 33 0.07% 96.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120-5123 41 0.08% 96.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184-5187 51 0.10% 96.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5248-5251 44 0.09% 96.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312-5315 32 0.06% 96.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376-5379 40 0.08% 96.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5440-5443 37 0.07% 96.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5504-5507 43 0.09% 96.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5568-5571 35 0.07% 97.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5632-5635 40 0.08% 97.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5696-5699 33 0.07% 97.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5760-5763 47 0.10% 97.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5824-5827 34 0.07% 97.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5888-5891 43 0.09% 97.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952-5955 35 0.07% 97.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016-6019 44 0.09% 97.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6083 34 0.07% 97.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6147 44 0.09% 97.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208-6211 38 0.08% 97.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6272-6275 42 0.09% 97.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6339 35 0.07% 97.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6400-6403 43 0.09% 98.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6464-6467 32 0.06% 98.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6528-6531 40 0.08% 98.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592-6595 37 0.07% 98.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656-6659 41 0.08% 98.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6723 32 0.06% 98.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6784-6787 431 0.87% 99.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7171 10 0.02% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.35% # Bytes accessed per row activation
293,311c293,311
< system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7616-7619 1 0.00% 99.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7680-7683 2 0.00% 99.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7811 2 0.00% 99.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7939 1 0.00% 99.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8195 6 0.01% 99.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8448-8451 1 0.00% 99.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8704-8707 2 0.00% 99.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8768-8771 1 0.00% 99.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9024-9027 2 0.00% 99.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.41% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7616-7619 3 0.01% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9088-9091 3 0.01% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.42% # Bytes accessed per row activation
313,316c313,314
< system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9664-9667 2 0.00% 99.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9792-9795 2 0.00% 99.43% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.43% # Bytes accessed per row activation
318,337c316,335
< system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10432-10435 1 0.00% 99.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10944-10947 4 0.01% 99.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11072-11075 2 0.00% 99.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11264-11267 1 0.00% 99.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11648-11651 1 0.00% 99.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11712-11715 2 0.00% 99.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11776-11779 2 0.00% 99.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11840-11843 1 0.00% 99.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::11968-11971 1 0.00% 99.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12032-12035 2 0.00% 99.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12096-12099 1 0.00% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12288-12291 3 0.01% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12672-12675 2 0.00% 99.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13056-13059 3 0.01% 99.50% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11520-11523 2 0.00% 99.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12288-12291 2 0.00% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12352-12355 3 0.01% 99.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12672-12675 3 0.01% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.49% # Bytes accessed per row activation
339,341c337,343
< system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13696-13699 4 0.01% 99.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14208-14211 4 0.01% 99.52% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.52% # Bytes accessed per row activation
343,364c345,366
< system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14848-14851 1 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14912-14915 1 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15296-15299 2 0.00% 99.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15360-15363 40 0.08% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15424-15427 2 0.00% 99.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15488-15491 1 0.00% 99.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15744-15747 1 0.00% 99.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15936-15939 1 0.00% 99.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16384-16387 179 0.36% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 49252 # Bytes accessed per row activation
< system.physmem.totQLat 6314810500 # Total ticks spent queuing
< system.physmem.totMemAccLat 14686644250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2245150000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 6126683750 # Total ticks spent accessing banks
< system.physmem.avgQLat 14063.23 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 13644.26 # Average bank access latency per DRAM burst
---
> system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation
> system.physmem.totQLat 6346588750 # Total ticks spent queuing
> system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks
> system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst
366,367c368,369
< system.physmem.avgMemAccLat 32707.49 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 14.65 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s
369c371
< system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s
376,382c378,384
< system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing
< system.physmem.readRowHits 424855 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95885 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 94.62 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 79.26 # Row buffer hit rate for writes
< system.physmem.avgGap 3441445.42 # Average gap between requests
< system.physmem.pageHitRate 91.36 # Row buffer hit rate, read and write combined
---
> system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing
> system.physmem.readRowHits 424775 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95849 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes
> system.physmem.avgGap 3439715.80 # Average gap between requests
> system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined
384,409c386,411
< system.membus.throughput 18657286 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 292799 # Transaction distribution
< system.membus.trans_dist::ReadResp 292799 # Transaction distribution
< system.membus.trans_dist::WriteReq 14111 # Transaction distribution
< system.membus.trans_dist::WriteResp 14111 # Transaction distribution
< system.membus.trans_dist::Writeback 120976 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 16467 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 11554 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 7080 # Transaction distribution
< system.membus.trans_dist::ReadExReq 164905 # Transaction distribution
< system.membus.trans_dist::ReadExResp 164053 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42620 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930997 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 973617 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1098283 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82306 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31175680 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::total 31257986 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 36566146 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 36566146 # Total data (bytes)
< system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 43190000 # Layer occupancy (ticks)
---
> system.membus.throughput 18666756 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 292805 # Transaction distribution
> system.membus.trans_dist::ReadResp 292805 # Transaction distribution
> system.membus.trans_dist::WriteReq 14109 # Transaction distribution
> system.membus.trans_dist::WriteResp 14109 # Transaction distribution
> system.membus.trans_dist::Writeback 120995 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution
> system.membus.trans_dist::ReadExReq 164894 # Transaction distribution
> system.membus.trans_dist::ReadExResp 164048 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 36567218 # Total data (bytes)
> system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes)
> system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks)
411c413
< system.membus.reqLayer1.occupancy 1566162500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks)
413c415
< system.membus.respLayer1.occupancy 3824002662 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks)
415c417
< system.membus.respLayer2.occupancy 376301000 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks)
417,431c419,433
< system.l2c.tags.replacements 342163 # number of replacements
< system.l2c.tags.tagsinuse 65223.750612 # Cycle average of tags in use
< system.l2c.tags.total_refs 2442870 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 407350 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 5.996980 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 8613125750 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 55316.946263 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4805.666179 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 4897.139369 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 159.783438 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 44.215363 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.844070 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.073329 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.074724 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.002438 # Average percentage of cache occupancy
---
> system.l2c.tags.replacements 342160 # number of replacements
> system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use
> system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy
433,445c435,447
< system.l2c.tags.occ_percent::total 0.995235 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.inst 684304 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 664415 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 317640 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 107160 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1773519 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 792069 # number of Writeback hits
< system.l2c.Writeback_hits::total 792069 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 188 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 543 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits
---
> system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits
> system.l2c.Writeback_hits::total 791641 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 180 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 539 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 719 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits
447,461c449,463
< system.l2c.ReadExReq_hits::cpu0.data 129070 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 43262 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 172332 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 684304 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 793485 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 317640 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 150422 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1945851 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 684304 # number of overall hits
< system.l2c.overall_hits::cpu0.data 793485 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 317640 # number of overall hits
< system.l2c.overall_hits::cpu1.data 150422 # number of overall hits
< system.l2c.overall_hits::total 1945851 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 13023 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 271669 # number of ReadReq misses
---
> system.l2c.ReadExReq_hits::cpu0.data 129054 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 42974 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 172028 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 684719 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 793579 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 317383 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 150404 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1946085 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 684719 # number of overall hits
> system.l2c.overall_hits::cpu0.data 793579 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 317383 # number of overall hits
> system.l2c.overall_hits::cpu1.data 150404 # number of overall hits
> system.l2c.overall_hits::total 1946085 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 13026 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 271672 # number of ReadReq misses
464,467c466,469
< system.l2c.ReadReq_misses::total 285437 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 2958 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 1767 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 4725 # number of UpgradeReq misses
---
> system.l2c.ReadReq_misses::total 285443 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 1793 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 4742 # number of UpgradeReq misses
471,475c473,477
< system.l2c.ReadExReq_misses::cpu0.data 117954 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 5056 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 123010 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 13023 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 389623 # number of demand (read+write) misses
---
> system.l2c.ReadExReq_misses::cpu0.data 117950 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 5055 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 123005 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 13026 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 389622 # number of demand (read+write) misses
477,480c479,482
< system.l2c.demand_misses::cpu1.data 5298 # number of demand (read+write) misses
< system.l2c.demand_misses::total 408447 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 13023 # number of overall misses
< system.l2c.overall_misses::cpu0.data 389623 # number of overall misses
---
> system.l2c.demand_misses::cpu1.data 5297 # number of demand (read+write) misses
> system.l2c.demand_misses::total 408448 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 13026 # number of overall misses
> system.l2c.overall_misses::cpu0.data 389622 # number of overall misses
482,519c484,521
< system.l2c.overall_misses::cpu1.data 5298 # number of overall misses
< system.l2c.overall_misses::total 408447 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 996362741 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 17553106248 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 38541500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 19247750 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 18607258239 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1197458 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 10193060 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 11390518 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 953959 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 139494 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 1093453 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 8253462501 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 385340740 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 8638803241 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 996362741 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 25806568749 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 38541500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 404588490 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 27246061480 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 996362741 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 25806568749 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 38541500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 404588490 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 27246061480 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 697327 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 936084 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 318143 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 107402 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2058956 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 792069 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 792069 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 3146 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 2310 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 5456 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 956 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 949 # number of SCUpgradeReq accesses(hits+misses)
---
> system.l2c.overall_misses::cpu1.data 5297 # number of overall misses
> system.l2c.overall_misses::total 408448 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 997409492 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 17552881248 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 35450000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 19470500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 18605211240 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1291954 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 10252557 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 11544511 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 835964 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 163493 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 999457 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 8264985252 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 387201489 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 8652186741 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 997409492 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 25817866500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 35450000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 406671989 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 27257397981 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 997409492 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 25817866500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 35450000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 406671989 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 27257397981 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 697745 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 936197 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 317886 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 107672 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2059500 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 791641 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 791641 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 3129 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 2332 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 957 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 948 # number of SCUpgradeReq accesses(hits+misses)
521,543c523,545
< system.l2c.ReadExReq_accesses::cpu0.data 247024 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 48318 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 295342 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 697327 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1183108 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 318143 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 155720 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2354298 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 697327 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1183108 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 318143 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 155720 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2354298 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.018676 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.290219 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.001581 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.002253 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.138632 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.940242 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764935 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.866019 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961297 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.976818 # miss rate for SCUpgradeReq accesses
---
> system.l2c.ReadExReq_accesses::cpu0.data 247004 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 48029 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 295033 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 697745 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1183201 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 317886 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 155701 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2354533 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 697745 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1183201 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 317886 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 155701 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2354533 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.018669 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.290187 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.001582 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.002248 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.138598 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942474 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768868 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.868339 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.960293 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.977848 # miss rate for SCUpgradeReq accesses
545,581c547,583
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.477500 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.104640 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.416500 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.018676 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.329322 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.001581 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.034023 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.173490 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.018676 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.329322 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.001581 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.034023 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.173490 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76507.927590 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 64612.106085 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76623.260437 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 79536.157025 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 65188.669440 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 404.820149 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5768.568195 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2410.691640 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1038.040261 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 150.478964 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 592.336403 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69971.874638 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76214.545095 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 70228.463060 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 76507.927590 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 66234.715992 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 76623.260437 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 76366.268403 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 66706.479617 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 76507.927590 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 66234.715992 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 76623.260437 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 76366.268403 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 66706.479617 # average overall miss latency
---
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.477523 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.105249 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.416919 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.018669 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.329295 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.001582 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.034020 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.173473 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.018669 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.329295 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.001582 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.034020 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.173473 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76570.665745 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 64610.564386 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70477.137177 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 80456.611570 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 65180.127871 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 438.099017 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5718.102064 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2434.523619 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 909.645267 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 176.367853 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 541.417660 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70071.939398 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76597.722849 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 70340.122280 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 76570.665745 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 66263.882686 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 70477.137177 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 76774.020955 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 66734.071365 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 76570.665745 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 66263.882686 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 70477.137177 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 76774.020955 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 66734.071365 # average overall miss latency
590,591c592,593
< system.l2c.writebacks::writebacks 79456 # number of writebacks
< system.l2c.writebacks::total 79456 # number of writebacks
---
> system.l2c.writebacks::writebacks 79475 # number of writebacks
> system.l2c.writebacks::total 79475 # number of writebacks
601,602c603,604
< system.l2c.ReadReq_mshr_misses::cpu0.inst 13020 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 271669 # number of ReadReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 13023 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 271672 # number of ReadReq MSHR misses
605,608c607,610
< system.l2c.ReadReq_mshr_misses::total 285426 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2958 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 1767 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 4725 # number of UpgradeReq MSHR misses
---
> system.l2c.ReadReq_mshr_misses::total 285432 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2949 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 1793 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 4742 # number of UpgradeReq MSHR misses
612,616c614,618
< system.l2c.ReadExReq_mshr_misses::cpu0.data 117954 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 5056 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 123010 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 13020 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 389623 # number of demand (read+write) MSHR misses
---
> system.l2c.ReadExReq_mshr_misses::cpu0.data 117950 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 5055 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 123005 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 13023 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 389622 # number of demand (read+write) MSHR misses
618,621c620,623
< system.l2c.demand_mshr_misses::cpu1.data 5298 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 408436 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 13020 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 389623 # number of overall MSHR misses
---
> system.l2c.demand_mshr_misses::cpu1.data 5297 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 408437 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 13023 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 389622 # number of overall MSHR misses
623,632c625,634
< system.l2c.overall_mshr_misses::cpu1.data 5298 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 408436 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 832352009 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14156448252 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31778000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 16225250 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 15036803511 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29732955 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17692267 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 47425222 # number of UpgradeReq MSHR miss cycles
---
> system.l2c.overall_mshr_misses::cpu1.data 5297 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 408437 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 831386758 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14156096752 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 28603000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 16450000 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 15032536510 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29642946 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17939793 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 47582739 # number of UpgradeReq MSHR miss cycles
636,667c638,669
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6776581499 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 321158260 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 7097739759 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 832352009 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 20933029751 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 31778000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 337383510 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 22134543270 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 832352009 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 20933029751 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 31778000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 337383510 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 22134543270 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373137500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17612000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1390749500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154547500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 679451000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2833998500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527685000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 697063000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4224748000 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290219 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002253 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.138627 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.940242 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764935 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.866019 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961297 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.976818 # mshr miss rate for SCUpgradeReq accesses
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6783022748 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 323366011 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 7106388759 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 831386758 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 20939119500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 28603000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 339816011 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 22138925269 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 831386758 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 20939119500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 28603000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 339816011 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 22138925269 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373164500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17619000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1390783500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154378500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 679235000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2833613500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527543000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 696854000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 4224397000 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290187 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002248 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.138593 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942474 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768868 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.868339 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.960293 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.977848 # mshr miss rate for SCUpgradeReq accesses
669,689c671,691
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477500 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.104640 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.416500 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.329322 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.034023 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.173485 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018671 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.329322 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001556 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.034023 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.173485 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52109.177904 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67046.487603 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 52681.968395 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.708925 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.601585 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.084021 # average UpgradeReq mshr miss latency
---
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477523 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.105249 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.416919 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.329295 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.034020 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.173468 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.329295 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.034020 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.173468 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52107.308637 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67975.206612 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 52665.911706 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.863683 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.461796 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.318642 # average UpgradeReq mshr miss latency
693,705c695,707
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57451.052944 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63520.225475 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 57700.510194 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63928.725730 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53726.370751 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64197.979798 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63681.296716 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 54193.418969 # average overall mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57507.611259 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63969.537290 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 57773.169863 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53742.138534 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53742.138534 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency
717c719
< system.iocache.tags.tagsinuse 0.571330 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.570482 # Cycle average of tags in use
721,724c723,726
< system.iocache.tags.warmup_cycle 1754532770000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 0.571330 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.035708 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.035708 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1754531382000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 0.570482 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.035655 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.035655 # Average percentage of cache occupancy
733,740c735,742
< system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::tsunami.ide 12952701816 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 12952701816 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 12973950199 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 12973950199 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 12973950199 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 12973950199 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::tsunami.ide 21249133 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21249133 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::tsunami.ide 12966402814 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 12966402814 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 12987651947 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 12987651947 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 12987651947 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 12987651947 # number of overall miss cycles
757,765c759,767
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 311722.704467 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 311722.704467 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 310932.037555 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 310932.037555 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 310932.037555 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 405757 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 122121.454023 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 312052.435839 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 311260.411901 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 311260.411901 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 401197 # number of cycles access was blocked
767c769
< system.iocache.blocked::no_mshrs 29467 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 28980 # number of cycles access was blocked
769c771
< system.iocache.avg_blocked_cycles::no_mshrs 13.769878 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 13.843927 # average number of cycles each access was blocked
783,790c785,792
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10790464816 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 10790464816 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 10802664199 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 10802664199 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 10802664199 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 10802664199 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12200133 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12200133 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10804136814 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 10804136814 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 10816336947 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 10816336947 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 10816336947 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles
799,806c801,808
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 259685.810936 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 259685.810936 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 258895.273906 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 258895.273906 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency
824,825c826,827
< system.cpu0.dtb.read_hits 7530179 # DTB read hits
< system.cpu0.dtb.read_misses 7765 # DTB read misses
---
> system.cpu0.dtb.read_hits 7532654 # DTB read hits
> system.cpu0.dtb.read_misses 7812 # DTB read misses
827,837c829,839
< system.cpu0.dtb.read_accesses 524069 # DTB read accesses
< system.cpu0.dtb.write_hits 5118893 # DTB write hits
< system.cpu0.dtb.write_misses 910 # DTB write misses
< system.cpu0.dtb.write_acv 133 # DTB write access violations
< system.cpu0.dtb.write_accesses 202595 # DTB write accesses
< system.cpu0.dtb.data_hits 12649072 # DTB hits
< system.cpu0.dtb.data_misses 8675 # DTB misses
< system.cpu0.dtb.data_acv 343 # DTB access violations
< system.cpu0.dtb.data_accesses 726664 # DTB accesses
< system.cpu0.itb.fetch_hits 3650586 # ITB hits
< system.cpu0.itb.fetch_misses 3984 # ITB misses
---
> system.cpu0.dtb.read_accesses 524694 # DTB read accesses
> system.cpu0.dtb.write_hits 5120278 # DTB write hits
> system.cpu0.dtb.write_misses 919 # DTB write misses
> system.cpu0.dtb.write_acv 139 # DTB write access violations
> system.cpu0.dtb.write_accesses 202960 # DTB write accesses
> system.cpu0.dtb.data_hits 12652932 # DTB hits
> system.cpu0.dtb.data_misses 8731 # DTB misses
> system.cpu0.dtb.data_acv 349 # DTB access violations
> system.cpu0.dtb.data_accesses 727654 # DTB accesses
> system.cpu0.itb.fetch_hits 3655515 # ITB hits
> system.cpu0.itb.fetch_misses 4023 # ITB misses
839c841
< system.cpu0.itb.fetch_accesses 3654570 # ITB accesses
---
> system.cpu0.itb.fetch_accesses 3659538 # ITB accesses
852c854
< system.cpu0.numCycles 3923674778 # number of cpu cycles simulated
---
> system.cpu0.numCycles 3921819749 # number of cpu cycles simulated
855,873c857,875
< system.cpu0.committedInsts 47959136 # Number of instructions committed
< system.cpu0.committedOps 47959136 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 44491652 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 211334 # Number of float alu accesses
< system.cpu0.num_func_calls 1203195 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 5632072 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 44491652 # number of integer instructions
< system.cpu0.num_fp_insts 211334 # number of float instructions
< system.cpu0.num_int_register_reads 61191395 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 33136181 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 103249 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 105046 # number of times the floating registers were written
< system.cpu0.num_mem_refs 12690027 # number of memory refs
< system.cpu0.num_load_insts 7557911 # Number of load instructions
< system.cpu0.num_store_insts 5132116 # Number of store instructions
< system.cpu0.num_idle_cycles 3700191977.998114 # Number of idle cycles
< system.cpu0.num_busy_cycles 223482800.001886 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.056958 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.943042 # Percentage of idle cycles
---
> system.cpu0.committedInsts 47983654 # Number of instructions committed
> system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses
> system.cpu0.num_func_calls 1203620 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 44515044 # number of integer instructions
> system.cpu0.num_fp_insts 211401 # number of float instructions
> system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written
> system.cpu0.num_mem_refs 12694028 # number of memory refs
> system.cpu0.num_load_insts 7560495 # Number of load instructions
> system.cpu0.num_store_insts 5133533 # Number of store instructions
> system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles
> system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles
875,877c877,879
< system.cpu0.kern.inst.quiesce 6812 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 165228 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 56779 40.23% 40.23% # number of times we switched to this ipl
---
> system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl
879,883c881,885
< system.cpu0.kern.ipl_count::22 1974 1.40% 41.72% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 435 0.31% 42.03% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 81809 57.97% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 141128 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 56269 49.08% 49.08% # number of times we switched to this ipl from a different ipl
---
> system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl
885c887
< system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl
---
> system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
887,895c889,897
< system.cpu0.kern.ipl_good::31 55834 48.70% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 114643 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1902446374500 96.97% 96.97% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 95095000 0.00% 96.98% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 766988500 0.04% 97.02% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 322426000 0.02% 97.03% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 58205747500 2.97% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1961836631500 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.991018 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl
899,900c901,902
< system.cpu0.kern.ipl_used::31 0.682492 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.812333 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl
936,937c938,939
< system.cpu0.kern.callpal::swpctx 3084 2.06% 2.41% # number of callpals executed
< system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed
---
> system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed
> system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed
939,940c941,942
< system.cpu0.kern.callpal::swpipl 134176 89.75% 92.20% # number of callpals executed
< system.cpu0.kern.callpal::rdps 6701 4.48% 96.68% # number of callpals executed
---
> system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed
> system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed
942c944
< system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed
---
> system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed
945,946c947,948
< system.cpu0.kern.callpal::rti 4411 2.95% 99.64% # number of callpals executed
< system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed
---
> system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed
> system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed
948,950c950,952
< system.cpu0.kern.callpal::total 149500 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 7010 # number of protection mode switches
< system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches
---
> system.cpu0.kern.callpal::total 149515 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches
> system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches
952,953c954,955
< system.cpu0.kern.mode_good::kernel 1372
< system.cpu0.kern.mode_good::user 1373
---
> system.cpu0.kern.mode_good::kernel 1377
> system.cpu0.kern.mode_good::user 1378
955c957
< system.cpu0.kern.mode_switch_good::kernel 0.195720 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches
958,960c960,962
< system.cpu0.kern.mode_switch_good::total 0.327448 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1958037655500 99.81% 99.81% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 3798971500 0.19% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode
962c964
< system.cpu0.kern.swap_context 3085 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 3091 # number of times the context was actually changed
994,1017c996,1019
< system.toL2Bus.throughput 103908079 # Throughput (bytes/s)
< system.toL2Bus.trans_dist::ReadReq 2101783 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2101768 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 14111 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 14111 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 792069 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 16689 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 11613 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 28302 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 338794 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 297244 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1394675 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121086 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 636287 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 464415 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 5616463 # Packet count per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44628928 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119461456 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20361152 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17008562 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 201460098 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 201449794 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 2400960 # Total snoop data (bytes)
< system.toL2Bus.reqLayer0.occupancy 4792055385 # Layer occupancy (ticks)
---
> system.toL2Bus.throughput 103937669 # Throughput (bytes/s)
> system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.data_through_bus 201437426 # Total data (bytes)
> system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes)
> system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks)
1021c1023
< system.toL2Bus.respLayer0.occupancy 3140628756 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks)
1023c1025
< system.toL2Bus.respLayer1.occupancy 5519397625 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks)
1025c1027
< system.toL2Bus.respLayer2.occupancy 1431747492 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks)
1027c1029
< system.toL2Bus.respLayer3.occupancy 796288703 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks)
1029c1031
< system.iobus.throughput 1398649 # Throughput (bytes/s)
---
> system.iobus.throughput 1399302 # Throughput (bytes/s)
1032,1034c1034,1036
< system.iobus.trans_dist::WriteReq 55663 # Transaction distribution
< system.iobus.trans_dist::WriteResp 55663 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14010 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::WriteReq 55661 # Transaction distribution
> system.iobus.trans_dist::WriteResp 55661 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes)
1046c1048
< system.iobus.pkt_count_system.bridge.master::total 42620 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes)
1049,1050c1051,1052
< system.iobus.pkt_count::total 126072 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56040 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes)
1062c1064
< system.iobus.tot_pkt_size_system.bridge.master::total 82306 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes)
1065,1067c1067,1069
< system.iobus.tot_pkt_size::total 2743922 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2743922 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 13365000 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 2743906 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks)
1089c1091
< system.iobus.reqLayer29.occupancy 377760199 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks)
1093c1095
< system.iobus.respLayer0.occupancy 28509000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks)
1095c1097
< system.iobus.respLayer1.occupancy 42664000 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks)
1097,1141c1099,1143
< system.cpu0.icache.tags.replacements 696718 # number of replacements
< system.cpu0.icache.tags.tagsinuse 508.401211 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 47270807 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 697230 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 67.798011 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 40083254250 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.401211 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992971 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.992971 # Average percentage of cache occupancy
< system.cpu0.icache.ReadReq_hits::cpu0.inst 47270807 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 47270807 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 47270807 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 47270807 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 47270807 # number of overall hits
< system.cpu0.icache.overall_hits::total 47270807 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 697348 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 697348 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 697348 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 697348 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 697348 # number of overall misses
< system.cpu0.icache.overall_misses::total 697348 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9977651756 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 9977651756 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 9977651756 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 9977651756 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 9977651756 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 9977651756 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 47968155 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 47968155 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 47968155 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 47968155 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 47968155 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 47968155 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014538 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.014538 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014538 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.014538 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014538 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.014538 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14307.995084 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14307.995084 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14307.995084 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14307.995084 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14307.995084 # average overall miss latency
---
> system.cpu0.icache.tags.replacements 697136 # number of replacements
> system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy
> system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits
> system.cpu0.icache.overall_hits::total 47294969 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses
> system.cpu0.icache.overall_misses::total 697766 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency
1150,1173c1152,1175
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697348 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 697348 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 697348 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 697348 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 697348 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 697348 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8577830244 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 8577830244 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8577830244 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 8577830244 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8577830244 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 8577830244 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014538 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.014538 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014538 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.014538 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12300.645078 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12300.645078 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12300.645078 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697766 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 697766 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 697766 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 697766 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 697766 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 697766 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8583721995 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 8583721995 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8583721995 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 8583721995 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8583721995 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 8583721995 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12301.720054 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency
1175,1255c1177,1257
< system.cpu0.dcache.tags.replacements 1186136 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 505.274988 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 11457169 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 1186648 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 9.655070 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 107469250 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.274988 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986865 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.986865 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6449366 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6449366 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 4705451 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 4705451 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140478 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 140478 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147984 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 147984 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 11154817 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 11154817 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 11154817 # number of overall hits
< system.cpu0.dcache.overall_hits::total 11154817 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 939343 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 939343 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 256772 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 256772 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13639 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 13639 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5591 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 5591 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 1196115 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 1196115 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1196115 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1196115 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27074316502 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 27074316502 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10448735954 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 10448735954 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148878750 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 148878750 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43336419 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 43336419 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 37523052456 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 37523052456 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 37523052456 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 37523052456 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 7388709 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 7388709 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4962223 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4962223 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154117 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 154117 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153575 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 153575 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 12350932 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 12350932 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 12350932 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 12350932 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127132 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.127132 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051745 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.051745 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088498 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088498 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036406 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036406 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096844 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.096844 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096844 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.096844 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28822.609528 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 28822.609528 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40692.661014 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 40692.661014 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10915.664638 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10915.664638 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7751.103380 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7751.103380 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 31370.773258 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31370.773258 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 31370.773258 # average overall miss latency
---
> system.cpu0.dcache.tags.replacements 1186229 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 505.271614 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 11460994 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 1186741 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 9.657536 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 107902250 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986859 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.986859 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 4706856 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140512 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 140512 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148003 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 148003 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 11158591 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 11158591 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 11158591 # number of overall hits
> system.cpu0.dcache.overall_hits::total 11158591 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 939483 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 939483 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 256736 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 256736 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13633 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 13633 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5600 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 5600 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 1196219 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1196219 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1196219 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1196219 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27076055500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 27076055500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10459807694 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 10459807694 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148332750 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 148332750 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43345419 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 43345419 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 37535863194 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 37535863194 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 37535863194 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 37535863194 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 7391218 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 7391218 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 4963592 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 4963592 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154145 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 154145 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153603 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 153603 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 12354810 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 12354810 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 12354810 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 12354810 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127108 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.127108 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051724 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.051724 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088443 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088443 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036458 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036458 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096822 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.096822 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096822 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.096822 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28820.165453 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 28820.165453 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40741.492015 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 40741.492015 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10880.418837 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10880.418837 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7740.253393 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7740.253393 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 31378.755223 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 31378.755223 # average overall miss latency
1264,1319c1266,1325
< system.cpu0.dcache.writebacks::writebacks 682430 # number of writebacks
< system.cpu0.dcache.writebacks::total 682430 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939343 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 939343 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256772 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 256772 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13639 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13639 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5590 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 5590 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196115 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1196115 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196115 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1196115 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25063726498 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25063726498 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9880374046 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9880374046 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121588250 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121588250 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32154581 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32154581 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34944100544 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 34944100544 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34944100544 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 34944100544 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465575000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465575000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284904500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284904500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750479500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750479500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127132 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127132 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051745 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051745 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036399 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036399 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.096844 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096844 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.096844 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26682.187974 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26682.187974 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38479.172363 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38479.172363 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8914.748149 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8914.748149 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5752.161181 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5752.161181 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29214.666269 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29214.666269 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks
> system.cpu0.dcache.writebacks::total 682519 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
> system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency
1331c1337
< system.cpu1.dtb.read_hits 2385380 # DTB read hits
---
> system.cpu1.dtb.read_hits 2383442 # DTB read hits
1335c1341
< system.cpu1.dtb.write_hits 1707840 # DTB write hits
---
> system.cpu1.dtb.write_hits 1706844 # DTB write hits
1339c1345
< system.cpu1.dtb.data_hits 4093220 # DTB hits
---
> system.cpu1.dtb.data_hits 4090286 # DTB hits
1343c1349
< system.cpu1.itb.fetch_hits 1814538 # ITB hits
---
> system.cpu1.itb.fetch_hits 1814139 # ITB hits
1346c1352
< system.cpu1.itb.fetch_accesses 1815602 # ITB accesses
---
> system.cpu1.itb.fetch_accesses 1815203 # ITB accesses
1359c1365
< system.cpu1.numCycles 3921880904 # number of cpu cycles simulated
---
> system.cpu1.numCycles 3919927793 # number of cpu cycles simulated
1362,1364c1368,1370
< system.cpu1.committedInsts 12967796 # Number of instructions committed
< system.cpu1.committedOps 12967796 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 11946960 # Number of integer alu accesses
---
> system.cpu1.committedInsts 12950293 # Number of instructions committed
> system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses
1366,1368c1372,1374
< system.cpu1.num_func_calls 410982 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 1284197 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 11946960 # number of integer instructions
---
> system.cpu1.num_func_calls 410658 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 11929999 # number of integer instructions
1370,1371c1376,1377
< system.cpu1.num_int_register_reads 16422187 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 8787604 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written
1374,1380c1380,1386
< system.cpu1.num_mem_refs 4116157 # number of memory refs
< system.cpu1.num_load_insts 2399132 # Number of load instructions
< system.cpu1.num_store_insts 1717025 # Number of store instructions
< system.cpu1.num_idle_cycles 3872385828.119347 # Number of idle cycles
< system.cpu1.num_busy_cycles 49495075.880653 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.012620 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.987380 # Percentage of idle cycles
---
> system.cpu1.num_mem_refs 4113222 # number of memory refs
> system.cpu1.num_load_insts 2397194 # Number of load instructions
> system.cpu1.num_store_insts 1716028 # Number of store instructions
> system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles
> system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles
1382,1384c1388,1390
< system.cpu1.kern.inst.quiesce 2742 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 78306 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 26634 38.27% 38.27% # number of times we switched to this ipl
---
> system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl
1387,1389c1393,1395
< system.cpu1.kern.ipl_count::31 40476 58.16% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 69596 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 25767 48.16% 48.16% # number of times we switched to this ipl from a different ipl
---
> system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl
1392,1399c1398,1405
< system.cpu1.kern.ipl_good::31 25250 47.19% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 53503 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1909643308000 97.38% 97.38% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 700945000 0.04% 97.42% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 361639500 0.02% 97.44% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 50234529500 2.56% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1960940422000 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.967448 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl
1402,1403c1408,1409
< system.cpu1.kern.ipl_used::31 0.623826 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.768765 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl
1422c1428
< system.cpu1.kern.callpal::swpctx 2001 2.78% 3.39% # number of callpals executed
---
> system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed
1425,1426c1431,1432
< system.cpu1.kern.callpal::swpipl 63390 88.19% 91.60% # number of callpals executed
< system.cpu1.kern.callpal::rdps 2146 2.99% 94.59% # number of callpals executed
---
> system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed
> system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed
1430c1436
< system.cpu1.kern.callpal::rti 3719 5.17% 99.77% # number of callpals executed
---
> system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed
1434c1440
< system.cpu1.kern.callpal::total 71875 # number of callpals executed
---
> system.cpu1.kern.callpal::total 71838 # number of callpals executed
1437c1443
< system.cpu1.kern.mode_switch::idle 2907 # number of protection mode switches
---
> system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches
1443,1447c1449,1453
< system.cpu1.kern.mode_switch_good::idle 0.151703 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.309310 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 17986321500 0.92% 0.92% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 1483696000 0.08% 0.99% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1940592550000 99.01% 100.00% # number of ticks spent at the given mode
---
> system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode
1449,1493c1455,1499
< system.cpu1.icache.tags.replacements 317593 # number of replacements
< system.cpu1.icache.tags.tagsinuse 446.454785 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 12652531 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 318104 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 39.774825 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 1959964216000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.454785 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871982 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.871982 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 12652531 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 12652531 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 12652531 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 12652531 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 12652531 # number of overall hits
< system.cpu1.icache.overall_hits::total 12652531 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 318144 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 318144 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 318144 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 318144 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 318144 # number of overall misses
< system.cpu1.icache.overall_misses::total 318144 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4187615492 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4187615492 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4187615492 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4187615492 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4187615492 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4187615492 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 12970675 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 12970675 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 12970675 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 12970675 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 12970675 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 12970675 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024528 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.024528 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024528 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.024528 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024528 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.024528 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13162.641735 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13162.641735 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13162.641735 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13162.641735 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13162.641735 # average overall miss latency
---
> system.cpu1.icache.tags.replacements 317336 # number of replacements
> system.cpu1.icache.tags.tagsinuse 446.450379 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 12635285 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 317847 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 39.752727 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 1958987590000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.450379 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871973 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.871973 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 12635285 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 12635285 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 12635285 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 12635285 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 12635285 # number of overall hits
> system.cpu1.icache.overall_hits::total 12635285 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 317887 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 317887 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 317887 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 317887 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 317887 # number of overall misses
> system.cpu1.icache.overall_misses::total 317887 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4180819492 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4180819492 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4180819492 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4180819492 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4180819492 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4180819492 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953172 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 12953172 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 12953172 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 12953172 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 12953172 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 12953172 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024541 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.024541 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024541 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.024541 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024541 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.024541 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13151.904582 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13151.904582 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13151.904582 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13151.904582 # average overall miss latency
1502,1525c1508,1531
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318144 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 318144 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 318144 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 318144 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 318144 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3551128508 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 3551128508 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3551128508 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 3551128508 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3551128508 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 3551128508 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024528 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.024528 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024528 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.024528 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11162.016282 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11162.016282 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11162.016282 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11162.016282 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317887 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 317887 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 317887 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 317887 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 317887 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 317887 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3544847508 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3544847508 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3544847508 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3544847508 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3544847508 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3544847508 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024541 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.024541 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.024541 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11151.281770 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency
1527,1607c1533,1613
< system.cpu1.dcache.tags.replacements 159205 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 486.204508 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 3919863 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 159531 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 24.571168 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 1048842695500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.204508 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949618 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.949618 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 2222453 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 2222453 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 1596000 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 1596000 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48034 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 48034 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50617 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 50617 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 3818453 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 3818453 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 3818453 # number of overall hits
< system.cpu1.dcache.overall_hits::total 3818453 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 116850 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 116850 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 57159 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 57159 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9086 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 9086 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6023 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 6023 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 174009 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 174009 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 174009 # number of overall misses
< system.cpu1.dcache.overall_misses::total 174009 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1411488249 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 1411488249 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1045308027 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 1045308027 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82519500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 82519500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44276427 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 44276427 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 2456796276 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 2456796276 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 2456796276 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 2456796276 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 2339303 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 2339303 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 1653159 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 1653159 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57120 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 57120 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56640 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 56640 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 3992462 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 3992462 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 3992462 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 3992462 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049951 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.049951 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034576 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.034576 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159069 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159069 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106338 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106338 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043584 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.043584 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043584 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.043584 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12079.488652 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12079.488652 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18287.724190 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 18287.724190 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9082.049307 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9082.049307 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7351.224805 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7351.224805 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14118.788545 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 14118.788545 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14118.788545 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 14118.788545 # average overall miss latency
---
> system.cpu1.dcache.tags.replacements 158764 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 485.752776 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 3916687 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 159090 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 24.619316 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 67802253000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.752776 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948736 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.948736 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 2220669 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 2220669 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 1595283 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 1595283 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48031 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 48031 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50613 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 50613 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 3815952 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 3815952 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 3815952 # number of overall hits
> system.cpu1.dcache.overall_hits::total 3815952 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 116704 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 116704 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 56889 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 56889 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9081 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 9081 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6019 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 6019 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 173593 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 173593 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 173593 # number of overall misses
> system.cpu1.dcache.overall_misses::total 173593 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1411486000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 1411486000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1044020804 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 1044020804 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82357000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 82357000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44184927 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 44184927 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 2455506804 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 2455506804 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 2455506804 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 2455506804 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 2337373 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 2337373 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 1652172 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 1652172 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57112 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 57112 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56632 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 56632 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 3989545 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 3989545 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 3989545 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 3989545 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049930 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.049930 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034433 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.034433 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159003 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159003 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106283 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106283 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043512 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.043512 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043512 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.043512 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12094.581163 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12094.581163 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18351.892352 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 18351.892352 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9069.155379 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9069.155379 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7340.908290 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7340.908290 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 14145.194818 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 14145.194818 # average overall miss latency
1616,1671c1622,1677
< system.cpu1.dcache.writebacks::writebacks 109639 # number of writebacks
< system.cpu1.dcache.writebacks::total 109639 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116850 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 116850 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57159 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 57159 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9086 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9086 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6023 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 6023 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 174009 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 174009 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 174009 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 174009 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1177711751 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1177711751 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 928682973 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 928682973 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64347500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64347500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32228573 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32228573 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2106394724 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 2106394724 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2106394724 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 2106394724 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18769000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18769000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718428000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718428000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737197000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737197000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049951 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049951 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034576 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034576 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159069 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159069 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106338 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106338 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.043584 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043584 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.043584 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10078.833984 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10078.833984 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16247.362148 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16247.362148 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7082.049307 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7082.049307 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5350.916985 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5350.916985 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12105.090679 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12105.090679 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 109122 # number of writebacks
> system.cpu1.dcache.writebacks::total 109122 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116704 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 116704 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 56889 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 56889 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9081 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9081 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6019 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 6019 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 173593 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 173593 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 173593 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 173593 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1178000000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1178000000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 927938196 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 927938196 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64195000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64195000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32145073 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32145073 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2105938196 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 2105938196 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2105938196 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 2105938196 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718207000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency