Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

Deleted Added

sdiff udiff text old ( 9490:e6a09d97bdc9 ) new ( 9568:cd1351d4d850 )

full compact

3,5c3,5
< sim_seconds 1.952724 # Number of seconds simulated
< sim_ticks 1952724269500 # Number of ticks simulated
< final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.954691 # Number of seconds simulated
> sim_ticks 1954691371500 # Number of ticks simulated
> final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,91c7,91
< host_inst_rate 1678586 # Simulator instruction rate (inst/s)
< host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 53851852439 # Simulator tick rate (ticks/s)
< host_mem_usage 333452 # Number of bytes of host memory used
< host_seconds 36.26 # Real time elapsed on the host
< sim_insts 60867235 # Number of instructions simulated
< sim_ops 60867235 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory
< system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory
< system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory
< system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory
< system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 448125 # Total number of read requests seen
< system.physmem.writeReqs 120294 # Total number of write requests seen
< system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady
< system.physmem.bytesRead 28680000 # Total number of bytes read from memory
< system.physmem.bytesWritten 7698816 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q
< system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis
---
> host_inst_rate 798728 # Simulator instruction rate (inst/s)
> host_op_rate 798728 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26318676085 # Simulator tick rate (ticks/s)
> host_mem_usage 332420 # Number of bytes of host memory used
> host_seconds 74.27 # Real time elapsed on the host
> sim_insts 59321614 # Number of instructions simulated
> sim_ops 59321614 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory
> system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory
> system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory
> system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1356130 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 199364 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 447836 # Total number of read requests seen
> system.physmem.writeReqs 119953 # Total number of write requests seen
> system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady
> system.physmem.bytesRead 28661504 # Total number of bytes read from memory
> system.physmem.bytesWritten 7676992 # Total number of bytes written to memory
> system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize()
> system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize()
> system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
> system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed
> system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis
> system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis
> system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::1 7504 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis
> system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis
93,94c93,94
< system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry
< system.physmem.totGap 1952670553500 # Total gap between requests
---
> system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry
> system.physmem.totGap 1954684300500 # Total gap between requests
101,142c101,129
< system.physmem.readPktSize::6 448125 # Categorize read packet sizes
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 121700 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
---
> system.physmem.readPktSize::6 447836 # Categorize read packet sizes
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 119953 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
154,184c141,170
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 1507 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 940 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 888 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
186,193c172,178
< system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 4798545467 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 13448530467 # Sum of mem lat for all requests
< system.physmem.totBusLat 2240285000 # Total cycles spent in databus access
< system.physmem.totBankLat 6409700000 # Total cycles spent in bank access
< system.physmem.avgQLat 10709.68 # Average queueing delay per request
< system.physmem.avgBankLat 14305.55 # Average bank access latency per request
---
> system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
> system.physmem.totQLat 4783798250 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 13397999500 # Sum of mem lat for all requests
> system.physmem.totBusLat 2238835000 # Total cycles spent in databus access
> system.physmem.totBankLat 6375366250 # Total cycles spent in bank access
> system.physmem.avgQLat 10683.68 # Average queueing delay per request
> system.physmem.avgBankLat 14238.13 # Average bank access latency per request
195,199c180,184
< system.physmem.avgMemAccLat 30015.22 # Average memory access latency
< system.physmem.avgRdBW 14.69 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 14.69 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 3.94 # Average consumed write bandwidth in MB/s
---
> system.physmem.avgMemAccLat 29921.81 # Average memory access latency
> system.physmem.avgRdBW 14.66 # Average achieved read bandwidth in MB/s
> system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s
> system.physmem.avgConsumedRdBW 14.66 # Average consumed read bandwidth in MB/s
> system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s
203,373c188,358
< system.physmem.avgWrQLen 10.11 # Average write queue length over time
< system.physmem.readRowHits 419119 # Number of row buffer hits during reads
< system.physmem.writeRowHits 92373 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 76.79 # Row buffer hit rate for writes
< system.physmem.avgGap 3435266.16 # Average gap between requests
< system.l2c.replacements 341268 # number of replacements
< system.l2c.tagsinuse 65240.270273 # Cycle average of tags in use
< system.l2c.total_refs 2443367 # Total number of references to valid blocks.
< system.l2c.sampled_refs 406244 # Sample count of references to valid blocks.
< system.l2c.avg_refs 6.014531 # Average number of references to valid blocks.
< system.l2c.warmup_cycle 6941595752 # Cycle when the warmup percentage was hit.
< system.l2c.occ_blocks::writebacks 55425.253207 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.inst 4870.495631 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu0.data 4790.652765 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.inst 116.277662 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu1.data 37.591009 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.845722 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.inst 0.074318 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu0.data 0.073100 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.inst 0.001774 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu1.data 0.000574 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.995488 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu0.inst 687318 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 665852 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 314877 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 108330 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1776377 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 794206 # number of Writeback hits
< system.l2c.Writeback_hits::total 794206 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 530 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 702 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 22 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 62 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 126888 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 47007 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 173895 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 687318 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 792740 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 314877 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 155337 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1950272 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 687318 # number of overall hits
< system.l2c.overall_hits::cpu0.data 792740 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 314877 # number of overall hits
< system.l2c.overall_hits::cpu1.data 155337 # number of overall hits
< system.l2c.overall_hits::total 1950272 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 12972 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 271609 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 561 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 240 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 285382 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 2946 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 1731 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 4677 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 877 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 894 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1771 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 115472 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 6625 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 122097 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 12972 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 387081 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 561 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 6865 # number of demand (read+write) misses
< system.l2c.demand_misses::total 407479 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 12972 # number of overall misses
< system.l2c.overall_misses::cpu0.data 387081 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 561 # number of overall misses
< system.l2c.overall_misses::cpu1.data 6865 # number of overall misses
< system.l2c.overall_misses::total 407479 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 816098500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 11712193000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 36330000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 18796500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 12583418000 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1197000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 9651997 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 10848997 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 863000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 1045500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 5538652000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 375096499 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 5913748499 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 816098500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 17250845000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 36330000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 393892999 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 18497166499 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 816098500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 17250845000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 36330000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 393892999 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 18497166499 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 700290 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 937461 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 315438 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 108570 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2061759 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 794206 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 794206 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 3118 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 2261 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 5379 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 917 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 916 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 1833 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 242360 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 53632 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 295992 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 700290 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1179821 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 315438 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 162202 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2357751 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 700290 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1179821 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 315438 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 162202 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2357751 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.018524 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.289728 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.001778 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.002211 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.138417 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.944836 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.765590 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.869492 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.956379 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975983 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.966176 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.476448 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.123527 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.412501 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.018524 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.328085 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.001778 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.042324 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.172825 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.018524 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.328085 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.001778 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.042324 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.172825 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 62912.311132 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 43121.520274 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 64759.358289 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 78318.750000 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 44093.243442 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 406.313646 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5575.965916 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 2319.648706 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 984.036488 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 204.138702 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 590.344438 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47965.324927 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 56618.339472 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 48434.838686 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 62912.311132 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 44566.499002 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 64759.358289 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 57376.984559 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 45394.158960 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 62912.311132 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 44566.499002 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 64759.358289 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 57376.984559 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 45394.158960 # average overall miss latency
---
> system.physmem.avgWrQLen 10.91 # Average write queue length over time
> system.physmem.readRowHits 419870 # Number of row buffer hits during reads
> system.physmem.writeRowHits 92076 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes
> system.physmem.avgGap 3442624.46 # Average gap between requests
> system.l2c.replacements 340771 # number of replacements
> system.l2c.tagsinuse 65303.436480 # Cycle average of tags in use
> system.l2c.total_refs 2493415 # Total number of references to valid blocks.
> system.l2c.sampled_refs 405943 # Sample count of references to valid blocks.
> system.l2c.avg_refs 6.142279 # Average number of references to valid blocks.
> system.l2c.warmup_cycle 6937754751 # Cycle when the warmup percentage was hit.
> system.l2c.occ_blocks::writebacks 55559.705668 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.inst 4839.489270 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu0.data 4775.815267 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.inst 117.980929 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu1.data 10.445347 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.847774 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.inst 0.073845 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu0.data 0.072873 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.inst 0.001800 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu1.data 0.000159 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.996451 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu0.inst 902966 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 773506 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 86370 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 33767 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1796609 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 820435 # number of Writeback hits
> system.l2c.Writeback_hits::total 820435 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 171833 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 12858 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 184691 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 902966 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 945339 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 86370 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 46625 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1981300 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 902966 # number of overall hits
> system.l2c.overall_hits::cpu0.data 945339 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 86370 # number of overall hits
> system.l2c.overall_hits::cpu1.data 46625 # number of overall hits
> system.l2c.overall_hits::total 1981300 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 12959 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 271596 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 545 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 189 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 285289 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 27 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 100 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 115623 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 5918 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 121541 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 12959 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 387219 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 545 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 6107 # number of demand (read+write) misses
> system.l2c.demand_misses::total 406830 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 12959 # number of overall misses
> system.l2c.overall_misses::cpu0.data 387219 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 545 # number of overall misses
> system.l2c.overall_misses::cpu1.data 6107 # number of overall misses
> system.l2c.overall_misses::total 406830 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 800348000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 11682390000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 34833000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 14789000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 12532360000 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1038000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 229000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 1267000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 5536684000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 338210000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 5874894000 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 800348000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 17219074000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 34833000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 352999000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 18407254000 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 800348000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 17219074000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 34833000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 352999000 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 18407254000 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 915925 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 1045102 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 86915 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 33956 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2081898 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 820435 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 820435 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2605 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 48 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 140 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 287456 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 18776 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 306232 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 915925 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1332558 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 86915 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 52732 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2388130 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 915925 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1332558 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 86915 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 52732 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2388130 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.014149 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.259875 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.006270 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.005566 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.137033 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.937428 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.896104 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.930344 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.562500 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.793478 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.714286 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.402229 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.315190 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.396892 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.014149 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.290583 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.006270 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.115812 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.170355 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.014149 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.290583 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.006270 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.115812 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.170355 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 61760.012347 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 43013.851456 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 63913.761468 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 78248.677249 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 43928.647792 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 425.061425 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 474.120083 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 433.162393 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 833.333333 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1575.342466 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 1375 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 47885.662887 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57149.374789 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 48336.725879 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 61760.012347 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 44468.566883 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 63913.761468 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 57802.357950 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 45245.566944 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 61760.012347 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 44468.566883 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 63913.761468 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 57802.357950 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 45245.566944 # average overall miss latency
382,383c367,368
< system.l2c.writebacks::writebacks 78774 # number of writebacks
< system.l2c.writebacks::total 78774 # number of writebacks
---
> system.l2c.writebacks::writebacks 78433 # number of writebacks
> system.l2c.writebacks::total 78433 # number of writebacks
390,479c375,464
< system.l2c.ReadReq_mshr_misses::cpu0.inst 12972 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 271609 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 550 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 240 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 285371 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2946 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 1731 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 4677 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 877 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 894 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1771 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 115472 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 6625 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 122097 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 12972 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 387081 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 550 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 6865 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 407468 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 12972 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 387081 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 550 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 6865 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 407468 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 652870719 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8377504856 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 28860821 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15792455 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 9075028851 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29675441 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17410227 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 47085668 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8897310 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 8940894 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 17838204 # number of SCUpgradeReq MSHR miss cycles
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< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 291507382 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 4404420928 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 652870719 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 12490418402 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 28860821 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 307299837 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 13479449779 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 652870719 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 12490418402 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 28860821 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 307299837 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 13479449779 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1372964000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1391135500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2145152500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 673668500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2818821000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3518116500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 691840000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4209956500 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289728 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002211 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.138411 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.944836 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.765590 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.869492 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.956379 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975983 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966176 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476448 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.123527 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.412501 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.172821 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018524 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.328085 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001744 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.042324 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.172821 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30843.988439 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65801.895833 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 31800.809651 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.130007 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.901213 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10067.493693 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10145.165336 # average SCUpgradeReq mshr miss latency
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 12959 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 271596 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 534 # number of ReadReq MSHR misses
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> system.l2c.ReadReq_mshr_misses::total 285278 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2442 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 2925 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 27 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 100 # number of SCUpgradeReq MSHR misses
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> system.l2c.ReadExReq_mshr_misses::cpu1.data 5918 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 121541 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 12959 # number of demand (read+write) MSHR misses
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> system.l2c.demand_mshr_misses::cpu1.inst 534 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 6107 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 406819 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 12959 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 387219 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 534 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 6107 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 406819 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 637272201 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8347679089 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 27561783 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 12429436 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 9024942509 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 24585937 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4830483 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 29416420 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 270027 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles
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> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 263408851 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 4372253453 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 637272201 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 12456523691 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 27561783 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 275838287 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 13397195962 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 637272201 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 12456523691 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 27561783 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 275838287 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 13397195962 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373082000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1391253000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1972248000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 500755000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2473003000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3345330000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 518926000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 3864256000 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259875 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.005566 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.137028 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.937428 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.896104 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.930344 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.562500 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.793478 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.714286 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.402229 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.315190 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.396892 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.290583 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.170350 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.290583 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30735.648128 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65764.211640 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 31635.606352 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.951269 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10056.895726 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
481,494c466,479
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10072.390740 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35618.275824 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44001.114264 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 36073.129790 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency
---
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35536.568001 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44509.775431 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 35973.485927 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency
505,506c490,491
< system.iocache.replacements 41696 # number of replacements
< system.iocache.tagsinuse 0.569993 # Cycle average of tags in use
---
> system.iocache.replacements 41694 # number of replacements
> system.iocache.tagsinuse 0.572561 # Cycle average of tags in use
508c493
< system.iocache.sampled_refs 41712 # Sample count of references to valid blocks.
---
> system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
510,515c495,500
< system.iocache.warmup_cycle 1746698431000 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::tsunami.ide 0.569993 # Average occupied blocks per requestor
< system.iocache.occ_percent::tsunami.ide 0.035625 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.035625 # Average percentage of cache occupancy
< system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
---
> system.iocache.warmup_cycle 1746701282000 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::tsunami.ide 0.572561 # Average occupied blocks per requestor
> system.iocache.occ_percent::tsunami.ide 0.035785 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.035785 # Average percentage of cache occupancy
> system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
518,531c503,516
< system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses
< system.iocache.demand_misses::total 41728 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses
< system.iocache.overall_misses::total 41728 # number of overall misses
< system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles
< system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
> system.iocache.overall_misses::total 41726 # number of overall misses
> system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::tsunami.ide 10674900806 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 10674900806 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 10695943804 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 10695943804 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 10695943804 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 10695943804 # number of overall miss cycles
> system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
534,537c519,522
< system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
546,554c531,539
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256904.620861 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 256904.620861 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 256337.626516 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 256337.626516 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 286340 # number of cycles access was blocked
556c541
< system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked
558c543
< system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked
564,565c549,550
< system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
568,579c553,564
< system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles
588,595c573,580
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
613,614c598,599
< system.cpu0.dtb.read_hits 7490982 # DTB read hits
< system.cpu0.dtb.read_misses 7443 # DTB read misses
---
> system.cpu0.dtb.read_hits 8631552 # DTB read hits
> system.cpu0.dtb.read_misses 7447 # DTB read misses
616,617c601,602
< system.cpu0.dtb.read_accesses 490673 # DTB read accesses
< system.cpu0.dtb.write_hits 5068153 # DTB write hits
---
> system.cpu0.dtb.read_accesses 490676 # DTB read accesses
> system.cpu0.dtb.write_hits 6044616 # DTB write hits
621,622c606,607
< system.cpu0.dtb.data_hits 12559135 # DTB hits
< system.cpu0.dtb.data_misses 8256 # DTB misses
---
> system.cpu0.dtb.data_hits 14676168 # DTB hits
> system.cpu0.dtb.data_misses 8260 # DTB misses
624,625c609,610
< system.cpu0.dtb.data_accesses 678125 # DTB accesses
< system.cpu0.itb.fetch_hits 3503456 # ITB hits
---
> system.cpu0.dtb.data_accesses 678128 # DTB accesses
> system.cpu0.itb.fetch_hits 3853435 # ITB hits
628c613
< system.cpu0.itb.fetch_accesses 3507327 # ITB accesses
---
> system.cpu0.itb.fetch_accesses 3857306 # ITB accesses
641c626
< system.cpu0.numCycles 3904305293 # number of cpu cycles simulated
---
> system.cpu0.numCycles 3908211536 # number of cpu cycles simulated
644,662c629,647
< system.cpu0.committedInsts 47706703 # Number of instructions committed
< system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses
< system.cpu0.num_func_calls 1201591 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 44241786 # number of integer instructions
< system.cpu0.num_fp_insts 211423 # number of float instructions
< system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written
< system.cpu0.num_mem_refs 12599388 # number of memory refs
< system.cpu0.num_load_insts 7518173 # Number of load instructions
< system.cpu0.num_store_insts 5081215 # Number of store instructions
< system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles
< system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles
---
> system.cpu0.committedInsts 54061829 # Number of instructions committed
> system.cpu0.committedOps 54061829 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 50032862 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 294101 # Number of float alu accesses
> system.cpu0.num_func_calls 1426501 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 6236445 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 50032862 # number of integer instructions
> system.cpu0.num_fp_insts 294101 # number of float instructions
> system.cpu0.num_int_register_reads 68513770 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 37070851 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 143419 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 146520 # number of times the floating registers were written
> system.cpu0.num_mem_refs 14722187 # number of memory refs
> system.cpu0.num_load_insts 8662865 # Number of load instructions
> system.cpu0.num_store_insts 6059322 # Number of store instructions
> system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles
> system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles
664,684c649,669
< system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl
688,689c673,674
< system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_used::31 0.684859 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.808964 # fraction of swpipl calls that actually changed the ipl
721,738c706,723
< system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed
< system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed
< system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
< system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
< system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed
< system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
< system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
< system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed
< system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed
< system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
< system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed
< system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
< system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed
< system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed
< system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
< system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
< system.cpu0.kern.callpal::total 149953 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches
---
> system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed
> system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
> system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
> system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
> system.cpu0.kern.callpal::swpctx 3896 2.07% 2.12% # number of callpals executed
> system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed
> system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed
> system.cpu0.kern.callpal::swpipl 172217 91.50% 93.65% # number of callpals executed
> system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed
> system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed
> system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed
> system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
> system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed
> system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed
> system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
> system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
> system.cpu0.kern.callpal::total 188224 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches
744c729
< system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches
747,749c732,734
< system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode
751c736
< system.cpu0.kern.swap_context 3075 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 3897 # number of times the context was actually changed
783,827c768,812
< system.cpu0.icache.replacements 699703 # number of replacements
< system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use
< system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks.
< system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks.
< system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks.
< system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor
< system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy
< system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy
< system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits
< system.cpu0.icache.overall_hits::total 47014995 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses
< system.cpu0.icache.overall_misses::total 700308 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency
---
> system.cpu0.icache.replacements 915312 # number of replacements
> system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use
> system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks.
> system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks.
> system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks.
> system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor
> system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy
> system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy
> system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 53154487 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 53154487 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 53154487 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 53154487 # number of overall hits
> system.cpu0.icache.overall_hits::total 53154487 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 915946 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 915946 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 915946 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses
> system.cpu0.icache.overall_misses::total 915946 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 54070433 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 54070433 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 54070433 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016940 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.016940 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency
836,859c821,844
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700308 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 700308 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 700308 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 700308 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 700308 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 700308 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8450781000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 8450781000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8450781000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 8450781000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8450781000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 8450781000 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.234702 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915946 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 915946 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 915946 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 915946 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 915946 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 915946 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813261500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813261500 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813261500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 10813261500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813261500 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 10813261500 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency
861,865c846,850
< system.cpu0.dcache.replacements 1182211 # number of replacements
< system.cpu0.dcache.tagsinuse 505.184188 # Cycle average of tags in use
< system.cpu0.dcache.total_refs 11367781 # Total number of references to valid blocks.
< system.cpu0.dcache.sampled_refs 1182629 # Sample count of references to valid blocks.
< system.cpu0.dcache.avg_refs 9.612297 # Average number of references to valid blocks.
---
> system.cpu0.dcache.replacements 1337909 # number of replacements
> system.cpu0.dcache.tagsinuse 506.537579 # Cycle average of tags in use
> system.cpu0.dcache.total_refs 13346950 # Total number of references to valid blocks.
> system.cpu0.dcache.sampled_refs 1338324 # Sample count of references to valid blocks.
> system.cpu0.dcache.avg_refs 9.972884 # Average number of references to valid blocks.
867,941c852,926
< system.cpu0.dcache.occ_blocks::cpu0.data 505.184188 # Average occupied blocks per requestor
< system.cpu0.dcache.occ_percent::cpu0.data 0.986688 # Average percentage of cache occupancy
< system.cpu0.dcache.occ_percent::total 0.986688 # Average percentage of cache occupancy
< system.cpu0.dcache.ReadReq_hits::cpu0.data 6409561 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 6409561 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 4659572 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 4659572 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140562 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 140562 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148239 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 148239 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 11069133 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 11069133 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 11069133 # number of overall hits
< system.cpu0.dcache.overall_hits::total 11069133 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 939643 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 939643 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 251886 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 251886 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13649 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 13649 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5418 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 5418 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 1191529 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 1191529 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 1191529 # number of overall misses
< system.cpu0.dcache.overall_misses::total 1191529 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 21121102500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 21121102500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7642676000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 7642676000 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149168500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 149168500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41236000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 41236000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 28763778500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 28763778500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 28763778500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 28763778500 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 7349204 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 7349204 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4911458 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4911458 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154211 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 154211 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153657 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 153657 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 12260662 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 12260662 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 12260662 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 12260662 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127856 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.127856 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051285 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.051285 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088509 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088509 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035260 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035260 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097183 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.097183 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097183 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.097183 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 22477.794758 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 22477.794758 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30341.805420 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 30341.805420 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10928.895890 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10928.895890 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7610.926541 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7610.926541 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 24140.225290 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24140.225290 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 24140.225290 # average overall miss latency
---
> system.cpu0.dcache.occ_blocks::cpu0.data 506.537579 # Average occupied blocks per requestor
> system.cpu0.dcache.occ_percent::cpu0.data 0.989331 # Average percentage of cache occupancy
> system.cpu0.dcache.occ_percent::total 0.989331 # Average percentage of cache occupancy
> system.cpu0.dcache.ReadReq_hits::cpu0.data 7419116 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 7419116 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 5560491 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 5560491 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 12979607 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 12979607 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 12979607 # number of overall hits
> system.cpu0.dcache.overall_hits::total 12979607 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 1035921 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 1035921 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 291041 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 291041 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 1326962 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1326962 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1326962 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1326962 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391252000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 22391252000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190685500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 8190685500 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 30581937500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 30581937500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 30581937500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 30581937500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 5851532 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193066 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 193066 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192099 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 192099 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 14306569 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122521 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.122521 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049738 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.049738 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.720441 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency
950,1005c935,990
< system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks
< system.cpu0.dcache.writebacks::total 680601 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7138904000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7138904000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks
> system.cpu0.dcache.writebacks::total 789805 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1326962 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326962 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1326962 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319410000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319410000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608603500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608603500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928013500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928013500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 27928013500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465455500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465455500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092162000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency
1017c1002
< system.cpu1.dtb.read_hits 2417694 # DTB read hits
---
> system.cpu1.dtb.read_hits 1047086 # DTB read hits
1021c1006
< system.cpu1.dtb.write_hits 1754404 # DTB write hits
---
> system.cpu1.dtb.write_hits 650181 # DTB write hits
1025c1010
< system.cpu1.dtb.data_hits 4172098 # DTB hits
---
> system.cpu1.dtb.data_hits 1697267 # DTB hits
1029c1014
< system.cpu1.itb.fetch_hits 1961503 # ITB hits
---
> system.cpu1.itb.fetch_hits 1487534 # ITB hits
1032c1017
< system.cpu1.itb.fetch_accesses 1962719 # ITB accesses
---
> system.cpu1.itb.fetch_accesses 1488750 # ITB accesses
1045c1030
< system.cpu1.numCycles 3905448539 # number of cpu cycles simulated
---
> system.cpu1.numCycles 3909382743 # number of cpu cycles simulated
1048,1066c1033,1051
< system.cpu1.committedInsts 13160532 # Number of instructions committed
< system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses
< system.cpu1.num_func_calls 411397 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 12141335 # number of integer instructions
< system.cpu1.num_fp_insts 171917 # number of float instructions
< system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read
< system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written
< system.cpu1.num_mem_refs 4195541 # number of memory refs
< system.cpu1.num_load_insts 2431931 # Number of load instructions
< system.cpu1.num_store_insts 1763610 # Number of store instructions
< system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles
< system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles
---
> system.cpu1.committedInsts 5259785 # Number of instructions committed
> system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
> system.cpu1.num_func_calls 156703 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 4928462 # number of integer instructions
> system.cpu1.num_fp_insts 34031 # number of float instructions
> system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
> system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
> system.cpu1.num_mem_refs 1706720 # number of memory refs
> system.cpu1.num_load_insts 1053093 # Number of load instructions
> system.cpu1.num_store_insts 653627 # Number of store instructions
> system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles
> system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles
1068,1085c1053,1070
< system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl
1088,1089c1073,1074
< system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl
1105,1118c1090,1103
< system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed
< system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
< system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
< system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed
< system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed
< system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed
< system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed
< system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed
< system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed
< system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed
< system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed
< system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed
< system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
< system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
---
> system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed
> system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
> system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
> system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed
> system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed
> system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed
> system.cpu1.kern.callpal::swpipl 23653 81.85% 83.08% # number of callpals executed
> system.cpu1.kern.callpal::rdps 2170 7.51% 90.59% # number of callpals executed
> system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed
> system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed
> system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed
> system.cpu1.kern.callpal::rti 2530 8.75% 99.37% # number of callpals executed
> system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed
> system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed
1120,1127c1105,1112
< system.cpu1.kern.callpal::total 71284 # number of callpals executed
< system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches
< system.cpu1.kern.mode_switch::user 465 # number of protection mode switches
< system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches
< system.cpu1.kern.mode_good::kernel 889
< system.cpu1.kern.mode_good::user 465
< system.cpu1.kern.mode_good::idle 424
< system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches
---
> system.cpu1.kern.callpal::total 28898 # number of callpals executed
> system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches
> system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
> system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches
> system.cpu1.kern.mode_good::kernel 477
> system.cpu1.kern.mode_good::user 464
> system.cpu1.kern.mode_good::idle 13
> system.cpu1.kern.mode_switch_good::kernel 0.594022 # fraction of useful protection mode switches
1129,1179c1114,1164
< system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode
< system.cpu1.kern.swap_context 1984 # number of times the context was actually changed
< system.cpu1.icache.replacements 314891 # number of replacements
< system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use
< system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks.
< system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks.
< system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks.
< system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor
< system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy
< system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy
< system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits
< system.cpu1.icache.overall_hits::total 12848456 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses
< system.cpu1.icache.overall_misses::total 315439 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency
---
> system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 3558805000 0.18% 0.18% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 1714794500 0.09% 0.27% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1949417010500 99.73% 100.00% # number of ticks spent at the given mode
> system.cpu1.kern.swap_context 338 # number of times the context was actually changed
> system.cpu1.icache.replacements 86368 # number of replacements
> system.cpu1.icache.tagsinuse 420.702382 # Cycle average of tags in use
> system.cpu1.icache.total_refs 5176232 # Total number of references to valid blocks.
> system.cpu1.icache.sampled_refs 86880 # Sample count of references to valid blocks.
> system.cpu1.icache.avg_refs 59.579098 # Average number of references to valid blocks.
> system.cpu1.icache.warmup_cycle 1938927920500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.occ_blocks::cpu1.inst 420.702382 # Average occupied blocks per requestor
> system.cpu1.icache.occ_percent::cpu1.inst 0.821684 # Average percentage of cache occupancy
> system.cpu1.icache.occ_percent::total 0.821684 # Average percentage of cache occupancy
> system.cpu1.icache.ReadReq_hits::cpu1.inst 5176232 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 5176232 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 5176232 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 5176232 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 5176232 # number of overall hits
> system.cpu1.icache.overall_hits::total 5176232 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 86916 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 86916 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 86916 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses
> system.cpu1.icache.overall_misses::total 86916 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 5263148 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 5263148 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 5263148 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016514 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency
1188,1211c1173,1196
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315439 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 315439 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 315439 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 315439 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 315439 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 315439 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3538039000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 3538039000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11216.238322 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86916 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 86916 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002119500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002119500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
1213,1293c1198,1278
< system.cpu1.dcache.replacements 165415 # number of replacements
< system.cpu1.dcache.tagsinuse 486.567196 # Cycle average of tags in use
< system.cpu1.dcache.total_refs 4004380 # Total number of references to valid blocks.
< system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks.
< system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks.
< system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor
< system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy
< system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy
< system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 47962 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50536 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 50536 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 3891916 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 3891916 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 3891916 # number of overall hits
< system.cpu1.dcache.overall_hits::total 3891916 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 117672 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 117672 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 62334 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 62334 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8861 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 8861 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5817 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 5817 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 180006 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 180006 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 180006 # number of overall misses
< system.cpu1.dcache.overall_misses::total 180006 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427906500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 1427906500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1084822000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 1084822000 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81394000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 81394000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 42192000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 42192000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 2512728500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 2512728500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 2512728500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 2512728500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 2372023 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 2372023 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 1699899 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 1699899 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56823 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 56823 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56353 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 56353 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 4071922 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 4071922 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 4071922 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 4071922 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049608 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.049608 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036669 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.036669 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155940 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency
---
> system.cpu1.dcache.replacements 52807 # number of replacements
> system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use
> system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks.
> system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks.
> system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks.
> system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor
> system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy
> system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy
> system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 1617458 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 1617458 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 1617458 # number of overall hits
> system.cpu1.dcache.overall_hits::total 1617458 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 37008 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 37008 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 57409 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 57409 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 57409 # number of overall misses
> system.cpu1.dcache.overall_misses::total 57409 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463706500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 463706500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540901000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 540901000 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10601500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 10601500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3694000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 3694000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 1004607500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 1004607500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 1004607500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 1004607500 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 636621 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11762 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 11762 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11703 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 11703 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 1674867 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 1674867 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035645 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081279 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042724 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042724 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency
1302,1357c1287,1342
< system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks
< system.cpu1.dcache.writebacks::total 113605 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks
> system.cpu1.dcache.writebacks::total 30630 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081279 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042724 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042724 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency