7,11c7,11
< host_inst_rate 753764 # Simulator instruction rate (inst/s)
< host_op_rate 753764 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 24497172234 # Simulator tick rate (ticks/s)
< host_mem_usage 320072 # Number of bytes of host memory used
< host_seconds 80.93 # Real time elapsed on the host
---
> host_inst_rate 1178528 # Simulator instruction rate (inst/s)
> host_op_rate 1178528 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 38301918928 # Simulator tick rate (ticks/s)
> host_mem_usage 332884 # Number of bytes of host memory used
> host_seconds 51.76 # Real time elapsed on the host
583,584d582
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
619,622c617,618
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451870500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451870500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4018772500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4018772500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566902000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566902000 # number of overall MSHR uncacheable cycles
649,653c645,646
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306 # average overall mshr uncacheable latency
711,712d703
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
739d729
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
992,993d981
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1028,1031c1016,1017
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 25051000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 25051000 # number of overall MSHR uncacheable cycles
1058,1062c1044,1045
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7227.639931 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7227.639931 # average overall mshr uncacheable latency
1122,1123d1104
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1150d1130
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1235,1238c1215,1218
< system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
< system.iocache.demand_misses::total 175 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
< system.iocache.overall_misses::total 175 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
> system.iocache.overall_misses::total 41727 # number of overall misses
1243,1246c1223,1226
< system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5267103412 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5267103412 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5267103412 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5267103412 # number of overall miss cycles
1251,1254c1231,1234
< system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
1267,1270c1247,1250
< system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126227.704172 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126227.704172 # average overall miss latency
1277,1278d1256
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1285,1288c1263,1266
< system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
1293,1296c1271,1274
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3178946624 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3178946624 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3178946624 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3178946624 # number of overall MSHR miss cycles
1309,1313c1287,1290
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency
1504,1505d1480
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
1578,1583c1553,1555
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2327774501 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 750967500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 3078742001 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3806101501 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 774543000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4580644501 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1478327000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 23575500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 1501902500 # number of overall MSHR uncacheable cycles
1639,1645c1611,1613
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82745.270346 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 6801.933064 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 70406.080068 # average overall mshr uncacheable latency
< host_inst_rate 753764 # Simulator instruction rate (inst/s)
< host_op_rate 753764 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 24497172234 # Simulator tick rate (ticks/s)
< host_mem_usage 320072 # Number of bytes of host memory used
< host_seconds 80.93 # Real time elapsed on the host
---
> host_inst_rate 1178528 # Simulator instruction rate (inst/s)
> host_op_rate 1178528 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 38301918928 # Simulator tick rate (ticks/s)
> host_mem_usage 332884 # Number of bytes of host memory used
> host_seconds 51.76 # Real time elapsed on the host
583,584d582
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
619,622c617,618
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451870500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451870500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4018772500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4018772500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566902000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566902000 # number of overall MSHR uncacheable cycles
649,653c645,646
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306 # average overall mshr uncacheable latency
711,712d703
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
739d729
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
992,993d981
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1028,1031c1016,1017
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 25051000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 25051000 # number of overall MSHR uncacheable cycles
1058,1062c1044,1045
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7227.639931 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7227.639931 # average overall mshr uncacheable latency
1122,1123d1104
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1150d1130
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1235,1238c1215,1218
< system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
< system.iocache.demand_misses::total 175 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
< system.iocache.overall_misses::total 175 # number of overall misses
---
> system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
> system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
> system.iocache.overall_misses::total 41727 # number of overall misses
1243,1246c1223,1226
< system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::tsunami.ide 5267103412 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 5267103412 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 5267103412 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 5267103412 # number of overall miss cycles
1251,1254c1231,1234
< system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
1267,1270c1247,1250
< system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126227.704172 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126227.704172 # average overall miss latency
1277,1278d1256
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1285,1288c1263,1266
< system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
1293,1296c1271,1274
< system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::tsunami.ide 3178946624 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3178946624 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 3178946624 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3178946624 # number of overall MSHR miss cycles
1309,1313c1287,1290
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency
1504,1505d1480
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
1578,1583c1553,1555
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2327774501 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 750967500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 3078742001 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3806101501 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 774543000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4580644501 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1478327000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 23575500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 1501902500 # number of overall MSHR uncacheable cycles
1639,1645c1611,1613
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82745.270346 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 6801.933064 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 70406.080068 # average overall mshr uncacheable latency