7,11c7,11
< host_inst_rate 1121045 # Simulator instruction rate (inst/s)
< host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 36128483856 # Simulator tick rate (ticks/s)
< host_mem_usage 373592 # Number of bytes of host memory used
< host_seconds 54.32 # Real time elapsed on the host
---
> host_inst_rate 1051716 # Simulator instruction rate (inst/s)
> host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 33894179183 # Simulator tick rate (ticks/s)
> host_mem_usage 374244 # Number of bytes of host memory used
> host_seconds 57.90 # Real time elapsed on the host
274,275c274,275
< system.physmem.totQLat 2137453500 # Total ticks spent queuing
< system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2137457500 # Total ticks spent queuing
> system.physmem.totMemAccLat 9763982500 # Total ticks spent from burst creation until serviced by the DRAM
277c277
< system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5254.99 # Average queueing delay per DRAM burst
279c279
< system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24004.99 # Average memory access latency per DRAM burst
301,303c301,303
< system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ)
---
> system.physmem_0.actBackEnergy 66287824245 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1119418910250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1316300550720 # Total energy per rank (pJ)
305c305
< system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 1862013796212 # Time in different power states
308c308
< system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 35060565038 # Time in different power states
315,317c315,317
< system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ)
---
> system.physmem_1.actBackEnergy 66523575105 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1119212111250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1316364135975 # Total energy per rank (pJ)
319c319
< system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 1861673236216 # Time in different power states
322c322
< system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 35401125034 # Time in different power states
545,546c545,546
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles
---
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906402435 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 10906402435 # number of WriteReq miss cycles
551,554c551,554
< system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 39966793434 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 39966793434 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 39966793434 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 39966793434 # number of overall miss cycles
581,582c581,582
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency
---
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232 # average WriteReq miss latency
587,590c587,590
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101 # average overall miss latency
615,616c615,616
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476948315 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476948315 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles
621,624c621,624
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003535066 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 38003535066 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003535066 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 38003535066 # number of overall MSHR miss cycles
627,630c627,630
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768311500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles
645,646c645,646
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.195596 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.195596 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497 # average WriteReq mshr miss latency
651,654c651,654
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
796,797c796,797
< system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles
< system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles
---
> system.cpu1.num_idle_cycles 3876126901.998025 # Number of idle cycles
> system.cpu1.num_busy_cycles 49098471.001975 # Number of busy cycles
948,949c948,949
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81194500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 81194500 # number of LoadLockedReq miss cycles
---
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81193500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 81193500 # number of LoadLockedReq miss cycles
984,985c984,985
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.649316 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.649316 # average LoadLockedReq miss latency
---
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.537133 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.537133 # average LoadLockedReq miss latency
1018,1019c1018,1019
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67823500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67823500 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles
1026,1031c1026,1031
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18864000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18864000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716373000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716373000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735237000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735237000 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18866000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18866000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716370000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716370000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735236000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735236000 # number of overall MSHR uncacheable cycles
1048,1049c1048,1049
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.649316 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency
---
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency
1326c1326
< system.l2c.tags.tagsinuse 65207.739778 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 65207.739779 # Cycle average of tags in use
1412c1412
< system.l2c.ReadExReq_miss_latency::cpu0.data 8793297261 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu0.data 8793301011 # number of ReadExReq miss cycles
1414c1414
< system.l2c.ReadExReq_miss_latency::total 9333391997 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::total 9333395747 # number of ReadExReq miss cycles
1416c1416
< system.l2c.demand_miss_latency::cpu0.data 28494183761 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.data 28494187511 # number of demand (read+write) miss cycles
1419c1419
< system.l2c.demand_miss_latency::total 30142853497 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::total 30142857247 # number of demand (read+write) miss cycles
1421c1421
< system.l2c.overall_miss_latency::cpu0.data 28494183761 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.data 28494187511 # number of overall miss cycles
1424c1424
< system.l2c.overall_miss_latency::total 30142853497 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::total 30142857247 # number of overall miss cycles
1486c1486
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.823034 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.855466 # average ReadExReq miss latency
1488c1488
< system.l2c.ReadExReq_avg_miss_latency::total 76368.004165 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::total 76368.034848 # average ReadExReq miss latency
1490c1490
< system.l2c.demand_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency
1493c1493
< system.l2c.demand_avg_miss_latency::total 73949.686337 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::total 73949.695537 # average overall miss latency
1495c1495
< system.l2c.overall_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency
1498c1498
< system.l2c.overall_avg_miss_latency::total 73949.686337 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::total 73949.695537 # average overall miss latency
1553c1553
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347142739 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347146989 # number of ReadExReq MSHR miss cycles
1555c1555
< system.l2c.ReadExReq_mshr_miss_latency::total 7804866503 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::total 7804870753 # number of ReadExReq MSHR miss cycles
1557c1557
< system.l2c.demand_mshr_miss_latency::cpu0.data 23652210239 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.data 23652214489 # number of demand (read+write) MSHR miss cycles
1560c1560
< system.l2c.demand_mshr_miss_latency::total 25045400003 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 25045404253 # number of demand (read+write) MSHR miss cycles
1562c1562
< system.l2c.overall_mshr_miss_latency::cpu0.data 23652210239 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.data 23652214489 # number of overall MSHR miss cycles
1565c1565
< system.l2c.overall_mshr_miss_latency::total 25045400003 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 25045404253 # number of overall MSHR miss cycles
1567,1574c1567,1574
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17618000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1392494000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153053500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674538500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2827592000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527929500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4220086000 # number of overall MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17620000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1392496000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153050500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674536000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2827586500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527926500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 4220082500 # number of overall MSHR uncacheable cycles
1610c1610
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777 # average ReadExReq mshr miss latency
1612c1612
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554 # average ReadExReq mshr miss latency
1614c1614
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency
1617c1617
< system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
1619c1619
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency
1622c1622
< system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
1669c1669
< system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks)
1673c1673
< system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks)
1718c1718
< system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks)
< host_inst_rate 1121045 # Simulator instruction rate (inst/s)
< host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 36128483856 # Simulator tick rate (ticks/s)
< host_mem_usage 373592 # Number of bytes of host memory used
< host_seconds 54.32 # Real time elapsed on the host
---
> host_inst_rate 1051716 # Simulator instruction rate (inst/s)
> host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 33894179183 # Simulator tick rate (ticks/s)
> host_mem_usage 374244 # Number of bytes of host memory used
> host_seconds 57.90 # Real time elapsed on the host
274,275c274,275
< system.physmem.totQLat 2137453500 # Total ticks spent queuing
< system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2137457500 # Total ticks spent queuing
> system.physmem.totMemAccLat 9763982500 # Total ticks spent from burst creation until serviced by the DRAM
277c277
< system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5254.99 # Average queueing delay per DRAM burst
279c279
< system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24004.99 # Average memory access latency per DRAM burst
301,303c301,303
< system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ)
---
> system.physmem_0.actBackEnergy 66287824245 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1119418910250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1316300550720 # Total energy per rank (pJ)
305c305
< system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 1862013796212 # Time in different power states
308c308
< system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 35060565038 # Time in different power states
315,317c315,317
< system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ)
---
> system.physmem_1.actBackEnergy 66523575105 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1119212111250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1316364135975 # Total energy per rank (pJ)
319c319
< system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 1861673236216 # Time in different power states
322c322
< system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 35401125034 # Time in different power states
545,546c545,546
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles
---
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906402435 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 10906402435 # number of WriteReq miss cycles
551,554c551,554
< system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 39966793434 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 39966793434 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 39966793434 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 39966793434 # number of overall miss cycles
581,582c581,582
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency
---
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232 # average WriteReq miss latency
587,590c587,590
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101 # average overall miss latency
615,616c615,616
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476948315 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476948315 # number of WriteReq MSHR miss cycles
---
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles
621,624c621,624
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003535066 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 38003535066 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003535066 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 38003535066 # number of overall MSHR miss cycles
627,630c627,630
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768311500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles
645,646c645,646
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.195596 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.195596 # average WriteReq mshr miss latency
---
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497 # average WriteReq mshr miss latency
651,654c651,654
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
796,797c796,797
< system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles
< system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles
---
> system.cpu1.num_idle_cycles 3876126901.998025 # Number of idle cycles
> system.cpu1.num_busy_cycles 49098471.001975 # Number of busy cycles
948,949c948,949
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81194500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 81194500 # number of LoadLockedReq miss cycles
---
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81193500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 81193500 # number of LoadLockedReq miss cycles
984,985c984,985
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.649316 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.649316 # average LoadLockedReq miss latency
---
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.537133 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.537133 # average LoadLockedReq miss latency
1018,1019c1018,1019
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67823500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67823500 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles
1026,1031c1026,1031
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18864000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18864000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716373000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716373000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735237000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735237000 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18866000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18866000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716370000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716370000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735236000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735236000 # number of overall MSHR uncacheable cycles
1048,1049c1048,1049
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.649316 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency
---
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency
1326c1326
< system.l2c.tags.tagsinuse 65207.739778 # Cycle average of tags in use
---
> system.l2c.tags.tagsinuse 65207.739779 # Cycle average of tags in use
1412c1412
< system.l2c.ReadExReq_miss_latency::cpu0.data 8793297261 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::cpu0.data 8793301011 # number of ReadExReq miss cycles
1414c1414
< system.l2c.ReadExReq_miss_latency::total 9333391997 # number of ReadExReq miss cycles
---
> system.l2c.ReadExReq_miss_latency::total 9333395747 # number of ReadExReq miss cycles
1416c1416
< system.l2c.demand_miss_latency::cpu0.data 28494183761 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::cpu0.data 28494187511 # number of demand (read+write) miss cycles
1419c1419
< system.l2c.demand_miss_latency::total 30142853497 # number of demand (read+write) miss cycles
---
> system.l2c.demand_miss_latency::total 30142857247 # number of demand (read+write) miss cycles
1421c1421
< system.l2c.overall_miss_latency::cpu0.data 28494183761 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::cpu0.data 28494187511 # number of overall miss cycles
1424c1424
< system.l2c.overall_miss_latency::total 30142853497 # number of overall miss cycles
---
> system.l2c.overall_miss_latency::total 30142857247 # number of overall miss cycles
1486c1486
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.823034 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.855466 # average ReadExReq miss latency
1488c1488
< system.l2c.ReadExReq_avg_miss_latency::total 76368.004165 # average ReadExReq miss latency
---
> system.l2c.ReadExReq_avg_miss_latency::total 76368.034848 # average ReadExReq miss latency
1490c1490
< system.l2c.demand_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency
1493c1493
< system.l2c.demand_avg_miss_latency::total 73949.686337 # average overall miss latency
---
> system.l2c.demand_avg_miss_latency::total 73949.695537 # average overall miss latency
1495c1495
< system.l2c.overall_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency
1498c1498
< system.l2c.overall_avg_miss_latency::total 73949.686337 # average overall miss latency
---
> system.l2c.overall_avg_miss_latency::total 73949.695537 # average overall miss latency
1553c1553
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347142739 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347146989 # number of ReadExReq MSHR miss cycles
1555c1555
< system.l2c.ReadExReq_mshr_miss_latency::total 7804866503 # number of ReadExReq MSHR miss cycles
---
> system.l2c.ReadExReq_mshr_miss_latency::total 7804870753 # number of ReadExReq MSHR miss cycles
1557c1557
< system.l2c.demand_mshr_miss_latency::cpu0.data 23652210239 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::cpu0.data 23652214489 # number of demand (read+write) MSHR miss cycles
1560c1560
< system.l2c.demand_mshr_miss_latency::total 25045400003 # number of demand (read+write) MSHR miss cycles
---
> system.l2c.demand_mshr_miss_latency::total 25045404253 # number of demand (read+write) MSHR miss cycles
1562c1562
< system.l2c.overall_mshr_miss_latency::cpu0.data 23652210239 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::cpu0.data 23652214489 # number of overall MSHR miss cycles
1565c1565
< system.l2c.overall_mshr_miss_latency::total 25045400003 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_miss_latency::total 25045404253 # number of overall MSHR miss cycles
1567,1574c1567,1574
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17618000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1392494000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153053500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674538500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2827592000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527929500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 4220086000 # number of overall MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17620000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1392496000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153050500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674536000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2827586500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527926500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 4220082500 # number of overall MSHR uncacheable cycles
1610c1610
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777 # average ReadExReq mshr miss latency
1612c1612
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554 # average ReadExReq mshr miss latency
1614c1614
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency
1617c1617
< system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency
---
> system.l2c.demand_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
1619c1619
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency
1622c1622
< system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency
---
> system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
1669c1669
< system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks)
1673c1673
< system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks)
1718c1718
< system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks)