7,11c7,11
< host_inst_rate 855480 # Simulator instruction rate (inst/s)
< host_op_rate 855480 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 27561784483 # Simulator tick rate (ticks/s)
< host_mem_usage 318220 # Number of bytes of host memory used
< host_seconds 71.18 # Real time elapsed on the host
---
> host_inst_rate 1248737 # Simulator instruction rate (inst/s)
> host_op_rate 1248737 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 40231703865 # Simulator tick rate (ticks/s)
> host_mem_usage 312404 # Number of bytes of host memory used
> host_seconds 48.76 # Real time elapsed on the host
731,732d730
< system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
< system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
747,748d744
< system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
755,756c751,752
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide inf # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency