3,5c3,5
< sim_seconds 1.962815 # Number of seconds simulated
< sim_ticks 1962815218500 # Number of ticks simulated
< final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.961827 # Number of seconds simulated
> sim_ticks 1961826628500 # Number of ticks simulated
> final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1506000 # Simulator instruction rate (inst/s)
< host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 49787604582 # Simulator tick rate (ticks/s)
< host_mem_usage 317424 # Number of bytes of host memory used
< host_seconds 39.42 # Real time elapsed on the host
< sim_insts 59372159 # Number of instructions simulated
< sim_ops 59372159 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1388652 # Simulator instruction rate (inst/s)
> host_op_rate 1388652 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 44739465331 # Simulator tick rate (ticks/s)
> host_mem_usage 370560 # Number of bytes of host memory used
> host_seconds 43.85 # Real time elapsed on the host
> sim_insts 60892387 # Number of instructions simulated
> sim_ops 60892387 # Number of ops (including micro ops) simulated
16,17c16,17
< system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory
19,25c19,25
< system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory
< system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 336832 # Number of bytes read from this memory
> system.physmem.bytes_read::total 26103680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 833152 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 31872 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5078656 # Number of bytes written to this memory
27,29c27,29
< system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 7737984 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.inst 13018 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 389076 # Number of read requests responded to by this memory
31,34c31,34
< system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 498 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 5263 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 407870 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 79354 # Number of write requests responded to by this memory
36,38c36,38
< system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 120906 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.inst 424682 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 12692693 # Total read bandwidth from this memory (bytes/s)
40,65c40,65
< system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 408000 # Number of read requests accepted
< system.physmem.writeReqs 121085 # Number of write requests accepted
< system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue
< system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_read::cpu1.inst 16246 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 171693 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 13305804 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 424682 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 16246 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 440928 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2588738 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::tsunami.ide 1355537 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3944275 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2588738 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 424682 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 12692693 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::tsunami.ide 1356026 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 16246 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 171693 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 17250079 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 407870 # Number of read requests accepted
> system.physmem.writeReqs 120906 # Number of write requests accepted
> system.physmem.readBursts 407870 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 120906 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 26092032 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue
> system.physmem.bytesWritten 7736064 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 26103680 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 7737984 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue
67,99c67,99
< system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 25223 # Per bank write bursts
< system.physmem.perBankRdBursts::1 25569 # Per bank write bursts
< system.physmem.perBankRdBursts::2 25254 # Per bank write bursts
< system.physmem.perBankRdBursts::3 25702 # Per bank write bursts
< system.physmem.perBankRdBursts::4 25695 # Per bank write bursts
< system.physmem.perBankRdBursts::5 25237 # Per bank write bursts
< system.physmem.perBankRdBursts::6 25154 # Per bank write bursts
< system.physmem.perBankRdBursts::7 25289 # Per bank write bursts
< system.physmem.perBankRdBursts::8 25197 # Per bank write bursts
< system.physmem.perBankRdBursts::9 25673 # Per bank write bursts
< system.physmem.perBankRdBursts::10 25761 # Per bank write bursts
< system.physmem.perBankRdBursts::11 25821 # Per bank write bursts
< system.physmem.perBankRdBursts::12 25887 # Per bank write bursts
< system.physmem.perBankRdBursts::13 25811 # Per bank write bursts
< system.physmem.perBankRdBursts::14 25568 # Per bank write bursts
< system.physmem.perBankRdBursts::15 24971 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7862 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7635 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7481 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8078 # Per bank write bursts
< system.physmem.perBankWrBursts::4 7635 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7244 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7160 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6937 # Per bank write bursts
< system.physmem.perBankWrBursts::8 6882 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7297 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7429 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7398 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8124 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8265 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8169 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7464 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 6995 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 25277 # Per bank write bursts
> system.physmem.perBankRdBursts::1 25718 # Per bank write bursts
> system.physmem.perBankRdBursts::2 25598 # Per bank write bursts
> system.physmem.perBankRdBursts::3 25075 # Per bank write bursts
> system.physmem.perBankRdBursts::4 25186 # Per bank write bursts
> system.physmem.perBankRdBursts::5 25258 # Per bank write bursts
> system.physmem.perBankRdBursts::6 25824 # Per bank write bursts
> system.physmem.perBankRdBursts::7 25548 # Per bank write bursts
> system.physmem.perBankRdBursts::8 25573 # Per bank write bursts
> system.physmem.perBankRdBursts::9 25196 # Per bank write bursts
> system.physmem.perBankRdBursts::10 25177 # Per bank write bursts
> system.physmem.perBankRdBursts::11 25610 # Per bank write bursts
> system.physmem.perBankRdBursts::12 25669 # Per bank write bursts
> system.physmem.perBankRdBursts::13 25717 # Per bank write bursts
> system.physmem.perBankRdBursts::14 26016 # Per bank write bursts
> system.physmem.perBankRdBursts::15 25246 # Per bank write bursts
> system.physmem.perBankWrBursts::0 7929 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7788 # Per bank write bursts
> system.physmem.perBankWrBursts::2 7545 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7026 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7134 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7133 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7657 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7252 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7395 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7084 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7119 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7401 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7832 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8315 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8567 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7699 # Per bank write bursts
101,102c101,102
< system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
< system.physmem.totGap 1962808109000 # Total gap between requests
---
> system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
> system.physmem.totGap 1961819616500 # Total gap between requests
109c109
< system.physmem.readPktSize::6 408000 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 407870 # Read request sizes (log2)
116,118c116,118
< system.physmem.writePktSize::6 121085 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 120906 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 407616 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see
164,230c164,230
< system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6272 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7040 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7344 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8568 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8887 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8584 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8726 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6736 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 5915 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5652 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5640 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5632 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 158 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 55 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 1871 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2613 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5895 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6008 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6964 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7304 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8598 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8970 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8975 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8647 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8791 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6804 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5901 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 5642 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 5617 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 148 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 82 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 61 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 66427 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 509.252202 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 306.095148 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 413.238328 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 15972 24.04% 24.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 12116 18.24% 42.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5140 7.74% 50.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2994 4.51% 54.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 3304 4.97% 59.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1746 2.63% 62.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1491 2.24% 64.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1317 1.98% 66.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 22347 33.64% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 66427 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5433 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 75.036996 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 2192.886898 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 5428 99.91% 99.91% # Reads before turning the bus around for writes
236,275c236,272
< system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 2 0.04% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 5 0.09% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 8 0.15% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 2 0.04% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5433 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5433 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 22.248482 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 19.059784 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 19.984616 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4773 87.85% 87.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 17 0.31% 88.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 17 0.31% 88.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 237 4.36% 92.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 33 0.61% 93.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 9 0.17% 93.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 6 0.11% 93.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 9 0.17% 93.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 24 0.44% 94.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 1 0.02% 94.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 10 0.18% 94.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 6 0.11% 94.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 3 0.06% 94.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 4 0.07% 94.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 32 0.59% 95.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 11 0.20% 95.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 3 0.06% 95.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 9 0.17% 95.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 180 3.31% 99.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 4 0.07% 99.17% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.02% 99.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 3 0.06% 99.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.02% 99.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 4 0.07% 99.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 4 0.07% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 5 0.09% 99.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 7 0.13% 99.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 13 0.24% 99.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 2 0.04% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.02% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 1 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 1 0.02% 99.96% # Writes before turning the bus around for reads
277,281c274,278
< system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads
< system.physmem.totQLat 2167934250 # Total ticks spent queuing
< system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 5433 # Writes before turning the bus around for reads
> system.physmem.totQLat 2198653000 # Total ticks spent queuing
> system.physmem.totMemAccLat 9842803000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2038440000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 5392.98 # Average queueing delay per DRAM burst
283c280
< system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24142.98 # Average memory access latency per DRAM burst
285,287c282,284
< system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s
293,301c290,298
< system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing
< system.physmem.readRowHits 365758 # Number of row buffer hits during reads
< system.physmem.writeRowHits 97091 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes
< system.physmem.avgGap 3709816.21 # Average gap between requests
< system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states
< system.physmem.memoryStateTime::REF 65542620000 # Time in different power states
---
> system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing
> system.physmem.readRowHits 365377 # Number of row buffer hits during reads
> system.physmem.writeRowHits 96760 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes
> system.physmem.avgGap 3710114.71 # Average gap between requests
> system.physmem.pageHitRate 87.43 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 1840052567250 # Time in different power states
> system.physmem.memoryStateTime::REF 65509600000 # Time in different power states
303c300
< system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 56261656500 # Time in different power states
305,310c302,306
< system.membus.throughput 17291736 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 292660 # Transaction distribution
< system.membus.trans_dist::ReadResp 292660 # Transaction distribution
< system.membus.trans_dist::WriteReq 12414 # Transaction distribution
< system.membus.trans_dist::WriteResp 12414 # Transaction distribution
< system.membus.trans_dist::Writeback 79533 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 292757 # Transaction distribution
> system.membus.trans_dist::ReadResp 292757 # Transaction distribution
> system.membus.trans_dist::WriteReq 14067 # Transaction distribution
> system.membus.trans_dist::WriteResp 14067 # Transaction distribution
> system.membus.trans_dist::Writeback 79354 # Transaction distribution
313,332c309,338
< system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution
< system.membus.trans_dist::ReadExReq 122803 # Transaction distribution
< system.membus.trans_dist::ReadExResp 122701 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31201152 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.l2c.mem_side::total 31269890 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 33930178 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 33930178 # Total data (bytes)
< system.membus.snoop_data_through_bus 10304 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 39224500 # Layer occupancy (ticks)
---
> system.membus.trans_dist::UpgradeReq 16159 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 11272 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 6995 # Transaction distribution
> system.membus.trans_dist::ReadExReq 123294 # Transaction distribution
> system.membus.trans_dist::ReadExResp 122471 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930313 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 972845 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83293 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 83293 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1056138 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31181376 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 31263330 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 33923618 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 21418 # Total snoops (count)
> system.membus.snoop_fanout::samples 557197 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 557197 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 557197 # Request fanout histogram
> system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks)
334c340
< system.membus.reqLayer1.occupancy 1533573250 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 1536995500 # Layer occupancy (ticks)
336c342
< system.membus.respLayer1.occupancy 3826483141 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 3833296255 # Layer occupancy (ticks)
338c344
< system.membus.respLayer2.occupancy 43139750 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 43122000 # Layer occupancy (ticks)
341,514c347,520
< system.l2c.tags.replacements 342222 # number of replacements
< system.l2c.tags.tagsinuse 65256.426750 # Cycle average of tags in use
< system.l2c.tags.total_refs 2542307 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 407368 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 6.240812 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 55518.260732 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 3744.767678 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 4299.632317 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 1171.746225 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 522.019798 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.847141 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.057141 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.065607 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.017879 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.007965 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.995734 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1024 65146 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 748 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 5288 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 7253 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 51739 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1024 0.994049 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 26946350 # Number of tag accesses
< system.l2c.tags.data_accesses 26946350 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.inst 527823 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 377901 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 461413 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 449863 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1817000 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 850078 # number of Writeback hits
< system.l2c.Writeback_hits::total 850078 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 70 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 205 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 25 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 113452 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 85004 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 198456 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.inst 527823 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 491353 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 461413 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 534867 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2015456 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.inst 527823 # number of overall hits
< system.l2c.overall_hits::cpu0.data 491353 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 461413 # number of overall hits
< system.l2c.overall_hits::cpu1.data 534867 # number of overall hits
< system.l2c.overall_hits::total 2015456 # number of overall hits
< system.l2c.ReadReq_misses::cpu0.inst 11331 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 270739 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.inst 2173 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 1052 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 2603 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 469 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 3072 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 62 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 80 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 142 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 107000 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 15847 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 122847 # number of ReadExReq misses
< system.l2c.demand_misses::cpu0.inst 11331 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 377739 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 2173 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 16899 # number of demand (read+write) misses
< system.l2c.demand_misses::total 408142 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.inst 11331 # number of overall misses
< system.l2c.overall_misses::cpu0.data 377739 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 2173 # number of overall misses
< system.l2c.overall_misses::cpu1.data 16899 # number of overall misses
< system.l2c.overall_misses::total 408142 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu0.inst 827161250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu0.data 17596749000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.inst 162190250 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu1.data 79449000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 18665549500 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu0.data 700470 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 348985 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 1049455 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 162993 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 93496 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 256489 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 7343632619 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 1157201235 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 8500833854 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 827161250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 24940381619 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 162190250 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 1236650235 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 27166383354 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 827161250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 24940381619 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 162190250 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 1236650235 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 27166383354 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu0.inst 539154 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 648640 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 463586 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 450915 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2102295 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 850078 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 850078 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2738 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 3277 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 87 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 101 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 220452 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 100851 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 321303 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.inst 539154 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 869092 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 463586 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 551766 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2423598 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 539154 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 869092 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 463586 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 551766 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2423598 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.021016 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.417395 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.004687 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.135706 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950694 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870130 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.937443 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.712644 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.792079 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.755319 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.485366 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.157133 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.382340 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.021016 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.434636 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.004687 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.030627 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.168403 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.021016 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.434636 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.004687 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.030627 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.168403 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72999.845556 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu0.data 64995.250038 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74638.863323 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu1.data 75521.863118 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 65425.435076 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 269.101037 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 744.104478 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 341.619466 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2628.919355 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1168.700000 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 1806.260563 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68632.080551 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73023.363097 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 69198.546599 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 72999.845556 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 66025.434543 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 74638.863323 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 73178.900231 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 66561.107051 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 72999.845556 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 66025.434543 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 74638.863323 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 73178.900231 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 66561.107051 # average overall miss latency
---
> system.l2c.tags.replacements 342092 # number of replacements
> system.l2c.tags.tagsinuse 65220.775537 # Cycle average of tags in use
> system.l2c.tags.total_refs 2444844 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 407280 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 6.002858 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 55275.158075 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4808.073812 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 4934.415131 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 159.916198 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 43.212322 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.843432 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.073365 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.075293 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.002440 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.995190 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1024 65188 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 763 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 5265 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 7161 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 51884 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1024 0.994690 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 25951455 # Number of tag accesses
> system.l2c.tags.data_accesses 25951455 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.inst 690677 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 668171 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 311497 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 104258 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1774603 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 792816 # number of Writeback hits
> system.l2c.Writeback_hits::total 792816 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 541 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 723 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 41 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 64 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 130531 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 42264 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 172795 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.inst 690677 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 798702 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 311497 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 146522 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1947398 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.inst 690677 # number of overall hits
> system.l2c.overall_hits::cpu0.data 798702 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 311497 # number of overall hits
> system.l2c.overall_hits::cpu1.data 146522 # number of overall hits
> system.l2c.overall_hits::total 1947398 # number of overall hits
> system.l2c.ReadReq_misses::cpu0.inst 13021 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 271630 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.inst 506 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 238 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 285395 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 2954 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 1743 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 4697 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 889 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 909 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1798 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 117934 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 5037 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 122971 # number of ReadExReq misses
> system.l2c.demand_misses::cpu0.inst 13021 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 389564 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 506 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 5275 # number of demand (read+write) misses
> system.l2c.demand_misses::total 408366 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.inst 13021 # number of overall misses
> system.l2c.overall_misses::cpu0.data 389564 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 506 # number of overall misses
> system.l2c.overall_misses::cpu1.data 5275 # number of overall misses
> system.l2c.overall_misses::total 408366 # number of overall misses
> system.l2c.ReadReq_miss_latency::cpu0.inst 953089000 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu0.data 17671814750 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.inst 36961500 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::cpu1.data 17116250 # number of ReadReq miss cycles
> system.l2c.ReadReq_miss_latency::total 18678981500 # number of ReadReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1049955 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 9987069 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 11037024 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 859463 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 161993 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 1021456 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 8143976512 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 374794238 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 8518770750 # number of ReadExReq miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 953089000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 25815791262 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 36961500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 391910488 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 27197752250 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 953089000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 25815791262 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 36961500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 391910488 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 27197752250 # number of overall miss cycles
> system.l2c.ReadReq_accesses::cpu0.inst 703698 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 939801 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 312003 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 104496 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2059998 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 792816 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 792816 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 3136 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 2284 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 5420 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 930 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 932 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 1862 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 248465 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 47301 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 295766 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.inst 703698 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1188266 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 312003 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 151797 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2355764 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 703698 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1188266 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 312003 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 151797 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2355764 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.018504 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.289029 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.001622 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.002278 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.138541 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941964 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.763135 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.866605 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.955914 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975322 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.965628 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.474650 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.106488 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.415771 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.018504 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.327842 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.001622 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.034750 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.173348 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.018504 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.327842 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.001622 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.034750 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.173348 # miss rate for overall accesses
> system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73196.298287 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu0.data 65058.405736 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73046.442688 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::cpu1.data 71917.016807 # average ReadReq miss latency
> system.l2c.ReadReq_avg_miss_latency::total 65449.575150 # average ReadReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 355.435003 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5729.815835 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 2349.802853 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 966.775028 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 178.210121 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 568.106785 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69055.374294 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74408.226722 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 69274.631824 # average ReadExReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 73196.298287 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 66268.421266 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 73046.442688 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 74295.827109 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 66601.412091 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 73196.298287 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 66268.421266 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 73046.442688 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 74295.827109 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 66601.412091 # average overall miss latency
523,524c529,530
< system.l2c.writebacks::writebacks 79533 # number of writebacks
< system.l2c.writebacks::total 79533 # number of writebacks
---
> system.l2c.writebacks::writebacks 79354 # number of writebacks
> system.l2c.writebacks::total 79354 # number of writebacks
534,620c540,626
< system.l2c.ReadReq_mshr_misses::cpu0.inst 11328 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu0.data 270739 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.inst 2165 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu1.data 1052 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 285284 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 2603 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 469 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 3072 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 62 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 80 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 142 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 107000 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 15847 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 122847 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 11328 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 377739 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 2165 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 16899 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 408131 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 11328 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 377739 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 2165 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 16899 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 408131 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 682834500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14211900500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 134094500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu1.data 66276000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 15095105500 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 26034602 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4690469 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 30725071 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 620062 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 800080 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 1420142 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5999575381 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 958453765 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 6958029146 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 682834500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 20211475881 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 134094500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 1024729765 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 22053134646 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 682834500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 20211475881 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 134094500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 1024729765 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 22053134646 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 941946000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 449028500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 1390974500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1618783500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 858261500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 2477045000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2560729500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1307290000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 3868019500 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.417395 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.135701 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.950694 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.870130 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.937443 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.712644 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.792079 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755319 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.485366 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.157133 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.382340 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.434636 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.030627 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.168399 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.021011 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.434636 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004670 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.030627 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.168399 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52492.993252 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 52912.555559 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001.767960 # average UpgradeReq mshr miss latency
---
> system.l2c.ReadReq_mshr_misses::cpu0.inst 13018 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu0.data 271630 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::cpu1.data 238 # number of ReadReq MSHR misses
> system.l2c.ReadReq_mshr_misses::total 285384 # number of ReadReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 2954 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 1743 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 4697 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 889 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 909 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1798 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 117934 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 5037 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 122971 # number of ReadExReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 13018 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 389564 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 5275 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 408355 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 13018 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 389564 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 5275 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 408355 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 787294250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14275629250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 30082250 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::cpu1.data 14147750 # number of ReadReq MSHR miss cycles
> system.l2c.ReadReq_mshr_miss_latency::total 15107153500 # number of ReadReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29547954 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17431743 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 46979697 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8890889 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9090909 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 17981798 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6662795488 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 311210762 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 6974006250 # number of ReadExReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 787294250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 20938424738 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 30082250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 325358512 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 22081159750 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 787294250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 20938424738 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 30082250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 325358512 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 22081159750 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373183500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17608500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 1390792000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2147807000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674603500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 2822410500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3520990500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692212000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 4213202500 # number of overall MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289029 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002278 # mshr miss rate for ReadReq accesses
> system.l2c.ReadReq_mshr_miss_rate::total 0.138536 # mshr miss rate for ReadReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941964 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.763135 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.866605 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.955914 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975322 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.965628 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.474650 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.106488 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.415771 # mshr miss rate for ReadExReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.327842 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.034750 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.173343 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.327842 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.034750 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.173343 # mshr miss rate for overall accesses
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52555.421897 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59444.327731 # average ReadReq mshr miss latency
> system.l2c.ReadReq_avg_mshr_miss_latency::total 52936.231534 # average ReadReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.692620 # average UpgradeReq mshr miss latency
622c628
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.650716 # average UpgradeReq mshr miss latency
---
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.064509 # average UpgradeReq mshr miss latency
626,638c632,644
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56070.797953 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60481.716729 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 56639.797032 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60278.469280 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53506.457848 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61937.413395 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60638.485413 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 54034.451306 # average overall mshr miss latency
---
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56495.967982 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61784.943816 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 56712.609070 # average ReadExReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency
649,650c655,656
< system.iocache.tags.replacements 41699 # number of replacements
< system.iocache.tags.tagsinuse 0.569942 # Cycle average of tags in use
---
> system.iocache.tags.replacements 41694 # number of replacements
> system.iocache.tags.tagsinuse 0.569739 # Cycle average of tags in use
652c658
< system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
654,657c660,663
< system.iocache.tags.warmup_cycle 1756486320000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::tsunami.ide 0.569942 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::tsunami.ide 0.035621 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.035621 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 1755504878000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::tsunami.ide 0.569739 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::tsunami.ide 0.035609 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.035609 # Average percentage of cache occupancy
661,662c667,668
< system.iocache.tags.tag_accesses 375552 # Number of tag accesses
< system.iocache.tags.data_accesses 375552 # Number of data accesses
---
> system.iocache.tags.tag_accesses 375534 # Number of tag accesses
> system.iocache.tags.data_accesses 375534 # Number of data accesses
665,678c671,684
< system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
< system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses
< system.iocache.demand_misses::total 176 # number of demand (read+write) misses
< system.iocache.overall_misses::tsunami.ide 176 # number of overall misses
< system.iocache.overall_misses::total 176 # number of overall misses
< system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles
< system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
> system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
> system.iocache.demand_misses::total 174 # number of demand (read+write) misses
> system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
> system.iocache.overall_misses::total 174 # number of overall misses
> system.iocache.ReadReq_miss_latency::tsunami.ide 21248383 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 21248383 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::tsunami.ide 21248383 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 21248383 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::tsunami.ide 21248383 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 21248383 # number of overall miss cycles
> system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
681,684c687,690
< system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses
< system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
> system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
691,696c697,702
< system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency
< system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 122117.143678 # average overall miss latency
> system.iocache.overall_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 122117.143678 # average overall miss latency
705,706c711,712
< system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
709,720c715,726
< system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2504351556 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2504351556 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2501404806 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2501404806 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::tsunami.ide 12199383 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 12199383 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles
729,736c735,742
< system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency
754c760
< system.cpu0.dtb.read_hits 6067147 # DTB read hits
---
> system.cpu0.dtb.read_hits 7562596 # DTB read hits
758c764
< system.cpu0.dtb.write_hits 4265547 # DTB write hits
---
> system.cpu0.dtb.write_hits 5147185 # DTB write hits
762c768
< system.cpu0.dtb.data_hits 10332694 # DTB hits
---
> system.cpu0.dtb.data_hits 12709781 # DTB hits
766c772
< system.cpu0.itb.fetch_hits 3354719 # ITB hits
---
> system.cpu0.itb.fetch_hits 3660706 # ITB hits
769c775
< system.cpu0.itb.fetch_accesses 3358703 # ITB accesses
---
> system.cpu0.itb.fetch_accesses 3664690 # ITB accesses
782c788
< system.cpu0.numCycles 3925630437 # number of cpu cycles simulated
---
> system.cpu0.numCycles 3923653257 # number of cpu cycles simulated
785,837c791,843
< system.cpu0.committedInsts 38276405 # Number of instructions committed
< system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses
< system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses
< system.cpu0.num_func_calls 936479 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 35596815 # number of integer instructions
< system.cpu0.num_fp_insts 153493 # number of float instructions
< system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written
< system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read
< system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written
< system.cpu0.num_mem_refs 10365856 # number of memory refs
< system.cpu0.num_load_insts 6090539 # Number of load instructions
< system.cpu0.num_store_insts 4275317 # Number of store instructions
< system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles
< system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles
< system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles
< system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles
< system.cpu0.Branches 5694884 # Number of branches fetched
< system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction
< system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction
< system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction
< system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction
< system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction
< system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::FloatDiv 1883 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::FloatSqrt 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdAdd 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdAddAcc 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdAlu 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdCmp 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdCvt 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdMisc 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdMult 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdMultAcc 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdShift 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdSqrt 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction
< system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction
< system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction
< system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction
---
> system.cpu0.committedInsts 48127777 # Number of instructions committed
> system.cpu0.committedOps 48127777 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 44643925 # Number of integer alu accesses
> system.cpu0.num_fp_alu_accesses 213512 # Number of float alu accesses
> system.cpu0.num_func_calls 1209739 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 5647172 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 44643925 # number of integer instructions
> system.cpu0.num_fp_insts 213512 # number of float instructions
> system.cpu0.num_int_register_reads 61387452 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 33242964 # number of times the integer registers were written
> system.cpu0.num_fp_register_reads 104337 # number of times the floating registers were read
> system.cpu0.num_fp_register_writes 106136 # number of times the floating registers were written
> system.cpu0.num_mem_refs 12750882 # number of memory refs
> system.cpu0.num_load_insts 7590433 # Number of load instructions
> system.cpu0.num_store_insts 5160449 # Number of store instructions
> system.cpu0.num_idle_cycles 3699495012.998114 # Number of idle cycles
> system.cpu0.num_busy_cycles 224158244.001886 # Number of busy cycles
> system.cpu0.not_idle_fraction 0.057130 # Percentage of non-idle cycles
> system.cpu0.idle_fraction 0.942870 # Percentage of idle cycles
> system.cpu0.Branches 7246936 # Number of branches fetched
> system.cpu0.op_class::No_OpClass 2741568 5.70% 5.70% # Class of executed instruction
> system.cpu0.op_class::IntAlu 31634980 65.72% 71.41% # Class of executed instruction
> system.cpu0.op_class::IntMult 52525 0.11% 71.52% # Class of executed instruction
> system.cpu0.op_class::IntDiv 0 0.00% 71.52% # Class of executed instruction
> system.cpu0.op_class::FloatAdd 26830 0.06% 71.58% # Class of executed instruction
> system.cpu0.op_class::FloatCmp 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::FloatCvt 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::FloatMult 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::FloatDiv 1883 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::FloatSqrt 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdAdd 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdAddAcc 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdAlu 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdCmp 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdCvt 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdMisc 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdMult 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdMultAcc 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdShift 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdSqrt 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMult 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.58% # Class of executed instruction
> system.cpu0.op_class::MemRead 7767201 16.14% 87.72% # Class of executed instruction
> system.cpu0.op_class::MemWrite 5166567 10.73% 98.45% # Class of executed instruction
> system.cpu0.op_class::IprAccess 745241 1.55% 100.00% # Class of executed instruction
839c845
< system.cpu0.op_class::total 38285423 # Class of executed instruction
---
> system.cpu0.op_class::total 48136795 # Class of executed instruction
841,861c847,867
< system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed
< system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed
< system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl
< system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl
< system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl
< system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl
< system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.inst.quiesce 6805 # number of quiesce instructions executed
> system.cpu0.kern.inst.hwrei 166328 # number of hwrei instructions executed
> system.cpu0.kern.ipl_count::0 57239 40.25% 40.25% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::22 1975 1.39% 41.73% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::31 82449 57.97% 100.00% # number of times we switched to this ipl
> system.cpu0.kern.ipl_count::total 142218 # number of times we switched to this ipl
> system.cpu0.kern.ipl_good::0 56706 49.09% 49.09% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::22 1975 1.71% 50.91% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl
> system.cpu0.kern.ipl_ticks::0 1902225794500 96.96% 96.96% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::21 94977500 0.00% 96.97% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::22 767421000 0.04% 97.01% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::30 314336500 0.02% 97.02% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::31 58423341500 2.98% 100.00% # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_ticks::total 1961825871000 # number of cycles we spent at this ipl
> system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl
865,866c871,872
< system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl
< system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu0.kern.ipl_used::31 0.682640 # fraction of swpipl calls that actually changed the ipl
> system.cpu0.kern.ipl_used::total 0.812267 # fraction of swpipl calls that actually changed the ipl
898,916c904,922
< system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # number of callpals executed
< system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed
< system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed
< system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed
< system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed
< system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed
< system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed
< system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed
< system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed
< system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed
< system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed
< system.cpu0.kern.callpal::rdusp 9 0.01% 96.30% # number of callpals executed
< system.cpu0.kern.callpal::whami 2 0.00% 96.30% # number of callpals executed
< system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed
< system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed
< system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed
< system.cpu0.kern.callpal::total 123047 # number of callpals executed
< system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches
< system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches
---
> system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed
> system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
> system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
> system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
> system.cpu0.kern.callpal::swpctx 3105 2.06% 2.40% # number of callpals executed
> system.cpu0.kern.callpal::tbi 51 0.03% 2.43% # number of callpals executed
> system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed
> system.cpu0.kern.callpal::swpipl 135265 89.81% 92.25% # number of callpals executed
> system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed
> system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed
> system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed
> system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed
> system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed
> system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed
> system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed
> system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
> system.cpu0.kern.callpal::total 150611 # number of callpals executed
> system.cpu0.kern.mode_switch::kernel 7020 # number of protection mode switches
> system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches
918,919c924,925
< system.cpu0.kern.mode_good::kernel 1371
< system.cpu0.kern.mode_good::user 1372
---
> system.cpu0.kern.mode_good::kernel 1370
> system.cpu0.kern.mode_good::user 1371
921c927
< system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches
---
> system.cpu0.kern.mode_switch_good::kernel 0.195157 # fraction of useful protection mode switches
924,926c930,932
< system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches
< system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode
< system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode
---
> system.cpu0.kern.mode_switch_good::total 0.326660 # fraction of useful protection mode switches
> system.cpu0.kern.mode_ticks::kernel 1958053140500 99.81% 99.81% # number of ticks spent at the given mode
> system.cpu0.kern.mode_ticks::user 3772726000 0.19% 100.00% # number of ticks spent at the given mode
928c934
< system.cpu0.kern.swap_context 2217 # number of times the context was actually changed
---
> system.cpu0.kern.swap_context 3106 # number of times the context was actually changed
960,986c966,1003
< system.toL2Bus.throughput 109416622 # Throughput (bytes/s)
< system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution
< system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.data_through_bus 209584002 # Total data (bytes)
< system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes)
< system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks)
< system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
< system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
---
> system.toL2Bus.trans_dist::ReadReq 2102030 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 2102015 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 792816 # Transaction distribution
> system.toL2Bus.trans_dist::WriteInvalidateReq 41560 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 16382 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 11336 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 27718 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 297616 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 297616 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407417 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134555 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624007 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452565 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 5618544 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45036672 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120042720 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19968192 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16553666 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 201601250 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 98838 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 3254541 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 3.012823 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.112512 # Request fanout histogram
> system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::3 3212807 98.72% 98.72% # Request fanout histogram
> system.toL2Bus.snoop_fanout::4 41734 1.28% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.toL2Bus.snoop_fanout::total 3254541 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 4795402363 # Layer occupancy (ticks)
> system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
> system.toL2Bus.snoopLayer0.occupancy 715500 # Layer occupancy (ticks)
988,992c1005,1009
< system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks)
< system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
< system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks)
< system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
< system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 3169257997 # Layer occupancy (ticks)
> system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
> system.toL2Bus.respLayer1.occupancy 5536514081 # Layer occupancy (ticks)
> system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
> system.toL2Bus.respLayer2.occupancy 1404115991 # Layer occupancy (ticks)
994,1002c1011,1018
< system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks)
< system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%)
< system.iobus.throughput 1391048 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 7376 # Transaction distribution
< system.iobus.trans_dist::ReadResp 7376 # Transaction distribution
< system.iobus.trans_dist::WriteReq 53966 # Transaction distribution
< system.iobus.trans_dist::WriteResp 53966 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10614 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 484 # Packet count per connected master and slave (bytes)
---
> system.toL2Bus.respLayer3.occupancy 776560164 # Layer occupancy (ticks)
> system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
> system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
> system.iobus.trans_dist::WriteReq 55619 # Transaction distribution
> system.iobus.trans_dist::WriteResp 55619 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1013,1034c1029,1049
< system.iobus.pkt_count_system.bridge.master::total 39228 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 122684 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42456 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1936 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::total 68738 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 2730370 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 2730370 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 9969000 # Layer occupancy (ticks)
---
> system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks)
1036c1051
< system.iobus.reqLayer1.occupancy 362000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1056c1071
< system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks)
---
> system.iobus.reqLayer29.occupancy 374410189 # Layer occupancy (ticks)
1060c1075
< system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks)
1062c1077
< system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 42017000 # Layer occupancy (ticks)
1064,1068c1079,1083
< system.cpu0.icache.tags.replacements 538541 # number of replacements
< system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.replacements 703089 # number of replacements
> system.cpu0.icache.tags.tagsinuse 508.385515 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 47433077 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 703601 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 67.414738 # Average number of references to valid blocks.
1070,1072c1085,1087
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.385515 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992940 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy
1074c1089
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
1076,1077c1091,1092
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
1079,1116c1094,1131
< system.cpu0.icache.tags.tag_accesses 38824598 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits
< system.cpu0.icache.overall_hits::total 37746250 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 539174 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 539174 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 539174 # number of overall misses
< system.cpu0.icache.overall_misses::total 539174 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7756302744 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 7756302744 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 7756302744 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 7756302744 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 7756302744 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 7756302744 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285424 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 38285424 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 38285424 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 38285424 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 38285424 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 38285424 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014083 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.014083 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014083 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.014083 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014083 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.014083 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14385.528130 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 14385.528130 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 14385.528130 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 14385.528130 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 48840515 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 48840515 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 47433077 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 47433077 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 47433077 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 47433077 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 47433077 # number of overall hits
> system.cpu0.icache.overall_hits::total 47433077 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 703719 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 703719 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 703719 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 703719 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 703719 # number of overall misses
> system.cpu0.icache.overall_misses::total 703719 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017635497 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 10017635497 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 10017635497 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 10017635497 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 10017635497 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 10017635497 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136796 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 48136796 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 48136796 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 48136796 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 48136796 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 48136796 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014619 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.014619 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014619 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.014619 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014619 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.014619 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14235.277855 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 14235.277855 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 14235.277855 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 14235.277855 # average overall miss latency
1125,1148c1140,1163
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539174 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 539174 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 539174 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 539174 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 539174 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 539174 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6673548256 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 6673548256 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6673548256 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 6673548256 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6673548256 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 6673548256 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014083 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.014083 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.014083 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12377.355466 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703719 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 703719 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 703719 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 703719 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 703719 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 703719 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8605152503 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 8605152503 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8605152503 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 8605152503 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8605152503 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 8605152503 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014619 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.014619 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.014619 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.108809 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency
1150,1154c1165,1169
< system.cpu0.dcache.tags.replacements 871192 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 481.742326 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 9465806 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 871704 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 10.858968 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.replacements 1191194 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 505.224955 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 11513307 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 1191706 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 9.661197 # Average number of references to valid blocks.
1156,1158c1171,1173
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.742326 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940903 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.940903 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.224955 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986767 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.986767 # Average percentage of cache occupancy
1160,1162c1175,1177
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1164,1237c1179,1252
< system.cpu0.dcache.tags.tag_accesses 42232679 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 42232679 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 5299779 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 5299779 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 3905718 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 3905718 # number of WriteReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124794 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 124794 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131579 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 131579 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 9205497 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 9205497 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 9205497 # number of overall hits
< system.cpu0.dcache.overall_hits::total 9205497 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 645318 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 645318 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 224183 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 224183 # number of WriteReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7829 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 7829 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 497 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 497 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 869501 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 869501 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 869501 # number of overall misses
< system.cpu0.dcache.overall_misses::total 869501 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374202500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 23374202500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262527483 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 9262527483 # number of WriteReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102834500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 102834500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3584562 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 3584562 # number of StoreCondReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 32636729983 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 32636729983 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 32636729983 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 32636729983 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945097 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 5945097 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 4129901 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 4129901 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132623 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 132623 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132076 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 132076 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 10074998 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 10074998 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 10074998 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 10074998 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108546 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.108546 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054283 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.054283 # miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059032 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059032 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003763 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003763 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086303 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.086303 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086303 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.086303 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758 # average WriteReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7212.398390 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7212.398390 # average StoreCondReq miss latency
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency
---
> system.cpu0.dcache.tags.tag_accesses 52084143 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 52084143 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 6477469 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 6477469 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 4731394 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 4731394 # number of WriteReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141563 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 141563 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149256 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 149256 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 11208863 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 11208863 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 11208863 # number of overall hits
> system.cpu0.dcache.overall_hits::total 11208863 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 942620 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 942620 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 258040 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 258040 # number of WriteReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13696 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 13696 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 1200660 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 1200660 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 1200660 # number of overall misses
> system.cpu0.dcache.overall_misses::total 1200660 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27232981250 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 27232981250 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10355566942 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 10355566942 # number of WriteReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149859500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 149859500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42011389 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 42011389 # number of StoreCondReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 37588548192 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 37588548192 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 37588548192 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 37588548192 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420089 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 7420089 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989434 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 4989434 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155259 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 155259 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154708 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 154708 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 12409523 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 12409523 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 12409523 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 12409523 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127036 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.127036 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051717 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.051717 # miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088214 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088214 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035241 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035241 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096753 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.096753 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096753 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.096753 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28890.731419 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 28890.731419 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40131.634406 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 40131.634406 # average WriteReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.844334 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.844334 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7705.683969 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7705.683969 # average StoreCondReq miss latency
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 31306.571546 # average overall miss latency
1246,1301c1261,1316
< system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks
< system.cpu0.dcache.writebacks::total 405151 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 686359 # number of writebacks
> system.cpu0.dcache.writebacks::total 686359 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942620 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 942620 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258040 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 258040 # number of WriteReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13696 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13696 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200660 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 1200660 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200660 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 1200660 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25222171750 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25222171750 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9786377058 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9786377058 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122453500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122453500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31105611 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31105611 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35008548808 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 35008548808 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35008548808 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 35008548808 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465625500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465625500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2277904000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2277904000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3743529500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3743529500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127036 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127036 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051717 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051717 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088214 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088214 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035241 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035241 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.096753 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.096753 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052 # average WriteReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.822138 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.822138 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5705.357850 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5705.357850 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency
1313c1328
< system.cpu1.dtb.read_hits 3617054 # DTB read hits
---
> system.cpu1.dtb.read_hits 2348280 # DTB read hits
1317c1332
< system.cpu1.dtb.write_hits 2433875 # DTB write hits
---
> system.cpu1.dtb.write_hits 1676993 # DTB write hits
1321c1336
< system.cpu1.dtb.data_hits 6050929 # DTB hits
---
> system.cpu1.dtb.data_hits 4025273 # DTB hits
1325c1340
< system.cpu1.itb.fetch_hits 1988100 # ITB hits
---
> system.cpu1.itb.fetch_hits 1801078 # ITB hits
1328c1343
< system.cpu1.itb.fetch_accesses 1989164 # ITB accesses
---
> system.cpu1.itb.fetch_accesses 1802142 # ITB accesses
1341c1356
< system.cpu1.numCycles 3923841470 # number of cpu cycles simulated
---
> system.cpu1.numCycles 3921880878 # number of cpu cycles simulated
1344,1396c1359,1411
< system.cpu1.committedInsts 21095754 # Number of instructions committed
< system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses
< system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses
< system.cpu1.num_func_calls 648514 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 19410964 # number of integer instructions
< system.cpu1.num_fp_insts 175175 # number of float instructions
< system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written
< system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read
< system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written
< system.cpu1.num_mem_refs 6073169 # number of memory refs
< system.cpu1.num_load_insts 3630901 # Number of load instructions
< system.cpu1.num_store_insts 2442268 # Number of store instructions
< system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles
< system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles
< system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles
< system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles
< system.cpu1.Branches 3165037 # Number of branches fetched
< system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction
< system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction
< system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction
< system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction
< system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction
< system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction
< system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction
< system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction
< system.cpu1.op_class::FloatDiv 1759 0.01% 68.64% # Class of executed instruction
< system.cpu1.op_class::FloatSqrt 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdAdd 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdAddAcc 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdAlu 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdCmp 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdCvt 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdMisc 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdMult 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdMultAcc 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdShift 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdSqrt 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction
< system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction
< system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction
< system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction
---
> system.cpu1.committedInsts 12764610 # Number of instructions committed
> system.cpu1.committedOps 12764610 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 11762987 # Number of integer alu accesses
> system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses
> system.cpu1.num_func_calls 404048 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 1265459 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 11762987 # number of integer instructions
> system.cpu1.num_fp_insts 170364 # number of float instructions
> system.cpu1.num_int_register_reads 16177090 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 8656212 # number of times the integer registers were written
> system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read
> system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written
> system.cpu1.num_mem_refs 4047820 # number of memory refs
> system.cpu1.num_load_insts 2361802 # Number of load instructions
> system.cpu1.num_store_insts 1686018 # Number of store instructions
> system.cpu1.num_idle_cycles 3873240792.459649 # Number of idle cycles
> system.cpu1.num_busy_cycles 48640085.540351 # Number of busy cycles
> system.cpu1.not_idle_fraction 0.012402 # Percentage of non-idle cycles
> system.cpu1.idle_fraction 0.987598 # Percentage of idle cycles
> system.cpu1.Branches 1821460 # Number of branches fetched
> system.cpu1.op_class::No_OpClass 690637 5.41% 5.41% # Class of executed instruction
> system.cpu1.op_class::IntAlu 7566798 59.27% 64.68% # Class of executed instruction
> system.cpu1.op_class::IntMult 21839 0.17% 64.85% # Class of executed instruction
> system.cpu1.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction
> system.cpu1.op_class::FloatAdd 13058 0.10% 64.95% # Class of executed instruction
> system.cpu1.op_class::FloatCmp 0 0.00% 64.95% # Class of executed instruction
> system.cpu1.op_class::FloatCvt 0 0.00% 64.95% # Class of executed instruction
> system.cpu1.op_class::FloatMult 0 0.00% 64.95% # Class of executed instruction
> system.cpu1.op_class::FloatDiv 1759 0.01% 64.96% # Class of executed instruction
> system.cpu1.op_class::FloatSqrt 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdAdd 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdAddAcc 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdAlu 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdCmp 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdCvt 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdMisc 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdMult 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdMultAcc 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdShift 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdSqrt 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMult 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.96% # Class of executed instruction
> system.cpu1.op_class::MemRead 2432293 19.05% 84.01% # Class of executed instruction
> system.cpu1.op_class::MemWrite 1686990 13.21% 97.23% # Class of executed instruction
> system.cpu1.op_class::IprAccess 354115 2.77% 100.00% # Class of executed instruction
1398c1413
< system.cpu1.op_class::total 21098633 # Class of executed instruction
---
> system.cpu1.op_class::total 12767489 # Class of executed instruction
1400,1417c1415,1432
< system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed
< system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed
< system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl
< system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl
< system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl
< system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl
< system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
> system.cpu1.kern.inst.hwrei 77083 # number of hwrei instructions executed
> system.cpu1.kern.ipl_count::0 26133 38.19% 38.19% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::31 39822 58.19% 100.00% # number of times we switched to this ipl
> system.cpu1.kern.ipl_count::total 68430 # number of times we switched to this ipl
> system.cpu1.kern.ipl_good::0 25289 48.13% 48.13% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::31 24783 47.16% 100.00% # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_good::total 52547 # number of times we switched to this ipl from a different ipl
> system.cpu1.kern.ipl_ticks::0 1909614154000 97.38% 97.38% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::22 700846000 0.04% 97.42% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::30 353816000 0.02% 97.44% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::31 50271593000 2.56% 100.00% # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_ticks::total 1960940409000 # number of cycles we spent at this ipl
> system.cpu1.kern.ipl_used::0 0.967704 # fraction of swpipl calls that actually changed the ipl
1420,1421c1435,1436
< system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl
< system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl
---
> system.cpu1.kern.ipl_used::31 0.622344 # fraction of swpipl calls that actually changed the ipl
> system.cpu1.kern.ipl_used::total 0.767894 # fraction of swpipl calls that actually changed the ipl
1437,1450c1452,1465
< system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed
< system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed
< system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed
< system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed
< system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed
< system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed
< system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed
< system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed
< system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed
< system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed
< system.cpu1.kern.callpal::whami 3 0.00% 96.38% # number of callpals executed
< system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # number of callpals executed
< system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed
< system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed
---
> system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed
> system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
> system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
> system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed
> system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed
> system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed
> system.cpu1.kern.callpal::swpipl 62269 88.12% 91.51% # number of callpals executed
> system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed
> system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed
> system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed
> system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed
> system.cpu1.kern.callpal::rti 3685 5.21% 99.77% # number of callpals executed
> system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
> system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
1452,1453c1467,1468
< system.cpu1.kern.callpal::total 94732 # number of callpals executed
< system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches
---
> system.cpu1.kern.callpal::total 70663 # number of callpals executed
> system.cpu1.kern.mode_switch::kernel 1918 # number of protection mode switches
1455,1456c1470,1471
< system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches
< system.cpu1.kern.mode_good::kernel 415
---
> system.cpu1.kern.mode_switch::idle 2888 # number of protection mode switches
> system.cpu1.kern.mode_good::kernel 797
1458,1459c1473,1474
< system.cpu1.kern.mode_good::idle 48
< system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches
---
> system.cpu1.kern.mode_good::idle 430
> system.cpu1.kern.mode_switch_good::kernel 0.415537 # fraction of useful protection mode switches
1461,1517c1476,1532
< system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches
< system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches
< system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode
< system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode
< system.cpu1.kern.swap_context 2021 # number of times the context was actually changed
< system.cpu1.icache.tags.replacements 463035 # number of replacements
< system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id
< system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 20635046 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 20635046 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 20635046 # number of overall hits
< system.cpu1.icache.overall_hits::total 20635046 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 463587 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 463587 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 463587 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 463587 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 463587 # number of overall misses
< system.cpu1.icache.overall_misses::total 463587 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6202855739 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 6202855739 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 6202855739 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 6202855739 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 6202855739 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 6202855739 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098633 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 21098633 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 21098633 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 21098633 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 21098633 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 21098633 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021972 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021972 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.021972 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021972 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency
---
> system.cpu1.kern.mode_switch_good::idle 0.148892 # fraction of useful protection mode switches
> system.cpu1.kern.mode_switch_good::total 0.308138 # fraction of useful protection mode switches
> system.cpu1.kern.mode_ticks::kernel 17565031500 0.90% 0.90% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::user 1483893000 0.08% 0.97% # number of ticks spent at the given mode
> system.cpu1.kern.mode_ticks::idle 1941003590000 99.03% 100.00% # number of ticks spent at the given mode
> system.cpu1.kern.swap_context 1956 # number of times the context was actually changed
> system.cpu1.icache.tags.replacements 311453 # number of replacements
> system.cpu1.icache.tags.tagsinuse 446.345950 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 12455485 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 311964 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 39.926033 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 1960014862500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.345950 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871769 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.871769 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::3 440 # Occupied blocks per task id
> system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
> system.cpu1.icache.tags.tag_accesses 13079493 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 13079493 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 12455485 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 12455485 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 12455485 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 12455485 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 12455485 # number of overall hits
> system.cpu1.icache.overall_hits::total 12455485 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 312004 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 312004 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 312004 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 312004 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 312004 # number of overall misses
> system.cpu1.icache.overall_misses::total 312004 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4105450991 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 4105450991 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 4105450991 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 4105450991 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 4105450991 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 4105450991 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767489 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 12767489 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 12767489 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 12767489 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 12767489 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 12767489 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024437 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.024437 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024437 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.024437 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024437 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.024437 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13158.328070 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 13158.328070 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 13158.328070 # average overall miss latency
1526,1549c1541,1564
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 463587 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 463587 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 463587 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 463587 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5274833261 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 5274833261 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312004 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 312004 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 312004 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 312004 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 312004 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 312004 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3481247009 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 3481247009 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3481247009 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 3481247009 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3481247009 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 3481247009 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024437 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.024437 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.024437 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency
1551,1637c1566,1652
< system.cpu1.dcache.tags.replacements 581700 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 492.027042 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 5462019 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 582040 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 9.384267 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027042 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 340 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.664062 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 24828314 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 24828314 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 3080149 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 3080149 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 2259986 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 2259986 # number of WriteReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60927 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 60927 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71555 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 71555 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 5340135 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 5340135 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 5340135 # number of overall hits
< system.cpu1.dcache.overall_hits::total 5340135 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 473178 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 473178 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 102501 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 102501 # number of WriteReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11671 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 11671 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 568 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 568 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 575679 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 575679 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 575679 # number of overall misses
< system.cpu1.dcache.overall_misses::total 575679 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938208750 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 5938208750 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2338814234 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 2338814234 # number of WriteReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149892750 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 149892750 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4181580 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 8277022984 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 8277022984 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 8277022984 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 3553327 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362487 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 2362487 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72598 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 72598 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72123 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 72123 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 5915814 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 5915814 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 5915814 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 5915814 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133165 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.133165 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160762 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160762 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007875 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007875 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097312 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.097312 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097312 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.097312 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22817.477234 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 22817.477234 # average WriteReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.179676 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.179676 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.936620 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.936620 # average StoreCondReq miss latency
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 14377.844222 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14377.844222 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 14377.844222 # average overall miss latency
---
> system.cpu1.dcache.tags.replacements 155174 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 486.308424 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 3855056 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 155503 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 24.790879 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308424 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949821 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.949821 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 16322131 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 16322131 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 2189503 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 2189503 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 1567525 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 1567525 # number of WriteReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46972 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 46972 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49481 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 49481 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 3757028 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 3757028 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 3757028 # number of overall hits
> system.cpu1.dcache.overall_hits::total 3757028 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 113756 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 113756 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 55958 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 55958 # number of WriteReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8862 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 8862 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5884 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 5884 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 169714 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 169714 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 169714 # number of overall misses
> system.cpu1.dcache.overall_misses::total 169714 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1372027750 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 1372027750 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1020320505 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 1020320505 # number of WriteReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80442000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 80442000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43305909 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 43305909 # number of StoreCondReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 2392348255 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 2392348255 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 2392348255 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 2392348255 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303259 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 2303259 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623483 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 1623483 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55834 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 55834 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55365 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 55365 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 3926742 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 3926742 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 3926742 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 3926742 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049389 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.049389 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034468 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.034468 # miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158720 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158720 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106277 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106277 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043220 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.043220 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043220 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.043220 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18233.684281 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281 # average WriteReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9077.183480 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9077.183480 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7359.943746 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7359.943746 # average StoreCondReq miss latency
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833 # average overall miss latency
1646,1701c1661,1716
< system.cpu1.dcache.writebacks::writebacks 444927 # number of writebacks
< system.cpu1.dcache.writebacks::total 444927 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473178 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 473178 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102501 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 102501 # number of WriteReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11671 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11671 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 568 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 568 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 575679 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 575679 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 575679 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 575679 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4991497250 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4991497250 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2127317766 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2127317766 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126550250 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3045420 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3045420 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7118815016 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7118815016 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 7118815016 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907862000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907862000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387520500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387520500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133165 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133165 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160762 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007875 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007875 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.097312 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.097312 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 106457 # number of writebacks
> system.cpu1.dcache.writebacks::total 106457 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113756 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 113756 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55958 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 55958 # number of WriteReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8862 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8862 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5884 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 5884 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 169714 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 169714 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 169714 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 169714 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144439250 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144439250 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 906162495 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 906162495 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62718000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62718000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31536091 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31536091 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2050601745 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 2050601745 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2050601745 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 2050601745 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18765500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18765500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713325000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713325000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732090500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732090500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049389 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049389 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034468 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034468 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158720 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158720 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106277 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106277 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.043220 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.043220 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339 # average WriteReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7077.183480 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7077.183480 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5359.634772 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5359.634772 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency