Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

stats.txt (11502:e273e86a873d)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.963613 # Number of seconds simulated 4sim_ticks 1963612574000 # Number of ticks simulated 5final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.963613 # Number of seconds simulated 4sim_ticks 1963612574000 # Number of ticks simulated 5final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 993881 # Simulator instruction rate (inst/s) 8host_op_rate 993880 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32036346352 # Simulator tick rate (ticks/s) 10host_mem_usage 331076 # Number of bytes of host memory used 11host_seconds 61.29 # Real time elapsed on the host	7host_inst_rate 1460699 # Simulator instruction rate (inst/s) 8host_op_rate 1460699 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 47083590827 # Simulator tick rate (ticks/s) 10host_mem_usage 378804 # Number of bytes of host memory used 11host_seconds 41.70 # Real time elapsed on the host
12sim_insts 60918165 # Number of instructions simulated 13sim_ops 60918165 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 60918165 # Number of instructions simulated 13sim_ops 60918165 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 859200 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7709248 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7709248 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 12981 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 386432 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 444 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 6816 # Number of read requests responded to by this memory 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 406688 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120457 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120457 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 423090 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12594973 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 14471 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 222154 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13255177 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 423090 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 14471 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 437561 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3926053 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3926053 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3926053 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 423090 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12594973 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 14471 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 222154 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17181230 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 406688 # Number of read requests accepted 54system.physmem.writeReqs 120457 # Number of write requests accepted 55system.physmem.readBursts 406688 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 120457 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26019904 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7707200 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26028032 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7709248 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25130 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25381 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25483 # Per bank write bursts 68system.physmem.perBankRdBursts::3 24909 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25165 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25252 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25797 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25541 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25672 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25333 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25279 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25593 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25647 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25645 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25712 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25022 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7825 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7603 # Per bank write bursts 83system.physmem.perBankWrBursts::2 7492 # Per bank write bursts 84system.physmem.perBankWrBursts::3 6933 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7149 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7135 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7628 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7255 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7538 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7229 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7235 # Per bank write bursts 92system.physmem.perBankWrBursts::11 7425 # Per bank write bursts 93system.physmem.perBankWrBursts::12 7840 # Per bank write bursts 94system.physmem.perBankWrBursts::13 8302 # Per bank write bursts 95system.physmem.perBankWrBursts::14 8309 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7527 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 17 # Number of times write queue was full causing retry 99system.physmem.totGap 1963565980500 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 406688 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 120457 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 406481 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 3207 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 5887 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6006 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 6734 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6782 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 7812 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 9118 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 7274 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 8021 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8672 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 7905 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7057 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7090 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 185 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 128 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 129 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 80 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 99 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 224 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 165 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 172 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 147 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 178 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 114 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 134 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 66393 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 507.991867 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 305.024910 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 413.812380 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 15899 23.95% 23.95% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12177 18.34% 42.29% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5415 8.16% 50.44% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3379 5.09% 55.53% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2311 3.48% 59.01% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 2006 3.02% 62.04% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1513 2.28% 64.31% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 1280 1.93% 66.24% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 22413 33.76% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 66393 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5392 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 75.397255 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2872.179140 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5389 99.94% 99.94% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 5392 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5392 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.334013 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.995867 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 21.838616 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 4788 88.80% 88.80% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 33 0.61% 89.41% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 252 4.67% 94.08% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 18 0.33% 94.42% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 6 0.11% 94.53% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 13 0.24% 94.77% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 10 0.19% 94.96% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 1 0.02% 94.97% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 18 0.33% 95.31% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 18 0.33% 95.64% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 190 3.52% 99.17% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 3 0.06% 99.22% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::120-127 7 0.13% 99.37% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::128-135 1 0.02% 99.39% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::136-143 1 0.02% 99.41% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::152-159 2 0.04% 99.46% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::160-167 1 0.02% 99.48% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::168-175 6 0.11% 99.59% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::176-183 2 0.04% 99.63% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::184-191 2 0.04% 99.67% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::192-199 3 0.06% 99.72% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::224-231 13 0.24% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 5392 # Writes before turning the bus around for reads 263system.physmem.totQLat 2148968000 # Total ticks spent queuing 264system.physmem.totMemAccLat 9771986750 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 2032805000 # Total ticks spent in databus transfers 266system.physmem.avgQLat 5285.72 # Average queueing delay per DRAM burst 267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 268system.physmem.avgMemAccLat 24035.72 # Average memory access latency per DRAM burst 269system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s 270system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s 271system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s 272system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s 273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.13 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 276system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 277system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 278system.physmem.avgWrQLen 24.84 # Average write queue length when enqueuing 279system.physmem.readRowHits 364299 # Number of row buffer hits during reads 280system.physmem.writeRowHits 96294 # Number of row buffer hits during writes 281system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads 282system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes 283system.physmem.avgGap 3724906.77 # Average gap between requests 284system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined 285system.physmem_0.actEnergy 248179680 # Energy for activate commands per rank (pJ) 286system.physmem_0.preEnergy 135415500 # Energy for precharge commands per rank (pJ) 287system.physmem_0.readEnergy 1580732400 # Energy for read commands per rank (pJ) 288system.physmem_0.writeEnergy 382449600 # Energy for write commands per rank (pJ) 289system.physmem_0.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) 290system.physmem_0.actBackEnergy 66024340605 # Energy for active background per rank (pJ) 291system.physmem_0.preBackEnergy 1120248020250 # Energy for precharge background per rank (pJ) 292system.physmem_0.totalEnergy 1316872375875 # Total energy per rank (pJ) 293system.physmem_0.averagePower 670.639531 # Core power per rank (mW) 294system.physmem_0.memoryStateTime::IDLE 1863393486000 # Time in different power states 295system.physmem_0.memoryStateTime::REF 65569140000 # Time in different power states 296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 297system.physmem_0.memoryStateTime::ACT 34644235250 # Time in different power states 298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 299system.physmem_1.actEnergy 253751400 # Energy for activate commands per rank (pJ) 300system.physmem_1.preEnergy 138455625 # Energy for precharge commands per rank (pJ) 301system.physmem_1.readEnergy 1590443400 # Energy for read commands per rank (pJ) 302system.physmem_1.writeEnergy 397904400 # Energy for write commands per rank (pJ) 303system.physmem_1.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) 304system.physmem_1.actBackEnergy 66573650745 # Energy for active background per rank (pJ) 305system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ) 306system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ) 307system.physmem_1.averagePower 670.691088 # Core power per rank (mW) 308system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states 309system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states 310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 311system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states 312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory 21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 859200 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 7709248 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7709248 # Number of bytes written to this memory 28system.physmem.num_reads::cpu0.inst 12981 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu0.data 386432 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.inst 444 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu1.data 6816 # Number of read requests responded to by this memory 32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 406688 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 120457 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 120457 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu0.inst 423090 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu0.data 12594973 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.inst 14471 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu1.data 222154 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 13255177 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu0.inst 423090 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu1.inst 14471 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 437561 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 3926053 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 3926053 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 3926053 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.inst 423090 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu0.data 12594973 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.inst 14471 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu1.data 222154 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 17181230 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 406688 # Number of read requests accepted 55system.physmem.writeReqs 120457 # Number of write requests accepted 56system.physmem.readBursts 406688 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 120457 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 26019904 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue 60system.physmem.bytesWritten 7707200 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 26028032 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 7709248 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 25130 # Per bank write bursts 67system.physmem.perBankRdBursts::1 25381 # Per bank write bursts 68system.physmem.perBankRdBursts::2 25483 # Per bank write bursts 69system.physmem.perBankRdBursts::3 24909 # Per bank write bursts 70system.physmem.perBankRdBursts::4 25165 # Per bank write bursts 71system.physmem.perBankRdBursts::5 25252 # Per bank write bursts 72system.physmem.perBankRdBursts::6 25797 # Per bank write bursts 73system.physmem.perBankRdBursts::7 25541 # Per bank write bursts 74system.physmem.perBankRdBursts::8 25672 # Per bank write bursts 75system.physmem.perBankRdBursts::9 25333 # Per bank write bursts 76system.physmem.perBankRdBursts::10 25279 # Per bank write bursts 77system.physmem.perBankRdBursts::11 25593 # Per bank write bursts 78system.physmem.perBankRdBursts::12 25647 # Per bank write bursts 79system.physmem.perBankRdBursts::13 25645 # Per bank write bursts 80system.physmem.perBankRdBursts::14 25712 # Per bank write bursts 81system.physmem.perBankRdBursts::15 25022 # Per bank write bursts 82system.physmem.perBankWrBursts::0 7825 # Per bank write bursts 83system.physmem.perBankWrBursts::1 7603 # Per bank write bursts 84system.physmem.perBankWrBursts::2 7492 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6933 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7149 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7135 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7628 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7255 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7538 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7229 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7235 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7425 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7840 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8302 # Per bank write bursts 96system.physmem.perBankWrBursts::14 8309 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7527 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 17 # Number of times write queue was full causing retry 100system.physmem.totGap 1963565980500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 406688 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 120457 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 406481 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3207 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5887 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6006 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6734 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6782 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7812 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 9118 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 7274 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 8021 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 8672 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 7905 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7057 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7090 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 185 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 128 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 129 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 80 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 99 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 224 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 165 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 172 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 147 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 178 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 114 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 134 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 66393 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 507.991867 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 305.024910 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 413.812380 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 15899 23.95% 23.95% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 12177 18.34% 42.29% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5415 8.16% 50.44% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3379 5.09% 55.53% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2311 3.48% 59.01% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 2006 3.02% 62.04% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1513 2.28% 64.31% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1280 1.93% 66.24% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 22413 33.76% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 66393 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5392 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 75.397255 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 2872.179140 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-8191 5389 99.94% 99.94% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 5392 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 5392 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 22.334013 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.995867 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 21.838616 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-23 4788 88.80% 88.80% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-31 33 0.61% 89.41% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-39 252 4.67% 94.08% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::40-47 18 0.33% 94.42% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::48-55 6 0.11% 94.53% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-63 13 0.24% 94.77% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::64-71 10 0.19% 94.96% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::72-79 1 0.02% 94.97% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::80-87 18 0.33% 95.31% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::88-95 18 0.33% 95.64% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::96-103 190 3.52% 99.17% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::104-111 3 0.06% 99.22% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::120-127 7 0.13% 99.37% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::128-135 1 0.02% 99.39% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::136-143 1 0.02% 99.41% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::152-159 2 0.04% 99.46% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::160-167 1 0.02% 99.48% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::168-175 6 0.11% 99.59% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::176-183 2 0.04% 99.63% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::184-191 2 0.04% 99.67% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::192-199 3 0.06% 99.72% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::224-231 13 0.24% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::total 5392 # Writes before turning the bus around for reads 264system.physmem.totQLat 2148968000 # Total ticks spent queuing 265system.physmem.totMemAccLat 9771986750 # Total ticks spent from burst creation until serviced by the DRAM 266system.physmem.totBusLat 2032805000 # Total ticks spent in databus transfers 267system.physmem.avgQLat 5285.72 # Average queueing delay per DRAM burst 268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 269system.physmem.avgMemAccLat 24035.72 # Average memory access latency per DRAM burst 270system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s 271system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s 272system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s 273system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s 274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 275system.physmem.busUtil 0.13 # Data bus utilization in percentage 276system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 277system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 278system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 279system.physmem.avgWrQLen 24.84 # Average write queue length when enqueuing 280system.physmem.readRowHits 364299 # Number of row buffer hits during reads 281system.physmem.writeRowHits 96294 # Number of row buffer hits during writes 282system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads 283system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes 284system.physmem.avgGap 3724906.77 # Average gap between requests 285system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined 286system.physmem_0.actEnergy 248179680 # Energy for activate commands per rank (pJ) 287system.physmem_0.preEnergy 135415500 # Energy for precharge commands per rank (pJ) 288system.physmem_0.readEnergy 1580732400 # Energy for read commands per rank (pJ) 289system.physmem_0.writeEnergy 382449600 # Energy for write commands per rank (pJ) 290system.physmem_0.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) 291system.physmem_0.actBackEnergy 66024340605 # Energy for active background per rank (pJ) 292system.physmem_0.preBackEnergy 1120248020250 # Energy for precharge background per rank (pJ) 293system.physmem_0.totalEnergy 1316872375875 # Total energy per rank (pJ) 294system.physmem_0.averagePower 670.639531 # Core power per rank (mW) 295system.physmem_0.memoryStateTime::IDLE 1863393486000 # Time in different power states 296system.physmem_0.memoryStateTime::REF 65569140000 # Time in different power states 297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 298system.physmem_0.memoryStateTime::ACT 34644235250 # Time in different power states 299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 300system.physmem_1.actEnergy 253751400 # Energy for activate commands per rank (pJ) 301system.physmem_1.preEnergy 138455625 # Energy for precharge commands per rank (pJ) 302system.physmem_1.readEnergy 1590443400 # Energy for read commands per rank (pJ) 303system.physmem_1.writeEnergy 397904400 # Energy for write commands per rank (pJ) 304system.physmem_1.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) 305system.physmem_1.actBackEnergy 66573650745 # Energy for active background per rank (pJ) 306system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ) 307system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ) 308system.physmem_1.averagePower 670.691088 # Core power per rank (mW) 309system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states 310system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states 311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 312system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states 313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	314system.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 315system.bridge.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
313system.cpu_clk_domain.clock 500 # Clock period in ticks 314system.cpu0.dtb.fetch_hits 0 # ITB hits 315system.cpu0.dtb.fetch_misses 0 # ITB misses 316system.cpu0.dtb.fetch_acv 0 # ITB acv 317system.cpu0.dtb.fetch_accesses 0 # ITB accesses 318system.cpu0.dtb.read_hits 7494168 # DTB read hits 319system.cpu0.dtb.read_misses 7443 # DTB read misses 320system.cpu0.dtb.read_acv 210 # DTB read access violations 321system.cpu0.dtb.read_accesses 490673 # DTB read accesses 322system.cpu0.dtb.write_hits 5065702 # DTB write hits 323system.cpu0.dtb.write_misses 813 # DTB write misses 324system.cpu0.dtb.write_acv 134 # DTB write access violations 325system.cpu0.dtb.write_accesses 187452 # DTB write accesses 326system.cpu0.dtb.data_hits 12559870 # DTB hits 327system.cpu0.dtb.data_misses 8256 # DTB misses 328system.cpu0.dtb.data_acv 344 # DTB access violations 329system.cpu0.dtb.data_accesses 678125 # DTB accesses 330system.cpu0.itb.fetch_hits 3501177 # ITB hits 331system.cpu0.itb.fetch_misses 3871 # ITB misses 332system.cpu0.itb.fetch_acv 184 # ITB acv 333system.cpu0.itb.fetch_accesses 3505048 # ITB accesses 334system.cpu0.itb.read_hits 0 # DTB read hits 335system.cpu0.itb.read_misses 0 # DTB read misses 336system.cpu0.itb.read_acv 0 # DTB read access violations 337system.cpu0.itb.read_accesses 0 # DTB read accesses 338system.cpu0.itb.write_hits 0 # DTB write hits 339system.cpu0.itb.write_misses 0 # DTB write misses 340system.cpu0.itb.write_acv 0 # DTB write access violations 341system.cpu0.itb.write_accesses 0 # DTB write accesses 342system.cpu0.itb.data_hits 0 # DTB hits 343system.cpu0.itb.data_misses 0 # DTB misses 344system.cpu0.itb.data_acv 0 # DTB access violations 345system.cpu0.itb.data_accesses 0 # DTB accesses	316system.cpu_clk_domain.clock 500 # Clock period in ticks 317system.cpu0.dtb.fetch_hits 0 # ITB hits 318system.cpu0.dtb.fetch_misses 0 # ITB misses 319system.cpu0.dtb.fetch_acv 0 # ITB acv 320system.cpu0.dtb.fetch_accesses 0 # ITB accesses 321system.cpu0.dtb.read_hits 7494168 # DTB read hits 322system.cpu0.dtb.read_misses 7443 # DTB read misses 323system.cpu0.dtb.read_acv 210 # DTB read access violations 324system.cpu0.dtb.read_accesses 490673 # DTB read accesses 325system.cpu0.dtb.write_hits 5065702 # DTB write hits 326system.cpu0.dtb.write_misses 813 # DTB write misses 327system.cpu0.dtb.write_acv 134 # DTB write access violations 328system.cpu0.dtb.write_accesses 187452 # DTB write accesses 329system.cpu0.dtb.data_hits 12559870 # DTB hits 330system.cpu0.dtb.data_misses 8256 # DTB misses 331system.cpu0.dtb.data_acv 344 # DTB access violations 332system.cpu0.dtb.data_accesses 678125 # DTB accesses 333system.cpu0.itb.fetch_hits 3501177 # ITB hits 334system.cpu0.itb.fetch_misses 3871 # ITB misses 335system.cpu0.itb.fetch_acv 184 # ITB acv 336system.cpu0.itb.fetch_accesses 3505048 # ITB accesses 337system.cpu0.itb.read_hits 0 # DTB read hits 338system.cpu0.itb.read_misses 0 # DTB read misses 339system.cpu0.itb.read_acv 0 # DTB read access violations 340system.cpu0.itb.read_accesses 0 # DTB read accesses 341system.cpu0.itb.write_hits 0 # DTB write hits 342system.cpu0.itb.write_misses 0 # DTB write misses 343system.cpu0.itb.write_acv 0 # DTB write access violations 344system.cpu0.itb.write_accesses 0 # DTB write accesses 345system.cpu0.itb.data_hits 0 # DTB hits 346system.cpu0.itb.data_misses 0 # DTB misses 347system.cpu0.itb.data_acv 0 # DTB access violations 348system.cpu0.itb.data_accesses 0 # DTB accesses
	349system.cpu0.numPwrStateTransitions 13591 # Number of power state transitions 350system.cpu0.pwrStateClkGateDist::samples 6796 # Distribution of time spent in the clock gated state 351system.cpu0.pwrStateClkGateDist::mean 272307750.367863 # Distribution of time spent in the clock gated state 352system.cpu0.pwrStateClkGateDist::stdev 432682187.397928 # Distribution of time spent in the clock gated state 353system.cpu0.pwrStateClkGateDist::1000-5e+10 6796 100.00% 100.00% # Distribution of time spent in the clock gated state 354system.cpu0.pwrStateClkGateDist::min_value 55000 # Distribution of time spent in the clock gated state 355system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 356system.cpu0.pwrStateClkGateDist::total 6796 # Distribution of time spent in the clock gated state 357system.cpu0.pwrStateResidencyTicks::ON 113009102500 # Cumulative time (in ticks) in various power states 358system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850603471500 # Cumulative time (in ticks) in various power states
346system.cpu0.numCycles 3925790590 # number of cpu cycles simulated 347system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 348system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 349system.cpu0.kern.inst.arm 0 # number of arm instructions executed 350system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed 351system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed 352system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl 353system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl 354system.cpu0.kern.ipl_count::22 1974 1.40% 41.68% # number of times we switched to this ipl 355system.cpu0.kern.ipl_count::30 422 0.30% 41.97% # number of times we switched to this ipl 356system.cpu0.kern.ipl_count::31 82045 58.03% 100.00% # number of times we switched to this ipl 357system.cpu0.kern.ipl_count::total 141394 # number of times we switched to this ipl 358system.cpu0.kern.ipl_good::0 56288 49.08% 49.08% # number of times we switched to this ipl from a different ipl 359system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl 360system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl 361system.cpu0.kern.ipl_good::30 422 0.37% 51.29% # number of times we switched to this ipl from a different ipl 362system.cpu0.kern.ipl_good::31 55866 48.71% 100.00% # number of times we switched to this ipl from a different ipl 363system.cpu0.kern.ipl_good::total 114681 # number of times we switched to this ipl from a different ipl 364system.cpu0.kern.ipl_ticks::0 1901241129000 96.86% 96.86% # number of cycles we spent at this ipl 365system.cpu0.kern.ipl_ticks::21 93739000 0.00% 96.86% # number of cycles we spent at this ipl 366system.cpu0.kern.ipl_ticks::22 789776000 0.04% 96.90% # number of cycles we spent at this ipl 367system.cpu0.kern.ipl_ticks::30 316619500 0.02% 96.92% # number of cycles we spent at this ipl 368system.cpu0.kern.ipl_ticks::31 60454001500 3.08% 100.00% # number of cycles we spent at this ipl 369system.cpu0.kern.ipl_ticks::total 1962895265000 # number of cycles we spent at this ipl 370system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl 371system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 372system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 373system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 374system.cpu0.kern.ipl_used::31 0.680919 # fraction of swpipl calls that actually changed the ipl 375system.cpu0.kern.ipl_used::total 0.811074 # fraction of swpipl calls that actually changed the ipl 376system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 377system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 378system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 379system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 380system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 381system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 382system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 383system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 384system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 385system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 386system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 387system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 388system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 389system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 390system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 391system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 392system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 393system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 394system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 395system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 396system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 397system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 398system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 399system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 400system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 401system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 402system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 403system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 404system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 405system.cpu0.kern.syscall::total 222 # number of syscalls executed 406system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 407system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed 408system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 409system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 410system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed 411system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed 412system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed 413system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed 414system.cpu0.kern.callpal::swpipl 134533 89.85% 92.28% # number of callpals executed 415system.cpu0.kern.callpal::rdps 6700 4.47% 96.75% # number of callpals executed 416system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed 417system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed 418system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed 419system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed 420system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed 421system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed 422system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed 423system.cpu0.kern.callpal::total 149727 # number of callpals executed 424system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches 425system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches 426system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 427system.cpu0.kern.mode_good::kernel 1282 428system.cpu0.kern.mode_good::user 1282 429system.cpu0.kern.mode_good::idle 0 430system.cpu0.kern.mode_switch_good::kernel 0.186175 # fraction of useful protection mode switches 431system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 432system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 433system.cpu0.kern.mode_switch_good::total 0.313908 # fraction of useful protection mode switches 434system.cpu0.kern.mode_ticks::kernel 1959142459500 99.82% 99.82% # number of ticks spent at the given mode 435system.cpu0.kern.mode_ticks::user 3540793500 0.18% 100.00% # number of ticks spent at the given mode 436system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 437system.cpu0.kern.swap_context 3064 # number of times the context was actually changed 438system.cpu0.committedInsts 47755591 # Number of instructions committed 439system.cpu0.committedOps 47755591 # Number of ops (including micro ops) committed 440system.cpu0.num_int_alu_accesses 44289668 # Number of integer alu accesses 441system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses 442system.cpu0.num_func_calls 1202061 # number of times a function call or return occured 443system.cpu0.num_conditional_control_insts 5613734 # number of instructions that are conditional controls 444system.cpu0.num_int_insts 44289668 # number of integer instructions 445system.cpu0.num_fp_insts 210363 # number of float instructions 446system.cpu0.num_int_register_reads 60881629 # number of times the integer registers were read 447system.cpu0.num_int_register_writes 33006420 # number of times the integer registers were written 448system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read 449system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written 450system.cpu0.num_mem_refs 12600044 # number of memory refs 451system.cpu0.num_load_insts 7521304 # Number of load instructions 452system.cpu0.num_store_insts 5078740 # Number of store instructions 453system.cpu0.num_idle_cycles 3699854946.150013 # Number of idle cycles 454system.cpu0.num_busy_cycles 225935643.849987 # Number of busy cycles 455system.cpu0.not_idle_fraction 0.057552 # Percentage of non-idle cycles 456system.cpu0.idle_fraction 0.942448 # Percentage of idle cycles 457system.cpu0.Branches 7206590 # Number of branches fetched 458system.cpu0.op_class::No_OpClass 2726655 5.71% 5.71% # Class of executed instruction 459system.cpu0.op_class::IntAlu 31439878 65.82% 71.53% # Class of executed instruction 460system.cpu0.op_class::IntMult 52896 0.11% 71.64% # Class of executed instruction 461system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction 462system.cpu0.op_class::FloatAdd 25705 0.05% 71.70% # Class of executed instruction 463system.cpu0.op_class::FloatCmp 0 0.00% 71.70% # Class of executed instruction 464system.cpu0.op_class::FloatCvt 0 0.00% 71.70% # Class of executed instruction 465system.cpu0.op_class::FloatMult 0 0.00% 71.70% # Class of executed instruction 466system.cpu0.op_class::FloatDiv 1656 0.00% 71.70% # Class of executed instruction 467system.cpu0.op_class::FloatSqrt 0 0.00% 71.70% # Class of executed instruction 468system.cpu0.op_class::SimdAdd 0 0.00% 71.70% # Class of executed instruction 469system.cpu0.op_class::SimdAddAcc 0 0.00% 71.70% # Class of executed instruction 470system.cpu0.op_class::SimdAlu 0 0.00% 71.70% # Class of executed instruction 471system.cpu0.op_class::SimdCmp 0 0.00% 71.70% # Class of executed instruction 472system.cpu0.op_class::SimdCvt 0 0.00% 71.70% # Class of executed instruction 473system.cpu0.op_class::SimdMisc 0 0.00% 71.70% # Class of executed instruction 474system.cpu0.op_class::SimdMult 0 0.00% 71.70% # Class of executed instruction 475system.cpu0.op_class::SimdMultAcc 0 0.00% 71.70% # Class of executed instruction 476system.cpu0.op_class::SimdShift 0 0.00% 71.70% # Class of executed instruction 477system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.70% # Class of executed instruction 478system.cpu0.op_class::SimdSqrt 0 0.00% 71.70% # Class of executed instruction 479system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.70% # Class of executed instruction 480system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.70% # Class of executed instruction 481system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.70% # Class of executed instruction 482system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.70% # Class of executed instruction 483system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.70% # Class of executed instruction 484system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.70% # Class of executed instruction 485system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction 486system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction 487system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction 488system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction 489system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction 490system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction 491system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 492system.cpu0.op_class::total 47764191 # Class of executed instruction	359system.cpu0.numCycles 3925790590 # number of cpu cycles simulated 360system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 361system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 362system.cpu0.kern.inst.arm 0 # number of arm instructions executed 363system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed 364system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed 365system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl 366system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl 367system.cpu0.kern.ipl_count::22 1974 1.40% 41.68% # number of times we switched to this ipl 368system.cpu0.kern.ipl_count::30 422 0.30% 41.97% # number of times we switched to this ipl 369system.cpu0.kern.ipl_count::31 82045 58.03% 100.00% # number of times we switched to this ipl 370system.cpu0.kern.ipl_count::total 141394 # number of times we switched to this ipl 371system.cpu0.kern.ipl_good::0 56288 49.08% 49.08% # number of times we switched to this ipl from a different ipl 372system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl 373system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl 374system.cpu0.kern.ipl_good::30 422 0.37% 51.29% # number of times we switched to this ipl from a different ipl 375system.cpu0.kern.ipl_good::31 55866 48.71% 100.00% # number of times we switched to this ipl from a different ipl 376system.cpu0.kern.ipl_good::total 114681 # number of times we switched to this ipl from a different ipl 377system.cpu0.kern.ipl_ticks::0 1901241129000 96.86% 96.86% # number of cycles we spent at this ipl 378system.cpu0.kern.ipl_ticks::21 93739000 0.00% 96.86% # number of cycles we spent at this ipl 379system.cpu0.kern.ipl_ticks::22 789776000 0.04% 96.90% # number of cycles we spent at this ipl 380system.cpu0.kern.ipl_ticks::30 316619500 0.02% 96.92% # number of cycles we spent at this ipl 381system.cpu0.kern.ipl_ticks::31 60454001500 3.08% 100.00% # number of cycles we spent at this ipl 382system.cpu0.kern.ipl_ticks::total 1962895265000 # number of cycles we spent at this ipl 383system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl 384system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 385system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 386system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 387system.cpu0.kern.ipl_used::31 0.680919 # fraction of swpipl calls that actually changed the ipl 388system.cpu0.kern.ipl_used::total 0.811074 # fraction of swpipl calls that actually changed the ipl 389system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 390system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 391system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 392system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 393system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 394system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 395system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 396system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 397system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 398system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 399system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 400system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 401system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 402system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 403system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 404system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 405system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 406system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 407system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 408system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 409system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 410system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 411system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 412system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 413system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 414system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 415system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 416system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 417system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 418system.cpu0.kern.syscall::total 222 # number of syscalls executed 419system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 420system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed 421system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed 422system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed 423system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed 424system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed 425system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed 426system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed 427system.cpu0.kern.callpal::swpipl 134533 89.85% 92.28% # number of callpals executed 428system.cpu0.kern.callpal::rdps 6700 4.47% 96.75% # number of callpals executed 429system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed 430system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed 431system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed 432system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed 433system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed 434system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed 435system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed 436system.cpu0.kern.callpal::total 149727 # number of callpals executed 437system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches 438system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches 439system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 440system.cpu0.kern.mode_good::kernel 1282 441system.cpu0.kern.mode_good::user 1282 442system.cpu0.kern.mode_good::idle 0 443system.cpu0.kern.mode_switch_good::kernel 0.186175 # fraction of useful protection mode switches 444system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 445system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 446system.cpu0.kern.mode_switch_good::total 0.313908 # fraction of useful protection mode switches 447system.cpu0.kern.mode_ticks::kernel 1959142459500 99.82% 99.82% # number of ticks spent at the given mode 448system.cpu0.kern.mode_ticks::user 3540793500 0.18% 100.00% # number of ticks spent at the given mode 449system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 450system.cpu0.kern.swap_context 3064 # number of times the context was actually changed 451system.cpu0.committedInsts 47755591 # Number of instructions committed 452system.cpu0.committedOps 47755591 # Number of ops (including micro ops) committed 453system.cpu0.num_int_alu_accesses 44289668 # Number of integer alu accesses 454system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses 455system.cpu0.num_func_calls 1202061 # number of times a function call or return occured 456system.cpu0.num_conditional_control_insts 5613734 # number of instructions that are conditional controls 457system.cpu0.num_int_insts 44289668 # number of integer instructions 458system.cpu0.num_fp_insts 210363 # number of float instructions 459system.cpu0.num_int_register_reads 60881629 # number of times the integer registers were read 460system.cpu0.num_int_register_writes 33006420 # number of times the integer registers were written 461system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read 462system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written 463system.cpu0.num_mem_refs 12600044 # number of memory refs 464system.cpu0.num_load_insts 7521304 # Number of load instructions 465system.cpu0.num_store_insts 5078740 # Number of store instructions 466system.cpu0.num_idle_cycles 3699854946.150013 # Number of idle cycles 467system.cpu0.num_busy_cycles 225935643.849987 # Number of busy cycles 468system.cpu0.not_idle_fraction 0.057552 # Percentage of non-idle cycles 469system.cpu0.idle_fraction 0.942448 # Percentage of idle cycles 470system.cpu0.Branches 7206590 # Number of branches fetched 471system.cpu0.op_class::No_OpClass 2726655 5.71% 5.71% # Class of executed instruction 472system.cpu0.op_class::IntAlu 31439878 65.82% 71.53% # Class of executed instruction 473system.cpu0.op_class::IntMult 52896 0.11% 71.64% # Class of executed instruction 474system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction 475system.cpu0.op_class::FloatAdd 25705 0.05% 71.70% # Class of executed instruction 476system.cpu0.op_class::FloatCmp 0 0.00% 71.70% # Class of executed instruction 477system.cpu0.op_class::FloatCvt 0 0.00% 71.70% # Class of executed instruction 478system.cpu0.op_class::FloatMult 0 0.00% 71.70% # Class of executed instruction 479system.cpu0.op_class::FloatDiv 1656 0.00% 71.70% # Class of executed instruction 480system.cpu0.op_class::FloatSqrt 0 0.00% 71.70% # Class of executed instruction 481system.cpu0.op_class::SimdAdd 0 0.00% 71.70% # Class of executed instruction 482system.cpu0.op_class::SimdAddAcc 0 0.00% 71.70% # Class of executed instruction 483system.cpu0.op_class::SimdAlu 0 0.00% 71.70% # Class of executed instruction 484system.cpu0.op_class::SimdCmp 0 0.00% 71.70% # Class of executed instruction 485system.cpu0.op_class::SimdCvt 0 0.00% 71.70% # Class of executed instruction 486system.cpu0.op_class::SimdMisc 0 0.00% 71.70% # Class of executed instruction 487system.cpu0.op_class::SimdMult 0 0.00% 71.70% # Class of executed instruction 488system.cpu0.op_class::SimdMultAcc 0 0.00% 71.70% # Class of executed instruction 489system.cpu0.op_class::SimdShift 0 0.00% 71.70% # Class of executed instruction 490system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.70% # Class of executed instruction 491system.cpu0.op_class::SimdSqrt 0 0.00% 71.70% # Class of executed instruction 492system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.70% # Class of executed instruction 493system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.70% # Class of executed instruction 494system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.70% # Class of executed instruction 495system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.70% # Class of executed instruction 496system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.70% # Class of executed instruction 497system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.70% # Class of executed instruction 498system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction 499system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction 500system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction 501system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction 502system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction 503system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction 504system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 505system.cpu0.op_class::total 47764191 # Class of executed instruction
	506system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
493system.cpu0.dcache.tags.replacements 1179864 # number of replacements 494system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use 495system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks. 496system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks. 497system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks. 498system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. 499system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor 500system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy 501system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy 502system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id 503system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id 504system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 505system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 506system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses 507system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses	507system.cpu0.dcache.tags.replacements 1179864 # number of replacements 508system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use 509system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks. 510system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks. 511system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks. 512system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. 513system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor 514system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy 515system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy 516system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id 517system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id 518system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id 519system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 520system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses 521system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses
	522system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
508system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits 509system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits 510system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits 511system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits 512system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits 513system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits 514system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits 515system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits 516system.cpu0.dcache.demand_hits::cpu0.data 11068906 # number of demand (read+write) hits 517system.cpu0.dcache.demand_hits::total 11068906 # number of demand (read+write) hits 518system.cpu0.dcache.overall_hits::cpu0.data 11068906 # number of overall hits 519system.cpu0.dcache.overall_hits::total 11068906 # number of overall hits 520system.cpu0.dcache.ReadReq_misses::cpu0.data 937797 # number of ReadReq misses 521system.cpu0.dcache.ReadReq_misses::total 937797 # number of ReadReq misses 522system.cpu0.dcache.WriteReq_misses::cpu0.data 251494 # number of WriteReq misses 523system.cpu0.dcache.WriteReq_misses::total 251494 # number of WriteReq misses 524system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses 525system.cpu0.dcache.LoadLockedReq_misses::total 13653 # number of LoadLockedReq misses 526system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5444 # number of StoreCondReq misses 527system.cpu0.dcache.StoreCondReq_misses::total 5444 # number of StoreCondReq misses 528system.cpu0.dcache.demand_misses::cpu0.data 1189291 # number of demand (read+write) misses 529system.cpu0.dcache.demand_misses::total 1189291 # number of demand (read+write) misses 530system.cpu0.dcache.overall_misses::cpu0.data 1189291 # number of overall misses 531system.cpu0.dcache.overall_misses::total 1189291 # number of overall misses 532system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29158420500 # number of ReadReq miss cycles 533system.cpu0.dcache.ReadReq_miss_latency::total 29158420500 # number of ReadReq miss cycles 534system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10960256500 # number of WriteReq miss cycles 535system.cpu0.dcache.WriteReq_miss_latency::total 10960256500 # number of WriteReq miss cycles 536system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150265500 # number of LoadLockedReq miss cycles 537system.cpu0.dcache.LoadLockedReq_miss_latency::total 150265500 # number of LoadLockedReq miss cycles 538system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47401000 # number of StoreCondReq miss cycles 539system.cpu0.dcache.StoreCondReq_miss_latency::total 47401000 # number of StoreCondReq miss cycles 540system.cpu0.dcache.demand_miss_latency::cpu0.data 40118677000 # number of demand (read+write) miss cycles 541system.cpu0.dcache.demand_miss_latency::total 40118677000 # number of demand (read+write) miss cycles 542system.cpu0.dcache.overall_miss_latency::cpu0.data 40118677000 # number of overall miss cycles 543system.cpu0.dcache.overall_miss_latency::total 40118677000 # number of overall miss cycles 544system.cpu0.dcache.ReadReq_accesses::cpu0.data 7348970 # number of ReadReq accesses(hits+misses) 545system.cpu0.dcache.ReadReq_accesses::total 7348970 # number of ReadReq accesses(hits+misses) 546system.cpu0.dcache.WriteReq_accesses::cpu0.data 4909227 # number of WriteReq accesses(hits+misses) 547system.cpu0.dcache.WriteReq_accesses::total 4909227 # number of WriteReq accesses(hits+misses) 548system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157571 # number of LoadLockedReq accesses(hits+misses) 549system.cpu0.dcache.LoadLockedReq_accesses::total 157571 # number of LoadLockedReq accesses(hits+misses) 550system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153396 # number of StoreCondReq accesses(hits+misses) 551system.cpu0.dcache.StoreCondReq_accesses::total 153396 # number of StoreCondReq accesses(hits+misses) 552system.cpu0.dcache.demand_accesses::cpu0.data 12258197 # number of demand (read+write) accesses 553system.cpu0.dcache.demand_accesses::total 12258197 # number of demand (read+write) accesses 554system.cpu0.dcache.overall_accesses::cpu0.data 12258197 # number of overall (read+write) accesses 555system.cpu0.dcache.overall_accesses::total 12258197 # number of overall (read+write) accesses 556system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127609 # miss rate for ReadReq accesses 557system.cpu0.dcache.ReadReq_miss_rate::total 0.127609 # miss rate for ReadReq accesses 558system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051229 # miss rate for WriteReq accesses 559system.cpu0.dcache.WriteReq_miss_rate::total 0.051229 # miss rate for WriteReq accesses 560system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086647 # miss rate for LoadLockedReq accesses 561system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086647 # miss rate for LoadLockedReq accesses 562system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035490 # miss rate for StoreCondReq accesses 563system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035490 # miss rate for StoreCondReq accesses 564system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097020 # miss rate for demand accesses 565system.cpu0.dcache.demand_miss_rate::total 0.097020 # miss rate for demand accesses 566system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097020 # miss rate for overall accesses 567system.cpu0.dcache.overall_miss_rate::total 0.097020 # miss rate for overall accesses 568system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107 # average ReadReq miss latency 569system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107 # average ReadReq miss latency 570system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404 # average WriteReq miss latency 571system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404 # average WriteReq miss latency 572system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628 # average LoadLockedReq miss latency 573system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628 # average LoadLockedReq miss latency 574system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8707.016899 # average StoreCondReq miss latency 575system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8707.016899 # average StoreCondReq miss latency 576system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency 577system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176 # average overall miss latency 578system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency 579system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176 # average overall miss latency 580system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 581system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 582system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 583system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 584system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 585system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 586system.cpu0.dcache.writebacks::writebacks 678308 # number of writebacks 587system.cpu0.dcache.writebacks::total 678308 # number of writebacks 588system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937797 # number of ReadReq MSHR misses 589system.cpu0.dcache.ReadReq_mshr_misses::total 937797 # number of ReadReq MSHR misses 590system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251494 # number of WriteReq MSHR misses 591system.cpu0.dcache.WriteReq_mshr_misses::total 251494 # number of WriteReq MSHR misses 592system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13653 # number of LoadLockedReq MSHR misses 593system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13653 # number of LoadLockedReq MSHR misses 594system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5444 # number of StoreCondReq MSHR misses 595system.cpu0.dcache.StoreCondReq_mshr_misses::total 5444 # number of StoreCondReq MSHR misses 596system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189291 # number of demand (read+write) MSHR misses 597system.cpu0.dcache.demand_mshr_misses::total 1189291 # number of demand (read+write) MSHR misses 598system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189291 # number of overall MSHR misses 599system.cpu0.dcache.overall_mshr_misses::total 1189291 # number of overall MSHR misses 600system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable 601system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable 602system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable 603system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable 604system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses 605system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses 606system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28220623500 # number of ReadReq MSHR miss cycles 607system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28220623500 # number of ReadReq MSHR miss cycles 608system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10708762500 # number of WriteReq MSHR miss cycles 609system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10708762500 # number of WriteReq MSHR miss cycles 610system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136612500 # number of LoadLockedReq MSHR miss cycles 611system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136612500 # number of LoadLockedReq MSHR miss cycles 612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41957000 # number of StoreCondReq MSHR miss cycles 613system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41957000 # number of StoreCondReq MSHR miss cycles 614system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38929386000 # number of demand (read+write) MSHR miss cycles 615system.cpu0.dcache.demand_mshr_miss_latency::total 38929386000 # number of demand (read+write) MSHR miss cycles 616system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38929386000 # number of overall MSHR miss cycles 617system.cpu0.dcache.overall_mshr_miss_latency::total 38929386000 # number of overall MSHR miss cycles 618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578468500 # number of ReadReq MSHR uncacheable cycles 619system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578468500 # number of ReadReq MSHR uncacheable cycles 620system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578468500 # number of overall MSHR uncacheable cycles 621system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578468500 # number of overall MSHR uncacheable cycles 622system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127609 # mshr miss rate for ReadReq accesses 623system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127609 # mshr miss rate for ReadReq accesses 624system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051229 # mshr miss rate for WriteReq accesses 625system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051229 # mshr miss rate for WriteReq accesses 626system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086647 # mshr miss rate for LoadLockedReq accesses 627system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086647 # mshr miss rate for LoadLockedReq accesses 628system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for StoreCondReq accesses 629system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035490 # mshr miss rate for StoreCondReq accesses 630system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for demand accesses 631system.cpu0.dcache.demand_mshr_miss_rate::total 0.097020 # mshr miss rate for demand accesses 632system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for overall accesses 633system.cpu0.dcache.overall_mshr_miss_rate::total 0.097020 # mshr miss rate for overall accesses 634system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107 # average ReadReq mshr miss latency 635system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107 # average ReadReq mshr miss latency 636system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404 # average WriteReq mshr miss latency 637system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404 # average WriteReq mshr miss latency 638system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628 # average LoadLockedReq mshr miss latency 639system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628 # average LoadLockedReq mshr miss latency 640system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7707.016899 # average StoreCondReq mshr miss latency 641system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7707.016899 # average StoreCondReq mshr miss latency 642system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency 643system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency 644system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency 645system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency 646system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency 647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency 648system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency 649system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency	523system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits 524system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits 525system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits 526system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits 527system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits 528system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits 529system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits 530system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits 531system.cpu0.dcache.demand_hits::cpu0.data 11068906 # number of demand (read+write) hits 532system.cpu0.dcache.demand_hits::total 11068906 # number of demand (read+write) hits 533system.cpu0.dcache.overall_hits::cpu0.data 11068906 # number of overall hits 534system.cpu0.dcache.overall_hits::total 11068906 # number of overall hits 535system.cpu0.dcache.ReadReq_misses::cpu0.data 937797 # number of ReadReq misses 536system.cpu0.dcache.ReadReq_misses::total 937797 # number of ReadReq misses 537system.cpu0.dcache.WriteReq_misses::cpu0.data 251494 # number of WriteReq misses 538system.cpu0.dcache.WriteReq_misses::total 251494 # number of WriteReq misses 539system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses 540system.cpu0.dcache.LoadLockedReq_misses::total 13653 # number of LoadLockedReq misses 541system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5444 # number of StoreCondReq misses 542system.cpu0.dcache.StoreCondReq_misses::total 5444 # number of StoreCondReq misses 543system.cpu0.dcache.demand_misses::cpu0.data 1189291 # number of demand (read+write) misses 544system.cpu0.dcache.demand_misses::total 1189291 # number of demand (read+write) misses 545system.cpu0.dcache.overall_misses::cpu0.data 1189291 # number of overall misses 546system.cpu0.dcache.overall_misses::total 1189291 # number of overall misses 547system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29158420500 # number of ReadReq miss cycles 548system.cpu0.dcache.ReadReq_miss_latency::total 29158420500 # number of ReadReq miss cycles 549system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10960256500 # number of WriteReq miss cycles 550system.cpu0.dcache.WriteReq_miss_latency::total 10960256500 # number of WriteReq miss cycles 551system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150265500 # number of LoadLockedReq miss cycles 552system.cpu0.dcache.LoadLockedReq_miss_latency::total 150265500 # number of LoadLockedReq miss cycles 553system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47401000 # number of StoreCondReq miss cycles 554system.cpu0.dcache.StoreCondReq_miss_latency::total 47401000 # number of StoreCondReq miss cycles 555system.cpu0.dcache.demand_miss_latency::cpu0.data 40118677000 # number of demand (read+write) miss cycles 556system.cpu0.dcache.demand_miss_latency::total 40118677000 # number of demand (read+write) miss cycles 557system.cpu0.dcache.overall_miss_latency::cpu0.data 40118677000 # number of overall miss cycles 558system.cpu0.dcache.overall_miss_latency::total 40118677000 # number of overall miss cycles 559system.cpu0.dcache.ReadReq_accesses::cpu0.data 7348970 # number of ReadReq accesses(hits+misses) 560system.cpu0.dcache.ReadReq_accesses::total 7348970 # number of ReadReq accesses(hits+misses) 561system.cpu0.dcache.WriteReq_accesses::cpu0.data 4909227 # number of WriteReq accesses(hits+misses) 562system.cpu0.dcache.WriteReq_accesses::total 4909227 # number of WriteReq accesses(hits+misses) 563system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157571 # number of LoadLockedReq accesses(hits+misses) 564system.cpu0.dcache.LoadLockedReq_accesses::total 157571 # number of LoadLockedReq accesses(hits+misses) 565system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153396 # number of StoreCondReq accesses(hits+misses) 566system.cpu0.dcache.StoreCondReq_accesses::total 153396 # number of StoreCondReq accesses(hits+misses) 567system.cpu0.dcache.demand_accesses::cpu0.data 12258197 # number of demand (read+write) accesses 568system.cpu0.dcache.demand_accesses::total 12258197 # number of demand (read+write) accesses 569system.cpu0.dcache.overall_accesses::cpu0.data 12258197 # number of overall (read+write) accesses 570system.cpu0.dcache.overall_accesses::total 12258197 # number of overall (read+write) accesses 571system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127609 # miss rate for ReadReq accesses 572system.cpu0.dcache.ReadReq_miss_rate::total 0.127609 # miss rate for ReadReq accesses 573system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051229 # miss rate for WriteReq accesses 574system.cpu0.dcache.WriteReq_miss_rate::total 0.051229 # miss rate for WriteReq accesses 575system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086647 # miss rate for LoadLockedReq accesses 576system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086647 # miss rate for LoadLockedReq accesses 577system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035490 # miss rate for StoreCondReq accesses 578system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035490 # miss rate for StoreCondReq accesses 579system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097020 # miss rate for demand accesses 580system.cpu0.dcache.demand_miss_rate::total 0.097020 # miss rate for demand accesses 581system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097020 # miss rate for overall accesses 582system.cpu0.dcache.overall_miss_rate::total 0.097020 # miss rate for overall accesses 583system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107 # average ReadReq miss latency 584system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107 # average ReadReq miss latency 585system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404 # average WriteReq miss latency 586system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404 # average WriteReq miss latency 587system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628 # average LoadLockedReq miss latency 588system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628 # average LoadLockedReq miss latency 589system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8707.016899 # average StoreCondReq miss latency 590system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8707.016899 # average StoreCondReq miss latency 591system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency 592system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176 # average overall miss latency 593system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency 594system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176 # average overall miss latency 595system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 596system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 597system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 598system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 599system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 600system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 601system.cpu0.dcache.writebacks::writebacks 678308 # number of writebacks 602system.cpu0.dcache.writebacks::total 678308 # number of writebacks 603system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937797 # number of ReadReq MSHR misses 604system.cpu0.dcache.ReadReq_mshr_misses::total 937797 # number of ReadReq MSHR misses 605system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251494 # number of WriteReq MSHR misses 606system.cpu0.dcache.WriteReq_mshr_misses::total 251494 # number of WriteReq MSHR misses 607system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13653 # number of LoadLockedReq MSHR misses 608system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13653 # number of LoadLockedReq MSHR misses 609system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5444 # number of StoreCondReq MSHR misses 610system.cpu0.dcache.StoreCondReq_mshr_misses::total 5444 # number of StoreCondReq MSHR misses 611system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189291 # number of demand (read+write) MSHR misses 612system.cpu0.dcache.demand_mshr_misses::total 1189291 # number of demand (read+write) MSHR misses 613system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189291 # number of overall MSHR misses 614system.cpu0.dcache.overall_mshr_misses::total 1189291 # number of overall MSHR misses 615system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable 616system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable 617system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable 618system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable 619system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses 620system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses 621system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28220623500 # number of ReadReq MSHR miss cycles 622system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28220623500 # number of ReadReq MSHR miss cycles 623system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10708762500 # number of WriteReq MSHR miss cycles 624system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10708762500 # number of WriteReq MSHR miss cycles 625system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136612500 # number of LoadLockedReq MSHR miss cycles 626system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136612500 # number of LoadLockedReq MSHR miss cycles 627system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41957000 # number of StoreCondReq MSHR miss cycles 628system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41957000 # number of StoreCondReq MSHR miss cycles 629system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38929386000 # number of demand (read+write) MSHR miss cycles 630system.cpu0.dcache.demand_mshr_miss_latency::total 38929386000 # number of demand (read+write) MSHR miss cycles 631system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38929386000 # number of overall MSHR miss cycles 632system.cpu0.dcache.overall_mshr_miss_latency::total 38929386000 # number of overall MSHR miss cycles 633system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578468500 # number of ReadReq MSHR uncacheable cycles 634system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578468500 # number of ReadReq MSHR uncacheable cycles 635system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578468500 # number of overall MSHR uncacheable cycles 636system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578468500 # number of overall MSHR uncacheable cycles 637system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127609 # mshr miss rate for ReadReq accesses 638system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127609 # mshr miss rate for ReadReq accesses 639system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051229 # mshr miss rate for WriteReq accesses 640system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051229 # mshr miss rate for WriteReq accesses 641system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086647 # mshr miss rate for LoadLockedReq accesses 642system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086647 # mshr miss rate for LoadLockedReq accesses 643system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for StoreCondReq accesses 644system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035490 # mshr miss rate for StoreCondReq accesses 645system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for demand accesses 646system.cpu0.dcache.demand_mshr_miss_rate::total 0.097020 # mshr miss rate for demand accesses 647system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for overall accesses 648system.cpu0.dcache.overall_mshr_miss_rate::total 0.097020 # mshr miss rate for overall accesses 649system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107 # average ReadReq mshr miss latency 650system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107 # average ReadReq mshr miss latency 651system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404 # average WriteReq mshr miss latency 652system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404 # average WriteReq mshr miss latency 653system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628 # average LoadLockedReq mshr miss latency 654system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628 # average LoadLockedReq mshr miss latency 655system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7707.016899 # average StoreCondReq mshr miss latency 656system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7707.016899 # average StoreCondReq mshr miss latency 657system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency 658system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency 659system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency 660system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency 661system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency 662system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency 663system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency 664system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency
	665system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
650system.cpu0.icache.tags.replacements 698162 # number of replacements 651system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use 652system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks. 653system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks. 654system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks. 655system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit. 656system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor 657system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy 658system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy 659system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 660system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id 661system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 662system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 663system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses 664system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses	666system.cpu0.icache.tags.replacements 698162 # number of replacements 667system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use 668system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks. 669system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks. 670system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks. 671system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit. 672system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor 673system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy 674system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy 675system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 676system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id 677system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id 678system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 679system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses 680system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses
	681system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
665system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits 666system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits 667system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits 668system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits 669system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits 670system.cpu0.icache.overall_hits::total 47065399 # number of overall hits 671system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses 672system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses 673system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses 674system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses 675system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses 676system.cpu0.icache.overall_misses::total 698792 # number of overall misses 677system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10197257500 # number of ReadReq miss cycles 678system.cpu0.icache.ReadReq_miss_latency::total 10197257500 # number of ReadReq miss cycles 679system.cpu0.icache.demand_miss_latency::cpu0.inst 10197257500 # number of demand (read+write) miss cycles 680system.cpu0.icache.demand_miss_latency::total 10197257500 # number of demand (read+write) miss cycles 681system.cpu0.icache.overall_miss_latency::cpu0.inst 10197257500 # number of overall miss cycles 682system.cpu0.icache.overall_miss_latency::total 10197257500 # number of overall miss cycles 683system.cpu0.icache.ReadReq_accesses::cpu0.inst 47764191 # number of ReadReq accesses(hits+misses) 684system.cpu0.icache.ReadReq_accesses::total 47764191 # number of ReadReq accesses(hits+misses) 685system.cpu0.icache.demand_accesses::cpu0.inst 47764191 # number of demand (read+write) accesses 686system.cpu0.icache.demand_accesses::total 47764191 # number of demand (read+write) accesses 687system.cpu0.icache.overall_accesses::cpu0.inst 47764191 # number of overall (read+write) accesses 688system.cpu0.icache.overall_accesses::total 47764191 # number of overall (read+write) accesses 689system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014630 # miss rate for ReadReq accesses 690system.cpu0.icache.ReadReq_miss_rate::total 0.014630 # miss rate for ReadReq accesses 691system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014630 # miss rate for demand accesses 692system.cpu0.icache.demand_miss_rate::total 0.014630 # miss rate for demand accesses 693system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014630 # miss rate for overall accesses 694system.cpu0.icache.overall_miss_rate::total 0.014630 # miss rate for overall accesses 695system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534 # average ReadReq miss latency 696system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534 # average ReadReq miss latency 697system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency 698system.cpu0.icache.demand_avg_miss_latency::total 14592.693534 # average overall miss latency 699system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency 700system.cpu0.icache.overall_avg_miss_latency::total 14592.693534 # average overall miss latency 701system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 702system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 703system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 704system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 705system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 706system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 707system.cpu0.icache.writebacks::writebacks 698162 # number of writebacks 708system.cpu0.icache.writebacks::total 698162 # number of writebacks 709system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses 710system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses 711system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses 712system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses 713system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses 714system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses 715system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9498465500 # number of ReadReq MSHR miss cycles 716system.cpu0.icache.ReadReq_mshr_miss_latency::total 9498465500 # number of ReadReq MSHR miss cycles 717system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9498465500 # number of demand (read+write) MSHR miss cycles 718system.cpu0.icache.demand_mshr_miss_latency::total 9498465500 # number of demand (read+write) MSHR miss cycles 719system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9498465500 # number of overall MSHR miss cycles 720system.cpu0.icache.overall_mshr_miss_latency::total 9498465500 # number of overall MSHR miss cycles 721system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for ReadReq accesses 722system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014630 # mshr miss rate for ReadReq accesses 723system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for demand accesses 724system.cpu0.icache.demand_mshr_miss_rate::total 0.014630 # mshr miss rate for demand accesses 725system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for overall accesses 726system.cpu0.icache.overall_mshr_miss_rate::total 0.014630 # mshr miss rate for overall accesses 727system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average ReadReq mshr miss latency 728system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534 # average ReadReq mshr miss latency 729system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency 730system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency 731system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency 732system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency 733system.cpu1.dtb.fetch_hits 0 # ITB hits 734system.cpu1.dtb.fetch_misses 0 # ITB misses 735system.cpu1.dtb.fetch_acv 0 # ITB acv 736system.cpu1.dtb.fetch_accesses 0 # ITB accesses 737system.cpu1.dtb.read_hits 2421538 # DTB read hits 738system.cpu1.dtb.read_misses 2992 # DTB read misses 739system.cpu1.dtb.read_acv 0 # DTB read access violations 740system.cpu1.dtb.read_accesses 239363 # DTB read accesses 741system.cpu1.dtb.write_hits 1759460 # DTB write hits 742system.cpu1.dtb.write_misses 341 # DTB write misses 743system.cpu1.dtb.write_acv 29 # DTB write access violations 744system.cpu1.dtb.write_accesses 105247 # DTB write accesses 745system.cpu1.dtb.data_hits 4180998 # DTB hits 746system.cpu1.dtb.data_misses 3333 # DTB misses 747system.cpu1.dtb.data_acv 29 # DTB access violations 748system.cpu1.dtb.data_accesses 344610 # DTB accesses 749system.cpu1.itb.fetch_hits 1965348 # ITB hits 750system.cpu1.itb.fetch_misses 1216 # ITB misses 751system.cpu1.itb.fetch_acv 0 # ITB acv 752system.cpu1.itb.fetch_accesses 1966564 # ITB accesses 753system.cpu1.itb.read_hits 0 # DTB read hits 754system.cpu1.itb.read_misses 0 # DTB read misses 755system.cpu1.itb.read_acv 0 # DTB read access violations 756system.cpu1.itb.read_accesses 0 # DTB read accesses 757system.cpu1.itb.write_hits 0 # DTB write hits 758system.cpu1.itb.write_misses 0 # DTB write misses 759system.cpu1.itb.write_acv 0 # DTB write access violations 760system.cpu1.itb.write_accesses 0 # DTB write accesses 761system.cpu1.itb.data_hits 0 # DTB hits 762system.cpu1.itb.data_misses 0 # DTB misses 763system.cpu1.itb.data_acv 0 # DTB access violations 764system.cpu1.itb.data_accesses 0 # DTB accesses	682system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits 683system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits 684system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits 685system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits 686system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits 687system.cpu0.icache.overall_hits::total 47065399 # number of overall hits 688system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses 689system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses 690system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses 691system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses 692system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses 693system.cpu0.icache.overall_misses::total 698792 # number of overall misses 694system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10197257500 # number of ReadReq miss cycles 695system.cpu0.icache.ReadReq_miss_latency::total 10197257500 # number of ReadReq miss cycles 696system.cpu0.icache.demand_miss_latency::cpu0.inst 10197257500 # number of demand (read+write) miss cycles 697system.cpu0.icache.demand_miss_latency::total 10197257500 # number of demand (read+write) miss cycles 698system.cpu0.icache.overall_miss_latency::cpu0.inst 10197257500 # number of overall miss cycles 699system.cpu0.icache.overall_miss_latency::total 10197257500 # number of overall miss cycles 700system.cpu0.icache.ReadReq_accesses::cpu0.inst 47764191 # number of ReadReq accesses(hits+misses) 701system.cpu0.icache.ReadReq_accesses::total 47764191 # number of ReadReq accesses(hits+misses) 702system.cpu0.icache.demand_accesses::cpu0.inst 47764191 # number of demand (read+write) accesses 703system.cpu0.icache.demand_accesses::total 47764191 # number of demand (read+write) accesses 704system.cpu0.icache.overall_accesses::cpu0.inst 47764191 # number of overall (read+write) accesses 705system.cpu0.icache.overall_accesses::total 47764191 # number of overall (read+write) accesses 706system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014630 # miss rate for ReadReq accesses 707system.cpu0.icache.ReadReq_miss_rate::total 0.014630 # miss rate for ReadReq accesses 708system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014630 # miss rate for demand accesses 709system.cpu0.icache.demand_miss_rate::total 0.014630 # miss rate for demand accesses 710system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014630 # miss rate for overall accesses 711system.cpu0.icache.overall_miss_rate::total 0.014630 # miss rate for overall accesses 712system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534 # average ReadReq miss latency 713system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534 # average ReadReq miss latency 714system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency 715system.cpu0.icache.demand_avg_miss_latency::total 14592.693534 # average overall miss latency 716system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency 717system.cpu0.icache.overall_avg_miss_latency::total 14592.693534 # average overall miss latency 718system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 719system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 721system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 723system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu0.icache.writebacks::writebacks 698162 # number of writebacks 725system.cpu0.icache.writebacks::total 698162 # number of writebacks 726system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses 727system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses 728system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses 729system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses 730system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses 731system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses 732system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9498465500 # number of ReadReq MSHR miss cycles 733system.cpu0.icache.ReadReq_mshr_miss_latency::total 9498465500 # number of ReadReq MSHR miss cycles 734system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9498465500 # number of demand (read+write) MSHR miss cycles 735system.cpu0.icache.demand_mshr_miss_latency::total 9498465500 # number of demand (read+write) MSHR miss cycles 736system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9498465500 # number of overall MSHR miss cycles 737system.cpu0.icache.overall_mshr_miss_latency::total 9498465500 # number of overall MSHR miss cycles 738system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for ReadReq accesses 739system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014630 # mshr miss rate for ReadReq accesses 740system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for demand accesses 741system.cpu0.icache.demand_mshr_miss_rate::total 0.014630 # mshr miss rate for demand accesses 742system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for overall accesses 743system.cpu0.icache.overall_mshr_miss_rate::total 0.014630 # mshr miss rate for overall accesses 744system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average ReadReq mshr miss latency 745system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534 # average ReadReq mshr miss latency 746system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency 747system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency 748system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency 749system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency 750system.cpu1.dtb.fetch_hits 0 # ITB hits 751system.cpu1.dtb.fetch_misses 0 # ITB misses 752system.cpu1.dtb.fetch_acv 0 # ITB acv 753system.cpu1.dtb.fetch_accesses 0 # ITB accesses 754system.cpu1.dtb.read_hits 2421538 # DTB read hits 755system.cpu1.dtb.read_misses 2992 # DTB read misses 756system.cpu1.dtb.read_acv 0 # DTB read access violations 757system.cpu1.dtb.read_accesses 239363 # DTB read accesses 758system.cpu1.dtb.write_hits 1759460 # DTB write hits 759system.cpu1.dtb.write_misses 341 # DTB write misses 760system.cpu1.dtb.write_acv 29 # DTB write access violations 761system.cpu1.dtb.write_accesses 105247 # DTB write accesses 762system.cpu1.dtb.data_hits 4180998 # DTB hits 763system.cpu1.dtb.data_misses 3333 # DTB misses 764system.cpu1.dtb.data_acv 29 # DTB access violations 765system.cpu1.dtb.data_accesses 344610 # DTB accesses 766system.cpu1.itb.fetch_hits 1965348 # ITB hits 767system.cpu1.itb.fetch_misses 1216 # ITB misses 768system.cpu1.itb.fetch_acv 0 # ITB acv 769system.cpu1.itb.fetch_accesses 1966564 # ITB accesses 770system.cpu1.itb.read_hits 0 # DTB read hits 771system.cpu1.itb.read_misses 0 # DTB read misses 772system.cpu1.itb.read_acv 0 # DTB read access violations 773system.cpu1.itb.read_accesses 0 # DTB read accesses 774system.cpu1.itb.write_hits 0 # DTB write hits 775system.cpu1.itb.write_misses 0 # DTB write misses 776system.cpu1.itb.write_acv 0 # DTB write access violations 777system.cpu1.itb.write_accesses 0 # DTB write accesses 778system.cpu1.itb.data_hits 0 # DTB hits 779system.cpu1.itb.data_misses 0 # DTB misses 780system.cpu1.itb.data_acv 0 # DTB access violations 781system.cpu1.itb.data_accesses 0 # DTB accesses
	782system.cpu1.numPwrStateTransitions 5480 # Number of power state transitions 783system.cpu1.pwrStateClkGateDist::samples 2740 # Distribution of time spent in the clock gated state 784system.cpu1.pwrStateClkGateDist::mean 707616074.452555 # Distribution of time spent in the clock gated state 785system.cpu1.pwrStateClkGateDist::stdev 409900069.702285 # Distribution of time spent in the clock gated state 786system.cpu1.pwrStateClkGateDist::1000-5e+10 2740 100.00% 100.00% # Distribution of time spent in the clock gated state 787system.cpu1.pwrStateClkGateDist::min_value 76500 # Distribution of time spent in the clock gated state 788system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state 789system.cpu1.pwrStateClkGateDist::total 2740 # Distribution of time spent in the clock gated state 790system.cpu1.pwrStateResidencyTicks::ON 24744530000 # Cumulative time (in ticks) in various power states 791system.cpu1.pwrStateResidencyTicks::CLK_GATED 1938868044000 # Cumulative time (in ticks) in various power states
765system.cpu1.numCycles 3927225148 # number of cpu cycles simulated 766system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 767system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 768system.cpu1.kern.inst.arm 0 # number of arm instructions executed 769system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed 770system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed 771system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl 772system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl 773system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl 774system.cpu1.kern.ipl_count::31 40242 58.09% 100.00% # number of times we switched to this ipl 775system.cpu1.kern.ipl_count::total 69281 # number of times we switched to this ipl 776system.cpu1.kern.ipl_good::0 25724 48.16% 48.16% # number of times we switched to this ipl from a different ipl 777system.cpu1.kern.ipl_good::22 1968 3.68% 51.84% # number of times we switched to this ipl from a different ipl 778system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl 779system.cpu1.kern.ipl_good::31 25220 47.21% 100.00% # number of times we switched to this ipl from a different ipl 780system.cpu1.kern.ipl_good::total 53416 # number of times we switched to this ipl from a different ipl 781system.cpu1.kern.ipl_ticks::0 1910368546000 97.29% 97.29% # number of cycles we spent at this ipl 782system.cpu1.kern.ipl_ticks::22 730956000 0.04% 97.33% # number of cycles we spent at this ipl 783system.cpu1.kern.ipl_ticks::30 356511000 0.02% 97.34% # number of cycles we spent at this ipl 784system.cpu1.kern.ipl_ticks::31 52155834000 2.66% 100.00% # number of cycles we spent at this ipl 785system.cpu1.kern.ipl_ticks::total 1963611847000 # number of cycles we spent at this ipl 786system.cpu1.kern.ipl_used::0 0.968269 # fraction of swpipl calls that actually changed the ipl 787system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 788system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 789system.cpu1.kern.ipl_used::31 0.626708 # fraction of swpipl calls that actually changed the ipl 790system.cpu1.kern.ipl_used::total 0.771005 # fraction of swpipl calls that actually changed the ipl 791system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 792system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 793system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 794system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 795system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 796system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 797system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 798system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 799system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 800system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 801system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 802system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 803system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 804system.cpu1.kern.syscall::total 104 # number of syscalls executed 805system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 806system.cpu1.kern.callpal::wripir 422 0.59% 0.59% # number of callpals executed 807system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 808system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 809system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed 810system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed 811system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed 812system.cpu1.kern.callpal::swpipl 63030 88.06% 91.46% # number of callpals executed 813system.cpu1.kern.callpal::rdps 2146 3.00% 94.46% # number of callpals executed 814system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed 815system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed 816system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed 817system.cpu1.kern.callpal::rti 3778 5.28% 99.75% # number of callpals executed 818system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed 819system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 820system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 821system.cpu1.kern.callpal::total 71579 # number of callpals executed 822system.cpu1.kern.mode_switch::kernel 2069 # number of protection mode switches 823system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 824system.cpu1.kern.mode_switch::idle 2878 # number of protection mode switches 825system.cpu1.kern.mode_good::kernel 892 826system.cpu1.kern.mode_good::user 464 827system.cpu1.kern.mode_good::idle 428 828system.cpu1.kern.mode_switch_good::kernel 0.431126 # fraction of useful protection mode switches 829system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 830system.cpu1.kern.mode_switch_good::idle 0.148714 # fraction of useful protection mode switches 831system.cpu1.kern.mode_switch_good::total 0.329699 # fraction of useful protection mode switches 832system.cpu1.kern.mode_ticks::kernel 17834392500 0.91% 0.91% # number of ticks spent at the given mode 833system.cpu1.kern.mode_ticks::user 1709021000 0.09% 1.00% # number of ticks spent at the given mode 834system.cpu1.kern.mode_ticks::idle 1944068431500 99.00% 100.00% # number of ticks spent at the given mode 835system.cpu1.kern.swap_context 2002 # number of times the context was actually changed 836system.cpu1.committedInsts 13162574 # Number of instructions committed 837system.cpu1.committedOps 13162574 # Number of ops (including micro ops) committed 838system.cpu1.num_int_alu_accesses 12139381 # Number of integer alu accesses 839system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses 840system.cpu1.num_func_calls 411749 # number of times a function call or return occured 841system.cpu1.num_conditional_control_insts 1304648 # number of instructions that are conditional controls 842system.cpu1.num_int_insts 12139381 # number of integer instructions 843system.cpu1.num_fp_insts 173446 # number of float instructions 844system.cpu1.num_int_register_reads 16710166 # number of times the integer registers were read 845system.cpu1.num_int_register_writes 8908141 # number of times the integer registers were written 846system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read 847system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written 848system.cpu1.num_mem_refs 4204594 # number of memory refs 849system.cpu1.num_load_insts 2435865 # Number of load instructions 850system.cpu1.num_store_insts 1768729 # Number of store instructions 851system.cpu1.num_idle_cycles 3877736087.998025 # Number of idle cycles 852system.cpu1.num_busy_cycles 49489060.001975 # Number of busy cycles 853system.cpu1.not_idle_fraction 0.012602 # Percentage of non-idle cycles 854system.cpu1.idle_fraction 0.987398 # Percentage of idle cycles 855system.cpu1.Branches 1871255 # Number of branches fetched 856system.cpu1.op_class::No_OpClass 705493 5.36% 5.36% # Class of executed instruction 857system.cpu1.op_class::IntAlu 7781042 59.10% 64.46% # Class of executed instruction 858system.cpu1.op_class::IntMult 21322 0.16% 64.62% # Class of executed instruction 859system.cpu1.op_class::IntDiv 0 0.00% 64.62% # Class of executed instruction 860system.cpu1.op_class::FloatAdd 14181 0.11% 64.73% # Class of executed instruction 861system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction 862system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction 863system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction 864system.cpu1.op_class::FloatDiv 1986 0.02% 64.74% # Class of executed instruction 865system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction 866system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction 867system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction 868system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction 869system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction 870system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction 871system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction 872system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction 873system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction 874system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction 875system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction 876system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction 877system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction 878system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction 879system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction 880system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction 881system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction 882system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction 883system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction 884system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction 885system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction 886system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction 887system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction 888system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction 889system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 890system.cpu1.op_class::total 13165936 # Class of executed instruction	792system.cpu1.numCycles 3927225148 # number of cpu cycles simulated 793system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 794system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 795system.cpu1.kern.inst.arm 0 # number of arm instructions executed 796system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed 797system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed 798system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl 799system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl 800system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl 801system.cpu1.kern.ipl_count::31 40242 58.09% 100.00% # number of times we switched to this ipl 802system.cpu1.kern.ipl_count::total 69281 # number of times we switched to this ipl 803system.cpu1.kern.ipl_good::0 25724 48.16% 48.16% # number of times we switched to this ipl from a different ipl 804system.cpu1.kern.ipl_good::22 1968 3.68% 51.84% # number of times we switched to this ipl from a different ipl 805system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl 806system.cpu1.kern.ipl_good::31 25220 47.21% 100.00% # number of times we switched to this ipl from a different ipl 807system.cpu1.kern.ipl_good::total 53416 # number of times we switched to this ipl from a different ipl 808system.cpu1.kern.ipl_ticks::0 1910368546000 97.29% 97.29% # number of cycles we spent at this ipl 809system.cpu1.kern.ipl_ticks::22 730956000 0.04% 97.33% # number of cycles we spent at this ipl 810system.cpu1.kern.ipl_ticks::30 356511000 0.02% 97.34% # number of cycles we spent at this ipl 811system.cpu1.kern.ipl_ticks::31 52155834000 2.66% 100.00% # number of cycles we spent at this ipl 812system.cpu1.kern.ipl_ticks::total 1963611847000 # number of cycles we spent at this ipl 813system.cpu1.kern.ipl_used::0 0.968269 # fraction of swpipl calls that actually changed the ipl 814system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 815system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 816system.cpu1.kern.ipl_used::31 0.626708 # fraction of swpipl calls that actually changed the ipl 817system.cpu1.kern.ipl_used::total 0.771005 # fraction of swpipl calls that actually changed the ipl 818system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 819system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 820system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 821system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 822system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 823system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 824system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 825system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 826system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 827system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 828system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 829system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 830system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 831system.cpu1.kern.syscall::total 104 # number of syscalls executed 832system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 833system.cpu1.kern.callpal::wripir 422 0.59% 0.59% # number of callpals executed 834system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 835system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 836system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed 837system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed 838system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed 839system.cpu1.kern.callpal::swpipl 63030 88.06% 91.46% # number of callpals executed 840system.cpu1.kern.callpal::rdps 2146 3.00% 94.46% # number of callpals executed 841system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed 842system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed 843system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed 844system.cpu1.kern.callpal::rti 3778 5.28% 99.75% # number of callpals executed 845system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed 846system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 847system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 848system.cpu1.kern.callpal::total 71579 # number of callpals executed 849system.cpu1.kern.mode_switch::kernel 2069 # number of protection mode switches 850system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 851system.cpu1.kern.mode_switch::idle 2878 # number of protection mode switches 852system.cpu1.kern.mode_good::kernel 892 853system.cpu1.kern.mode_good::user 464 854system.cpu1.kern.mode_good::idle 428 855system.cpu1.kern.mode_switch_good::kernel 0.431126 # fraction of useful protection mode switches 856system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 857system.cpu1.kern.mode_switch_good::idle 0.148714 # fraction of useful protection mode switches 858system.cpu1.kern.mode_switch_good::total 0.329699 # fraction of useful protection mode switches 859system.cpu1.kern.mode_ticks::kernel 17834392500 0.91% 0.91% # number of ticks spent at the given mode 860system.cpu1.kern.mode_ticks::user 1709021000 0.09% 1.00% # number of ticks spent at the given mode 861system.cpu1.kern.mode_ticks::idle 1944068431500 99.00% 100.00% # number of ticks spent at the given mode 862system.cpu1.kern.swap_context 2002 # number of times the context was actually changed 863system.cpu1.committedInsts 13162574 # Number of instructions committed 864system.cpu1.committedOps 13162574 # Number of ops (including micro ops) committed 865system.cpu1.num_int_alu_accesses 12139381 # Number of integer alu accesses 866system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses 867system.cpu1.num_func_calls 411749 # number of times a function call or return occured 868system.cpu1.num_conditional_control_insts 1304648 # number of instructions that are conditional controls 869system.cpu1.num_int_insts 12139381 # number of integer instructions 870system.cpu1.num_fp_insts 173446 # number of float instructions 871system.cpu1.num_int_register_reads 16710166 # number of times the integer registers were read 872system.cpu1.num_int_register_writes 8908141 # number of times the integer registers were written 873system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read 874system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written 875system.cpu1.num_mem_refs 4204594 # number of memory refs 876system.cpu1.num_load_insts 2435865 # Number of load instructions 877system.cpu1.num_store_insts 1768729 # Number of store instructions 878system.cpu1.num_idle_cycles 3877736087.998025 # Number of idle cycles 879system.cpu1.num_busy_cycles 49489060.001975 # Number of busy cycles 880system.cpu1.not_idle_fraction 0.012602 # Percentage of non-idle cycles 881system.cpu1.idle_fraction 0.987398 # Percentage of idle cycles 882system.cpu1.Branches 1871255 # Number of branches fetched 883system.cpu1.op_class::No_OpClass 705493 5.36% 5.36% # Class of executed instruction 884system.cpu1.op_class::IntAlu 7781042 59.10% 64.46% # Class of executed instruction 885system.cpu1.op_class::IntMult 21322 0.16% 64.62% # Class of executed instruction 886system.cpu1.op_class::IntDiv 0 0.00% 64.62% # Class of executed instruction 887system.cpu1.op_class::FloatAdd 14181 0.11% 64.73% # Class of executed instruction 888system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction 889system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction 890system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction 891system.cpu1.op_class::FloatDiv 1986 0.02% 64.74% # Class of executed instruction 892system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction 893system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction 894system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction 895system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction 896system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction 897system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction 898system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction 899system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction 900system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction 901system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction 902system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction 903system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction 904system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction 905system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction 906system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction 907system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction 908system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction 909system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction 910system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction 911system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction 912system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction 913system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction 914system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction 915system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction 916system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 917system.cpu1.op_class::total 13165936 # Class of executed instruction
	918system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
891system.cpu1.dcache.tags.replacements 166516 # number of replacements 892system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use 893system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks. 894system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks. 895system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks. 896system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit. 897system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor 898system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy 899system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy 900system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 901system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 902system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 903system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id 904system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 905system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses 906system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses	919system.cpu1.dcache.tags.replacements 166516 # number of replacements 920system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use 921system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks. 922system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks. 923system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks. 924system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit. 925system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor 926system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy 927system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy 928system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 929system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 930system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 931system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id 932system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 933system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses 934system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses
	935system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
907system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits 908system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits 909system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits 910system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits 911system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits 912system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits 913system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits 914system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits 915system.cpu1.dcache.demand_hits::cpu1.data 3899224 # number of demand (read+write) hits 916system.cpu1.dcache.demand_hits::total 3899224 # number of demand (read+write) hits 917system.cpu1.dcache.overall_hits::cpu1.data 3899224 # number of overall hits 918system.cpu1.dcache.overall_hits::total 3899224 # number of overall hits 919system.cpu1.dcache.ReadReq_misses::cpu1.data 118432 # number of ReadReq misses 920system.cpu1.dcache.ReadReq_misses::total 118432 # number of ReadReq misses 921system.cpu1.dcache.WriteReq_misses::cpu1.data 62660 # number of WriteReq misses 922system.cpu1.dcache.WriteReq_misses::total 62660 # number of WriteReq misses 923system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8936 # number of LoadLockedReq misses 924system.cpu1.dcache.LoadLockedReq_misses::total 8936 # number of LoadLockedReq misses 925system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5856 # number of StoreCondReq misses 926system.cpu1.dcache.StoreCondReq_misses::total 5856 # number of StoreCondReq misses 927system.cpu1.dcache.demand_misses::cpu1.data 181092 # number of demand (read+write) misses 928system.cpu1.dcache.demand_misses::total 181092 # number of demand (read+write) misses 929system.cpu1.dcache.overall_misses::cpu1.data 181092 # number of overall misses 930system.cpu1.dcache.overall_misses::total 181092 # number of overall misses 931system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1454494000 # number of ReadReq miss cycles 932system.cpu1.dcache.ReadReq_miss_latency::total 1454494000 # number of ReadReq miss cycles 933system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1265962000 # number of WriteReq miss cycles 934system.cpu1.dcache.WriteReq_miss_latency::total 1265962000 # number of WriteReq miss cycles 935system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82083000 # number of LoadLockedReq miss cycles 936system.cpu1.dcache.LoadLockedReq_miss_latency::total 82083000 # number of LoadLockedReq miss cycles 937system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49296000 # number of StoreCondReq miss cycles 938system.cpu1.dcache.StoreCondReq_miss_latency::total 49296000 # number of StoreCondReq miss cycles 939system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5500 # number of StoreCondFailReq miss cycles 940system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5500 # number of StoreCondFailReq miss cycles 941system.cpu1.dcache.demand_miss_latency::cpu1.data 2720456000 # number of demand (read+write) miss cycles 942system.cpu1.dcache.demand_miss_latency::total 2720456000 # number of demand (read+write) miss cycles 943system.cpu1.dcache.overall_miss_latency::cpu1.data 2720456000 # number of overall miss cycles 944system.cpu1.dcache.overall_miss_latency::total 2720456000 # number of overall miss cycles 945system.cpu1.dcache.ReadReq_accesses::cpu1.data 2375633 # number of ReadReq accesses(hits+misses) 946system.cpu1.dcache.ReadReq_accesses::total 2375633 # number of ReadReq accesses(hits+misses) 947system.cpu1.dcache.WriteReq_accesses::cpu1.data 1704683 # number of WriteReq accesses(hits+misses) 948system.cpu1.dcache.WriteReq_accesses::total 1704683 # number of WriteReq accesses(hits+misses) 949system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57151 # number of LoadLockedReq accesses(hits+misses) 950system.cpu1.dcache.LoadLockedReq_accesses::total 57151 # number of LoadLockedReq accesses(hits+misses) 951system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56677 # number of StoreCondReq accesses(hits+misses) 952system.cpu1.dcache.StoreCondReq_accesses::total 56677 # number of StoreCondReq accesses(hits+misses) 953system.cpu1.dcache.demand_accesses::cpu1.data 4080316 # number of demand (read+write) accesses 954system.cpu1.dcache.demand_accesses::total 4080316 # number of demand (read+write) accesses 955system.cpu1.dcache.overall_accesses::cpu1.data 4080316 # number of overall (read+write) accesses 956system.cpu1.dcache.overall_accesses::total 4080316 # number of overall (read+write) accesses 957system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049853 # miss rate for ReadReq accesses 958system.cpu1.dcache.ReadReq_miss_rate::total 0.049853 # miss rate for ReadReq accesses 959system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036758 # miss rate for WriteReq accesses 960system.cpu1.dcache.WriteReq_miss_rate::total 0.036758 # miss rate for WriteReq accesses 961system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156358 # miss rate for LoadLockedReq accesses 962system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156358 # miss rate for LoadLockedReq accesses 963system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103322 # miss rate for StoreCondReq accesses 964system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103322 # miss rate for StoreCondReq accesses 965system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044382 # miss rate for demand accesses 966system.cpu1.dcache.demand_miss_rate::total 0.044382 # miss rate for demand accesses 967system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044382 # miss rate for overall accesses 968system.cpu1.dcache.overall_miss_rate::total 0.044382 # miss rate for overall accesses 969system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444 # average ReadReq miss latency 970system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444 # average ReadReq miss latency 971system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603 # average WriteReq miss latency 972system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603 # average WriteReq miss latency 973system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.653536 # average LoadLockedReq miss latency 974system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.653536 # average LoadLockedReq miss latency 975system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8418.032787 # average StoreCondReq miss latency 976system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8418.032787 # average StoreCondReq miss latency 977system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 978system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 979system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency 980system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897 # average overall miss latency 981system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency 982system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897 # average overall miss latency 983system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 984system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 985system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 986system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 987system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 988system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 989system.cpu1.dcache.writebacks::writebacks 114398 # number of writebacks 990system.cpu1.dcache.writebacks::total 114398 # number of writebacks 991system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118432 # number of ReadReq MSHR misses 992system.cpu1.dcache.ReadReq_mshr_misses::total 118432 # number of ReadReq MSHR misses 993system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62660 # number of WriteReq MSHR misses 994system.cpu1.dcache.WriteReq_mshr_misses::total 62660 # number of WriteReq MSHR misses 995system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8936 # number of LoadLockedReq MSHR misses 996system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8936 # number of LoadLockedReq MSHR misses 997system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5856 # number of StoreCondReq MSHR misses 998system.cpu1.dcache.StoreCondReq_mshr_misses::total 5856 # number of StoreCondReq MSHR misses 999system.cpu1.dcache.demand_mshr_misses::cpu1.data 181092 # number of demand (read+write) MSHR misses 1000system.cpu1.dcache.demand_mshr_misses::total 181092 # number of demand (read+write) MSHR misses 1001system.cpu1.dcache.overall_mshr_misses::cpu1.data 181092 # number of overall MSHR misses 1002system.cpu1.dcache.overall_mshr_misses::total 181092 # number of overall MSHR misses 1003system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable 1004system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable 1005system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable 1006system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable 1007system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses 1008system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses 1009system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1336062000 # number of ReadReq MSHR miss cycles 1010system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1336062000 # number of ReadReq MSHR miss cycles 1011system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1203302000 # number of WriteReq MSHR miss cycles 1012system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1203302000 # number of WriteReq MSHR miss cycles 1013system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73147000 # number of LoadLockedReq MSHR miss cycles 1014system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73147000 # number of LoadLockedReq MSHR miss cycles 1015system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43441000 # number of StoreCondReq MSHR miss cycles 1016system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43441000 # number of StoreCondReq MSHR miss cycles 1017system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4500 # number of StoreCondFailReq MSHR miss cycles 1018system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4500 # number of StoreCondFailReq MSHR miss cycles 1019system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539364000 # number of demand (read+write) MSHR miss cycles 1020system.cpu1.dcache.demand_mshr_miss_latency::total 2539364000 # number of demand (read+write) MSHR miss cycles 1021system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539364000 # number of overall MSHR miss cycles 1022system.cpu1.dcache.overall_mshr_miss_latency::total 2539364000 # number of overall MSHR miss cycles 1023system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles 1024system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles 1025system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles 1026system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles 1027system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049853 # mshr miss rate for ReadReq accesses 1028system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049853 # mshr miss rate for ReadReq accesses 1029system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036758 # mshr miss rate for WriteReq accesses 1030system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036758 # mshr miss rate for WriteReq accesses 1031system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156358 # mshr miss rate for LoadLockedReq accesses 1032system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156358 # mshr miss rate for LoadLockedReq accesses 1033system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103322 # mshr miss rate for StoreCondReq accesses 1034system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103322 # mshr miss rate for StoreCondReq accesses 1035system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for demand accesses 1036system.cpu1.dcache.demand_mshr_miss_rate::total 0.044382 # mshr miss rate for demand accesses 1037system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for overall accesses 1038system.cpu1.dcache.overall_mshr_miss_rate::total 0.044382 # mshr miss rate for overall accesses 1039system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444 # average ReadReq mshr miss latency 1040system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444 # average ReadReq mshr miss latency 1041system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603 # average WriteReq mshr miss latency 1042system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603 # average WriteReq mshr miss latency 1043system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.653536 # average LoadLockedReq mshr miss latency 1044system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.653536 # average LoadLockedReq mshr miss latency 1045system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7418.203552 # average StoreCondReq mshr miss latency 1046system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7418.203552 # average StoreCondReq mshr miss latency 1047system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1048system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1049system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency 1050system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency 1051system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency 1052system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency 1053system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency 1054system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency 1055system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency 1056system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency	936system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits 937system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits 938system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits 939system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits 940system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits 941system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits 942system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits 943system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits 944system.cpu1.dcache.demand_hits::cpu1.data 3899224 # number of demand (read+write) hits 945system.cpu1.dcache.demand_hits::total 3899224 # number of demand (read+write) hits 946system.cpu1.dcache.overall_hits::cpu1.data 3899224 # number of overall hits 947system.cpu1.dcache.overall_hits::total 3899224 # number of overall hits 948system.cpu1.dcache.ReadReq_misses::cpu1.data 118432 # number of ReadReq misses 949system.cpu1.dcache.ReadReq_misses::total 118432 # number of ReadReq misses 950system.cpu1.dcache.WriteReq_misses::cpu1.data 62660 # number of WriteReq misses 951system.cpu1.dcache.WriteReq_misses::total 62660 # number of WriteReq misses 952system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8936 # number of LoadLockedReq misses 953system.cpu1.dcache.LoadLockedReq_misses::total 8936 # number of LoadLockedReq misses 954system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5856 # number of StoreCondReq misses 955system.cpu1.dcache.StoreCondReq_misses::total 5856 # number of StoreCondReq misses 956system.cpu1.dcache.demand_misses::cpu1.data 181092 # number of demand (read+write) misses 957system.cpu1.dcache.demand_misses::total 181092 # number of demand (read+write) misses 958system.cpu1.dcache.overall_misses::cpu1.data 181092 # number of overall misses 959system.cpu1.dcache.overall_misses::total 181092 # number of overall misses 960system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1454494000 # number of ReadReq miss cycles 961system.cpu1.dcache.ReadReq_miss_latency::total 1454494000 # number of ReadReq miss cycles 962system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1265962000 # number of WriteReq miss cycles 963system.cpu1.dcache.WriteReq_miss_latency::total 1265962000 # number of WriteReq miss cycles 964system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82083000 # number of LoadLockedReq miss cycles 965system.cpu1.dcache.LoadLockedReq_miss_latency::total 82083000 # number of LoadLockedReq miss cycles 966system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49296000 # number of StoreCondReq miss cycles 967system.cpu1.dcache.StoreCondReq_miss_latency::total 49296000 # number of StoreCondReq miss cycles 968system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5500 # number of StoreCondFailReq miss cycles 969system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5500 # number of StoreCondFailReq miss cycles 970system.cpu1.dcache.demand_miss_latency::cpu1.data 2720456000 # number of demand (read+write) miss cycles 971system.cpu1.dcache.demand_miss_latency::total 2720456000 # number of demand (read+write) miss cycles 972system.cpu1.dcache.overall_miss_latency::cpu1.data 2720456000 # number of overall miss cycles 973system.cpu1.dcache.overall_miss_latency::total 2720456000 # number of overall miss cycles 974system.cpu1.dcache.ReadReq_accesses::cpu1.data 2375633 # number of ReadReq accesses(hits+misses) 975system.cpu1.dcache.ReadReq_accesses::total 2375633 # number of ReadReq accesses(hits+misses) 976system.cpu1.dcache.WriteReq_accesses::cpu1.data 1704683 # number of WriteReq accesses(hits+misses) 977system.cpu1.dcache.WriteReq_accesses::total 1704683 # number of WriteReq accesses(hits+misses) 978system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57151 # number of LoadLockedReq accesses(hits+misses) 979system.cpu1.dcache.LoadLockedReq_accesses::total 57151 # number of LoadLockedReq accesses(hits+misses) 980system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56677 # number of StoreCondReq accesses(hits+misses) 981system.cpu1.dcache.StoreCondReq_accesses::total 56677 # number of StoreCondReq accesses(hits+misses) 982system.cpu1.dcache.demand_accesses::cpu1.data 4080316 # number of demand (read+write) accesses 983system.cpu1.dcache.demand_accesses::total 4080316 # number of demand (read+write) accesses 984system.cpu1.dcache.overall_accesses::cpu1.data 4080316 # number of overall (read+write) accesses 985system.cpu1.dcache.overall_accesses::total 4080316 # number of overall (read+write) accesses 986system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049853 # miss rate for ReadReq accesses 987system.cpu1.dcache.ReadReq_miss_rate::total 0.049853 # miss rate for ReadReq accesses 988system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036758 # miss rate for WriteReq accesses 989system.cpu1.dcache.WriteReq_miss_rate::total 0.036758 # miss rate for WriteReq accesses 990system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156358 # miss rate for LoadLockedReq accesses 991system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156358 # miss rate for LoadLockedReq accesses 992system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103322 # miss rate for StoreCondReq accesses 993system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103322 # miss rate for StoreCondReq accesses 994system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044382 # miss rate for demand accesses 995system.cpu1.dcache.demand_miss_rate::total 0.044382 # miss rate for demand accesses 996system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044382 # miss rate for overall accesses 997system.cpu1.dcache.overall_miss_rate::total 0.044382 # miss rate for overall accesses 998system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444 # average ReadReq miss latency 999system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444 # average ReadReq miss latency 1000system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603 # average WriteReq miss latency 1001system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603 # average WriteReq miss latency 1002system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.653536 # average LoadLockedReq miss latency 1003system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.653536 # average LoadLockedReq miss latency 1004system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8418.032787 # average StoreCondReq miss latency 1005system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8418.032787 # average StoreCondReq miss latency 1006system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1007system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1008system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency 1009system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897 # average overall miss latency 1010system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency 1011system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897 # average overall miss latency 1012system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1013system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1014system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1015system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1016system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1017system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1018system.cpu1.dcache.writebacks::writebacks 114398 # number of writebacks 1019system.cpu1.dcache.writebacks::total 114398 # number of writebacks 1020system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118432 # number of ReadReq MSHR misses 1021system.cpu1.dcache.ReadReq_mshr_misses::total 118432 # number of ReadReq MSHR misses 1022system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62660 # number of WriteReq MSHR misses 1023system.cpu1.dcache.WriteReq_mshr_misses::total 62660 # number of WriteReq MSHR misses 1024system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8936 # number of LoadLockedReq MSHR misses 1025system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8936 # number of LoadLockedReq MSHR misses 1026system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5856 # number of StoreCondReq MSHR misses 1027system.cpu1.dcache.StoreCondReq_mshr_misses::total 5856 # number of StoreCondReq MSHR misses 1028system.cpu1.dcache.demand_mshr_misses::cpu1.data 181092 # number of demand (read+write) MSHR misses 1029system.cpu1.dcache.demand_mshr_misses::total 181092 # number of demand (read+write) MSHR misses 1030system.cpu1.dcache.overall_mshr_misses::cpu1.data 181092 # number of overall MSHR misses 1031system.cpu1.dcache.overall_mshr_misses::total 181092 # number of overall MSHR misses 1032system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable 1033system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable 1034system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable 1035system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable 1036system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses 1037system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses 1038system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1336062000 # number of ReadReq MSHR miss cycles 1039system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1336062000 # number of ReadReq MSHR miss cycles 1040system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1203302000 # number of WriteReq MSHR miss cycles 1041system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1203302000 # number of WriteReq MSHR miss cycles 1042system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73147000 # number of LoadLockedReq MSHR miss cycles 1043system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73147000 # number of LoadLockedReq MSHR miss cycles 1044system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43441000 # number of StoreCondReq MSHR miss cycles 1045system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43441000 # number of StoreCondReq MSHR miss cycles 1046system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4500 # number of StoreCondFailReq MSHR miss cycles 1047system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4500 # number of StoreCondFailReq MSHR miss cycles 1048system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539364000 # number of demand (read+write) MSHR miss cycles 1049system.cpu1.dcache.demand_mshr_miss_latency::total 2539364000 # number of demand (read+write) MSHR miss cycles 1050system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539364000 # number of overall MSHR miss cycles 1051system.cpu1.dcache.overall_mshr_miss_latency::total 2539364000 # number of overall MSHR miss cycles 1052system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles 1053system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles 1054system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles 1055system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles 1056system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049853 # mshr miss rate for ReadReq accesses 1057system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049853 # mshr miss rate for ReadReq accesses 1058system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036758 # mshr miss rate for WriteReq accesses 1059system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036758 # mshr miss rate for WriteReq accesses 1060system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156358 # mshr miss rate for LoadLockedReq accesses 1061system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156358 # mshr miss rate for LoadLockedReq accesses 1062system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103322 # mshr miss rate for StoreCondReq accesses 1063system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103322 # mshr miss rate for StoreCondReq accesses 1064system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for demand accesses 1065system.cpu1.dcache.demand_mshr_miss_rate::total 0.044382 # mshr miss rate for demand accesses 1066system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for overall accesses 1067system.cpu1.dcache.overall_mshr_miss_rate::total 0.044382 # mshr miss rate for overall accesses 1068system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444 # average ReadReq mshr miss latency 1069system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444 # average ReadReq mshr miss latency 1070system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603 # average WriteReq mshr miss latency 1071system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603 # average WriteReq mshr miss latency 1072system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.653536 # average LoadLockedReq mshr miss latency 1073system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.653536 # average LoadLockedReq mshr miss latency 1074system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7418.203552 # average StoreCondReq mshr miss latency 1075system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7418.203552 # average StoreCondReq mshr miss latency 1076system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1077system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1078system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency 1079system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency 1080system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency 1081system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency 1082system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency 1083system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency 1084system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency 1085system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency
	1086system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1057system.cpu1.icache.tags.replacements 316153 # number of replacements 1058system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use 1059system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks. 1060system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks. 1061system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks. 1062system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit. 1063system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor 1064system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy 1065system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy 1066system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1067system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1068system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 1069system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id 1070system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1071system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1072system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses 1073system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses	1087system.cpu1.icache.tags.replacements 316153 # number of replacements 1088system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use 1089system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks. 1090system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks. 1091system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks. 1092system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit. 1093system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor 1094system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy 1095system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy 1096system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1097system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 1098system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 1099system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id 1100system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1101system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1102system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses 1103system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses
	1104system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1074system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits 1075system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits 1076system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits 1077system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits 1078system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits 1079system.cpu1.icache.overall_hits::total 12849230 # number of overall hits 1080system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses 1081system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses 1082system.cpu1.icache.demand_misses::cpu1.inst 316707 # number of demand (read+write) misses 1083system.cpu1.icache.demand_misses::total 316707 # number of demand (read+write) misses 1084system.cpu1.icache.overall_misses::cpu1.inst 316707 # number of overall misses 1085system.cpu1.icache.overall_misses::total 316707 # number of overall misses 1086system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4252859000 # number of ReadReq miss cycles 1087system.cpu1.icache.ReadReq_miss_latency::total 4252859000 # number of ReadReq miss cycles 1088system.cpu1.icache.demand_miss_latency::cpu1.inst 4252859000 # number of demand (read+write) miss cycles 1089system.cpu1.icache.demand_miss_latency::total 4252859000 # number of demand (read+write) miss cycles 1090system.cpu1.icache.overall_miss_latency::cpu1.inst 4252859000 # number of overall miss cycles 1091system.cpu1.icache.overall_miss_latency::total 4252859000 # number of overall miss cycles 1092system.cpu1.icache.ReadReq_accesses::cpu1.inst 13165937 # number of ReadReq accesses(hits+misses) 1093system.cpu1.icache.ReadReq_accesses::total 13165937 # number of ReadReq accesses(hits+misses) 1094system.cpu1.icache.demand_accesses::cpu1.inst 13165937 # number of demand (read+write) accesses 1095system.cpu1.icache.demand_accesses::total 13165937 # number of demand (read+write) accesses 1096system.cpu1.icache.overall_accesses::cpu1.inst 13165937 # number of overall (read+write) accesses 1097system.cpu1.icache.overall_accesses::total 13165937 # number of overall (read+write) accesses 1098system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024055 # miss rate for ReadReq accesses 1099system.cpu1.icache.ReadReq_miss_rate::total 0.024055 # miss rate for ReadReq accesses 1100system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024055 # miss rate for demand accesses 1101system.cpu1.icache.demand_miss_rate::total 0.024055 # miss rate for demand accesses 1102system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024055 # miss rate for overall accesses 1103system.cpu1.icache.overall_miss_rate::total 0.024055 # miss rate for overall accesses 1104system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702 # average ReadReq miss latency 1105system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702 # average ReadReq miss latency 1106system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency 1107system.cpu1.icache.demand_avg_miss_latency::total 13428.370702 # average overall miss latency 1108system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency 1109system.cpu1.icache.overall_avg_miss_latency::total 13428.370702 # average overall miss latency 1110system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1111system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1112system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1113system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1114system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1115system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1116system.cpu1.icache.writebacks::writebacks 316153 # number of writebacks 1117system.cpu1.icache.writebacks::total 316153 # number of writebacks 1118system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316707 # number of ReadReq MSHR misses 1119system.cpu1.icache.ReadReq_mshr_misses::total 316707 # number of ReadReq MSHR misses 1120system.cpu1.icache.demand_mshr_misses::cpu1.inst 316707 # number of demand (read+write) MSHR misses 1121system.cpu1.icache.demand_mshr_misses::total 316707 # number of demand (read+write) MSHR misses 1122system.cpu1.icache.overall_mshr_misses::cpu1.inst 316707 # number of overall MSHR misses 1123system.cpu1.icache.overall_mshr_misses::total 316707 # number of overall MSHR misses 1124system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3936152000 # number of ReadReq MSHR miss cycles 1125system.cpu1.icache.ReadReq_mshr_miss_latency::total 3936152000 # number of ReadReq MSHR miss cycles 1126system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3936152000 # number of demand (read+write) MSHR miss cycles 1127system.cpu1.icache.demand_mshr_miss_latency::total 3936152000 # number of demand (read+write) MSHR miss cycles 1128system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3936152000 # number of overall MSHR miss cycles 1129system.cpu1.icache.overall_mshr_miss_latency::total 3936152000 # number of overall MSHR miss cycles 1130system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for ReadReq accesses 1131system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024055 # mshr miss rate for ReadReq accesses 1132system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for demand accesses 1133system.cpu1.icache.demand_mshr_miss_rate::total 0.024055 # mshr miss rate for demand accesses 1134system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for overall accesses 1135system.cpu1.icache.overall_mshr_miss_rate::total 0.024055 # mshr miss rate for overall accesses 1136system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average ReadReq mshr miss latency 1137system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702 # average ReadReq mshr miss latency 1138system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency 1139system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency 1140system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency 1141system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency 1142system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1143system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1144system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1145system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1146system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1147system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1148system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1149system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1150system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1151system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1152system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1153system.disk2.dma_write_txs 1 # Number of DMA write transactions.	1105system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits 1106system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits 1107system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits 1108system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits 1109system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits 1110system.cpu1.icache.overall_hits::total 12849230 # number of overall hits 1111system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses 1112system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses 1113system.cpu1.icache.demand_misses::cpu1.inst 316707 # number of demand (read+write) misses 1114system.cpu1.icache.demand_misses::total 316707 # number of demand (read+write) misses 1115system.cpu1.icache.overall_misses::cpu1.inst 316707 # number of overall misses 1116system.cpu1.icache.overall_misses::total 316707 # number of overall misses 1117system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4252859000 # number of ReadReq miss cycles 1118system.cpu1.icache.ReadReq_miss_latency::total 4252859000 # number of ReadReq miss cycles 1119system.cpu1.icache.demand_miss_latency::cpu1.inst 4252859000 # number of demand (read+write) miss cycles 1120system.cpu1.icache.demand_miss_latency::total 4252859000 # number of demand (read+write) miss cycles 1121system.cpu1.icache.overall_miss_latency::cpu1.inst 4252859000 # number of overall miss cycles 1122system.cpu1.icache.overall_miss_latency::total 4252859000 # number of overall miss cycles 1123system.cpu1.icache.ReadReq_accesses::cpu1.inst 13165937 # number of ReadReq accesses(hits+misses) 1124system.cpu1.icache.ReadReq_accesses::total 13165937 # number of ReadReq accesses(hits+misses) 1125system.cpu1.icache.demand_accesses::cpu1.inst 13165937 # number of demand (read+write) accesses 1126system.cpu1.icache.demand_accesses::total 13165937 # number of demand (read+write) accesses 1127system.cpu1.icache.overall_accesses::cpu1.inst 13165937 # number of overall (read+write) accesses 1128system.cpu1.icache.overall_accesses::total 13165937 # number of overall (read+write) accesses 1129system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024055 # miss rate for ReadReq accesses 1130system.cpu1.icache.ReadReq_miss_rate::total 0.024055 # miss rate for ReadReq accesses 1131system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024055 # miss rate for demand accesses 1132system.cpu1.icache.demand_miss_rate::total 0.024055 # miss rate for demand accesses 1133system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024055 # miss rate for overall accesses 1134system.cpu1.icache.overall_miss_rate::total 0.024055 # miss rate for overall accesses 1135system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702 # average ReadReq miss latency 1136system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702 # average ReadReq miss latency 1137system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency 1138system.cpu1.icache.demand_avg_miss_latency::total 13428.370702 # average overall miss latency 1139system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency 1140system.cpu1.icache.overall_avg_miss_latency::total 13428.370702 # average overall miss latency 1141system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1142system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1143system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1144system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1145system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1146system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1147system.cpu1.icache.writebacks::writebacks 316153 # number of writebacks 1148system.cpu1.icache.writebacks::total 316153 # number of writebacks 1149system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316707 # number of ReadReq MSHR misses 1150system.cpu1.icache.ReadReq_mshr_misses::total 316707 # number of ReadReq MSHR misses 1151system.cpu1.icache.demand_mshr_misses::cpu1.inst 316707 # number of demand (read+write) MSHR misses 1152system.cpu1.icache.demand_mshr_misses::total 316707 # number of demand (read+write) MSHR misses 1153system.cpu1.icache.overall_mshr_misses::cpu1.inst 316707 # number of overall MSHR misses 1154system.cpu1.icache.overall_mshr_misses::total 316707 # number of overall MSHR misses 1155system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3936152000 # number of ReadReq MSHR miss cycles 1156system.cpu1.icache.ReadReq_mshr_miss_latency::total 3936152000 # number of ReadReq MSHR miss cycles 1157system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3936152000 # number of demand (read+write) MSHR miss cycles 1158system.cpu1.icache.demand_mshr_miss_latency::total 3936152000 # number of demand (read+write) MSHR miss cycles 1159system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3936152000 # number of overall MSHR miss cycles 1160system.cpu1.icache.overall_mshr_miss_latency::total 3936152000 # number of overall MSHR miss cycles 1161system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for ReadReq accesses 1162system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024055 # mshr miss rate for ReadReq accesses 1163system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for demand accesses 1164system.cpu1.icache.demand_mshr_miss_rate::total 0.024055 # mshr miss rate for demand accesses 1165system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for overall accesses 1166system.cpu1.icache.overall_mshr_miss_rate::total 0.024055 # mshr miss rate for overall accesses 1167system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average ReadReq mshr miss latency 1168system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702 # average ReadReq mshr miss latency 1169system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency 1170system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency 1171system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency 1172system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency 1173system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1174system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1175system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1176system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1177system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1178system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1179system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1180system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1181system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1182system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1183system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1184system.disk2.dma_write_txs 1 # Number of DMA write transactions.
	1185system.iobus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1154system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1155system.iobus.trans_dist::ReadResp 7373 # Transaction distribution 1156system.iobus.trans_dist::WriteReq 55610 # Transaction distribution 1157system.iobus.trans_dist::WriteResp 55610 # Transaction distribution 1158system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) 1159system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) 1160system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1161system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1163system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1164system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1165system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1166system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1167system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count::total 125966 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) 1172system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) 1173system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1174system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1175system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1176system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1177system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1178system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1179system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1180system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) 1181system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size::total 2743498 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.reqLayer0.occupancy 14957500 # Layer occupancy (ticks) 1185system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1186system.iobus.reqLayer1.occupancy 764000 # Layer occupancy (ticks) 1187system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1188system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1189system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1190system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1191system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1192system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) 1193system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1194system.iobus.reqLayer23.occupancy 15839500 # Layer occupancy (ticks) 1195system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1196system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) 1197system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1198system.iobus.reqLayer25.occupancy 6056000 # Layer occupancy (ticks) 1199system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1200system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1201system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks) 1203system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1204system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) 1205system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1206system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) 1207system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)	1186system.iobus.trans_dist::ReadReq 7373 # Transaction distribution 1187system.iobus.trans_dist::ReadResp 7373 # Transaction distribution 1188system.iobus.trans_dist::WriteReq 55610 # Transaction distribution 1189system.iobus.trans_dist::WriteResp 55610 # Transaction distribution 1190system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 1195system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 1197system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1198system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1199system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) 1200system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 1201system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 1202system.iobus.pkt_count::total 125966 # Packet count per connected master and slave (bytes) 1203system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) 1205system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1206system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1207system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1211system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size::total 2743498 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.reqLayer0.occupancy 14957500 # Layer occupancy (ticks) 1217system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1218system.iobus.reqLayer1.occupancy 764000 # Layer occupancy (ticks) 1219system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1220system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1221system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1222system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1223system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1224system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) 1225system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1226system.iobus.reqLayer23.occupancy 15839500 # Layer occupancy (ticks) 1227system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1228system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) 1229system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1230system.iobus.reqLayer25.occupancy 6056000 # Layer occupancy (ticks) 1231system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1232system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 1233system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1234system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks) 1235system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1236system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) 1237system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1238system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) 1239system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
	1240system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1208system.iocache.tags.replacements 41694 # number of replacements 1209system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use 1210system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1211system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. 1212system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1213system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit. 1214system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor 1215system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy 1216system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy 1217system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1218system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1219system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1220system.iocache.tags.tag_accesses 375534 # Number of tag accesses 1221system.iocache.tags.data_accesses 375534 # Number of data accesses	1241system.iocache.tags.replacements 41694 # number of replacements 1242system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use 1243system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1244system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. 1245system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1246system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit. 1247system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor 1248system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy 1249system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy 1250system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1251system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1252system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1253system.iocache.tags.tag_accesses 375534 # Number of tag accesses 1254system.iocache.tags.data_accesses 375534 # Number of data accesses
	1255system.iocache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1222system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 1223system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 1224system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1225system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1226system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 1227system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 1228system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 1229system.iocache.overall_misses::total 41726 # number of overall misses 1230system.iocache.ReadReq_miss_latency::tsunami.ide 21854883 # number of ReadReq miss cycles 1231system.iocache.ReadReq_miss_latency::total 21854883 # number of ReadReq miss cycles 1232system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858321174 # number of WriteLineReq miss cycles 1233system.iocache.WriteLineReq_miss_latency::total 4858321174 # number of WriteLineReq miss cycles 1234system.iocache.demand_miss_latency::tsunami.ide 4880176057 # number of demand (read+write) miss cycles 1235system.iocache.demand_miss_latency::total 4880176057 # number of demand (read+write) miss cycles 1236system.iocache.overall_miss_latency::tsunami.ide 4880176057 # number of overall miss cycles 1237system.iocache.overall_miss_latency::total 4880176057 # number of overall miss cycles 1238system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 1239system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 1240system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1241system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1242system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 1243system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 1244system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 1245system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 1246system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1247system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1248system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1249system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1250system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1251system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1252system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1253system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1254system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862 # average ReadReq miss latency 1255system.iocache.ReadReq_avg_miss_latency::total 125602.775862 # average ReadReq miss latency 1256system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078 # average WriteLineReq miss latency 1257system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078 # average WriteLineReq miss latency 1258system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency 1259system.iocache.demand_avg_miss_latency::total 116957.677635 # average overall miss latency 1260system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency 1261system.iocache.overall_avg_miss_latency::total 116957.677635 # average overall miss latency 1262system.iocache.blocked_cycles::no_mshrs 1 # number of cycles access was blocked 1263system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1264system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 1265system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1266system.iocache.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked 1267system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1268system.iocache.writebacks::writebacks 41520 # number of writebacks 1269system.iocache.writebacks::total 41520 # number of writebacks 1270system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 1271system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 1272system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1273system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1274system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses 1275system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses 1276system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses 1277system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses 1278system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13154883 # number of ReadReq MSHR miss cycles 1279system.iocache.ReadReq_mshr_miss_latency::total 13154883 # number of ReadReq MSHR miss cycles 1280system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778324656 # number of WriteLineReq MSHR miss cycles 1281system.iocache.WriteLineReq_mshr_miss_latency::total 2778324656 # number of WriteLineReq MSHR miss cycles 1282system.iocache.demand_mshr_miss_latency::tsunami.ide 2791479539 # number of demand (read+write) MSHR miss cycles 1283system.iocache.demand_mshr_miss_latency::total 2791479539 # number of demand (read+write) MSHR miss cycles 1284system.iocache.overall_mshr_miss_latency::tsunami.ide 2791479539 # number of overall MSHR miss cycles 1285system.iocache.overall_mshr_miss_latency::total 2791479539 # number of overall MSHR miss cycles 1286system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1287system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1288system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1289system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1290system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1291system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1292system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1293system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1294system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency 1295system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency 1296system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency 1297system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency 1298system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency 1299system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency 1300system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency 1301system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency	1256system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 1257system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 1258system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1259system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 1260system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 1261system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 1262system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 1263system.iocache.overall_misses::total 41726 # number of overall misses 1264system.iocache.ReadReq_miss_latency::tsunami.ide 21854883 # number of ReadReq miss cycles 1265system.iocache.ReadReq_miss_latency::total 21854883 # number of ReadReq miss cycles 1266system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858321174 # number of WriteLineReq miss cycles 1267system.iocache.WriteLineReq_miss_latency::total 4858321174 # number of WriteLineReq miss cycles 1268system.iocache.demand_miss_latency::tsunami.ide 4880176057 # number of demand (read+write) miss cycles 1269system.iocache.demand_miss_latency::total 4880176057 # number of demand (read+write) miss cycles 1270system.iocache.overall_miss_latency::tsunami.ide 4880176057 # number of overall miss cycles 1271system.iocache.overall_miss_latency::total 4880176057 # number of overall miss cycles 1272system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 1273system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 1274system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1275system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 1276system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 1277system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 1278system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 1279system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 1280system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1281system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1282system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1283system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1284system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1285system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1286system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1287system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1288system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862 # average ReadReq miss latency 1289system.iocache.ReadReq_avg_miss_latency::total 125602.775862 # average ReadReq miss latency 1290system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078 # average WriteLineReq miss latency 1291system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078 # average WriteLineReq miss latency 1292system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency 1293system.iocache.demand_avg_miss_latency::total 116957.677635 # average overall miss latency 1294system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency 1295system.iocache.overall_avg_miss_latency::total 116957.677635 # average overall miss latency 1296system.iocache.blocked_cycles::no_mshrs 1 # number of cycles access was blocked 1297system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1298system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked 1299system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1300system.iocache.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked 1301system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1302system.iocache.writebacks::writebacks 41520 # number of writebacks 1303system.iocache.writebacks::total 41520 # number of writebacks 1304system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses 1305system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses 1306system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1307system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 1308system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses 1309system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses 1310system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses 1311system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses 1312system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13154883 # number of ReadReq MSHR miss cycles 1313system.iocache.ReadReq_mshr_miss_latency::total 13154883 # number of ReadReq MSHR miss cycles 1314system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778324656 # number of WriteLineReq MSHR miss cycles 1315system.iocache.WriteLineReq_mshr_miss_latency::total 2778324656 # number of WriteLineReq MSHR miss cycles 1316system.iocache.demand_mshr_miss_latency::tsunami.ide 2791479539 # number of demand (read+write) MSHR miss cycles 1317system.iocache.demand_mshr_miss_latency::total 2791479539 # number of demand (read+write) MSHR miss cycles 1318system.iocache.overall_mshr_miss_latency::tsunami.ide 2791479539 # number of overall MSHR miss cycles 1319system.iocache.overall_mshr_miss_latency::total 2791479539 # number of overall MSHR miss cycles 1320system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1321system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1322system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1323system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1324system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1325system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1326system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1327system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1328system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency 1329system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency 1330system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency 1331system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency 1332system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency 1333system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency 1334system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency 1335system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency
	1336system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1302system.l2c.tags.replacements 341504 # number of replacements 1303system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use 1304system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks. 1305system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks. 1306system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks. 1307system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit. 1308system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor 1309system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor 1310system.l2c.tags.occ_blocks::cpu0.data 5040.815485 # Average occupied blocks per requestor 1311system.l2c.tags.occ_blocks::cpu1.inst 110.867276 # Average occupied blocks per requestor 1312system.l2c.tags.occ_blocks::cpu1.data 39.914491 # Average occupied blocks per requestor 1313system.l2c.tags.occ_percent::writebacks 0.841968 # Average percentage of cache occupancy 1314system.l2c.tags.occ_percent::cpu0.inst 0.073886 # Average percentage of cache occupancy 1315system.l2c.tags.occ_percent::cpu0.data 0.076917 # Average percentage of cache occupancy 1316system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy 1317system.l2c.tags.occ_percent::cpu1.data 0.000609 # Average percentage of cache occupancy 1318system.l2c.tags.occ_percent::total 0.995072 # Average percentage of cache occupancy 1319system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id 1320system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 1321system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id 1322system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id 1323system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id 1324system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id 1325system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id 1326system.l2c.tags.tag_accesses 35882279 # Number of tag accesses 1327system.l2c.tags.data_accesses 35882279 # Number of data accesses	1337system.l2c.tags.replacements 341504 # number of replacements 1338system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use 1339system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks. 1340system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks. 1341system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks. 1342system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit. 1343system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor 1344system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor 1345system.l2c.tags.occ_blocks::cpu0.data 5040.815485 # Average occupied blocks per requestor 1346system.l2c.tags.occ_blocks::cpu1.inst 110.867276 # Average occupied blocks per requestor 1347system.l2c.tags.occ_blocks::cpu1.data 39.914491 # Average occupied blocks per requestor 1348system.l2c.tags.occ_percent::writebacks 0.841968 # Average percentage of cache occupancy 1349system.l2c.tags.occ_percent::cpu0.inst 0.073886 # Average percentage of cache occupancy 1350system.l2c.tags.occ_percent::cpu0.data 0.076917 # Average percentage of cache occupancy 1351system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy 1352system.l2c.tags.occ_percent::cpu1.data 0.000609 # Average percentage of cache occupancy 1353system.l2c.tags.occ_percent::total 0.995072 # Average percentage of cache occupancy 1354system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id 1355system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id 1356system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id 1357system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id 1358system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id 1359system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id 1360system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id 1361system.l2c.tags.tag_accesses 35882279 # Number of tag accesses 1362system.l2c.tags.data_accesses 35882279 # Number of data accesses
	1363system.l2c.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1328system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits 1329system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits 1330system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits 1331system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits 1332system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits 1333system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits 1334system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits 1335system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits 1336system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 1337system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits 1338system.l2c.ReadExReq_hits::cpu0.data 126431 # number of ReadExReq hits 1339system.l2c.ReadExReq_hits::cpu1.data 47312 # number of ReadExReq hits 1340system.l2c.ReadExReq_hits::total 173743 # number of ReadExReq hits 1341system.l2c.ReadCleanReq_hits::cpu0.inst 685790 # number of ReadCleanReq hits 1342system.l2c.ReadCleanReq_hits::cpu1.inst 316251 # number of ReadCleanReq hits 1343system.l2c.ReadCleanReq_hits::total 1002041 # number of ReadCleanReq hits 1344system.l2c.ReadSharedReq_hits::cpu0.data 663459 # number of ReadSharedReq hits 1345system.l2c.ReadSharedReq_hits::cpu1.data 109055 # number of ReadSharedReq hits 1346system.l2c.ReadSharedReq_hits::total 772514 # number of ReadSharedReq hits 1347system.l2c.demand_hits::cpu0.inst 685790 # number of demand (read+write) hits 1348system.l2c.demand_hits::cpu0.data 789890 # number of demand (read+write) hits 1349system.l2c.demand_hits::cpu1.inst 316251 # number of demand (read+write) hits 1350system.l2c.demand_hits::cpu1.data 156367 # number of demand (read+write) hits 1351system.l2c.demand_hits::total 1948298 # number of demand (read+write) hits 1352system.l2c.overall_hits::cpu0.inst 685790 # number of overall hits 1353system.l2c.overall_hits::cpu0.data 789890 # number of overall hits 1354system.l2c.overall_hits::cpu1.inst 316251 # number of overall hits 1355system.l2c.overall_hits::cpu1.data 156367 # number of overall hits 1356system.l2c.overall_hits::total 1948298 # number of overall hits 1357system.l2c.UpgradeReq_misses::cpu0.data 2941 # number of UpgradeReq misses 1358system.l2c.UpgradeReq_misses::cpu1.data 1732 # number of UpgradeReq misses 1359system.l2c.UpgradeReq_misses::total 4673 # number of UpgradeReq misses 1360system.l2c.SCUpgradeReq_misses::cpu0.data 898 # number of SCUpgradeReq misses 1361system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses 1362system.l2c.SCUpgradeReq_misses::total 1795 # number of SCUpgradeReq misses 1363system.l2c.ReadExReq_misses::cpu0.data 115557 # number of ReadExReq misses 1364system.l2c.ReadExReq_misses::cpu1.data 6591 # number of ReadExReq misses 1365system.l2c.ReadExReq_misses::total 122148 # number of ReadExReq misses 1366system.l2c.ReadCleanReq_misses::cpu0.inst 12981 # number of ReadCleanReq misses 1367system.l2c.ReadCleanReq_misses::cpu1.inst 455 # number of ReadCleanReq misses 1368system.l2c.ReadCleanReq_misses::total 13436 # number of ReadCleanReq misses 1369system.l2c.ReadSharedReq_misses::cpu0.data 271641 # number of ReadSharedReq misses 1370system.l2c.ReadSharedReq_misses::cpu1.data 237 # number of ReadSharedReq misses 1371system.l2c.ReadSharedReq_misses::total 271878 # number of ReadSharedReq misses 1372system.l2c.demand_misses::cpu0.inst 12981 # number of demand (read+write) misses 1373system.l2c.demand_misses::cpu0.data 387198 # number of demand (read+write) misses 1374system.l2c.demand_misses::cpu1.inst 455 # number of demand (read+write) misses 1375system.l2c.demand_misses::cpu1.data 6828 # number of demand (read+write) misses 1376system.l2c.demand_misses::total 407462 # number of demand (read+write) misses 1377system.l2c.overall_misses::cpu0.inst 12981 # number of overall misses 1378system.l2c.overall_misses::cpu0.data 387198 # number of overall misses 1379system.l2c.overall_misses::cpu1.inst 455 # number of overall misses 1380system.l2c.overall_misses::cpu1.data 6828 # number of overall misses 1381system.l2c.overall_misses::total 407462 # number of overall misses 1382system.l2c.UpgradeReq_miss_latency::cpu0.data 1599000 # number of UpgradeReq miss cycles 1383system.l2c.UpgradeReq_miss_latency::cpu1.data 12643000 # number of UpgradeReq miss cycles 1384system.l2c.UpgradeReq_miss_latency::total 14242000 # number of UpgradeReq miss cycles 1385system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1259500 # number of SCUpgradeReq miss cycles 1386system.l2c.SCUpgradeReq_miss_latency::cpu1.data 178000 # number of SCUpgradeReq miss cycles 1387system.l2c.SCUpgradeReq_miss_latency::total 1437500 # number of SCUpgradeReq miss cycles 1388system.l2c.ReadExReq_miss_latency::cpu0.data 8901595500 # number of ReadExReq miss cycles 1389system.l2c.ReadExReq_miss_latency::cpu1.data 544185500 # number of ReadExReq miss cycles 1390system.l2c.ReadExReq_miss_latency::total 9445781000 # number of ReadExReq miss cycles 1391system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1065078500 # number of ReadCleanReq miss cycles 1392system.l2c.ReadCleanReq_miss_latency::cpu1.inst 37559000 # number of ReadCleanReq miss cycles 1393system.l2c.ReadCleanReq_miss_latency::total 1102637500 # number of ReadCleanReq miss cycles 1394system.l2c.ReadSharedReq_miss_latency::cpu0.data 19890941000 # number of ReadSharedReq miss cycles 1395system.l2c.ReadSharedReq_miss_latency::cpu1.data 19543500 # number of ReadSharedReq miss cycles 1396system.l2c.ReadSharedReq_miss_latency::total 19910484500 # number of ReadSharedReq miss cycles 1397system.l2c.demand_miss_latency::cpu0.inst 1065078500 # number of demand (read+write) miss cycles 1398system.l2c.demand_miss_latency::cpu0.data 28792536500 # number of demand (read+write) miss cycles 1399system.l2c.demand_miss_latency::cpu1.inst 37559000 # number of demand (read+write) miss cycles 1400system.l2c.demand_miss_latency::cpu1.data 563729000 # number of demand (read+write) miss cycles 1401system.l2c.demand_miss_latency::total 30458903000 # number of demand (read+write) miss cycles 1402system.l2c.overall_miss_latency::cpu0.inst 1065078500 # number of overall miss cycles 1403system.l2c.overall_miss_latency::cpu0.data 28792536500 # number of overall miss cycles 1404system.l2c.overall_miss_latency::cpu1.inst 37559000 # number of overall miss cycles 1405system.l2c.overall_miss_latency::cpu1.data 563729000 # number of overall miss cycles 1406system.l2c.overall_miss_latency::total 30458903000 # number of overall miss cycles 1407system.l2c.WritebackDirty_accesses::writebacks 792706 # number of WritebackDirty accesses(hits+misses) 1408system.l2c.WritebackDirty_accesses::total 792706 # number of WritebackDirty accesses(hits+misses) 1409system.l2c.WritebackClean_accesses::writebacks 747201 # number of WritebackClean accesses(hits+misses) 1410system.l2c.WritebackClean_accesses::total 747201 # number of WritebackClean accesses(hits+misses) 1411system.l2c.UpgradeReq_accesses::cpu0.data 3116 # number of UpgradeReq accesses(hits+misses) 1412system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses) 1413system.l2c.UpgradeReq_accesses::total 5382 # number of UpgradeReq accesses(hits+misses) 1414system.l2c.SCUpgradeReq_accesses::cpu0.data 931 # number of SCUpgradeReq accesses(hits+misses) 1415system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses) 1416system.l2c.SCUpgradeReq_accesses::total 1852 # number of SCUpgradeReq accesses(hits+misses) 1417system.l2c.ReadExReq_accesses::cpu0.data 241988 # number of ReadExReq accesses(hits+misses) 1418system.l2c.ReadExReq_accesses::cpu1.data 53903 # number of ReadExReq accesses(hits+misses) 1419system.l2c.ReadExReq_accesses::total 295891 # number of ReadExReq accesses(hits+misses) 1420system.l2c.ReadCleanReq_accesses::cpu0.inst 698771 # number of ReadCleanReq accesses(hits+misses) 1421system.l2c.ReadCleanReq_accesses::cpu1.inst 316706 # number of ReadCleanReq accesses(hits+misses) 1422system.l2c.ReadCleanReq_accesses::total 1015477 # number of ReadCleanReq accesses(hits+misses) 1423system.l2c.ReadSharedReq_accesses::cpu0.data 935100 # number of ReadSharedReq accesses(hits+misses) 1424system.l2c.ReadSharedReq_accesses::cpu1.data 109292 # number of ReadSharedReq accesses(hits+misses) 1425system.l2c.ReadSharedReq_accesses::total 1044392 # number of ReadSharedReq accesses(hits+misses) 1426system.l2c.demand_accesses::cpu0.inst 698771 # number of demand (read+write) accesses 1427system.l2c.demand_accesses::cpu0.data 1177088 # number of demand (read+write) accesses 1428system.l2c.demand_accesses::cpu1.inst 316706 # number of demand (read+write) accesses 1429system.l2c.demand_accesses::cpu1.data 163195 # number of demand (read+write) accesses 1430system.l2c.demand_accesses::total 2355760 # number of demand (read+write) accesses 1431system.l2c.overall_accesses::cpu0.inst 698771 # number of overall (read+write) accesses 1432system.l2c.overall_accesses::cpu0.data 1177088 # number of overall (read+write) accesses 1433system.l2c.overall_accesses::cpu1.inst 316706 # number of overall (read+write) accesses 1434system.l2c.overall_accesses::cpu1.data 163195 # number of overall (read+write) accesses 1435system.l2c.overall_accesses::total 2355760 # number of overall (read+write) accesses 1436system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943838 # miss rate for UpgradeReq accesses 1437system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764342 # miss rate for UpgradeReq accesses 1438system.l2c.UpgradeReq_miss_rate::total 0.868265 # miss rate for UpgradeReq accesses 1439system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.964554 # miss rate for SCUpgradeReq accesses 1440system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses 1441system.l2c.SCUpgradeReq_miss_rate::total 0.969222 # miss rate for SCUpgradeReq accesses 1442system.l2c.ReadExReq_miss_rate::cpu0.data 0.477532 # miss rate for ReadExReq accesses 1443system.l2c.ReadExReq_miss_rate::cpu1.data 0.122275 # miss rate for ReadExReq accesses 1444system.l2c.ReadExReq_miss_rate::total 0.412814 # miss rate for ReadExReq accesses 1445system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018577 # miss rate for ReadCleanReq accesses 1446system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001437 # miss rate for ReadCleanReq accesses 1447system.l2c.ReadCleanReq_miss_rate::total 0.013231 # miss rate for ReadCleanReq accesses 1448system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290494 # miss rate for ReadSharedReq accesses 1449system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002169 # miss rate for ReadSharedReq accesses 1450system.l2c.ReadSharedReq_miss_rate::total 0.260322 # miss rate for ReadSharedReq accesses 1451system.l2c.demand_miss_rate::cpu0.inst 0.018577 # miss rate for demand accesses 1452system.l2c.demand_miss_rate::cpu0.data 0.328946 # miss rate for demand accesses 1453system.l2c.demand_miss_rate::cpu1.inst 0.001437 # miss rate for demand accesses 1454system.l2c.demand_miss_rate::cpu1.data 0.041840 # miss rate for demand accesses 1455system.l2c.demand_miss_rate::total 0.172964 # miss rate for demand accesses 1456system.l2c.overall_miss_rate::cpu0.inst 0.018577 # miss rate for overall accesses 1457system.l2c.overall_miss_rate::cpu0.data 0.328946 # miss rate for overall accesses 1458system.l2c.overall_miss_rate::cpu1.inst 0.001437 # miss rate for overall accesses 1459system.l2c.overall_miss_rate::cpu1.data 0.041840 # miss rate for overall accesses 1460system.l2c.overall_miss_rate::total 0.172964 # miss rate for overall accesses 1461system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 543.692622 # average UpgradeReq miss latency 1462system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7299.653580 # average UpgradeReq miss latency 1463system.l2c.UpgradeReq_avg_miss_latency::total 3047.720950 # average UpgradeReq miss latency 1464system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1402.561247 # average SCUpgradeReq miss latency 1465system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 198.439242 # average SCUpgradeReq miss latency 1466system.l2c.SCUpgradeReq_avg_miss_latency::total 800.835655 # average SCUpgradeReq miss latency 1467system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77032.075080 # average ReadExReq miss latency 1468system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82564.937035 # average ReadExReq miss latency 1469system.l2c.ReadExReq_avg_miss_latency::total 77330.623506 # average ReadExReq miss latency 1470system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82049.033202 # average ReadCleanReq miss latency 1471system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82547.252747 # average ReadCleanReq miss latency 1472system.l2c.ReadCleanReq_avg_miss_latency::total 82065.905031 # average ReadCleanReq miss latency 1473system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73225.105930 # average ReadSharedReq miss latency 1474system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82462.025316 # average ReadSharedReq miss latency 1475system.l2c.ReadSharedReq_avg_miss_latency::total 73233.157887 # average ReadSharedReq miss latency 1476system.l2c.demand_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency 1477system.l2c.demand_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency 1478system.l2c.demand_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency 1479system.l2c.demand_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency 1480system.l2c.demand_avg_miss_latency::total 74752.745041 # average overall miss latency 1481system.l2c.overall_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency 1482system.l2c.overall_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency 1483system.l2c.overall_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency 1484system.l2c.overall_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency 1485system.l2c.overall_avg_miss_latency::total 74752.745041 # average overall miss latency 1486system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1487system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1488system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1489system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1490system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1491system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1492system.l2c.writebacks::writebacks 78937 # number of writebacks 1493system.l2c.writebacks::total 78937 # number of writebacks 1494system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits 1495system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits 1496system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 1497system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 1498system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 1499system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits 1500system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 1501system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 1502system.l2c.UpgradeReq_mshr_misses::cpu0.data 2941 # number of UpgradeReq MSHR misses 1503system.l2c.UpgradeReq_mshr_misses::cpu1.data 1732 # number of UpgradeReq MSHR misses 1504system.l2c.UpgradeReq_mshr_misses::total 4673 # number of UpgradeReq MSHR misses 1505system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 898 # number of SCUpgradeReq MSHR misses 1506system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses 1507system.l2c.SCUpgradeReq_mshr_misses::total 1795 # number of SCUpgradeReq MSHR misses 1508system.l2c.ReadExReq_mshr_misses::cpu0.data 115557 # number of ReadExReq MSHR misses 1509system.l2c.ReadExReq_mshr_misses::cpu1.data 6591 # number of ReadExReq MSHR misses 1510system.l2c.ReadExReq_mshr_misses::total 122148 # number of ReadExReq MSHR misses 1511system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12981 # number of ReadCleanReq MSHR misses 1512system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 444 # number of ReadCleanReq MSHR misses 1513system.l2c.ReadCleanReq_mshr_misses::total 13425 # number of ReadCleanReq MSHR misses 1514system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271641 # number of ReadSharedReq MSHR misses 1515system.l2c.ReadSharedReq_mshr_misses::cpu1.data 237 # number of ReadSharedReq MSHR misses 1516system.l2c.ReadSharedReq_mshr_misses::total 271878 # number of ReadSharedReq MSHR misses 1517system.l2c.demand_mshr_misses::cpu0.inst 12981 # number of demand (read+write) MSHR misses 1518system.l2c.demand_mshr_misses::cpu0.data 387198 # number of demand (read+write) MSHR misses 1519system.l2c.demand_mshr_misses::cpu1.inst 444 # number of demand (read+write) MSHR misses 1520system.l2c.demand_mshr_misses::cpu1.data 6828 # number of demand (read+write) MSHR misses 1521system.l2c.demand_mshr_misses::total 407451 # number of demand (read+write) MSHR misses 1522system.l2c.overall_mshr_misses::cpu0.inst 12981 # number of overall MSHR misses 1523system.l2c.overall_mshr_misses::cpu0.data 387198 # number of overall MSHR misses 1524system.l2c.overall_mshr_misses::cpu1.inst 444 # number of overall MSHR misses 1525system.l2c.overall_mshr_misses::cpu1.data 6828 # number of overall MSHR misses 1526system.l2c.overall_mshr_misses::total 407451 # number of overall MSHR misses 1527system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable 1528system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable 1529system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable 1530system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable 1531system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable 1532system.l2c.WriteReq_mshr_uncacheable::total 14058 # number of WriteReq MSHR uncacheable 1533system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses 1534system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses 1535system.l2c.overall_mshr_uncacheable_misses::total 21257 # number of overall MSHR uncacheable misses 1536system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 58492500 # number of UpgradeReq MSHR miss cycles 1537system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34311000 # number of UpgradeReq MSHR miss cycles 1538system.l2c.UpgradeReq_mshr_miss_latency::total 92803500 # number of UpgradeReq MSHR miss cycles 1539system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17536000 # number of SCUpgradeReq MSHR miss cycles 1540system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 17907500 # number of SCUpgradeReq MSHR miss cycles 1541system.l2c.SCUpgradeReq_mshr_miss_latency::total 35443500 # number of SCUpgradeReq MSHR miss cycles 1542system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7746025500 # number of ReadExReq MSHR miss cycles 1543system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 478275500 # number of ReadExReq MSHR miss cycles 1544system.l2c.ReadExReq_mshr_miss_latency::total 8224301000 # number of ReadExReq MSHR miss cycles 1545system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 935268500 # number of ReadCleanReq MSHR miss cycles 1546system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 32302501 # number of ReadCleanReq MSHR miss cycles 1547system.l2c.ReadCleanReq_mshr_miss_latency::total 967571001 # number of ReadCleanReq MSHR miss cycles 1548system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17174531000 # number of ReadSharedReq MSHR miss cycles 1549system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 17173500 # number of ReadSharedReq MSHR miss cycles 1550system.l2c.ReadSharedReq_mshr_miss_latency::total 17191704500 # number of ReadSharedReq MSHR miss cycles 1551system.l2c.demand_mshr_miss_latency::cpu0.inst 935268500 # number of demand (read+write) MSHR miss cycles 1552system.l2c.demand_mshr_miss_latency::cpu0.data 24920556500 # number of demand (read+write) MSHR miss cycles 1553system.l2c.demand_mshr_miss_latency::cpu1.inst 32302501 # number of demand (read+write) MSHR miss cycles 1554system.l2c.demand_mshr_miss_latency::cpu1.data 495449000 # number of demand (read+write) MSHR miss cycles 1555system.l2c.demand_mshr_miss_latency::total 26383576501 # number of demand (read+write) MSHR miss cycles 1556system.l2c.overall_mshr_miss_latency::cpu0.inst 935268500 # number of overall MSHR miss cycles 1557system.l2c.overall_mshr_miss_latency::cpu0.data 24920556500 # number of overall MSHR miss cycles 1558system.l2c.overall_mshr_miss_latency::cpu1.inst 32302501 # number of overall MSHR miss cycles 1559system.l2c.overall_mshr_miss_latency::cpu1.data 495449000 # number of overall MSHR miss cycles 1560system.l2c.overall_mshr_miss_latency::total 26383576501 # number of overall MSHR miss cycles 1561system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1489559500 # number of ReadReq MSHR uncacheable cycles 1562system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19061000 # number of ReadReq MSHR uncacheable cycles 1563system.l2c.ReadReq_mshr_uncacheable_latency::total 1508620500 # number of ReadReq MSHR uncacheable cycles 1564system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1489559500 # number of overall MSHR uncacheable cycles 1565system.l2c.overall_mshr_uncacheable_latency::cpu1.data 19061000 # number of overall MSHR uncacheable cycles 1566system.l2c.overall_mshr_uncacheable_latency::total 1508620500 # number of overall MSHR uncacheable cycles 1567system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1568system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1569system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943838 # mshr miss rate for UpgradeReq accesses 1570system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764342 # mshr miss rate for UpgradeReq accesses 1571system.l2c.UpgradeReq_mshr_miss_rate::total 0.868265 # mshr miss rate for UpgradeReq accesses 1572system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.964554 # mshr miss rate for SCUpgradeReq accesses 1573system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses 1574system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969222 # mshr miss rate for SCUpgradeReq accesses 1575system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477532 # mshr miss rate for ReadExReq accesses 1576system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122275 # mshr miss rate for ReadExReq accesses 1577system.l2c.ReadExReq_mshr_miss_rate::total 0.412814 # mshr miss rate for ReadExReq accesses 1578system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for ReadCleanReq accesses 1579system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for ReadCleanReq accesses 1580system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013220 # mshr miss rate for ReadCleanReq accesses 1581system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290494 # mshr miss rate for ReadSharedReq accesses 1582system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002169 # mshr miss rate for ReadSharedReq accesses 1583system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260322 # mshr miss rate for ReadSharedReq accesses 1584system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for demand accesses 1585system.l2c.demand_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for demand accesses 1586system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for demand accesses 1587system.l2c.demand_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for demand accesses 1588system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses 1589system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for overall accesses 1590system.l2c.overall_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for overall accesses 1591system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for overall accesses 1592system.l2c.overall_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for overall accesses 1593system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses 1594system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19888.643319 # average UpgradeReq mshr miss latency 1595system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19810.046189 # average UpgradeReq mshr miss latency 1596system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19859.512091 # average UpgradeReq mshr miss latency 1597system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19527.839644 # average SCUpgradeReq mshr miss latency 1598system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19963.768116 # average SCUpgradeReq mshr miss latency 1599system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19745.682451 # average SCUpgradeReq mshr miss latency 1600system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67032.075080 # average ReadExReq mshr miss latency 1601system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72564.937035 # average ReadExReq mshr miss latency 1602system.l2c.ReadExReq_avg_mshr_miss_latency::total 67330.623506 # average ReadExReq mshr miss latency 1603system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average ReadCleanReq mshr miss latency 1604system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average ReadCleanReq mshr miss latency 1605system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821 # average ReadCleanReq mshr miss latency 1606system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930 # average ReadSharedReq mshr miss latency 1607system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316 # average ReadSharedReq mshr miss latency 1608system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887 # average ReadSharedReq mshr miss latency 1609system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency 1610system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency 1611system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency 1612system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency 1613system.l2c.demand_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency 1614system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency 1615system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency 1616system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency 1617system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency 1618system.l2c.overall_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency 1619system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381 # average ReadReq mshr uncacheable latency 1620system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency 1621system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518 # average ReadReq mshr uncacheable latency 1622system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636 # average overall mshr uncacheable latency 1623system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency 1624system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency 1625system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter. 1626system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1627system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1628system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1629system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1630system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	1364system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits 1365system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits 1366system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits 1367system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits 1368system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits 1369system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits 1370system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits 1371system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits 1372system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 1373system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits 1374system.l2c.ReadExReq_hits::cpu0.data 126431 # number of ReadExReq hits 1375system.l2c.ReadExReq_hits::cpu1.data 47312 # number of ReadExReq hits 1376system.l2c.ReadExReq_hits::total 173743 # number of ReadExReq hits 1377system.l2c.ReadCleanReq_hits::cpu0.inst 685790 # number of ReadCleanReq hits 1378system.l2c.ReadCleanReq_hits::cpu1.inst 316251 # number of ReadCleanReq hits 1379system.l2c.ReadCleanReq_hits::total 1002041 # number of ReadCleanReq hits 1380system.l2c.ReadSharedReq_hits::cpu0.data 663459 # number of ReadSharedReq hits 1381system.l2c.ReadSharedReq_hits::cpu1.data 109055 # number of ReadSharedReq hits 1382system.l2c.ReadSharedReq_hits::total 772514 # number of ReadSharedReq hits 1383system.l2c.demand_hits::cpu0.inst 685790 # number of demand (read+write) hits 1384system.l2c.demand_hits::cpu0.data 789890 # number of demand (read+write) hits 1385system.l2c.demand_hits::cpu1.inst 316251 # number of demand (read+write) hits 1386system.l2c.demand_hits::cpu1.data 156367 # number of demand (read+write) hits 1387system.l2c.demand_hits::total 1948298 # number of demand (read+write) hits 1388system.l2c.overall_hits::cpu0.inst 685790 # number of overall hits 1389system.l2c.overall_hits::cpu0.data 789890 # number of overall hits 1390system.l2c.overall_hits::cpu1.inst 316251 # number of overall hits 1391system.l2c.overall_hits::cpu1.data 156367 # number of overall hits 1392system.l2c.overall_hits::total 1948298 # number of overall hits 1393system.l2c.UpgradeReq_misses::cpu0.data 2941 # number of UpgradeReq misses 1394system.l2c.UpgradeReq_misses::cpu1.data 1732 # number of UpgradeReq misses 1395system.l2c.UpgradeReq_misses::total 4673 # number of UpgradeReq misses 1396system.l2c.SCUpgradeReq_misses::cpu0.data 898 # number of SCUpgradeReq misses 1397system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses 1398system.l2c.SCUpgradeReq_misses::total 1795 # number of SCUpgradeReq misses 1399system.l2c.ReadExReq_misses::cpu0.data 115557 # number of ReadExReq misses 1400system.l2c.ReadExReq_misses::cpu1.data 6591 # number of ReadExReq misses 1401system.l2c.ReadExReq_misses::total 122148 # number of ReadExReq misses 1402system.l2c.ReadCleanReq_misses::cpu0.inst 12981 # number of ReadCleanReq misses 1403system.l2c.ReadCleanReq_misses::cpu1.inst 455 # number of ReadCleanReq misses 1404system.l2c.ReadCleanReq_misses::total 13436 # number of ReadCleanReq misses 1405system.l2c.ReadSharedReq_misses::cpu0.data 271641 # number of ReadSharedReq misses 1406system.l2c.ReadSharedReq_misses::cpu1.data 237 # number of ReadSharedReq misses 1407system.l2c.ReadSharedReq_misses::total 271878 # number of ReadSharedReq misses 1408system.l2c.demand_misses::cpu0.inst 12981 # number of demand (read+write) misses 1409system.l2c.demand_misses::cpu0.data 387198 # number of demand (read+write) misses 1410system.l2c.demand_misses::cpu1.inst 455 # number of demand (read+write) misses 1411system.l2c.demand_misses::cpu1.data 6828 # number of demand (read+write) misses 1412system.l2c.demand_misses::total 407462 # number of demand (read+write) misses 1413system.l2c.overall_misses::cpu0.inst 12981 # number of overall misses 1414system.l2c.overall_misses::cpu0.data 387198 # number of overall misses 1415system.l2c.overall_misses::cpu1.inst 455 # number of overall misses 1416system.l2c.overall_misses::cpu1.data 6828 # number of overall misses 1417system.l2c.overall_misses::total 407462 # number of overall misses 1418system.l2c.UpgradeReq_miss_latency::cpu0.data 1599000 # number of UpgradeReq miss cycles 1419system.l2c.UpgradeReq_miss_latency::cpu1.data 12643000 # number of UpgradeReq miss cycles 1420system.l2c.UpgradeReq_miss_latency::total 14242000 # number of UpgradeReq miss cycles 1421system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1259500 # number of SCUpgradeReq miss cycles 1422system.l2c.SCUpgradeReq_miss_latency::cpu1.data 178000 # number of SCUpgradeReq miss cycles 1423system.l2c.SCUpgradeReq_miss_latency::total 1437500 # number of SCUpgradeReq miss cycles 1424system.l2c.ReadExReq_miss_latency::cpu0.data 8901595500 # number of ReadExReq miss cycles 1425system.l2c.ReadExReq_miss_latency::cpu1.data 544185500 # number of ReadExReq miss cycles 1426system.l2c.ReadExReq_miss_latency::total 9445781000 # number of ReadExReq miss cycles 1427system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1065078500 # number of ReadCleanReq miss cycles 1428system.l2c.ReadCleanReq_miss_latency::cpu1.inst 37559000 # number of ReadCleanReq miss cycles 1429system.l2c.ReadCleanReq_miss_latency::total 1102637500 # number of ReadCleanReq miss cycles 1430system.l2c.ReadSharedReq_miss_latency::cpu0.data 19890941000 # number of ReadSharedReq miss cycles 1431system.l2c.ReadSharedReq_miss_latency::cpu1.data 19543500 # number of ReadSharedReq miss cycles 1432system.l2c.ReadSharedReq_miss_latency::total 19910484500 # number of ReadSharedReq miss cycles 1433system.l2c.demand_miss_latency::cpu0.inst 1065078500 # number of demand (read+write) miss cycles 1434system.l2c.demand_miss_latency::cpu0.data 28792536500 # number of demand (read+write) miss cycles 1435system.l2c.demand_miss_latency::cpu1.inst 37559000 # number of demand (read+write) miss cycles 1436system.l2c.demand_miss_latency::cpu1.data 563729000 # number of demand (read+write) miss cycles 1437system.l2c.demand_miss_latency::total 30458903000 # number of demand (read+write) miss cycles 1438system.l2c.overall_miss_latency::cpu0.inst 1065078500 # number of overall miss cycles 1439system.l2c.overall_miss_latency::cpu0.data 28792536500 # number of overall miss cycles 1440system.l2c.overall_miss_latency::cpu1.inst 37559000 # number of overall miss cycles 1441system.l2c.overall_miss_latency::cpu1.data 563729000 # number of overall miss cycles 1442system.l2c.overall_miss_latency::total 30458903000 # number of overall miss cycles 1443system.l2c.WritebackDirty_accesses::writebacks 792706 # number of WritebackDirty accesses(hits+misses) 1444system.l2c.WritebackDirty_accesses::total 792706 # number of WritebackDirty accesses(hits+misses) 1445system.l2c.WritebackClean_accesses::writebacks 747201 # number of WritebackClean accesses(hits+misses) 1446system.l2c.WritebackClean_accesses::total 747201 # number of WritebackClean accesses(hits+misses) 1447system.l2c.UpgradeReq_accesses::cpu0.data 3116 # number of UpgradeReq accesses(hits+misses) 1448system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses) 1449system.l2c.UpgradeReq_accesses::total 5382 # number of UpgradeReq accesses(hits+misses) 1450system.l2c.SCUpgradeReq_accesses::cpu0.data 931 # number of SCUpgradeReq accesses(hits+misses) 1451system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses) 1452system.l2c.SCUpgradeReq_accesses::total 1852 # number of SCUpgradeReq accesses(hits+misses) 1453system.l2c.ReadExReq_accesses::cpu0.data 241988 # number of ReadExReq accesses(hits+misses) 1454system.l2c.ReadExReq_accesses::cpu1.data 53903 # number of ReadExReq accesses(hits+misses) 1455system.l2c.ReadExReq_accesses::total 295891 # number of ReadExReq accesses(hits+misses) 1456system.l2c.ReadCleanReq_accesses::cpu0.inst 698771 # number of ReadCleanReq accesses(hits+misses) 1457system.l2c.ReadCleanReq_accesses::cpu1.inst 316706 # number of ReadCleanReq accesses(hits+misses) 1458system.l2c.ReadCleanReq_accesses::total 1015477 # number of ReadCleanReq accesses(hits+misses) 1459system.l2c.ReadSharedReq_accesses::cpu0.data 935100 # number of ReadSharedReq accesses(hits+misses) 1460system.l2c.ReadSharedReq_accesses::cpu1.data 109292 # number of ReadSharedReq accesses(hits+misses) 1461system.l2c.ReadSharedReq_accesses::total 1044392 # number of ReadSharedReq accesses(hits+misses) 1462system.l2c.demand_accesses::cpu0.inst 698771 # number of demand (read+write) accesses 1463system.l2c.demand_accesses::cpu0.data 1177088 # number of demand (read+write) accesses 1464system.l2c.demand_accesses::cpu1.inst 316706 # number of demand (read+write) accesses 1465system.l2c.demand_accesses::cpu1.data 163195 # number of demand (read+write) accesses 1466system.l2c.demand_accesses::total 2355760 # number of demand (read+write) accesses 1467system.l2c.overall_accesses::cpu0.inst 698771 # number of overall (read+write) accesses 1468system.l2c.overall_accesses::cpu0.data 1177088 # number of overall (read+write) accesses 1469system.l2c.overall_accesses::cpu1.inst 316706 # number of overall (read+write) accesses 1470system.l2c.overall_accesses::cpu1.data 163195 # number of overall (read+write) accesses 1471system.l2c.overall_accesses::total 2355760 # number of overall (read+write) accesses 1472system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943838 # miss rate for UpgradeReq accesses 1473system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764342 # miss rate for UpgradeReq accesses 1474system.l2c.UpgradeReq_miss_rate::total 0.868265 # miss rate for UpgradeReq accesses 1475system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.964554 # miss rate for SCUpgradeReq accesses 1476system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses 1477system.l2c.SCUpgradeReq_miss_rate::total 0.969222 # miss rate for SCUpgradeReq accesses 1478system.l2c.ReadExReq_miss_rate::cpu0.data 0.477532 # miss rate for ReadExReq accesses 1479system.l2c.ReadExReq_miss_rate::cpu1.data 0.122275 # miss rate for ReadExReq accesses 1480system.l2c.ReadExReq_miss_rate::total 0.412814 # miss rate for ReadExReq accesses 1481system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018577 # miss rate for ReadCleanReq accesses 1482system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001437 # miss rate for ReadCleanReq accesses 1483system.l2c.ReadCleanReq_miss_rate::total 0.013231 # miss rate for ReadCleanReq accesses 1484system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290494 # miss rate for ReadSharedReq accesses 1485system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002169 # miss rate for ReadSharedReq accesses 1486system.l2c.ReadSharedReq_miss_rate::total 0.260322 # miss rate for ReadSharedReq accesses 1487system.l2c.demand_miss_rate::cpu0.inst 0.018577 # miss rate for demand accesses 1488system.l2c.demand_miss_rate::cpu0.data 0.328946 # miss rate for demand accesses 1489system.l2c.demand_miss_rate::cpu1.inst 0.001437 # miss rate for demand accesses 1490system.l2c.demand_miss_rate::cpu1.data 0.041840 # miss rate for demand accesses 1491system.l2c.demand_miss_rate::total 0.172964 # miss rate for demand accesses 1492system.l2c.overall_miss_rate::cpu0.inst 0.018577 # miss rate for overall accesses 1493system.l2c.overall_miss_rate::cpu0.data 0.328946 # miss rate for overall accesses 1494system.l2c.overall_miss_rate::cpu1.inst 0.001437 # miss rate for overall accesses 1495system.l2c.overall_miss_rate::cpu1.data 0.041840 # miss rate for overall accesses 1496system.l2c.overall_miss_rate::total 0.172964 # miss rate for overall accesses 1497system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 543.692622 # average UpgradeReq miss latency 1498system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7299.653580 # average UpgradeReq miss latency 1499system.l2c.UpgradeReq_avg_miss_latency::total 3047.720950 # average UpgradeReq miss latency 1500system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1402.561247 # average SCUpgradeReq miss latency 1501system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 198.439242 # average SCUpgradeReq miss latency 1502system.l2c.SCUpgradeReq_avg_miss_latency::total 800.835655 # average SCUpgradeReq miss latency 1503system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77032.075080 # average ReadExReq miss latency 1504system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82564.937035 # average ReadExReq miss latency 1505system.l2c.ReadExReq_avg_miss_latency::total 77330.623506 # average ReadExReq miss latency 1506system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82049.033202 # average ReadCleanReq miss latency 1507system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82547.252747 # average ReadCleanReq miss latency 1508system.l2c.ReadCleanReq_avg_miss_latency::total 82065.905031 # average ReadCleanReq miss latency 1509system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73225.105930 # average ReadSharedReq miss latency 1510system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82462.025316 # average ReadSharedReq miss latency 1511system.l2c.ReadSharedReq_avg_miss_latency::total 73233.157887 # average ReadSharedReq miss latency 1512system.l2c.demand_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency 1513system.l2c.demand_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency 1514system.l2c.demand_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency 1515system.l2c.demand_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency 1516system.l2c.demand_avg_miss_latency::total 74752.745041 # average overall miss latency 1517system.l2c.overall_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency 1518system.l2c.overall_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency 1519system.l2c.overall_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency 1520system.l2c.overall_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency 1521system.l2c.overall_avg_miss_latency::total 74752.745041 # average overall miss latency 1522system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1523system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1524system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1525system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1526system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1527system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1528system.l2c.writebacks::writebacks 78937 # number of writebacks 1529system.l2c.writebacks::total 78937 # number of writebacks 1530system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits 1531system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits 1532system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 1533system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits 1534system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 1535system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits 1536system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses 1537system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses 1538system.l2c.UpgradeReq_mshr_misses::cpu0.data 2941 # number of UpgradeReq MSHR misses 1539system.l2c.UpgradeReq_mshr_misses::cpu1.data 1732 # number of UpgradeReq MSHR misses 1540system.l2c.UpgradeReq_mshr_misses::total 4673 # number of UpgradeReq MSHR misses 1541system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 898 # number of SCUpgradeReq MSHR misses 1542system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses 1543system.l2c.SCUpgradeReq_mshr_misses::total 1795 # number of SCUpgradeReq MSHR misses 1544system.l2c.ReadExReq_mshr_misses::cpu0.data 115557 # number of ReadExReq MSHR misses 1545system.l2c.ReadExReq_mshr_misses::cpu1.data 6591 # number of ReadExReq MSHR misses 1546system.l2c.ReadExReq_mshr_misses::total 122148 # number of ReadExReq MSHR misses 1547system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12981 # number of ReadCleanReq MSHR misses 1548system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 444 # number of ReadCleanReq MSHR misses 1549system.l2c.ReadCleanReq_mshr_misses::total 13425 # number of ReadCleanReq MSHR misses 1550system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271641 # number of ReadSharedReq MSHR misses 1551system.l2c.ReadSharedReq_mshr_misses::cpu1.data 237 # number of ReadSharedReq MSHR misses 1552system.l2c.ReadSharedReq_mshr_misses::total 271878 # number of ReadSharedReq MSHR misses 1553system.l2c.demand_mshr_misses::cpu0.inst 12981 # number of demand (read+write) MSHR misses 1554system.l2c.demand_mshr_misses::cpu0.data 387198 # number of demand (read+write) MSHR misses 1555system.l2c.demand_mshr_misses::cpu1.inst 444 # number of demand (read+write) MSHR misses 1556system.l2c.demand_mshr_misses::cpu1.data 6828 # number of demand (read+write) MSHR misses 1557system.l2c.demand_mshr_misses::total 407451 # number of demand (read+write) MSHR misses 1558system.l2c.overall_mshr_misses::cpu0.inst 12981 # number of overall MSHR misses 1559system.l2c.overall_mshr_misses::cpu0.data 387198 # number of overall MSHR misses 1560system.l2c.overall_mshr_misses::cpu1.inst 444 # number of overall MSHR misses 1561system.l2c.overall_mshr_misses::cpu1.data 6828 # number of overall MSHR misses 1562system.l2c.overall_mshr_misses::total 407451 # number of overall MSHR misses 1563system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable 1564system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable 1565system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable 1566system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable 1567system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable 1568system.l2c.WriteReq_mshr_uncacheable::total 14058 # number of WriteReq MSHR uncacheable 1569system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses 1570system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses 1571system.l2c.overall_mshr_uncacheable_misses::total 21257 # number of overall MSHR uncacheable misses 1572system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 58492500 # number of UpgradeReq MSHR miss cycles 1573system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34311000 # number of UpgradeReq MSHR miss cycles 1574system.l2c.UpgradeReq_mshr_miss_latency::total 92803500 # number of UpgradeReq MSHR miss cycles 1575system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17536000 # number of SCUpgradeReq MSHR miss cycles 1576system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 17907500 # number of SCUpgradeReq MSHR miss cycles 1577system.l2c.SCUpgradeReq_mshr_miss_latency::total 35443500 # number of SCUpgradeReq MSHR miss cycles 1578system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7746025500 # number of ReadExReq MSHR miss cycles 1579system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 478275500 # number of ReadExReq MSHR miss cycles 1580system.l2c.ReadExReq_mshr_miss_latency::total 8224301000 # number of ReadExReq MSHR miss cycles 1581system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 935268500 # number of ReadCleanReq MSHR miss cycles 1582system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 32302501 # number of ReadCleanReq MSHR miss cycles 1583system.l2c.ReadCleanReq_mshr_miss_latency::total 967571001 # number of ReadCleanReq MSHR miss cycles 1584system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17174531000 # number of ReadSharedReq MSHR miss cycles 1585system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 17173500 # number of ReadSharedReq MSHR miss cycles 1586system.l2c.ReadSharedReq_mshr_miss_latency::total 17191704500 # number of ReadSharedReq MSHR miss cycles 1587system.l2c.demand_mshr_miss_latency::cpu0.inst 935268500 # number of demand (read+write) MSHR miss cycles 1588system.l2c.demand_mshr_miss_latency::cpu0.data 24920556500 # number of demand (read+write) MSHR miss cycles 1589system.l2c.demand_mshr_miss_latency::cpu1.inst 32302501 # number of demand (read+write) MSHR miss cycles 1590system.l2c.demand_mshr_miss_latency::cpu1.data 495449000 # number of demand (read+write) MSHR miss cycles 1591system.l2c.demand_mshr_miss_latency::total 26383576501 # number of demand (read+write) MSHR miss cycles 1592system.l2c.overall_mshr_miss_latency::cpu0.inst 935268500 # number of overall MSHR miss cycles 1593system.l2c.overall_mshr_miss_latency::cpu0.data 24920556500 # number of overall MSHR miss cycles 1594system.l2c.overall_mshr_miss_latency::cpu1.inst 32302501 # number of overall MSHR miss cycles 1595system.l2c.overall_mshr_miss_latency::cpu1.data 495449000 # number of overall MSHR miss cycles 1596system.l2c.overall_mshr_miss_latency::total 26383576501 # number of overall MSHR miss cycles 1597system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1489559500 # number of ReadReq MSHR uncacheable cycles 1598system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19061000 # number of ReadReq MSHR uncacheable cycles 1599system.l2c.ReadReq_mshr_uncacheable_latency::total 1508620500 # number of ReadReq MSHR uncacheable cycles 1600system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1489559500 # number of overall MSHR uncacheable cycles 1601system.l2c.overall_mshr_uncacheable_latency::cpu1.data 19061000 # number of overall MSHR uncacheable cycles 1602system.l2c.overall_mshr_uncacheable_latency::total 1508620500 # number of overall MSHR uncacheable cycles 1603system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1604system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1605system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943838 # mshr miss rate for UpgradeReq accesses 1606system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764342 # mshr miss rate for UpgradeReq accesses 1607system.l2c.UpgradeReq_mshr_miss_rate::total 0.868265 # mshr miss rate for UpgradeReq accesses 1608system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.964554 # mshr miss rate for SCUpgradeReq accesses 1609system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses 1610system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969222 # mshr miss rate for SCUpgradeReq accesses 1611system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477532 # mshr miss rate for ReadExReq accesses 1612system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122275 # mshr miss rate for ReadExReq accesses 1613system.l2c.ReadExReq_mshr_miss_rate::total 0.412814 # mshr miss rate for ReadExReq accesses 1614system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for ReadCleanReq accesses 1615system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for ReadCleanReq accesses 1616system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013220 # mshr miss rate for ReadCleanReq accesses 1617system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290494 # mshr miss rate for ReadSharedReq accesses 1618system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002169 # mshr miss rate for ReadSharedReq accesses 1619system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260322 # mshr miss rate for ReadSharedReq accesses 1620system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for demand accesses 1621system.l2c.demand_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for demand accesses 1622system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for demand accesses 1623system.l2c.demand_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for demand accesses 1624system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses 1625system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for overall accesses 1626system.l2c.overall_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for overall accesses 1627system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for overall accesses 1628system.l2c.overall_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for overall accesses 1629system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses 1630system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19888.643319 # average UpgradeReq mshr miss latency 1631system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19810.046189 # average UpgradeReq mshr miss latency 1632system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19859.512091 # average UpgradeReq mshr miss latency 1633system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19527.839644 # average SCUpgradeReq mshr miss latency 1634system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19963.768116 # average SCUpgradeReq mshr miss latency 1635system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19745.682451 # average SCUpgradeReq mshr miss latency 1636system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67032.075080 # average ReadExReq mshr miss latency 1637system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72564.937035 # average ReadExReq mshr miss latency 1638system.l2c.ReadExReq_avg_mshr_miss_latency::total 67330.623506 # average ReadExReq mshr miss latency 1639system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average ReadCleanReq mshr miss latency 1640system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average ReadCleanReq mshr miss latency 1641system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821 # average ReadCleanReq mshr miss latency 1642system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930 # average ReadSharedReq mshr miss latency 1643system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316 # average ReadSharedReq mshr miss latency 1644system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887 # average ReadSharedReq mshr miss latency 1645system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency 1646system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency 1647system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency 1648system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency 1649system.l2c.demand_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency 1650system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency 1651system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency 1652system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency 1653system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency 1654system.l2c.overall_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency 1655system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381 # average ReadReq mshr uncacheable latency 1656system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency 1657system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518 # average ReadReq mshr uncacheable latency 1658system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636 # average overall mshr uncacheable latency 1659system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency 1660system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency 1661system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter. 1662system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1663system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1664system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1665system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1666system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	1667system.membus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1631system.membus.trans_dist::ReadReq 7199 # Transaction distribution 1632system.membus.trans_dist::ReadResp 292676 # Transaction distribution 1633system.membus.trans_dist::WriteReq 14058 # Transaction distribution 1634system.membus.trans_dist::WriteResp 14058 # Transaction distribution 1635system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution 1636system.membus.trans_dist::CleanEvict 261938 # Transaction distribution 1637system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution 1638system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution 1639system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1640system.membus.trans_dist::ReadExReq 122469 # Transaction distribution 1641system.membus.trans_dist::ReadExResp 121633 # Transaction distribution 1642system.membus.trans_dist::ReadSharedReq 285477 # Transaction distribution 1643system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1644system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) 1645system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182508 # Packet count per connected master and slave (bytes) 1646system.membus.pkt_count_system.l2c.mem_side::total 1225022 # Packet count per connected master and slave (bytes) 1647system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83435 # Packet count per connected master and slave (bytes) 1648system.membus.pkt_count_system.iocache.mem_side::total 83435 # Packet count per connected master and slave (bytes) 1649system.membus.pkt_count::total 1308457 # Packet count per connected master and slave (bytes) 1650system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) 1651system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31079040 # Cumulative packet size per connected master and slave (bytes) 1652system.membus.pkt_size_system.l2c.mem_side::total 31160922 # Cumulative packet size per connected master and slave (bytes) 1653system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 1654system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 1655system.membus.pkt_size::total 33819162 # Cumulative packet size per connected master and slave (bytes) 1656system.membus.snoops 21640 # Total snoops (count) 1657system.membus.snoop_fanout::samples 498117 # Request fanout histogram 1658system.membus.snoop_fanout::mean 0.001313 # Request fanout histogram 1659system.membus.snoop_fanout::stdev 0.036211 # Request fanout histogram 1660system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1661system.membus.snoop_fanout::0 497463 99.87% 99.87% # Request fanout histogram 1662system.membus.snoop_fanout::1 654 0.13% 100.00% # Request fanout histogram 1663system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1664system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1665system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1666system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1667system.membus.snoop_fanout::total 498117 # Request fanout histogram 1668system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks) 1669system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1670system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks) 1671system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1672system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks) 1673system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1674system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks) 1675system.membus.respLayer2.utilization 0.0 # Layer utilization (%)	1668system.membus.trans_dist::ReadReq 7199 # Transaction distribution 1669system.membus.trans_dist::ReadResp 292676 # Transaction distribution 1670system.membus.trans_dist::WriteReq 14058 # Transaction distribution 1671system.membus.trans_dist::WriteResp 14058 # Transaction distribution 1672system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution 1673system.membus.trans_dist::CleanEvict 261938 # Transaction distribution 1674system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution 1675system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution 1676system.membus.trans_dist::UpgradeResp 3 # Transaction distribution 1677system.membus.trans_dist::ReadExReq 122469 # Transaction distribution 1678system.membus.trans_dist::ReadExResp 121633 # Transaction distribution 1679system.membus.trans_dist::ReadSharedReq 285477 # Transaction distribution 1680system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 1681system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) 1682system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182508 # Packet count per connected master and slave (bytes) 1683system.membus.pkt_count_system.l2c.mem_side::total 1225022 # Packet count per connected master and slave (bytes) 1684system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83435 # Packet count per connected master and slave (bytes) 1685system.membus.pkt_count_system.iocache.mem_side::total 83435 # Packet count per connected master and slave (bytes) 1686system.membus.pkt_count::total 1308457 # Packet count per connected master and slave (bytes) 1687system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) 1688system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31079040 # Cumulative packet size per connected master and slave (bytes) 1689system.membus.pkt_size_system.l2c.mem_side::total 31160922 # Cumulative packet size per connected master and slave (bytes) 1690system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 1691system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 1692system.membus.pkt_size::total 33819162 # Cumulative packet size per connected master and slave (bytes) 1693system.membus.snoops 21640 # Total snoops (count) 1694system.membus.snoop_fanout::samples 498117 # Request fanout histogram 1695system.membus.snoop_fanout::mean 0.001313 # Request fanout histogram 1696system.membus.snoop_fanout::stdev 0.036211 # Request fanout histogram 1697system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1698system.membus.snoop_fanout::0 497463 99.87% 99.87% # Request fanout histogram 1699system.membus.snoop_fanout::1 654 0.13% 100.00% # Request fanout histogram 1700system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1701system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1702system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1703system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1704system.membus.snoop_fanout::total 498117 # Request fanout histogram 1705system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks) 1706system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1707system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks) 1708system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 1709system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks) 1710system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1711system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks) 1712system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
	1713system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1676system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter. 1677system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1678system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1679system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter. 1680system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1681system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	1714system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter. 1715system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1716system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1717system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter. 1718system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1719system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	1720system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1682system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution 1683system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution 1684system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution 1685system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution 1686system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution 1687system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution 1688system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution 1689system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution 1690system.toL2Bus.trans_dist::SCUpgradeReq 11299 # Transaction distribution 1691system.toL2Bus.trans_dist::UpgradeResp 27613 # Transaction distribution 1692system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 1693system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution 1694system.toL2Bus.trans_dist::ReadExReq 297840 # Transaction distribution 1695system.toL2Bus.trans_dist::ReadExResp 297840 # Transaction distribution 1696system.toL2Bus.trans_dist::ReadCleanReq 1015499 # Transaction distribution 1697system.toL2Bus.trans_dist::ReadSharedReq 1078979 # Transaction distribution 1698system.toL2Bus.trans_dist::InvalidateReq 227 # Transaction distribution 1699system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2095725 # Packet count per connected master and slave (bytes) 1700system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605435 # Packet count per connected master and slave (bytes) 1701system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949566 # Packet count per connected master and slave (bytes) 1702system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535407 # Packet count per connected master and slave (bytes) 1703system.toL2Bus.pkt_count::total 7186133 # Packet count per connected master and slave (bytes) 1704system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89403712 # Cumulative packet size per connected master and slave (bytes) 1705system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118812032 # Cumulative packet size per connected master and slave (bytes) 1706system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40502976 # Cumulative packet size per connected master and slave (bytes) 1707system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17791322 # Cumulative packet size per connected master and slave (bytes) 1708system.toL2Bus.pkt_size::total 266510042 # Cumulative packet size per connected master and slave (bytes) 1709system.toL2Bus.snoops 398828 # Total snoops (count) 1710system.toL2Bus.snoop_fanout::samples 2782920 # Request fanout histogram 1711system.toL2Bus.snoop_fanout::mean 0.138526 # Request fanout histogram 1712system.toL2Bus.snoop_fanout::stdev 0.345713 # Request fanout histogram 1713system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1714system.toL2Bus.snoop_fanout::0 2397661 86.16% 86.16% # Request fanout histogram 1715system.toL2Bus.snoop_fanout::1 385012 13.83% 99.99% # Request fanout histogram 1716system.toL2Bus.snoop_fanout::2 245 0.01% 100.00% # Request fanout histogram 1717system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram 1718system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1719system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1720system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1721system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1722system.toL2Bus.snoop_fanout::total 2782920 # Request fanout histogram 1723system.toL2Bus.reqLayer0.occupancy 4214914494 # Layer occupancy (ticks) 1724system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1725system.toL2Bus.snoopLayer0.occupancy 296383 # Layer occupancy (ticks) 1726system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1727system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks) 1728system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1729system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks) 1730system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1731system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks) 1732system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1733system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks) 1734system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)	1721system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution 1722system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution 1723system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution 1724system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution 1725system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution 1726system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution 1727system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution 1728system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution 1729system.toL2Bus.trans_dist::SCUpgradeReq 11299 # Transaction distribution 1730system.toL2Bus.trans_dist::UpgradeResp 27613 # Transaction distribution 1731system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 1732system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution 1733system.toL2Bus.trans_dist::ReadExReq 297840 # Transaction distribution 1734system.toL2Bus.trans_dist::ReadExResp 297840 # Transaction distribution 1735system.toL2Bus.trans_dist::ReadCleanReq 1015499 # Transaction distribution 1736system.toL2Bus.trans_dist::ReadSharedReq 1078979 # Transaction distribution 1737system.toL2Bus.trans_dist::InvalidateReq 227 # Transaction distribution 1738system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2095725 # Packet count per connected master and slave (bytes) 1739system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605435 # Packet count per connected master and slave (bytes) 1740system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949566 # Packet count per connected master and slave (bytes) 1741system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535407 # Packet count per connected master and slave (bytes) 1742system.toL2Bus.pkt_count::total 7186133 # Packet count per connected master and slave (bytes) 1743system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89403712 # Cumulative packet size per connected master and slave (bytes) 1744system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118812032 # Cumulative packet size per connected master and slave (bytes) 1745system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40502976 # Cumulative packet size per connected master and slave (bytes) 1746system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17791322 # Cumulative packet size per connected master and slave (bytes) 1747system.toL2Bus.pkt_size::total 266510042 # Cumulative packet size per connected master and slave (bytes) 1748system.toL2Bus.snoops 398828 # Total snoops (count) 1749system.toL2Bus.snoop_fanout::samples 2782920 # Request fanout histogram 1750system.toL2Bus.snoop_fanout::mean 0.138526 # Request fanout histogram 1751system.toL2Bus.snoop_fanout::stdev 0.345713 # Request fanout histogram 1752system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1753system.toL2Bus.snoop_fanout::0 2397661 86.16% 86.16% # Request fanout histogram 1754system.toL2Bus.snoop_fanout::1 385012 13.83% 99.99% # Request fanout histogram 1755system.toL2Bus.snoop_fanout::2 245 0.01% 100.00% # Request fanout histogram 1756system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram 1757system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1758system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1759system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1760system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 1761system.toL2Bus.snoop_fanout::total 2782920 # Request fanout histogram 1762system.toL2Bus.reqLayer0.occupancy 4214914494 # Layer occupancy (ticks) 1763system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1764system.toL2Bus.snoopLayer0.occupancy 296383 # Layer occupancy (ticks) 1765system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1766system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks) 1767system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1768system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks) 1769system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1770system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks) 1771system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1772system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks) 1773system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
	1774system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1775system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1776system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1777system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1735system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1736system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1737system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1738system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1739system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1740system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1741system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1742system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1743system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1744system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1745system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1746system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1747system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1748system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1749system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1750system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1751system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1752system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1753system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1754system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1755system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1756system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1757system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1758system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1759system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1760system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1761system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1762system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1763system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1764system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1765system.tsunami.ethernet.droppedPackets 0 # number of packets dropped	1778system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1779system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1780system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1781system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1782system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1783system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1784system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 1785system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1786system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1787system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1788system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1789system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1790system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1791system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1792system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1793system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1794system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1795system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1796system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1797system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1798system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1799system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1800system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1801system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1802system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1803system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1804system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1805system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1806system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1807system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 1808system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
	1809system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1810system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1811system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1812system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1813system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1814system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1815system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1816system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1817system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1818system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1819system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1820system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1821system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1822system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1823system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1824system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1825system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1826system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1827system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1828system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1829system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1830system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states 1831system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1766 1767---------- End Simulation Statistics ----------	1832 1833---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.963613 # Number of seconds simulated
4sim_ticks 1963612574000 # Number of ticks simulated
5final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 993881 # Simulator instruction rate (inst/s)
8host_op_rate 993880 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 32036346352 # Simulator tick rate (ticks/s)
10host_mem_usage 331076 # Number of bytes of host memory used
11host_seconds 61.29 # Real time elapsed on the host

7host_inst_rate 1460699 # Simulator instruction rate (inst/s)
8host_op_rate 1460699 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 47083590827 # Simulator tick rate (ticks/s)
10host_mem_usage 378804 # Number of bytes of host memory used
11host_seconds 41.70 # Real time elapsed on the host

12sim_insts 60918165 # Number of instructions simulated
13sim_ops 60918165 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 859200 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7709248 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7709248 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 12981 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 386432 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 444 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 6816 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 406688 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 120457 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 120457 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 423090 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 12594973 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 14471 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 222154 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 13255177 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 423090 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 14471 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 437561 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 3926053 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 3926053 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 3926053 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 423090 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 12594973 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 14471 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 222154 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 17181230 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 406688 # Number of read requests accepted
54system.physmem.writeReqs 120457 # Number of write requests accepted
55system.physmem.readBursts 406688 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 120457 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 26019904 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue
59system.physmem.bytesWritten 7707200 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 26028032 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 7709248 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 25130 # Per bank write bursts
66system.physmem.perBankRdBursts::1 25381 # Per bank write bursts
67system.physmem.perBankRdBursts::2 25483 # Per bank write bursts
68system.physmem.perBankRdBursts::3 24909 # Per bank write bursts
69system.physmem.perBankRdBursts::4 25165 # Per bank write bursts
70system.physmem.perBankRdBursts::5 25252 # Per bank write bursts
71system.physmem.perBankRdBursts::6 25797 # Per bank write bursts
72system.physmem.perBankRdBursts::7 25541 # Per bank write bursts
73system.physmem.perBankRdBursts::8 25672 # Per bank write bursts
74system.physmem.perBankRdBursts::9 25333 # Per bank write bursts
75system.physmem.perBankRdBursts::10 25279 # Per bank write bursts
76system.physmem.perBankRdBursts::11 25593 # Per bank write bursts
77system.physmem.perBankRdBursts::12 25647 # Per bank write bursts
78system.physmem.perBankRdBursts::13 25645 # Per bank write bursts
79system.physmem.perBankRdBursts::14 25712 # Per bank write bursts
80system.physmem.perBankRdBursts::15 25022 # Per bank write bursts
81system.physmem.perBankWrBursts::0 7825 # Per bank write bursts
82system.physmem.perBankWrBursts::1 7603 # Per bank write bursts
83system.physmem.perBankWrBursts::2 7492 # Per bank write bursts
84system.physmem.perBankWrBursts::3 6933 # Per bank write bursts
85system.physmem.perBankWrBursts::4 7149 # Per bank write bursts
86system.physmem.perBankWrBursts::5 7135 # Per bank write bursts
87system.physmem.perBankWrBursts::6 7628 # Per bank write bursts
88system.physmem.perBankWrBursts::7 7255 # Per bank write bursts
89system.physmem.perBankWrBursts::8 7538 # Per bank write bursts
90system.physmem.perBankWrBursts::9 7229 # Per bank write bursts
91system.physmem.perBankWrBursts::10 7235 # Per bank write bursts
92system.physmem.perBankWrBursts::11 7425 # Per bank write bursts
93system.physmem.perBankWrBursts::12 7840 # Per bank write bursts
94system.physmem.perBankWrBursts::13 8302 # Per bank write bursts
95system.physmem.perBankWrBursts::14 8309 # Per bank write bursts
96system.physmem.perBankWrBursts::15 7527 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
99system.physmem.totGap 1963565980500 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 406688 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 120457 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 406481 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 3207 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 5887 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 6006 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 6734 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 6782 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 7812 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 9118 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 7274 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 8021 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 8672 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 7905 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 7057 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 7090 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 185 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 128 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 129 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 80 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 99 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 224 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 165 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 172 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 147 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 178 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 114 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 134 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 66393 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 507.991867 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 305.024910 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 413.812380 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 15899 23.95% 23.95% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 12177 18.34% 42.29% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 5415 8.16% 50.44% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 3379 5.09% 55.53% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 2311 3.48% 59.01% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 2006 3.02% 62.04% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 1513 2.28% 64.31% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 1280 1.93% 66.24% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 22413 33.76% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 66393 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 5392 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 75.397255 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2872.179140 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-8191 5389 99.94% 99.94% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 5392 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 5392 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 22.334013 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 18.995867 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 21.838616 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-23 4788 88.80% 88.80% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-31 33 0.61% 89.41% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::32-39 252 4.67% 94.08% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::40-47 18 0.33% 94.42% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::48-55 6 0.11% 94.53% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::56-63 13 0.24% 94.77% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::64-71 10 0.19% 94.96% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::72-79 1 0.02% 94.97% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::80-87 18 0.33% 95.31% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::88-95 18 0.33% 95.64% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::96-103 190 3.52% 99.17% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::104-111 3 0.06% 99.22% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::120-127 7 0.13% 99.37% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::128-135 1 0.02% 99.39% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::136-143 1 0.02% 99.41% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::152-159 2 0.04% 99.46% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::160-167 1 0.02% 99.48% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::168-175 6 0.11% 99.59% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::176-183 2 0.04% 99.63% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::184-191 2 0.04% 99.67% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::192-199 3 0.06% 99.72% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::224-231 13 0.24% 99.98% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::total 5392 # Writes before turning the bus around for reads
263system.physmem.totQLat 2148968000 # Total ticks spent queuing
264system.physmem.totMemAccLat 9771986750 # Total ticks spent from burst creation until serviced by the DRAM
265system.physmem.totBusLat 2032805000 # Total ticks spent in databus transfers
266system.physmem.avgQLat 5285.72 # Average queueing delay per DRAM burst
267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
268system.physmem.avgMemAccLat 24035.72 # Average memory access latency per DRAM burst
269system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s
270system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s
271system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s
272system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s
273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
274system.physmem.busUtil 0.13 # Data bus utilization in percentage
275system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
276system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
277system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
278system.physmem.avgWrQLen 24.84 # Average write queue length when enqueuing
279system.physmem.readRowHits 364299 # Number of row buffer hits during reads
280system.physmem.writeRowHits 96294 # Number of row buffer hits during writes
281system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads
282system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes
283system.physmem.avgGap 3724906.77 # Average gap between requests
284system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined
285system.physmem_0.actEnergy 248179680 # Energy for activate commands per rank (pJ)
286system.physmem_0.preEnergy 135415500 # Energy for precharge commands per rank (pJ)
287system.physmem_0.readEnergy 1580732400 # Energy for read commands per rank (pJ)
288system.physmem_0.writeEnergy 382449600 # Energy for write commands per rank (pJ)
289system.physmem_0.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ)
290system.physmem_0.actBackEnergy 66024340605 # Energy for active background per rank (pJ)
291system.physmem_0.preBackEnergy 1120248020250 # Energy for precharge background per rank (pJ)
292system.physmem_0.totalEnergy 1316872375875 # Total energy per rank (pJ)
293system.physmem_0.averagePower 670.639531 # Core power per rank (mW)
294system.physmem_0.memoryStateTime::IDLE 1863393486000 # Time in different power states
295system.physmem_0.memoryStateTime::REF 65569140000 # Time in different power states
296system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
297system.physmem_0.memoryStateTime::ACT 34644235250 # Time in different power states
298system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
299system.physmem_1.actEnergy 253751400 # Energy for activate commands per rank (pJ)
300system.physmem_1.preEnergy 138455625 # Energy for precharge commands per rank (pJ)
301system.physmem_1.readEnergy 1590443400 # Energy for read commands per rank (pJ)
302system.physmem_1.writeEnergy 397904400 # Energy for write commands per rank (pJ)
303system.physmem_1.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ)
304system.physmem_1.actBackEnergy 66573650745 # Energy for active background per rank (pJ)
305system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ)
306system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ)
307system.physmem_1.averagePower 670.691088 # Core power per rank (mW)
308system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states
309system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states
310system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
311system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states
312system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

17system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory
21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
22system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::total 859200 # Number of instructions bytes read from this memory
26system.physmem.bytes_written::writebacks 7709248 # Number of bytes written to this memory
27system.physmem.bytes_written::total 7709248 # Number of bytes written to this memory
28system.physmem.num_reads::cpu0.inst 12981 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 386432 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 444 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 6816 # Number of read requests responded to by this memory
32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
33system.physmem.num_reads::total 406688 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 120457 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 120457 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu0.inst 423090 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu0.data 12594973 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.inst 14471 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.data 222154 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 13255177 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu0.inst 423090 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu1.inst 14471 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 437561 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_write::writebacks 3926053 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 3926053 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 3926053 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.inst 423090 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu0.data 12594973 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.inst 14471 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu1.data 222154 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 17181230 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.readReqs 406688 # Number of read requests accepted
55system.physmem.writeReqs 120457 # Number of write requests accepted
56system.physmem.readBursts 406688 # Number of DRAM read bursts, including those serviced by the write queue
57system.physmem.writeBursts 120457 # Number of DRAM write bursts, including those merged in the write queue
58system.physmem.bytesReadDRAM 26019904 # Total number of bytes read from DRAM
59system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue
60system.physmem.bytesWritten 7707200 # Total number of bytes written to DRAM
61system.physmem.bytesReadSys 26028032 # Total read bytes from the system interface side
62system.physmem.bytesWrittenSys 7709248 # Total written bytes from the system interface side
63system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue
64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
66system.physmem.perBankRdBursts::0 25130 # Per bank write bursts
67system.physmem.perBankRdBursts::1 25381 # Per bank write bursts
68system.physmem.perBankRdBursts::2 25483 # Per bank write bursts
69system.physmem.perBankRdBursts::3 24909 # Per bank write bursts
70system.physmem.perBankRdBursts::4 25165 # Per bank write bursts
71system.physmem.perBankRdBursts::5 25252 # Per bank write bursts
72system.physmem.perBankRdBursts::6 25797 # Per bank write bursts
73system.physmem.perBankRdBursts::7 25541 # Per bank write bursts
74system.physmem.perBankRdBursts::8 25672 # Per bank write bursts
75system.physmem.perBankRdBursts::9 25333 # Per bank write bursts
76system.physmem.perBankRdBursts::10 25279 # Per bank write bursts
77system.physmem.perBankRdBursts::11 25593 # Per bank write bursts
78system.physmem.perBankRdBursts::12 25647 # Per bank write bursts
79system.physmem.perBankRdBursts::13 25645 # Per bank write bursts
80system.physmem.perBankRdBursts::14 25712 # Per bank write bursts
81system.physmem.perBankRdBursts::15 25022 # Per bank write bursts
82system.physmem.perBankWrBursts::0 7825 # Per bank write bursts
83system.physmem.perBankWrBursts::1 7603 # Per bank write bursts
84system.physmem.perBankWrBursts::2 7492 # Per bank write bursts
85system.physmem.perBankWrBursts::3 6933 # Per bank write bursts
86system.physmem.perBankWrBursts::4 7149 # Per bank write bursts
87system.physmem.perBankWrBursts::5 7135 # Per bank write bursts
88system.physmem.perBankWrBursts::6 7628 # Per bank write bursts
89system.physmem.perBankWrBursts::7 7255 # Per bank write bursts
90system.physmem.perBankWrBursts::8 7538 # Per bank write bursts
91system.physmem.perBankWrBursts::9 7229 # Per bank write bursts
92system.physmem.perBankWrBursts::10 7235 # Per bank write bursts
93system.physmem.perBankWrBursts::11 7425 # Per bank write bursts
94system.physmem.perBankWrBursts::12 7840 # Per bank write bursts
95system.physmem.perBankWrBursts::13 8302 # Per bank write bursts
96system.physmem.perBankWrBursts::14 8309 # Per bank write bursts
97system.physmem.perBankWrBursts::15 7527 # Per bank write bursts
98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
99system.physmem.numWrRetry 17 # Number of times write queue was full causing retry
100system.physmem.totGap 1963565980500 # Total gap between requests
101system.physmem.readPktSize::0 0 # Read request sizes (log2)
102system.physmem.readPktSize::1 0 # Read request sizes (log2)
103system.physmem.readPktSize::2 0 # Read request sizes (log2)
104system.physmem.readPktSize::3 0 # Read request sizes (log2)
105system.physmem.readPktSize::4 0 # Read request sizes (log2)
106system.physmem.readPktSize::5 0 # Read request sizes (log2)
107system.physmem.readPktSize::6 406688 # Read request sizes (log2)
108system.physmem.writePktSize::0 0 # Write request sizes (log2)
109system.physmem.writePktSize::1 0 # Write request sizes (log2)
110system.physmem.writePktSize::2 0 # Write request sizes (log2)
111system.physmem.writePktSize::3 0 # Write request sizes (log2)
112system.physmem.writePktSize::4 0 # Write request sizes (log2)
113system.physmem.writePktSize::5 0 # Write request sizes (log2)
114system.physmem.writePktSize::6 120457 # Write request sizes (log2)
115system.physmem.rdQLenPdf::0 406481 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::16 3207 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::17 5887 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::18 6006 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::19 6734 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::20 6782 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::21 7812 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::22 9118 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::23 7274 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::24 8021 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::25 8672 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::26 7905 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::27 7057 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::28 7090 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::34 185 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::35 128 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::36 129 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::37 80 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::38 99 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::44 224 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::46 165 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::48 172 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::49 147 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::50 178 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::51 114 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::52 134 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see
211system.physmem.bytesPerActivate::samples 66393 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::mean 507.991867 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::gmean 305.024910 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::stdev 413.812380 # Bytes accessed per row activation
215system.physmem.bytesPerActivate::0-127 15899 23.95% 23.95% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::128-255 12177 18.34% 42.29% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::256-383 5415 8.16% 50.44% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::384-511 3379 5.09% 55.53% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::512-639 2311 3.48% 59.01% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::640-767 2006 3.02% 62.04% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::768-895 1513 2.28% 64.31% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::896-1023 1280 1.93% 66.24% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1024-1151 22413 33.76% 100.00% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::total 66393 # Bytes accessed per row activation
225system.physmem.rdPerTurnAround::samples 5392 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::mean 75.397255 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::stdev 2872.179140 # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::0-8191 5389 99.94% 99.94% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
232system.physmem.rdPerTurnAround::total 5392 # Reads before turning the bus around for writes
233system.physmem.wrPerTurnAround::samples 5392 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::mean 22.334013 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::gmean 18.995867 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::stdev 21.838616 # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::16-23 4788 88.80% 88.80% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::24-31 33 0.61% 89.41% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::32-39 252 4.67% 94.08% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::40-47 18 0.33% 94.42% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::48-55 6 0.11% 94.53% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::56-63 13 0.24% 94.77% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::64-71 10 0.19% 94.96% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::72-79 1 0.02% 94.97% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::80-87 18 0.33% 95.31% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::88-95 18 0.33% 95.64% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::96-103 190 3.52% 99.17% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::104-111 3 0.06% 99.22% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::120-127 7 0.13% 99.37% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::128-135 1 0.02% 99.39% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::136-143 1 0.02% 99.41% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::152-159 2 0.04% 99.46% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::160-167 1 0.02% 99.48% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::168-175 6 0.11% 99.59% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::176-183 2 0.04% 99.63% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::184-191 2 0.04% 99.67% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::192-199 3 0.06% 99.72% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::224-231 13 0.24% 99.98% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::total 5392 # Writes before turning the bus around for reads
264system.physmem.totQLat 2148968000 # Total ticks spent queuing
265system.physmem.totMemAccLat 9771986750 # Total ticks spent from burst creation until serviced by the DRAM
266system.physmem.totBusLat 2032805000 # Total ticks spent in databus transfers
267system.physmem.avgQLat 5285.72 # Average queueing delay per DRAM burst
268system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
269system.physmem.avgMemAccLat 24035.72 # Average memory access latency per DRAM burst
270system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s
271system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s
272system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s
273system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s
274system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
275system.physmem.busUtil 0.13 # Data bus utilization in percentage
276system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
277system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
278system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
279system.physmem.avgWrQLen 24.84 # Average write queue length when enqueuing
280system.physmem.readRowHits 364299 # Number of row buffer hits during reads
281system.physmem.writeRowHits 96294 # Number of row buffer hits during writes
282system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads
283system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes
284system.physmem.avgGap 3724906.77 # Average gap between requests
285system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined
286system.physmem_0.actEnergy 248179680 # Energy for activate commands per rank (pJ)
287system.physmem_0.preEnergy 135415500 # Energy for precharge commands per rank (pJ)
288system.physmem_0.readEnergy 1580732400 # Energy for read commands per rank (pJ)
289system.physmem_0.writeEnergy 382449600 # Energy for write commands per rank (pJ)
290system.physmem_0.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ)
291system.physmem_0.actBackEnergy 66024340605 # Energy for active background per rank (pJ)
292system.physmem_0.preBackEnergy 1120248020250 # Energy for precharge background per rank (pJ)
293system.physmem_0.totalEnergy 1316872375875 # Total energy per rank (pJ)
294system.physmem_0.averagePower 670.639531 # Core power per rank (mW)
295system.physmem_0.memoryStateTime::IDLE 1863393486000 # Time in different power states
296system.physmem_0.memoryStateTime::REF 65569140000 # Time in different power states
297system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
298system.physmem_0.memoryStateTime::ACT 34644235250 # Time in different power states
299system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
300system.physmem_1.actEnergy 253751400 # Energy for activate commands per rank (pJ)
301system.physmem_1.preEnergy 138455625 # Energy for precharge commands per rank (pJ)
302system.physmem_1.readEnergy 1590443400 # Energy for read commands per rank (pJ)
303system.physmem_1.writeEnergy 397904400 # Energy for write commands per rank (pJ)
304system.physmem_1.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ)
305system.physmem_1.actBackEnergy 66573650745 # Energy for active background per rank (pJ)
306system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ)
307system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ)
308system.physmem_1.averagePower 670.691088 # Core power per rank (mW)
309system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states
310system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states
311system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
312system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states
313system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

314system.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
315system.bridge.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

313system.cpu_clk_domain.clock 500 # Clock period in ticks
314system.cpu0.dtb.fetch_hits 0 # ITB hits
315system.cpu0.dtb.fetch_misses 0 # ITB misses
316system.cpu0.dtb.fetch_acv 0 # ITB acv
317system.cpu0.dtb.fetch_accesses 0 # ITB accesses
318system.cpu0.dtb.read_hits 7494168 # DTB read hits
319system.cpu0.dtb.read_misses 7443 # DTB read misses
320system.cpu0.dtb.read_acv 210 # DTB read access violations
321system.cpu0.dtb.read_accesses 490673 # DTB read accesses
322system.cpu0.dtb.write_hits 5065702 # DTB write hits
323system.cpu0.dtb.write_misses 813 # DTB write misses
324system.cpu0.dtb.write_acv 134 # DTB write access violations
325system.cpu0.dtb.write_accesses 187452 # DTB write accesses
326system.cpu0.dtb.data_hits 12559870 # DTB hits
327system.cpu0.dtb.data_misses 8256 # DTB misses
328system.cpu0.dtb.data_acv 344 # DTB access violations
329system.cpu0.dtb.data_accesses 678125 # DTB accesses
330system.cpu0.itb.fetch_hits 3501177 # ITB hits
331system.cpu0.itb.fetch_misses 3871 # ITB misses
332system.cpu0.itb.fetch_acv 184 # ITB acv
333system.cpu0.itb.fetch_accesses 3505048 # ITB accesses
334system.cpu0.itb.read_hits 0 # DTB read hits
335system.cpu0.itb.read_misses 0 # DTB read misses
336system.cpu0.itb.read_acv 0 # DTB read access violations
337system.cpu0.itb.read_accesses 0 # DTB read accesses
338system.cpu0.itb.write_hits 0 # DTB write hits
339system.cpu0.itb.write_misses 0 # DTB write misses
340system.cpu0.itb.write_acv 0 # DTB write access violations
341system.cpu0.itb.write_accesses 0 # DTB write accesses
342system.cpu0.itb.data_hits 0 # DTB hits
343system.cpu0.itb.data_misses 0 # DTB misses
344system.cpu0.itb.data_acv 0 # DTB access violations
345system.cpu0.itb.data_accesses 0 # DTB accesses

316system.cpu_clk_domain.clock 500 # Clock period in ticks
317system.cpu0.dtb.fetch_hits 0 # ITB hits
318system.cpu0.dtb.fetch_misses 0 # ITB misses
319system.cpu0.dtb.fetch_acv 0 # ITB acv
320system.cpu0.dtb.fetch_accesses 0 # ITB accesses
321system.cpu0.dtb.read_hits 7494168 # DTB read hits
322system.cpu0.dtb.read_misses 7443 # DTB read misses
323system.cpu0.dtb.read_acv 210 # DTB read access violations
324system.cpu0.dtb.read_accesses 490673 # DTB read accesses
325system.cpu0.dtb.write_hits 5065702 # DTB write hits
326system.cpu0.dtb.write_misses 813 # DTB write misses
327system.cpu0.dtb.write_acv 134 # DTB write access violations
328system.cpu0.dtb.write_accesses 187452 # DTB write accesses
329system.cpu0.dtb.data_hits 12559870 # DTB hits
330system.cpu0.dtb.data_misses 8256 # DTB misses
331system.cpu0.dtb.data_acv 344 # DTB access violations
332system.cpu0.dtb.data_accesses 678125 # DTB accesses
333system.cpu0.itb.fetch_hits 3501177 # ITB hits
334system.cpu0.itb.fetch_misses 3871 # ITB misses
335system.cpu0.itb.fetch_acv 184 # ITB acv
336system.cpu0.itb.fetch_accesses 3505048 # ITB accesses
337system.cpu0.itb.read_hits 0 # DTB read hits
338system.cpu0.itb.read_misses 0 # DTB read misses
339system.cpu0.itb.read_acv 0 # DTB read access violations
340system.cpu0.itb.read_accesses 0 # DTB read accesses
341system.cpu0.itb.write_hits 0 # DTB write hits
342system.cpu0.itb.write_misses 0 # DTB write misses
343system.cpu0.itb.write_acv 0 # DTB write access violations
344system.cpu0.itb.write_accesses 0 # DTB write accesses
345system.cpu0.itb.data_hits 0 # DTB hits
346system.cpu0.itb.data_misses 0 # DTB misses
347system.cpu0.itb.data_acv 0 # DTB access violations
348system.cpu0.itb.data_accesses 0 # DTB accesses

349system.cpu0.numPwrStateTransitions 13591 # Number of power state transitions
350system.cpu0.pwrStateClkGateDist::samples 6796 # Distribution of time spent in the clock gated state
351system.cpu0.pwrStateClkGateDist::mean 272307750.367863 # Distribution of time spent in the clock gated state
352system.cpu0.pwrStateClkGateDist::stdev 432682187.397928 # Distribution of time spent in the clock gated state
353system.cpu0.pwrStateClkGateDist::1000-5e+10 6796 100.00% 100.00% # Distribution of time spent in the clock gated state
354system.cpu0.pwrStateClkGateDist::min_value 55000 # Distribution of time spent in the clock gated state
355system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
356system.cpu0.pwrStateClkGateDist::total 6796 # Distribution of time spent in the clock gated state
357system.cpu0.pwrStateResidencyTicks::ON 113009102500 # Cumulative time (in ticks) in various power states
358system.cpu0.pwrStateResidencyTicks::CLK_GATED 1850603471500 # Cumulative time (in ticks) in various power states

346system.cpu0.numCycles 3925790590 # number of cpu cycles simulated
347system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
348system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
349system.cpu0.kern.inst.arm 0 # number of arm instructions executed
350system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed
351system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed
352system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl
353system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
354system.cpu0.kern.ipl_count::22 1974 1.40% 41.68% # number of times we switched to this ipl
355system.cpu0.kern.ipl_count::30 422 0.30% 41.97% # number of times we switched to this ipl
356system.cpu0.kern.ipl_count::31 82045 58.03% 100.00% # number of times we switched to this ipl
357system.cpu0.kern.ipl_count::total 141394 # number of times we switched to this ipl
358system.cpu0.kern.ipl_good::0 56288 49.08% 49.08% # number of times we switched to this ipl from a different ipl
359system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
360system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl
361system.cpu0.kern.ipl_good::30 422 0.37% 51.29% # number of times we switched to this ipl from a different ipl
362system.cpu0.kern.ipl_good::31 55866 48.71% 100.00% # number of times we switched to this ipl from a different ipl
363system.cpu0.kern.ipl_good::total 114681 # number of times we switched to this ipl from a different ipl
364system.cpu0.kern.ipl_ticks::0 1901241129000 96.86% 96.86% # number of cycles we spent at this ipl
365system.cpu0.kern.ipl_ticks::21 93739000 0.00% 96.86% # number of cycles we spent at this ipl
366system.cpu0.kern.ipl_ticks::22 789776000 0.04% 96.90% # number of cycles we spent at this ipl
367system.cpu0.kern.ipl_ticks::30 316619500 0.02% 96.92% # number of cycles we spent at this ipl
368system.cpu0.kern.ipl_ticks::31 60454001500 3.08% 100.00% # number of cycles we spent at this ipl
369system.cpu0.kern.ipl_ticks::total 1962895265000 # number of cycles we spent at this ipl
370system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl
371system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
372system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
373system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
374system.cpu0.kern.ipl_used::31 0.680919 # fraction of swpipl calls that actually changed the ipl
375system.cpu0.kern.ipl_used::total 0.811074 # fraction of swpipl calls that actually changed the ipl
376system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
377system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
378system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
379system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
380system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
381system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
382system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
383system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
384system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
385system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
386system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
387system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
388system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
389system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
390system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
391system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
392system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
393system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
394system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
395system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
396system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
397system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
398system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
399system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
400system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
401system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
402system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
403system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
404system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
405system.cpu0.kern.syscall::total 222 # number of syscalls executed
406system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
407system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed
408system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
409system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
410system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
411system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed
412system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
413system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
414system.cpu0.kern.callpal::swpipl 134533 89.85% 92.28% # number of callpals executed
415system.cpu0.kern.callpal::rdps 6700 4.47% 96.75% # number of callpals executed
416system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
417system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed
418system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
419system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed
420system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed
421system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
422system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
423system.cpu0.kern.callpal::total 149727 # number of callpals executed
424system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches
425system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
426system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
427system.cpu0.kern.mode_good::kernel 1282
428system.cpu0.kern.mode_good::user 1282
429system.cpu0.kern.mode_good::idle 0
430system.cpu0.kern.mode_switch_good::kernel 0.186175 # fraction of useful protection mode switches
431system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
432system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
433system.cpu0.kern.mode_switch_good::total 0.313908 # fraction of useful protection mode switches
434system.cpu0.kern.mode_ticks::kernel 1959142459500 99.82% 99.82% # number of ticks spent at the given mode
435system.cpu0.kern.mode_ticks::user 3540793500 0.18% 100.00% # number of ticks spent at the given mode
436system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
437system.cpu0.kern.swap_context 3064 # number of times the context was actually changed
438system.cpu0.committedInsts 47755591 # Number of instructions committed
439system.cpu0.committedOps 47755591 # Number of ops (including micro ops) committed
440system.cpu0.num_int_alu_accesses 44289668 # Number of integer alu accesses
441system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses
442system.cpu0.num_func_calls 1202061 # number of times a function call or return occured
443system.cpu0.num_conditional_control_insts 5613734 # number of instructions that are conditional controls
444system.cpu0.num_int_insts 44289668 # number of integer instructions
445system.cpu0.num_fp_insts 210363 # number of float instructions
446system.cpu0.num_int_register_reads 60881629 # number of times the integer registers were read
447system.cpu0.num_int_register_writes 33006420 # number of times the integer registers were written
448system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read
449system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written
450system.cpu0.num_mem_refs 12600044 # number of memory refs
451system.cpu0.num_load_insts 7521304 # Number of load instructions
452system.cpu0.num_store_insts 5078740 # Number of store instructions
453system.cpu0.num_idle_cycles 3699854946.150013 # Number of idle cycles
454system.cpu0.num_busy_cycles 225935643.849987 # Number of busy cycles
455system.cpu0.not_idle_fraction 0.057552 # Percentage of non-idle cycles
456system.cpu0.idle_fraction 0.942448 # Percentage of idle cycles
457system.cpu0.Branches 7206590 # Number of branches fetched
458system.cpu0.op_class::No_OpClass 2726655 5.71% 5.71% # Class of executed instruction
459system.cpu0.op_class::IntAlu 31439878 65.82% 71.53% # Class of executed instruction
460system.cpu0.op_class::IntMult 52896 0.11% 71.64% # Class of executed instruction
461system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction
462system.cpu0.op_class::FloatAdd 25705 0.05% 71.70% # Class of executed instruction
463system.cpu0.op_class::FloatCmp 0 0.00% 71.70% # Class of executed instruction
464system.cpu0.op_class::FloatCvt 0 0.00% 71.70% # Class of executed instruction
465system.cpu0.op_class::FloatMult 0 0.00% 71.70% # Class of executed instruction
466system.cpu0.op_class::FloatDiv 1656 0.00% 71.70% # Class of executed instruction
467system.cpu0.op_class::FloatSqrt 0 0.00% 71.70% # Class of executed instruction
468system.cpu0.op_class::SimdAdd 0 0.00% 71.70% # Class of executed instruction
469system.cpu0.op_class::SimdAddAcc 0 0.00% 71.70% # Class of executed instruction
470system.cpu0.op_class::SimdAlu 0 0.00% 71.70% # Class of executed instruction
471system.cpu0.op_class::SimdCmp 0 0.00% 71.70% # Class of executed instruction
472system.cpu0.op_class::SimdCvt 0 0.00% 71.70% # Class of executed instruction
473system.cpu0.op_class::SimdMisc 0 0.00% 71.70% # Class of executed instruction
474system.cpu0.op_class::SimdMult 0 0.00% 71.70% # Class of executed instruction
475system.cpu0.op_class::SimdMultAcc 0 0.00% 71.70% # Class of executed instruction
476system.cpu0.op_class::SimdShift 0 0.00% 71.70% # Class of executed instruction
477system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.70% # Class of executed instruction
478system.cpu0.op_class::SimdSqrt 0 0.00% 71.70% # Class of executed instruction
479system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.70% # Class of executed instruction
480system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.70% # Class of executed instruction
481system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.70% # Class of executed instruction
482system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.70% # Class of executed instruction
483system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.70% # Class of executed instruction
484system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.70% # Class of executed instruction
485system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction
486system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction
487system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction
488system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction
489system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction
490system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction
491system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
492system.cpu0.op_class::total 47764191 # Class of executed instruction

359system.cpu0.numCycles 3925790590 # number of cpu cycles simulated
360system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
361system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
362system.cpu0.kern.inst.arm 0 # number of arm instructions executed
363system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed
364system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed
365system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl
366system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
367system.cpu0.kern.ipl_count::22 1974 1.40% 41.68% # number of times we switched to this ipl
368system.cpu0.kern.ipl_count::30 422 0.30% 41.97% # number of times we switched to this ipl
369system.cpu0.kern.ipl_count::31 82045 58.03% 100.00% # number of times we switched to this ipl
370system.cpu0.kern.ipl_count::total 141394 # number of times we switched to this ipl
371system.cpu0.kern.ipl_good::0 56288 49.08% 49.08% # number of times we switched to this ipl from a different ipl
372system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
373system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl
374system.cpu0.kern.ipl_good::30 422 0.37% 51.29% # number of times we switched to this ipl from a different ipl
375system.cpu0.kern.ipl_good::31 55866 48.71% 100.00% # number of times we switched to this ipl from a different ipl
376system.cpu0.kern.ipl_good::total 114681 # number of times we switched to this ipl from a different ipl
377system.cpu0.kern.ipl_ticks::0 1901241129000 96.86% 96.86% # number of cycles we spent at this ipl
378system.cpu0.kern.ipl_ticks::21 93739000 0.00% 96.86% # number of cycles we spent at this ipl
379system.cpu0.kern.ipl_ticks::22 789776000 0.04% 96.90% # number of cycles we spent at this ipl
380system.cpu0.kern.ipl_ticks::30 316619500 0.02% 96.92% # number of cycles we spent at this ipl
381system.cpu0.kern.ipl_ticks::31 60454001500 3.08% 100.00% # number of cycles we spent at this ipl
382system.cpu0.kern.ipl_ticks::total 1962895265000 # number of cycles we spent at this ipl
383system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl
384system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
385system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
386system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
387system.cpu0.kern.ipl_used::31 0.680919 # fraction of swpipl calls that actually changed the ipl
388system.cpu0.kern.ipl_used::total 0.811074 # fraction of swpipl calls that actually changed the ipl
389system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
390system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
391system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
392system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
393system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
394system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
395system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
396system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
397system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
398system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
399system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
400system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
401system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
402system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
403system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
404system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
405system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
406system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
407system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
408system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
409system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
410system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
411system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
412system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
413system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
414system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
415system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
416system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
417system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
418system.cpu0.kern.syscall::total 222 # number of syscalls executed
419system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
420system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed
421system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
422system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
423system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
424system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed
425system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
426system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
427system.cpu0.kern.callpal::swpipl 134533 89.85% 92.28% # number of callpals executed
428system.cpu0.kern.callpal::rdps 6700 4.47% 96.75% # number of callpals executed
429system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
430system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed
431system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
432system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed
433system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed
434system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
435system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
436system.cpu0.kern.callpal::total 149727 # number of callpals executed
437system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches
438system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
439system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
440system.cpu0.kern.mode_good::kernel 1282
441system.cpu0.kern.mode_good::user 1282
442system.cpu0.kern.mode_good::idle 0
443system.cpu0.kern.mode_switch_good::kernel 0.186175 # fraction of useful protection mode switches
444system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
445system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
446system.cpu0.kern.mode_switch_good::total 0.313908 # fraction of useful protection mode switches
447system.cpu0.kern.mode_ticks::kernel 1959142459500 99.82% 99.82% # number of ticks spent at the given mode
448system.cpu0.kern.mode_ticks::user 3540793500 0.18% 100.00% # number of ticks spent at the given mode
449system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
450system.cpu0.kern.swap_context 3064 # number of times the context was actually changed
451system.cpu0.committedInsts 47755591 # Number of instructions committed
452system.cpu0.committedOps 47755591 # Number of ops (including micro ops) committed
453system.cpu0.num_int_alu_accesses 44289668 # Number of integer alu accesses
454system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses
455system.cpu0.num_func_calls 1202061 # number of times a function call or return occured
456system.cpu0.num_conditional_control_insts 5613734 # number of instructions that are conditional controls
457system.cpu0.num_int_insts 44289668 # number of integer instructions
458system.cpu0.num_fp_insts 210363 # number of float instructions
459system.cpu0.num_int_register_reads 60881629 # number of times the integer registers were read
460system.cpu0.num_int_register_writes 33006420 # number of times the integer registers were written
461system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read
462system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written
463system.cpu0.num_mem_refs 12600044 # number of memory refs
464system.cpu0.num_load_insts 7521304 # Number of load instructions
465system.cpu0.num_store_insts 5078740 # Number of store instructions
466system.cpu0.num_idle_cycles 3699854946.150013 # Number of idle cycles
467system.cpu0.num_busy_cycles 225935643.849987 # Number of busy cycles
468system.cpu0.not_idle_fraction 0.057552 # Percentage of non-idle cycles
469system.cpu0.idle_fraction 0.942448 # Percentage of idle cycles
470system.cpu0.Branches 7206590 # Number of branches fetched
471system.cpu0.op_class::No_OpClass 2726655 5.71% 5.71% # Class of executed instruction
472system.cpu0.op_class::IntAlu 31439878 65.82% 71.53% # Class of executed instruction
473system.cpu0.op_class::IntMult 52896 0.11% 71.64% # Class of executed instruction
474system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction
475system.cpu0.op_class::FloatAdd 25705 0.05% 71.70% # Class of executed instruction
476system.cpu0.op_class::FloatCmp 0 0.00% 71.70% # Class of executed instruction
477system.cpu0.op_class::FloatCvt 0 0.00% 71.70% # Class of executed instruction
478system.cpu0.op_class::FloatMult 0 0.00% 71.70% # Class of executed instruction
479system.cpu0.op_class::FloatDiv 1656 0.00% 71.70% # Class of executed instruction
480system.cpu0.op_class::FloatSqrt 0 0.00% 71.70% # Class of executed instruction
481system.cpu0.op_class::SimdAdd 0 0.00% 71.70% # Class of executed instruction
482system.cpu0.op_class::SimdAddAcc 0 0.00% 71.70% # Class of executed instruction
483system.cpu0.op_class::SimdAlu 0 0.00% 71.70% # Class of executed instruction
484system.cpu0.op_class::SimdCmp 0 0.00% 71.70% # Class of executed instruction
485system.cpu0.op_class::SimdCvt 0 0.00% 71.70% # Class of executed instruction
486system.cpu0.op_class::SimdMisc 0 0.00% 71.70% # Class of executed instruction
487system.cpu0.op_class::SimdMult 0 0.00% 71.70% # Class of executed instruction
488system.cpu0.op_class::SimdMultAcc 0 0.00% 71.70% # Class of executed instruction
489system.cpu0.op_class::SimdShift 0 0.00% 71.70% # Class of executed instruction
490system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.70% # Class of executed instruction
491system.cpu0.op_class::SimdSqrt 0 0.00% 71.70% # Class of executed instruction
492system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.70% # Class of executed instruction
493system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.70% # Class of executed instruction
494system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.70% # Class of executed instruction
495system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.70% # Class of executed instruction
496system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.70% # Class of executed instruction
497system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.70% # Class of executed instruction
498system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction
499system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction
500system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction
501system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction
502system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction
503system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction
504system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
505system.cpu0.op_class::total 47764191 # Class of executed instruction

506system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

493system.cpu0.dcache.tags.replacements 1179864 # number of replacements
494system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use
495system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks.
496system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks.
497system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks.
498system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit.
499system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor
500system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy
501system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy
502system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id
503system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id
504system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
505system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
506system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses
507system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses

507system.cpu0.dcache.tags.replacements 1179864 # number of replacements
508system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use
509system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks.
510system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks.
511system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks.
512system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit.
513system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor
514system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy
515system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy
516system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id
517system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id
518system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
519system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id
520system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses
521system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses

522system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

508system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits
509system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits
510system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits
511system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits
512system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits
513system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits
514system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits
515system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits
516system.cpu0.dcache.demand_hits::cpu0.data 11068906 # number of demand (read+write) hits
517system.cpu0.dcache.demand_hits::total 11068906 # number of demand (read+write) hits
518system.cpu0.dcache.overall_hits::cpu0.data 11068906 # number of overall hits
519system.cpu0.dcache.overall_hits::total 11068906 # number of overall hits
520system.cpu0.dcache.ReadReq_misses::cpu0.data 937797 # number of ReadReq misses
521system.cpu0.dcache.ReadReq_misses::total 937797 # number of ReadReq misses
522system.cpu0.dcache.WriteReq_misses::cpu0.data 251494 # number of WriteReq misses
523system.cpu0.dcache.WriteReq_misses::total 251494 # number of WriteReq misses
524system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses
525system.cpu0.dcache.LoadLockedReq_misses::total 13653 # number of LoadLockedReq misses
526system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5444 # number of StoreCondReq misses
527system.cpu0.dcache.StoreCondReq_misses::total 5444 # number of StoreCondReq misses
528system.cpu0.dcache.demand_misses::cpu0.data 1189291 # number of demand (read+write) misses
529system.cpu0.dcache.demand_misses::total 1189291 # number of demand (read+write) misses
530system.cpu0.dcache.overall_misses::cpu0.data 1189291 # number of overall misses
531system.cpu0.dcache.overall_misses::total 1189291 # number of overall misses
532system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29158420500 # number of ReadReq miss cycles
533system.cpu0.dcache.ReadReq_miss_latency::total 29158420500 # number of ReadReq miss cycles
534system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10960256500 # number of WriteReq miss cycles
535system.cpu0.dcache.WriteReq_miss_latency::total 10960256500 # number of WriteReq miss cycles
536system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150265500 # number of LoadLockedReq miss cycles
537system.cpu0.dcache.LoadLockedReq_miss_latency::total 150265500 # number of LoadLockedReq miss cycles
538system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47401000 # number of StoreCondReq miss cycles
539system.cpu0.dcache.StoreCondReq_miss_latency::total 47401000 # number of StoreCondReq miss cycles
540system.cpu0.dcache.demand_miss_latency::cpu0.data 40118677000 # number of demand (read+write) miss cycles
541system.cpu0.dcache.demand_miss_latency::total 40118677000 # number of demand (read+write) miss cycles
542system.cpu0.dcache.overall_miss_latency::cpu0.data 40118677000 # number of overall miss cycles
543system.cpu0.dcache.overall_miss_latency::total 40118677000 # number of overall miss cycles
544system.cpu0.dcache.ReadReq_accesses::cpu0.data 7348970 # number of ReadReq accesses(hits+misses)
545system.cpu0.dcache.ReadReq_accesses::total 7348970 # number of ReadReq accesses(hits+misses)
546system.cpu0.dcache.WriteReq_accesses::cpu0.data 4909227 # number of WriteReq accesses(hits+misses)
547system.cpu0.dcache.WriteReq_accesses::total 4909227 # number of WriteReq accesses(hits+misses)
548system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157571 # number of LoadLockedReq accesses(hits+misses)
549system.cpu0.dcache.LoadLockedReq_accesses::total 157571 # number of LoadLockedReq accesses(hits+misses)
550system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153396 # number of StoreCondReq accesses(hits+misses)
551system.cpu0.dcache.StoreCondReq_accesses::total 153396 # number of StoreCondReq accesses(hits+misses)
552system.cpu0.dcache.demand_accesses::cpu0.data 12258197 # number of demand (read+write) accesses
553system.cpu0.dcache.demand_accesses::total 12258197 # number of demand (read+write) accesses
554system.cpu0.dcache.overall_accesses::cpu0.data 12258197 # number of overall (read+write) accesses
555system.cpu0.dcache.overall_accesses::total 12258197 # number of overall (read+write) accesses
556system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127609 # miss rate for ReadReq accesses
557system.cpu0.dcache.ReadReq_miss_rate::total 0.127609 # miss rate for ReadReq accesses
558system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051229 # miss rate for WriteReq accesses
559system.cpu0.dcache.WriteReq_miss_rate::total 0.051229 # miss rate for WriteReq accesses
560system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086647 # miss rate for LoadLockedReq accesses
561system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086647 # miss rate for LoadLockedReq accesses
562system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035490 # miss rate for StoreCondReq accesses
563system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035490 # miss rate for StoreCondReq accesses
564system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097020 # miss rate for demand accesses
565system.cpu0.dcache.demand_miss_rate::total 0.097020 # miss rate for demand accesses
566system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097020 # miss rate for overall accesses
567system.cpu0.dcache.overall_miss_rate::total 0.097020 # miss rate for overall accesses
568system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107 # average ReadReq miss latency
569system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107 # average ReadReq miss latency
570system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404 # average WriteReq miss latency
571system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404 # average WriteReq miss latency
572system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628 # average LoadLockedReq miss latency
573system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628 # average LoadLockedReq miss latency
574system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8707.016899 # average StoreCondReq miss latency
575system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8707.016899 # average StoreCondReq miss latency
576system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency
577system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176 # average overall miss latency
578system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency
579system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176 # average overall miss latency
580system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
581system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
582system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
583system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
584system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
585system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
586system.cpu0.dcache.writebacks::writebacks 678308 # number of writebacks
587system.cpu0.dcache.writebacks::total 678308 # number of writebacks
588system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937797 # number of ReadReq MSHR misses
589system.cpu0.dcache.ReadReq_mshr_misses::total 937797 # number of ReadReq MSHR misses
590system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251494 # number of WriteReq MSHR misses
591system.cpu0.dcache.WriteReq_mshr_misses::total 251494 # number of WriteReq MSHR misses
592system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13653 # number of LoadLockedReq MSHR misses
593system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13653 # number of LoadLockedReq MSHR misses
594system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5444 # number of StoreCondReq MSHR misses
595system.cpu0.dcache.StoreCondReq_mshr_misses::total 5444 # number of StoreCondReq MSHR misses
596system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189291 # number of demand (read+write) MSHR misses
597system.cpu0.dcache.demand_mshr_misses::total 1189291 # number of demand (read+write) MSHR misses
598system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189291 # number of overall MSHR misses
599system.cpu0.dcache.overall_mshr_misses::total 1189291 # number of overall MSHR misses
600system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
601system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable
602system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable
603system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable
604system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses
605system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses
606system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28220623500 # number of ReadReq MSHR miss cycles
607system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28220623500 # number of ReadReq MSHR miss cycles
608system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10708762500 # number of WriteReq MSHR miss cycles
609system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10708762500 # number of WriteReq MSHR miss cycles
610system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136612500 # number of LoadLockedReq MSHR miss cycles
611system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136612500 # number of LoadLockedReq MSHR miss cycles
612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41957000 # number of StoreCondReq MSHR miss cycles
613system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41957000 # number of StoreCondReq MSHR miss cycles
614system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38929386000 # number of demand (read+write) MSHR miss cycles
615system.cpu0.dcache.demand_mshr_miss_latency::total 38929386000 # number of demand (read+write) MSHR miss cycles
616system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38929386000 # number of overall MSHR miss cycles
617system.cpu0.dcache.overall_mshr_miss_latency::total 38929386000 # number of overall MSHR miss cycles
618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578468500 # number of ReadReq MSHR uncacheable cycles
619system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578468500 # number of ReadReq MSHR uncacheable cycles
620system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578468500 # number of overall MSHR uncacheable cycles
621system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578468500 # number of overall MSHR uncacheable cycles
622system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127609 # mshr miss rate for ReadReq accesses
623system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127609 # mshr miss rate for ReadReq accesses
624system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051229 # mshr miss rate for WriteReq accesses
625system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051229 # mshr miss rate for WriteReq accesses
626system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086647 # mshr miss rate for LoadLockedReq accesses
627system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086647 # mshr miss rate for LoadLockedReq accesses
628system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for StoreCondReq accesses
629system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035490 # mshr miss rate for StoreCondReq accesses
630system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for demand accesses
631system.cpu0.dcache.demand_mshr_miss_rate::total 0.097020 # mshr miss rate for demand accesses
632system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for overall accesses
633system.cpu0.dcache.overall_mshr_miss_rate::total 0.097020 # mshr miss rate for overall accesses
634system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107 # average ReadReq mshr miss latency
635system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107 # average ReadReq mshr miss latency
636system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404 # average WriteReq mshr miss latency
637system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404 # average WriteReq mshr miss latency
638system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628 # average LoadLockedReq mshr miss latency
639system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628 # average LoadLockedReq mshr miss latency
640system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7707.016899 # average StoreCondReq mshr miss latency
641system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7707.016899 # average StoreCondReq mshr miss latency
642system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency
643system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency
644system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency
645system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency
646system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency
647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency
648system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency
649system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency

523system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits
524system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits
525system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits
526system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits
527system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits
528system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits
529system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits
530system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits
531system.cpu0.dcache.demand_hits::cpu0.data 11068906 # number of demand (read+write) hits
532system.cpu0.dcache.demand_hits::total 11068906 # number of demand (read+write) hits
533system.cpu0.dcache.overall_hits::cpu0.data 11068906 # number of overall hits
534system.cpu0.dcache.overall_hits::total 11068906 # number of overall hits
535system.cpu0.dcache.ReadReq_misses::cpu0.data 937797 # number of ReadReq misses
536system.cpu0.dcache.ReadReq_misses::total 937797 # number of ReadReq misses
537system.cpu0.dcache.WriteReq_misses::cpu0.data 251494 # number of WriteReq misses
538system.cpu0.dcache.WriteReq_misses::total 251494 # number of WriteReq misses
539system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses
540system.cpu0.dcache.LoadLockedReq_misses::total 13653 # number of LoadLockedReq misses
541system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5444 # number of StoreCondReq misses
542system.cpu0.dcache.StoreCondReq_misses::total 5444 # number of StoreCondReq misses
543system.cpu0.dcache.demand_misses::cpu0.data 1189291 # number of demand (read+write) misses
544system.cpu0.dcache.demand_misses::total 1189291 # number of demand (read+write) misses
545system.cpu0.dcache.overall_misses::cpu0.data 1189291 # number of overall misses
546system.cpu0.dcache.overall_misses::total 1189291 # number of overall misses
547system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29158420500 # number of ReadReq miss cycles
548system.cpu0.dcache.ReadReq_miss_latency::total 29158420500 # number of ReadReq miss cycles
549system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10960256500 # number of WriteReq miss cycles
550system.cpu0.dcache.WriteReq_miss_latency::total 10960256500 # number of WriteReq miss cycles
551system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150265500 # number of LoadLockedReq miss cycles
552system.cpu0.dcache.LoadLockedReq_miss_latency::total 150265500 # number of LoadLockedReq miss cycles
553system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47401000 # number of StoreCondReq miss cycles
554system.cpu0.dcache.StoreCondReq_miss_latency::total 47401000 # number of StoreCondReq miss cycles
555system.cpu0.dcache.demand_miss_latency::cpu0.data 40118677000 # number of demand (read+write) miss cycles
556system.cpu0.dcache.demand_miss_latency::total 40118677000 # number of demand (read+write) miss cycles
557system.cpu0.dcache.overall_miss_latency::cpu0.data 40118677000 # number of overall miss cycles
558system.cpu0.dcache.overall_miss_latency::total 40118677000 # number of overall miss cycles
559system.cpu0.dcache.ReadReq_accesses::cpu0.data 7348970 # number of ReadReq accesses(hits+misses)
560system.cpu0.dcache.ReadReq_accesses::total 7348970 # number of ReadReq accesses(hits+misses)
561system.cpu0.dcache.WriteReq_accesses::cpu0.data 4909227 # number of WriteReq accesses(hits+misses)
562system.cpu0.dcache.WriteReq_accesses::total 4909227 # number of WriteReq accesses(hits+misses)
563system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157571 # number of LoadLockedReq accesses(hits+misses)
564system.cpu0.dcache.LoadLockedReq_accesses::total 157571 # number of LoadLockedReq accesses(hits+misses)
565system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153396 # number of StoreCondReq accesses(hits+misses)
566system.cpu0.dcache.StoreCondReq_accesses::total 153396 # number of StoreCondReq accesses(hits+misses)
567system.cpu0.dcache.demand_accesses::cpu0.data 12258197 # number of demand (read+write) accesses
568system.cpu0.dcache.demand_accesses::total 12258197 # number of demand (read+write) accesses
569system.cpu0.dcache.overall_accesses::cpu0.data 12258197 # number of overall (read+write) accesses
570system.cpu0.dcache.overall_accesses::total 12258197 # number of overall (read+write) accesses
571system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127609 # miss rate for ReadReq accesses
572system.cpu0.dcache.ReadReq_miss_rate::total 0.127609 # miss rate for ReadReq accesses
573system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051229 # miss rate for WriteReq accesses
574system.cpu0.dcache.WriteReq_miss_rate::total 0.051229 # miss rate for WriteReq accesses
575system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086647 # miss rate for LoadLockedReq accesses
576system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086647 # miss rate for LoadLockedReq accesses
577system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035490 # miss rate for StoreCondReq accesses
578system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035490 # miss rate for StoreCondReq accesses
579system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097020 # miss rate for demand accesses
580system.cpu0.dcache.demand_miss_rate::total 0.097020 # miss rate for demand accesses
581system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097020 # miss rate for overall accesses
582system.cpu0.dcache.overall_miss_rate::total 0.097020 # miss rate for overall accesses
583system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107 # average ReadReq miss latency
584system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107 # average ReadReq miss latency
585system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404 # average WriteReq miss latency
586system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404 # average WriteReq miss latency
587system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628 # average LoadLockedReq miss latency
588system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628 # average LoadLockedReq miss latency
589system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8707.016899 # average StoreCondReq miss latency
590system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8707.016899 # average StoreCondReq miss latency
591system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency
592system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176 # average overall miss latency
593system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency
594system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176 # average overall miss latency
595system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
596system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
597system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
598system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
599system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
600system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
601system.cpu0.dcache.writebacks::writebacks 678308 # number of writebacks
602system.cpu0.dcache.writebacks::total 678308 # number of writebacks
603system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937797 # number of ReadReq MSHR misses
604system.cpu0.dcache.ReadReq_mshr_misses::total 937797 # number of ReadReq MSHR misses
605system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251494 # number of WriteReq MSHR misses
606system.cpu0.dcache.WriteReq_mshr_misses::total 251494 # number of WriteReq MSHR misses
607system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13653 # number of LoadLockedReq MSHR misses
608system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13653 # number of LoadLockedReq MSHR misses
609system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5444 # number of StoreCondReq MSHR misses
610system.cpu0.dcache.StoreCondReq_mshr_misses::total 5444 # number of StoreCondReq MSHR misses
611system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189291 # number of demand (read+write) MSHR misses
612system.cpu0.dcache.demand_mshr_misses::total 1189291 # number of demand (read+write) MSHR misses
613system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189291 # number of overall MSHR misses
614system.cpu0.dcache.overall_mshr_misses::total 1189291 # number of overall MSHR misses
615system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
616system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable
617system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable
618system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable
619system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses
620system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses
621system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28220623500 # number of ReadReq MSHR miss cycles
622system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28220623500 # number of ReadReq MSHR miss cycles
623system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10708762500 # number of WriteReq MSHR miss cycles
624system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10708762500 # number of WriteReq MSHR miss cycles
625system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136612500 # number of LoadLockedReq MSHR miss cycles
626system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136612500 # number of LoadLockedReq MSHR miss cycles
627system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41957000 # number of StoreCondReq MSHR miss cycles
628system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41957000 # number of StoreCondReq MSHR miss cycles
629system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38929386000 # number of demand (read+write) MSHR miss cycles
630system.cpu0.dcache.demand_mshr_miss_latency::total 38929386000 # number of demand (read+write) MSHR miss cycles
631system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38929386000 # number of overall MSHR miss cycles
632system.cpu0.dcache.overall_mshr_miss_latency::total 38929386000 # number of overall MSHR miss cycles
633system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578468500 # number of ReadReq MSHR uncacheable cycles
634system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578468500 # number of ReadReq MSHR uncacheable cycles
635system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578468500 # number of overall MSHR uncacheable cycles
636system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578468500 # number of overall MSHR uncacheable cycles
637system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127609 # mshr miss rate for ReadReq accesses
638system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127609 # mshr miss rate for ReadReq accesses
639system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051229 # mshr miss rate for WriteReq accesses
640system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051229 # mshr miss rate for WriteReq accesses
641system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086647 # mshr miss rate for LoadLockedReq accesses
642system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086647 # mshr miss rate for LoadLockedReq accesses
643system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for StoreCondReq accesses
644system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035490 # mshr miss rate for StoreCondReq accesses
645system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for demand accesses
646system.cpu0.dcache.demand_mshr_miss_rate::total 0.097020 # mshr miss rate for demand accesses
647system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for overall accesses
648system.cpu0.dcache.overall_mshr_miss_rate::total 0.097020 # mshr miss rate for overall accesses
649system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107 # average ReadReq mshr miss latency
650system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107 # average ReadReq mshr miss latency
651system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404 # average WriteReq mshr miss latency
652system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404 # average WriteReq mshr miss latency
653system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628 # average LoadLockedReq mshr miss latency
654system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628 # average LoadLockedReq mshr miss latency
655system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7707.016899 # average StoreCondReq mshr miss latency
656system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7707.016899 # average StoreCondReq mshr miss latency
657system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency
658system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency
659system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency
660system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency
661system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency
662system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency
663system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency
664system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency

665system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

650system.cpu0.icache.tags.replacements 698162 # number of replacements
651system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use
652system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks.
653system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks.
654system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks.
655system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit.
656system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor
657system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy
658system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy
659system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
660system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id
661system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
662system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
663system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses
664system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses

666system.cpu0.icache.tags.replacements 698162 # number of replacements
667system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use
668system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks.
669system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks.
670system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks.
671system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit.
672system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor
673system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy
674system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy
675system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
676system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id
677system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
678system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
679system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses
680system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses

681system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

665system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits
666system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits
667system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits
668system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits
669system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits
670system.cpu0.icache.overall_hits::total 47065399 # number of overall hits
671system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses
672system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses
673system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses
674system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses
675system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses
676system.cpu0.icache.overall_misses::total 698792 # number of overall misses
677system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10197257500 # number of ReadReq miss cycles
678system.cpu0.icache.ReadReq_miss_latency::total 10197257500 # number of ReadReq miss cycles
679system.cpu0.icache.demand_miss_latency::cpu0.inst 10197257500 # number of demand (read+write) miss cycles
680system.cpu0.icache.demand_miss_latency::total 10197257500 # number of demand (read+write) miss cycles
681system.cpu0.icache.overall_miss_latency::cpu0.inst 10197257500 # number of overall miss cycles
682system.cpu0.icache.overall_miss_latency::total 10197257500 # number of overall miss cycles
683system.cpu0.icache.ReadReq_accesses::cpu0.inst 47764191 # number of ReadReq accesses(hits+misses)
684system.cpu0.icache.ReadReq_accesses::total 47764191 # number of ReadReq accesses(hits+misses)
685system.cpu0.icache.demand_accesses::cpu0.inst 47764191 # number of demand (read+write) accesses
686system.cpu0.icache.demand_accesses::total 47764191 # number of demand (read+write) accesses
687system.cpu0.icache.overall_accesses::cpu0.inst 47764191 # number of overall (read+write) accesses
688system.cpu0.icache.overall_accesses::total 47764191 # number of overall (read+write) accesses
689system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014630 # miss rate for ReadReq accesses
690system.cpu0.icache.ReadReq_miss_rate::total 0.014630 # miss rate for ReadReq accesses
691system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014630 # miss rate for demand accesses
692system.cpu0.icache.demand_miss_rate::total 0.014630 # miss rate for demand accesses
693system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014630 # miss rate for overall accesses
694system.cpu0.icache.overall_miss_rate::total 0.014630 # miss rate for overall accesses
695system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534 # average ReadReq miss latency
696system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534 # average ReadReq miss latency
697system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency
698system.cpu0.icache.demand_avg_miss_latency::total 14592.693534 # average overall miss latency
699system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency
700system.cpu0.icache.overall_avg_miss_latency::total 14592.693534 # average overall miss latency
701system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
702system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
703system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
704system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
705system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
706system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
707system.cpu0.icache.writebacks::writebacks 698162 # number of writebacks
708system.cpu0.icache.writebacks::total 698162 # number of writebacks
709system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses
710system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses
711system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses
712system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses
713system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses
714system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses
715system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9498465500 # number of ReadReq MSHR miss cycles
716system.cpu0.icache.ReadReq_mshr_miss_latency::total 9498465500 # number of ReadReq MSHR miss cycles
717system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9498465500 # number of demand (read+write) MSHR miss cycles
718system.cpu0.icache.demand_mshr_miss_latency::total 9498465500 # number of demand (read+write) MSHR miss cycles
719system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9498465500 # number of overall MSHR miss cycles
720system.cpu0.icache.overall_mshr_miss_latency::total 9498465500 # number of overall MSHR miss cycles
721system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for ReadReq accesses
722system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014630 # mshr miss rate for ReadReq accesses
723system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for demand accesses
724system.cpu0.icache.demand_mshr_miss_rate::total 0.014630 # mshr miss rate for demand accesses
725system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for overall accesses
726system.cpu0.icache.overall_mshr_miss_rate::total 0.014630 # mshr miss rate for overall accesses
727system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average ReadReq mshr miss latency
728system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534 # average ReadReq mshr miss latency
729system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency
730system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency
731system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency
732system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency
733system.cpu1.dtb.fetch_hits 0 # ITB hits
734system.cpu1.dtb.fetch_misses 0 # ITB misses
735system.cpu1.dtb.fetch_acv 0 # ITB acv
736system.cpu1.dtb.fetch_accesses 0 # ITB accesses
737system.cpu1.dtb.read_hits 2421538 # DTB read hits
738system.cpu1.dtb.read_misses 2992 # DTB read misses
739system.cpu1.dtb.read_acv 0 # DTB read access violations
740system.cpu1.dtb.read_accesses 239363 # DTB read accesses
741system.cpu1.dtb.write_hits 1759460 # DTB write hits
742system.cpu1.dtb.write_misses 341 # DTB write misses
743system.cpu1.dtb.write_acv 29 # DTB write access violations
744system.cpu1.dtb.write_accesses 105247 # DTB write accesses
745system.cpu1.dtb.data_hits 4180998 # DTB hits
746system.cpu1.dtb.data_misses 3333 # DTB misses
747system.cpu1.dtb.data_acv 29 # DTB access violations
748system.cpu1.dtb.data_accesses 344610 # DTB accesses
749system.cpu1.itb.fetch_hits 1965348 # ITB hits
750system.cpu1.itb.fetch_misses 1216 # ITB misses
751system.cpu1.itb.fetch_acv 0 # ITB acv
752system.cpu1.itb.fetch_accesses 1966564 # ITB accesses
753system.cpu1.itb.read_hits 0 # DTB read hits
754system.cpu1.itb.read_misses 0 # DTB read misses
755system.cpu1.itb.read_acv 0 # DTB read access violations
756system.cpu1.itb.read_accesses 0 # DTB read accesses
757system.cpu1.itb.write_hits 0 # DTB write hits
758system.cpu1.itb.write_misses 0 # DTB write misses
759system.cpu1.itb.write_acv 0 # DTB write access violations
760system.cpu1.itb.write_accesses 0 # DTB write accesses
761system.cpu1.itb.data_hits 0 # DTB hits
762system.cpu1.itb.data_misses 0 # DTB misses
763system.cpu1.itb.data_acv 0 # DTB access violations
764system.cpu1.itb.data_accesses 0 # DTB accesses

682system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits
683system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits
684system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits
685system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits
686system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits
687system.cpu0.icache.overall_hits::total 47065399 # number of overall hits
688system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses
689system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses
690system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses
691system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses
692system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses
693system.cpu0.icache.overall_misses::total 698792 # number of overall misses
694system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10197257500 # number of ReadReq miss cycles
695system.cpu0.icache.ReadReq_miss_latency::total 10197257500 # number of ReadReq miss cycles
696system.cpu0.icache.demand_miss_latency::cpu0.inst 10197257500 # number of demand (read+write) miss cycles
697system.cpu0.icache.demand_miss_latency::total 10197257500 # number of demand (read+write) miss cycles
698system.cpu0.icache.overall_miss_latency::cpu0.inst 10197257500 # number of overall miss cycles
699system.cpu0.icache.overall_miss_latency::total 10197257500 # number of overall miss cycles
700system.cpu0.icache.ReadReq_accesses::cpu0.inst 47764191 # number of ReadReq accesses(hits+misses)
701system.cpu0.icache.ReadReq_accesses::total 47764191 # number of ReadReq accesses(hits+misses)
702system.cpu0.icache.demand_accesses::cpu0.inst 47764191 # number of demand (read+write) accesses
703system.cpu0.icache.demand_accesses::total 47764191 # number of demand (read+write) accesses
704system.cpu0.icache.overall_accesses::cpu0.inst 47764191 # number of overall (read+write) accesses
705system.cpu0.icache.overall_accesses::total 47764191 # number of overall (read+write) accesses
706system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014630 # miss rate for ReadReq accesses
707system.cpu0.icache.ReadReq_miss_rate::total 0.014630 # miss rate for ReadReq accesses
708system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014630 # miss rate for demand accesses
709system.cpu0.icache.demand_miss_rate::total 0.014630 # miss rate for demand accesses
710system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014630 # miss rate for overall accesses
711system.cpu0.icache.overall_miss_rate::total 0.014630 # miss rate for overall accesses
712system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534 # average ReadReq miss latency
713system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534 # average ReadReq miss latency
714system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency
715system.cpu0.icache.demand_avg_miss_latency::total 14592.693534 # average overall miss latency
716system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency
717system.cpu0.icache.overall_avg_miss_latency::total 14592.693534 # average overall miss latency
718system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
719system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
720system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
721system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
722system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
723system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
724system.cpu0.icache.writebacks::writebacks 698162 # number of writebacks
725system.cpu0.icache.writebacks::total 698162 # number of writebacks
726system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses
727system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses
728system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses
729system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses
730system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses
731system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses
732system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9498465500 # number of ReadReq MSHR miss cycles
733system.cpu0.icache.ReadReq_mshr_miss_latency::total 9498465500 # number of ReadReq MSHR miss cycles
734system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9498465500 # number of demand (read+write) MSHR miss cycles
735system.cpu0.icache.demand_mshr_miss_latency::total 9498465500 # number of demand (read+write) MSHR miss cycles
736system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9498465500 # number of overall MSHR miss cycles
737system.cpu0.icache.overall_mshr_miss_latency::total 9498465500 # number of overall MSHR miss cycles
738system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for ReadReq accesses
739system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014630 # mshr miss rate for ReadReq accesses
740system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for demand accesses
741system.cpu0.icache.demand_mshr_miss_rate::total 0.014630 # mshr miss rate for demand accesses
742system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for overall accesses
743system.cpu0.icache.overall_mshr_miss_rate::total 0.014630 # mshr miss rate for overall accesses
744system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average ReadReq mshr miss latency
745system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534 # average ReadReq mshr miss latency
746system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency
747system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency
748system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency
749system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency
750system.cpu1.dtb.fetch_hits 0 # ITB hits
751system.cpu1.dtb.fetch_misses 0 # ITB misses
752system.cpu1.dtb.fetch_acv 0 # ITB acv
753system.cpu1.dtb.fetch_accesses 0 # ITB accesses
754system.cpu1.dtb.read_hits 2421538 # DTB read hits
755system.cpu1.dtb.read_misses 2992 # DTB read misses
756system.cpu1.dtb.read_acv 0 # DTB read access violations
757system.cpu1.dtb.read_accesses 239363 # DTB read accesses
758system.cpu1.dtb.write_hits 1759460 # DTB write hits
759system.cpu1.dtb.write_misses 341 # DTB write misses
760system.cpu1.dtb.write_acv 29 # DTB write access violations
761system.cpu1.dtb.write_accesses 105247 # DTB write accesses
762system.cpu1.dtb.data_hits 4180998 # DTB hits
763system.cpu1.dtb.data_misses 3333 # DTB misses
764system.cpu1.dtb.data_acv 29 # DTB access violations
765system.cpu1.dtb.data_accesses 344610 # DTB accesses
766system.cpu1.itb.fetch_hits 1965348 # ITB hits
767system.cpu1.itb.fetch_misses 1216 # ITB misses
768system.cpu1.itb.fetch_acv 0 # ITB acv
769system.cpu1.itb.fetch_accesses 1966564 # ITB accesses
770system.cpu1.itb.read_hits 0 # DTB read hits
771system.cpu1.itb.read_misses 0 # DTB read misses
772system.cpu1.itb.read_acv 0 # DTB read access violations
773system.cpu1.itb.read_accesses 0 # DTB read accesses
774system.cpu1.itb.write_hits 0 # DTB write hits
775system.cpu1.itb.write_misses 0 # DTB write misses
776system.cpu1.itb.write_acv 0 # DTB write access violations
777system.cpu1.itb.write_accesses 0 # DTB write accesses
778system.cpu1.itb.data_hits 0 # DTB hits
779system.cpu1.itb.data_misses 0 # DTB misses
780system.cpu1.itb.data_acv 0 # DTB access violations
781system.cpu1.itb.data_accesses 0 # DTB accesses

782system.cpu1.numPwrStateTransitions 5480 # Number of power state transitions
783system.cpu1.pwrStateClkGateDist::samples 2740 # Distribution of time spent in the clock gated state
784system.cpu1.pwrStateClkGateDist::mean 707616074.452555 # Distribution of time spent in the clock gated state
785system.cpu1.pwrStateClkGateDist::stdev 409900069.702285 # Distribution of time spent in the clock gated state
786system.cpu1.pwrStateClkGateDist::1000-5e+10 2740 100.00% 100.00% # Distribution of time spent in the clock gated state
787system.cpu1.pwrStateClkGateDist::min_value 76500 # Distribution of time spent in the clock gated state
788system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state
789system.cpu1.pwrStateClkGateDist::total 2740 # Distribution of time spent in the clock gated state
790system.cpu1.pwrStateResidencyTicks::ON 24744530000 # Cumulative time (in ticks) in various power states
791system.cpu1.pwrStateResidencyTicks::CLK_GATED 1938868044000 # Cumulative time (in ticks) in various power states

765system.cpu1.numCycles 3927225148 # number of cpu cycles simulated
766system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
767system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
768system.cpu1.kern.inst.arm 0 # number of arm instructions executed
769system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
770system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed
771system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl
772system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl
773system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl
774system.cpu1.kern.ipl_count::31 40242 58.09% 100.00% # number of times we switched to this ipl
775system.cpu1.kern.ipl_count::total 69281 # number of times we switched to this ipl
776system.cpu1.kern.ipl_good::0 25724 48.16% 48.16% # number of times we switched to this ipl from a different ipl
777system.cpu1.kern.ipl_good::22 1968 3.68% 51.84% # number of times we switched to this ipl from a different ipl
778system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl
779system.cpu1.kern.ipl_good::31 25220 47.21% 100.00% # number of times we switched to this ipl from a different ipl
780system.cpu1.kern.ipl_good::total 53416 # number of times we switched to this ipl from a different ipl
781system.cpu1.kern.ipl_ticks::0 1910368546000 97.29% 97.29% # number of cycles we spent at this ipl
782system.cpu1.kern.ipl_ticks::22 730956000 0.04% 97.33% # number of cycles we spent at this ipl
783system.cpu1.kern.ipl_ticks::30 356511000 0.02% 97.34% # number of cycles we spent at this ipl
784system.cpu1.kern.ipl_ticks::31 52155834000 2.66% 100.00% # number of cycles we spent at this ipl
785system.cpu1.kern.ipl_ticks::total 1963611847000 # number of cycles we spent at this ipl
786system.cpu1.kern.ipl_used::0 0.968269 # fraction of swpipl calls that actually changed the ipl
787system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
788system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
789system.cpu1.kern.ipl_used::31 0.626708 # fraction of swpipl calls that actually changed the ipl
790system.cpu1.kern.ipl_used::total 0.771005 # fraction of swpipl calls that actually changed the ipl
791system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
792system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
793system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
794system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
795system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
796system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
797system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
798system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
799system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
800system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
801system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
802system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
803system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
804system.cpu1.kern.syscall::total 104 # number of syscalls executed
805system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
806system.cpu1.kern.callpal::wripir 422 0.59% 0.59% # number of callpals executed
807system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
808system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
809system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed
810system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
811system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
812system.cpu1.kern.callpal::swpipl 63030 88.06% 91.46% # number of callpals executed
813system.cpu1.kern.callpal::rdps 2146 3.00% 94.46% # number of callpals executed
814system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed
815system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed
816system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed
817system.cpu1.kern.callpal::rti 3778 5.28% 99.75% # number of callpals executed
818system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
819system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
820system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
821system.cpu1.kern.callpal::total 71579 # number of callpals executed
822system.cpu1.kern.mode_switch::kernel 2069 # number of protection mode switches
823system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
824system.cpu1.kern.mode_switch::idle 2878 # number of protection mode switches
825system.cpu1.kern.mode_good::kernel 892
826system.cpu1.kern.mode_good::user 464
827system.cpu1.kern.mode_good::idle 428
828system.cpu1.kern.mode_switch_good::kernel 0.431126 # fraction of useful protection mode switches
829system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
830system.cpu1.kern.mode_switch_good::idle 0.148714 # fraction of useful protection mode switches
831system.cpu1.kern.mode_switch_good::total 0.329699 # fraction of useful protection mode switches
832system.cpu1.kern.mode_ticks::kernel 17834392500 0.91% 0.91% # number of ticks spent at the given mode
833system.cpu1.kern.mode_ticks::user 1709021000 0.09% 1.00% # number of ticks spent at the given mode
834system.cpu1.kern.mode_ticks::idle 1944068431500 99.00% 100.00% # number of ticks spent at the given mode
835system.cpu1.kern.swap_context 2002 # number of times the context was actually changed
836system.cpu1.committedInsts 13162574 # Number of instructions committed
837system.cpu1.committedOps 13162574 # Number of ops (including micro ops) committed
838system.cpu1.num_int_alu_accesses 12139381 # Number of integer alu accesses
839system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses
840system.cpu1.num_func_calls 411749 # number of times a function call or return occured
841system.cpu1.num_conditional_control_insts 1304648 # number of instructions that are conditional controls
842system.cpu1.num_int_insts 12139381 # number of integer instructions
843system.cpu1.num_fp_insts 173446 # number of float instructions
844system.cpu1.num_int_register_reads 16710166 # number of times the integer registers were read
845system.cpu1.num_int_register_writes 8908141 # number of times the integer registers were written
846system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read
847system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written
848system.cpu1.num_mem_refs 4204594 # number of memory refs
849system.cpu1.num_load_insts 2435865 # Number of load instructions
850system.cpu1.num_store_insts 1768729 # Number of store instructions
851system.cpu1.num_idle_cycles 3877736087.998025 # Number of idle cycles
852system.cpu1.num_busy_cycles 49489060.001975 # Number of busy cycles
853system.cpu1.not_idle_fraction 0.012602 # Percentage of non-idle cycles
854system.cpu1.idle_fraction 0.987398 # Percentage of idle cycles
855system.cpu1.Branches 1871255 # Number of branches fetched
856system.cpu1.op_class::No_OpClass 705493 5.36% 5.36% # Class of executed instruction
857system.cpu1.op_class::IntAlu 7781042 59.10% 64.46% # Class of executed instruction
858system.cpu1.op_class::IntMult 21322 0.16% 64.62% # Class of executed instruction
859system.cpu1.op_class::IntDiv 0 0.00% 64.62% # Class of executed instruction
860system.cpu1.op_class::FloatAdd 14181 0.11% 64.73% # Class of executed instruction
861system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
862system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
863system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
864system.cpu1.op_class::FloatDiv 1986 0.02% 64.74% # Class of executed instruction
865system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction
866system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction
867system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction
868system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction
869system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction
870system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction
871system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction
872system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction
873system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction
874system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction
875system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction
876system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction
877system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction
878system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
879system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
880system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
881system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
882system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
883system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
884system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
885system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
886system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction
887system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction
888system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction
889system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
890system.cpu1.op_class::total 13165936 # Class of executed instruction

792system.cpu1.numCycles 3927225148 # number of cpu cycles simulated
793system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
794system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
795system.cpu1.kern.inst.arm 0 # number of arm instructions executed
796system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
797system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed
798system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl
799system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl
800system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl
801system.cpu1.kern.ipl_count::31 40242 58.09% 100.00% # number of times we switched to this ipl
802system.cpu1.kern.ipl_count::total 69281 # number of times we switched to this ipl
803system.cpu1.kern.ipl_good::0 25724 48.16% 48.16% # number of times we switched to this ipl from a different ipl
804system.cpu1.kern.ipl_good::22 1968 3.68% 51.84% # number of times we switched to this ipl from a different ipl
805system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl
806system.cpu1.kern.ipl_good::31 25220 47.21% 100.00% # number of times we switched to this ipl from a different ipl
807system.cpu1.kern.ipl_good::total 53416 # number of times we switched to this ipl from a different ipl
808system.cpu1.kern.ipl_ticks::0 1910368546000 97.29% 97.29% # number of cycles we spent at this ipl
809system.cpu1.kern.ipl_ticks::22 730956000 0.04% 97.33% # number of cycles we spent at this ipl
810system.cpu1.kern.ipl_ticks::30 356511000 0.02% 97.34% # number of cycles we spent at this ipl
811system.cpu1.kern.ipl_ticks::31 52155834000 2.66% 100.00% # number of cycles we spent at this ipl
812system.cpu1.kern.ipl_ticks::total 1963611847000 # number of cycles we spent at this ipl
813system.cpu1.kern.ipl_used::0 0.968269 # fraction of swpipl calls that actually changed the ipl
814system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
815system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
816system.cpu1.kern.ipl_used::31 0.626708 # fraction of swpipl calls that actually changed the ipl
817system.cpu1.kern.ipl_used::total 0.771005 # fraction of swpipl calls that actually changed the ipl
818system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
819system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
820system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
821system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
822system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
823system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
824system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
825system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
826system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
827system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
828system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
829system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
830system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
831system.cpu1.kern.syscall::total 104 # number of syscalls executed
832system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
833system.cpu1.kern.callpal::wripir 422 0.59% 0.59% # number of callpals executed
834system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
835system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
836system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed
837system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
838system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
839system.cpu1.kern.callpal::swpipl 63030 88.06% 91.46% # number of callpals executed
840system.cpu1.kern.callpal::rdps 2146 3.00% 94.46% # number of callpals executed
841system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed
842system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed
843system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed
844system.cpu1.kern.callpal::rti 3778 5.28% 99.75% # number of callpals executed
845system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
846system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
847system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
848system.cpu1.kern.callpal::total 71579 # number of callpals executed
849system.cpu1.kern.mode_switch::kernel 2069 # number of protection mode switches
850system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
851system.cpu1.kern.mode_switch::idle 2878 # number of protection mode switches
852system.cpu1.kern.mode_good::kernel 892
853system.cpu1.kern.mode_good::user 464
854system.cpu1.kern.mode_good::idle 428
855system.cpu1.kern.mode_switch_good::kernel 0.431126 # fraction of useful protection mode switches
856system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
857system.cpu1.kern.mode_switch_good::idle 0.148714 # fraction of useful protection mode switches
858system.cpu1.kern.mode_switch_good::total 0.329699 # fraction of useful protection mode switches
859system.cpu1.kern.mode_ticks::kernel 17834392500 0.91% 0.91% # number of ticks spent at the given mode
860system.cpu1.kern.mode_ticks::user 1709021000 0.09% 1.00% # number of ticks spent at the given mode
861system.cpu1.kern.mode_ticks::idle 1944068431500 99.00% 100.00% # number of ticks spent at the given mode
862system.cpu1.kern.swap_context 2002 # number of times the context was actually changed
863system.cpu1.committedInsts 13162574 # Number of instructions committed
864system.cpu1.committedOps 13162574 # Number of ops (including micro ops) committed
865system.cpu1.num_int_alu_accesses 12139381 # Number of integer alu accesses
866system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses
867system.cpu1.num_func_calls 411749 # number of times a function call or return occured
868system.cpu1.num_conditional_control_insts 1304648 # number of instructions that are conditional controls
869system.cpu1.num_int_insts 12139381 # number of integer instructions
870system.cpu1.num_fp_insts 173446 # number of float instructions
871system.cpu1.num_int_register_reads 16710166 # number of times the integer registers were read
872system.cpu1.num_int_register_writes 8908141 # number of times the integer registers were written
873system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read
874system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written
875system.cpu1.num_mem_refs 4204594 # number of memory refs
876system.cpu1.num_load_insts 2435865 # Number of load instructions
877system.cpu1.num_store_insts 1768729 # Number of store instructions
878system.cpu1.num_idle_cycles 3877736087.998025 # Number of idle cycles
879system.cpu1.num_busy_cycles 49489060.001975 # Number of busy cycles
880system.cpu1.not_idle_fraction 0.012602 # Percentage of non-idle cycles
881system.cpu1.idle_fraction 0.987398 # Percentage of idle cycles
882system.cpu1.Branches 1871255 # Number of branches fetched
883system.cpu1.op_class::No_OpClass 705493 5.36% 5.36% # Class of executed instruction
884system.cpu1.op_class::IntAlu 7781042 59.10% 64.46% # Class of executed instruction
885system.cpu1.op_class::IntMult 21322 0.16% 64.62% # Class of executed instruction
886system.cpu1.op_class::IntDiv 0 0.00% 64.62% # Class of executed instruction
887system.cpu1.op_class::FloatAdd 14181 0.11% 64.73% # Class of executed instruction
888system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
889system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
890system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
891system.cpu1.op_class::FloatDiv 1986 0.02% 64.74% # Class of executed instruction
892system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction
893system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction
894system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction
895system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction
896system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction
897system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction
898system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction
899system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction
900system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction
901system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction
902system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction
903system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction
904system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction
905system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
906system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
907system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
908system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
909system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
910system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
911system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
912system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
913system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction
914system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction
915system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction
916system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
917system.cpu1.op_class::total 13165936 # Class of executed instruction

918system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

891system.cpu1.dcache.tags.replacements 166516 # number of replacements
892system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use
893system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks.
894system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks.
895system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks.
896system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit.
897system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor
898system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy
899system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy
900system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
901system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
902system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
903system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
904system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
905system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses
906system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses

919system.cpu1.dcache.tags.replacements 166516 # number of replacements
920system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use
921system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks.
922system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks.
923system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks.
924system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit.
925system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor
926system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy
927system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy
928system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
929system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
930system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
931system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
932system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
933system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses
934system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses

935system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

907system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits
908system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits
909system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits
910system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits
911system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits
912system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits
913system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits
914system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits
915system.cpu1.dcache.demand_hits::cpu1.data 3899224 # number of demand (read+write) hits
916system.cpu1.dcache.demand_hits::total 3899224 # number of demand (read+write) hits
917system.cpu1.dcache.overall_hits::cpu1.data 3899224 # number of overall hits
918system.cpu1.dcache.overall_hits::total 3899224 # number of overall hits
919system.cpu1.dcache.ReadReq_misses::cpu1.data 118432 # number of ReadReq misses
920system.cpu1.dcache.ReadReq_misses::total 118432 # number of ReadReq misses
921system.cpu1.dcache.WriteReq_misses::cpu1.data 62660 # number of WriteReq misses
922system.cpu1.dcache.WriteReq_misses::total 62660 # number of WriteReq misses
923system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8936 # number of LoadLockedReq misses
924system.cpu1.dcache.LoadLockedReq_misses::total 8936 # number of LoadLockedReq misses
925system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5856 # number of StoreCondReq misses
926system.cpu1.dcache.StoreCondReq_misses::total 5856 # number of StoreCondReq misses
927system.cpu1.dcache.demand_misses::cpu1.data 181092 # number of demand (read+write) misses
928system.cpu1.dcache.demand_misses::total 181092 # number of demand (read+write) misses
929system.cpu1.dcache.overall_misses::cpu1.data 181092 # number of overall misses
930system.cpu1.dcache.overall_misses::total 181092 # number of overall misses
931system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1454494000 # number of ReadReq miss cycles
932system.cpu1.dcache.ReadReq_miss_latency::total 1454494000 # number of ReadReq miss cycles
933system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1265962000 # number of WriteReq miss cycles
934system.cpu1.dcache.WriteReq_miss_latency::total 1265962000 # number of WriteReq miss cycles
935system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82083000 # number of LoadLockedReq miss cycles
936system.cpu1.dcache.LoadLockedReq_miss_latency::total 82083000 # number of LoadLockedReq miss cycles
937system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49296000 # number of StoreCondReq miss cycles
938system.cpu1.dcache.StoreCondReq_miss_latency::total 49296000 # number of StoreCondReq miss cycles
939system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5500 # number of StoreCondFailReq miss cycles
940system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5500 # number of StoreCondFailReq miss cycles
941system.cpu1.dcache.demand_miss_latency::cpu1.data 2720456000 # number of demand (read+write) miss cycles
942system.cpu1.dcache.demand_miss_latency::total 2720456000 # number of demand (read+write) miss cycles
943system.cpu1.dcache.overall_miss_latency::cpu1.data 2720456000 # number of overall miss cycles
944system.cpu1.dcache.overall_miss_latency::total 2720456000 # number of overall miss cycles
945system.cpu1.dcache.ReadReq_accesses::cpu1.data 2375633 # number of ReadReq accesses(hits+misses)
946system.cpu1.dcache.ReadReq_accesses::total 2375633 # number of ReadReq accesses(hits+misses)
947system.cpu1.dcache.WriteReq_accesses::cpu1.data 1704683 # number of WriteReq accesses(hits+misses)
948system.cpu1.dcache.WriteReq_accesses::total 1704683 # number of WriteReq accesses(hits+misses)
949system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57151 # number of LoadLockedReq accesses(hits+misses)
950system.cpu1.dcache.LoadLockedReq_accesses::total 57151 # number of LoadLockedReq accesses(hits+misses)
951system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56677 # number of StoreCondReq accesses(hits+misses)
952system.cpu1.dcache.StoreCondReq_accesses::total 56677 # number of StoreCondReq accesses(hits+misses)
953system.cpu1.dcache.demand_accesses::cpu1.data 4080316 # number of demand (read+write) accesses
954system.cpu1.dcache.demand_accesses::total 4080316 # number of demand (read+write) accesses
955system.cpu1.dcache.overall_accesses::cpu1.data 4080316 # number of overall (read+write) accesses
956system.cpu1.dcache.overall_accesses::total 4080316 # number of overall (read+write) accesses
957system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049853 # miss rate for ReadReq accesses
958system.cpu1.dcache.ReadReq_miss_rate::total 0.049853 # miss rate for ReadReq accesses
959system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036758 # miss rate for WriteReq accesses
960system.cpu1.dcache.WriteReq_miss_rate::total 0.036758 # miss rate for WriteReq accesses
961system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156358 # miss rate for LoadLockedReq accesses
962system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156358 # miss rate for LoadLockedReq accesses
963system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103322 # miss rate for StoreCondReq accesses
964system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103322 # miss rate for StoreCondReq accesses
965system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044382 # miss rate for demand accesses
966system.cpu1.dcache.demand_miss_rate::total 0.044382 # miss rate for demand accesses
967system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044382 # miss rate for overall accesses
968system.cpu1.dcache.overall_miss_rate::total 0.044382 # miss rate for overall accesses
969system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444 # average ReadReq miss latency
970system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444 # average ReadReq miss latency
971system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603 # average WriteReq miss latency
972system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603 # average WriteReq miss latency
973system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.653536 # average LoadLockedReq miss latency
974system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.653536 # average LoadLockedReq miss latency
975system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8418.032787 # average StoreCondReq miss latency
976system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8418.032787 # average StoreCondReq miss latency
977system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
978system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
979system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency
980system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897 # average overall miss latency
981system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency
982system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897 # average overall miss latency
983system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
984system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
985system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
986system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
987system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
988system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
989system.cpu1.dcache.writebacks::writebacks 114398 # number of writebacks
990system.cpu1.dcache.writebacks::total 114398 # number of writebacks
991system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118432 # number of ReadReq MSHR misses
992system.cpu1.dcache.ReadReq_mshr_misses::total 118432 # number of ReadReq MSHR misses
993system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62660 # number of WriteReq MSHR misses
994system.cpu1.dcache.WriteReq_mshr_misses::total 62660 # number of WriteReq MSHR misses
995system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8936 # number of LoadLockedReq MSHR misses
996system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8936 # number of LoadLockedReq MSHR misses
997system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5856 # number of StoreCondReq MSHR misses
998system.cpu1.dcache.StoreCondReq_mshr_misses::total 5856 # number of StoreCondReq MSHR misses
999system.cpu1.dcache.demand_mshr_misses::cpu1.data 181092 # number of demand (read+write) MSHR misses
1000system.cpu1.dcache.demand_mshr_misses::total 181092 # number of demand (read+write) MSHR misses
1001system.cpu1.dcache.overall_mshr_misses::cpu1.data 181092 # number of overall MSHR misses
1002system.cpu1.dcache.overall_mshr_misses::total 181092 # number of overall MSHR misses
1003system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
1004system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable
1005system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable
1006system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable
1007system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses
1008system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses
1009system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1336062000 # number of ReadReq MSHR miss cycles
1010system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1336062000 # number of ReadReq MSHR miss cycles
1011system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1203302000 # number of WriteReq MSHR miss cycles
1012system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1203302000 # number of WriteReq MSHR miss cycles
1013system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73147000 # number of LoadLockedReq MSHR miss cycles
1014system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73147000 # number of LoadLockedReq MSHR miss cycles
1015system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43441000 # number of StoreCondReq MSHR miss cycles
1016system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43441000 # number of StoreCondReq MSHR miss cycles
1017system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4500 # number of StoreCondFailReq MSHR miss cycles
1018system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4500 # number of StoreCondFailReq MSHR miss cycles
1019system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539364000 # number of demand (read+write) MSHR miss cycles
1020system.cpu1.dcache.demand_mshr_miss_latency::total 2539364000 # number of demand (read+write) MSHR miss cycles
1021system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539364000 # number of overall MSHR miss cycles
1022system.cpu1.dcache.overall_mshr_miss_latency::total 2539364000 # number of overall MSHR miss cycles
1023system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles
1024system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles
1025system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles
1026system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles
1027system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049853 # mshr miss rate for ReadReq accesses
1028system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049853 # mshr miss rate for ReadReq accesses
1029system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036758 # mshr miss rate for WriteReq accesses
1030system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036758 # mshr miss rate for WriteReq accesses
1031system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156358 # mshr miss rate for LoadLockedReq accesses
1032system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156358 # mshr miss rate for LoadLockedReq accesses
1033system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103322 # mshr miss rate for StoreCondReq accesses
1034system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103322 # mshr miss rate for StoreCondReq accesses
1035system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for demand accesses
1036system.cpu1.dcache.demand_mshr_miss_rate::total 0.044382 # mshr miss rate for demand accesses
1037system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for overall accesses
1038system.cpu1.dcache.overall_mshr_miss_rate::total 0.044382 # mshr miss rate for overall accesses
1039system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444 # average ReadReq mshr miss latency
1040system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444 # average ReadReq mshr miss latency
1041system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603 # average WriteReq mshr miss latency
1042system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603 # average WriteReq mshr miss latency
1043system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.653536 # average LoadLockedReq mshr miss latency
1044system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.653536 # average LoadLockedReq mshr miss latency
1045system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7418.203552 # average StoreCondReq mshr miss latency
1046system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7418.203552 # average StoreCondReq mshr miss latency
1047system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1048system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1049system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency
1050system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency
1051system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency
1052system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency
1053system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency
1054system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency
1055system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency
1056system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency

936system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits
937system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits
938system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits
939system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits
940system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits
941system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits
942system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits
943system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits
944system.cpu1.dcache.demand_hits::cpu1.data 3899224 # number of demand (read+write) hits
945system.cpu1.dcache.demand_hits::total 3899224 # number of demand (read+write) hits
946system.cpu1.dcache.overall_hits::cpu1.data 3899224 # number of overall hits
947system.cpu1.dcache.overall_hits::total 3899224 # number of overall hits
948system.cpu1.dcache.ReadReq_misses::cpu1.data 118432 # number of ReadReq misses
949system.cpu1.dcache.ReadReq_misses::total 118432 # number of ReadReq misses
950system.cpu1.dcache.WriteReq_misses::cpu1.data 62660 # number of WriteReq misses
951system.cpu1.dcache.WriteReq_misses::total 62660 # number of WriteReq misses
952system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8936 # number of LoadLockedReq misses
953system.cpu1.dcache.LoadLockedReq_misses::total 8936 # number of LoadLockedReq misses
954system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5856 # number of StoreCondReq misses
955system.cpu1.dcache.StoreCondReq_misses::total 5856 # number of StoreCondReq misses
956system.cpu1.dcache.demand_misses::cpu1.data 181092 # number of demand (read+write) misses
957system.cpu1.dcache.demand_misses::total 181092 # number of demand (read+write) misses
958system.cpu1.dcache.overall_misses::cpu1.data 181092 # number of overall misses
959system.cpu1.dcache.overall_misses::total 181092 # number of overall misses
960system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1454494000 # number of ReadReq miss cycles
961system.cpu1.dcache.ReadReq_miss_latency::total 1454494000 # number of ReadReq miss cycles
962system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1265962000 # number of WriteReq miss cycles
963system.cpu1.dcache.WriteReq_miss_latency::total 1265962000 # number of WriteReq miss cycles
964system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82083000 # number of LoadLockedReq miss cycles
965system.cpu1.dcache.LoadLockedReq_miss_latency::total 82083000 # number of LoadLockedReq miss cycles
966system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49296000 # number of StoreCondReq miss cycles
967system.cpu1.dcache.StoreCondReq_miss_latency::total 49296000 # number of StoreCondReq miss cycles
968system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5500 # number of StoreCondFailReq miss cycles
969system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5500 # number of StoreCondFailReq miss cycles
970system.cpu1.dcache.demand_miss_latency::cpu1.data 2720456000 # number of demand (read+write) miss cycles
971system.cpu1.dcache.demand_miss_latency::total 2720456000 # number of demand (read+write) miss cycles
972system.cpu1.dcache.overall_miss_latency::cpu1.data 2720456000 # number of overall miss cycles
973system.cpu1.dcache.overall_miss_latency::total 2720456000 # number of overall miss cycles
974system.cpu1.dcache.ReadReq_accesses::cpu1.data 2375633 # number of ReadReq accesses(hits+misses)
975system.cpu1.dcache.ReadReq_accesses::total 2375633 # number of ReadReq accesses(hits+misses)
976system.cpu1.dcache.WriteReq_accesses::cpu1.data 1704683 # number of WriteReq accesses(hits+misses)
977system.cpu1.dcache.WriteReq_accesses::total 1704683 # number of WriteReq accesses(hits+misses)
978system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57151 # number of LoadLockedReq accesses(hits+misses)
979system.cpu1.dcache.LoadLockedReq_accesses::total 57151 # number of LoadLockedReq accesses(hits+misses)
980system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56677 # number of StoreCondReq accesses(hits+misses)
981system.cpu1.dcache.StoreCondReq_accesses::total 56677 # number of StoreCondReq accesses(hits+misses)
982system.cpu1.dcache.demand_accesses::cpu1.data 4080316 # number of demand (read+write) accesses
983system.cpu1.dcache.demand_accesses::total 4080316 # number of demand (read+write) accesses
984system.cpu1.dcache.overall_accesses::cpu1.data 4080316 # number of overall (read+write) accesses
985system.cpu1.dcache.overall_accesses::total 4080316 # number of overall (read+write) accesses
986system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049853 # miss rate for ReadReq accesses
987system.cpu1.dcache.ReadReq_miss_rate::total 0.049853 # miss rate for ReadReq accesses
988system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036758 # miss rate for WriteReq accesses
989system.cpu1.dcache.WriteReq_miss_rate::total 0.036758 # miss rate for WriteReq accesses
990system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156358 # miss rate for LoadLockedReq accesses
991system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156358 # miss rate for LoadLockedReq accesses
992system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103322 # miss rate for StoreCondReq accesses
993system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103322 # miss rate for StoreCondReq accesses
994system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044382 # miss rate for demand accesses
995system.cpu1.dcache.demand_miss_rate::total 0.044382 # miss rate for demand accesses
996system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044382 # miss rate for overall accesses
997system.cpu1.dcache.overall_miss_rate::total 0.044382 # miss rate for overall accesses
998system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444 # average ReadReq miss latency
999system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444 # average ReadReq miss latency
1000system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603 # average WriteReq miss latency
1001system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603 # average WriteReq miss latency
1002system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.653536 # average LoadLockedReq miss latency
1003system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.653536 # average LoadLockedReq miss latency
1004system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8418.032787 # average StoreCondReq miss latency
1005system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8418.032787 # average StoreCondReq miss latency
1006system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1007system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1008system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency
1009system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897 # average overall miss latency
1010system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency
1011system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897 # average overall miss latency
1012system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1013system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1014system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1015system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1016system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1017system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1018system.cpu1.dcache.writebacks::writebacks 114398 # number of writebacks
1019system.cpu1.dcache.writebacks::total 114398 # number of writebacks
1020system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118432 # number of ReadReq MSHR misses
1021system.cpu1.dcache.ReadReq_mshr_misses::total 118432 # number of ReadReq MSHR misses
1022system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62660 # number of WriteReq MSHR misses
1023system.cpu1.dcache.WriteReq_mshr_misses::total 62660 # number of WriteReq MSHR misses
1024system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8936 # number of LoadLockedReq MSHR misses
1025system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8936 # number of LoadLockedReq MSHR misses
1026system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5856 # number of StoreCondReq MSHR misses
1027system.cpu1.dcache.StoreCondReq_mshr_misses::total 5856 # number of StoreCondReq MSHR misses
1028system.cpu1.dcache.demand_mshr_misses::cpu1.data 181092 # number of demand (read+write) MSHR misses
1029system.cpu1.dcache.demand_mshr_misses::total 181092 # number of demand (read+write) MSHR misses
1030system.cpu1.dcache.overall_mshr_misses::cpu1.data 181092 # number of overall MSHR misses
1031system.cpu1.dcache.overall_mshr_misses::total 181092 # number of overall MSHR misses
1032system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
1033system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable
1034system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable
1035system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable
1036system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses
1037system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses
1038system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1336062000 # number of ReadReq MSHR miss cycles
1039system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1336062000 # number of ReadReq MSHR miss cycles
1040system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1203302000 # number of WriteReq MSHR miss cycles
1041system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1203302000 # number of WriteReq MSHR miss cycles
1042system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73147000 # number of LoadLockedReq MSHR miss cycles
1043system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73147000 # number of LoadLockedReq MSHR miss cycles
1044system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43441000 # number of StoreCondReq MSHR miss cycles
1045system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43441000 # number of StoreCondReq MSHR miss cycles
1046system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4500 # number of StoreCondFailReq MSHR miss cycles
1047system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4500 # number of StoreCondFailReq MSHR miss cycles
1048system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539364000 # number of demand (read+write) MSHR miss cycles
1049system.cpu1.dcache.demand_mshr_miss_latency::total 2539364000 # number of demand (read+write) MSHR miss cycles
1050system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539364000 # number of overall MSHR miss cycles
1051system.cpu1.dcache.overall_mshr_miss_latency::total 2539364000 # number of overall MSHR miss cycles
1052system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles
1053system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles
1054system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles
1055system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles
1056system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049853 # mshr miss rate for ReadReq accesses
1057system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049853 # mshr miss rate for ReadReq accesses
1058system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036758 # mshr miss rate for WriteReq accesses
1059system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036758 # mshr miss rate for WriteReq accesses
1060system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156358 # mshr miss rate for LoadLockedReq accesses
1061system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156358 # mshr miss rate for LoadLockedReq accesses
1062system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103322 # mshr miss rate for StoreCondReq accesses
1063system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103322 # mshr miss rate for StoreCondReq accesses
1064system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for demand accesses
1065system.cpu1.dcache.demand_mshr_miss_rate::total 0.044382 # mshr miss rate for demand accesses
1066system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for overall accesses
1067system.cpu1.dcache.overall_mshr_miss_rate::total 0.044382 # mshr miss rate for overall accesses
1068system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444 # average ReadReq mshr miss latency
1069system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444 # average ReadReq mshr miss latency
1070system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603 # average WriteReq mshr miss latency
1071system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603 # average WriteReq mshr miss latency
1072system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.653536 # average LoadLockedReq mshr miss latency
1073system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.653536 # average LoadLockedReq mshr miss latency
1074system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7418.203552 # average StoreCondReq mshr miss latency
1075system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7418.203552 # average StoreCondReq mshr miss latency
1076system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1077system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1078system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency
1079system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency
1080system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency
1081system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency
1082system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency
1083system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency
1084system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency
1085system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency

1086system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1057system.cpu1.icache.tags.replacements 316153 # number of replacements
1058system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use
1059system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks.
1060system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks.
1061system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks.
1062system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit.
1063system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor
1064system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy
1065system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy
1066system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1067system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
1068system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
1069system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
1070system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
1071system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1072system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses
1073system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses

1087system.cpu1.icache.tags.replacements 316153 # number of replacements
1088system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use
1089system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks.
1090system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks.
1091system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks.
1092system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit.
1093system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor
1094system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy
1095system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy
1096system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1097system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
1098system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
1099system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
1100system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
1101system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1102system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses
1103system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses

1104system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1074system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits
1075system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits
1076system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits
1077system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits
1078system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits
1079system.cpu1.icache.overall_hits::total 12849230 # number of overall hits
1080system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses
1081system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses
1082system.cpu1.icache.demand_misses::cpu1.inst 316707 # number of demand (read+write) misses
1083system.cpu1.icache.demand_misses::total 316707 # number of demand (read+write) misses
1084system.cpu1.icache.overall_misses::cpu1.inst 316707 # number of overall misses
1085system.cpu1.icache.overall_misses::total 316707 # number of overall misses
1086system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4252859000 # number of ReadReq miss cycles
1087system.cpu1.icache.ReadReq_miss_latency::total 4252859000 # number of ReadReq miss cycles
1088system.cpu1.icache.demand_miss_latency::cpu1.inst 4252859000 # number of demand (read+write) miss cycles
1089system.cpu1.icache.demand_miss_latency::total 4252859000 # number of demand (read+write) miss cycles
1090system.cpu1.icache.overall_miss_latency::cpu1.inst 4252859000 # number of overall miss cycles
1091system.cpu1.icache.overall_miss_latency::total 4252859000 # number of overall miss cycles
1092system.cpu1.icache.ReadReq_accesses::cpu1.inst 13165937 # number of ReadReq accesses(hits+misses)
1093system.cpu1.icache.ReadReq_accesses::total 13165937 # number of ReadReq accesses(hits+misses)
1094system.cpu1.icache.demand_accesses::cpu1.inst 13165937 # number of demand (read+write) accesses
1095system.cpu1.icache.demand_accesses::total 13165937 # number of demand (read+write) accesses
1096system.cpu1.icache.overall_accesses::cpu1.inst 13165937 # number of overall (read+write) accesses
1097system.cpu1.icache.overall_accesses::total 13165937 # number of overall (read+write) accesses
1098system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024055 # miss rate for ReadReq accesses
1099system.cpu1.icache.ReadReq_miss_rate::total 0.024055 # miss rate for ReadReq accesses
1100system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024055 # miss rate for demand accesses
1101system.cpu1.icache.demand_miss_rate::total 0.024055 # miss rate for demand accesses
1102system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024055 # miss rate for overall accesses
1103system.cpu1.icache.overall_miss_rate::total 0.024055 # miss rate for overall accesses
1104system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702 # average ReadReq miss latency
1105system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702 # average ReadReq miss latency
1106system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency
1107system.cpu1.icache.demand_avg_miss_latency::total 13428.370702 # average overall miss latency
1108system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency
1109system.cpu1.icache.overall_avg_miss_latency::total 13428.370702 # average overall miss latency
1110system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1111system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1112system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1113system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1114system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1115system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1116system.cpu1.icache.writebacks::writebacks 316153 # number of writebacks
1117system.cpu1.icache.writebacks::total 316153 # number of writebacks
1118system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316707 # number of ReadReq MSHR misses
1119system.cpu1.icache.ReadReq_mshr_misses::total 316707 # number of ReadReq MSHR misses
1120system.cpu1.icache.demand_mshr_misses::cpu1.inst 316707 # number of demand (read+write) MSHR misses
1121system.cpu1.icache.demand_mshr_misses::total 316707 # number of demand (read+write) MSHR misses
1122system.cpu1.icache.overall_mshr_misses::cpu1.inst 316707 # number of overall MSHR misses
1123system.cpu1.icache.overall_mshr_misses::total 316707 # number of overall MSHR misses
1124system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3936152000 # number of ReadReq MSHR miss cycles
1125system.cpu1.icache.ReadReq_mshr_miss_latency::total 3936152000 # number of ReadReq MSHR miss cycles
1126system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3936152000 # number of demand (read+write) MSHR miss cycles
1127system.cpu1.icache.demand_mshr_miss_latency::total 3936152000 # number of demand (read+write) MSHR miss cycles
1128system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3936152000 # number of overall MSHR miss cycles
1129system.cpu1.icache.overall_mshr_miss_latency::total 3936152000 # number of overall MSHR miss cycles
1130system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for ReadReq accesses
1131system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024055 # mshr miss rate for ReadReq accesses
1132system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for demand accesses
1133system.cpu1.icache.demand_mshr_miss_rate::total 0.024055 # mshr miss rate for demand accesses
1134system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for overall accesses
1135system.cpu1.icache.overall_mshr_miss_rate::total 0.024055 # mshr miss rate for overall accesses
1136system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average ReadReq mshr miss latency
1137system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702 # average ReadReq mshr miss latency
1138system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency
1139system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency
1140system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency
1141system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency
1142system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1143system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1144system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1145system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1146system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1147system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1148system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1149system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1150system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1151system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1152system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1153system.disk2.dma_write_txs 1 # Number of DMA write transactions.

1105system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits
1106system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits
1107system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits
1108system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits
1109system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits
1110system.cpu1.icache.overall_hits::total 12849230 # number of overall hits
1111system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses
1112system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses
1113system.cpu1.icache.demand_misses::cpu1.inst 316707 # number of demand (read+write) misses
1114system.cpu1.icache.demand_misses::total 316707 # number of demand (read+write) misses
1115system.cpu1.icache.overall_misses::cpu1.inst 316707 # number of overall misses
1116system.cpu1.icache.overall_misses::total 316707 # number of overall misses
1117system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4252859000 # number of ReadReq miss cycles
1118system.cpu1.icache.ReadReq_miss_latency::total 4252859000 # number of ReadReq miss cycles
1119system.cpu1.icache.demand_miss_latency::cpu1.inst 4252859000 # number of demand (read+write) miss cycles
1120system.cpu1.icache.demand_miss_latency::total 4252859000 # number of demand (read+write) miss cycles
1121system.cpu1.icache.overall_miss_latency::cpu1.inst 4252859000 # number of overall miss cycles
1122system.cpu1.icache.overall_miss_latency::total 4252859000 # number of overall miss cycles
1123system.cpu1.icache.ReadReq_accesses::cpu1.inst 13165937 # number of ReadReq accesses(hits+misses)
1124system.cpu1.icache.ReadReq_accesses::total 13165937 # number of ReadReq accesses(hits+misses)
1125system.cpu1.icache.demand_accesses::cpu1.inst 13165937 # number of demand (read+write) accesses
1126system.cpu1.icache.demand_accesses::total 13165937 # number of demand (read+write) accesses
1127system.cpu1.icache.overall_accesses::cpu1.inst 13165937 # number of overall (read+write) accesses
1128system.cpu1.icache.overall_accesses::total 13165937 # number of overall (read+write) accesses
1129system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024055 # miss rate for ReadReq accesses
1130system.cpu1.icache.ReadReq_miss_rate::total 0.024055 # miss rate for ReadReq accesses
1131system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024055 # miss rate for demand accesses
1132system.cpu1.icache.demand_miss_rate::total 0.024055 # miss rate for demand accesses
1133system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024055 # miss rate for overall accesses
1134system.cpu1.icache.overall_miss_rate::total 0.024055 # miss rate for overall accesses
1135system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702 # average ReadReq miss latency
1136system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702 # average ReadReq miss latency
1137system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency
1138system.cpu1.icache.demand_avg_miss_latency::total 13428.370702 # average overall miss latency
1139system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency
1140system.cpu1.icache.overall_avg_miss_latency::total 13428.370702 # average overall miss latency
1141system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1142system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1143system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1144system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1145system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1146system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1147system.cpu1.icache.writebacks::writebacks 316153 # number of writebacks
1148system.cpu1.icache.writebacks::total 316153 # number of writebacks
1149system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316707 # number of ReadReq MSHR misses
1150system.cpu1.icache.ReadReq_mshr_misses::total 316707 # number of ReadReq MSHR misses
1151system.cpu1.icache.demand_mshr_misses::cpu1.inst 316707 # number of demand (read+write) MSHR misses
1152system.cpu1.icache.demand_mshr_misses::total 316707 # number of demand (read+write) MSHR misses
1153system.cpu1.icache.overall_mshr_misses::cpu1.inst 316707 # number of overall MSHR misses
1154system.cpu1.icache.overall_mshr_misses::total 316707 # number of overall MSHR misses
1155system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3936152000 # number of ReadReq MSHR miss cycles
1156system.cpu1.icache.ReadReq_mshr_miss_latency::total 3936152000 # number of ReadReq MSHR miss cycles
1157system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3936152000 # number of demand (read+write) MSHR miss cycles
1158system.cpu1.icache.demand_mshr_miss_latency::total 3936152000 # number of demand (read+write) MSHR miss cycles
1159system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3936152000 # number of overall MSHR miss cycles
1160system.cpu1.icache.overall_mshr_miss_latency::total 3936152000 # number of overall MSHR miss cycles
1161system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for ReadReq accesses
1162system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024055 # mshr miss rate for ReadReq accesses
1163system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for demand accesses
1164system.cpu1.icache.demand_mshr_miss_rate::total 0.024055 # mshr miss rate for demand accesses
1165system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for overall accesses
1166system.cpu1.icache.overall_mshr_miss_rate::total 0.024055 # mshr miss rate for overall accesses
1167system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average ReadReq mshr miss latency
1168system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702 # average ReadReq mshr miss latency
1169system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency
1170system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency
1171system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency
1172system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency
1173system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1174system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1175system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1176system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1177system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1178system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1179system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1180system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1181system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1182system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1183system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1184system.disk2.dma_write_txs 1 # Number of DMA write transactions.

1185system.iobus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1154system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
1155system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
1156system.iobus.trans_dist::WriteReq 55610 # Transaction distribution
1157system.iobus.trans_dist::WriteResp 55610 # Transaction distribution
1158system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes)
1159system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes)
1160system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1161system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1162system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1163system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1164system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
1165system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1166system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1167system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes)
1168system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
1169system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
1170system.iobus.pkt_count::total 125966 # Packet count per connected master and slave (bytes)
1171system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes)
1172system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes)
1173system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1174system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1175system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1176system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1177system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
1178system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1179system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1180system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes)
1181system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
1182system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
1183system.iobus.pkt_size::total 2743498 # Cumulative packet size per connected master and slave (bytes)
1184system.iobus.reqLayer0.occupancy 14957500 # Layer occupancy (ticks)
1185system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1186system.iobus.reqLayer1.occupancy 764000 # Layer occupancy (ticks)
1187system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1188system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
1189system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1190system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
1191system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1192system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks)
1193system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1194system.iobus.reqLayer23.occupancy 15839500 # Layer occupancy (ticks)
1195system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1196system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks)
1197system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1198system.iobus.reqLayer25.occupancy 6056000 # Layer occupancy (ticks)
1199system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1200system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
1201system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1202system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks)
1203system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1204system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks)
1205system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1206system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks)
1207system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)

1186system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
1187system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
1188system.iobus.trans_dist::WriteReq 55610 # Transaction distribution
1189system.iobus.trans_dist::WriteResp 55610 # Transaction distribution
1190system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes)
1191system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes)
1192system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1193system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1194system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1195system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1196system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
1197system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1198system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1199system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes)
1200system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
1201system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
1202system.iobus.pkt_count::total 125966 # Packet count per connected master and slave (bytes)
1203system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes)
1204system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes)
1205system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1206system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1207system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1208system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1209system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
1210system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1211system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1212system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes)
1213system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
1214system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
1215system.iobus.pkt_size::total 2743498 # Cumulative packet size per connected master and slave (bytes)
1216system.iobus.reqLayer0.occupancy 14957500 # Layer occupancy (ticks)
1217system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1218system.iobus.reqLayer1.occupancy 764000 # Layer occupancy (ticks)
1219system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1220system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks)
1221system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1222system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks)
1223system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1224system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks)
1225system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1226system.iobus.reqLayer23.occupancy 15839500 # Layer occupancy (ticks)
1227system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1228system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks)
1229system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1230system.iobus.reqLayer25.occupancy 6056000 # Layer occupancy (ticks)
1231system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1232system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks)
1233system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1234system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks)
1235system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1236system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks)
1237system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1238system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks)
1239system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)

1240system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1208system.iocache.tags.replacements 41694 # number of replacements
1209system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use
1210system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1211system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
1212system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1213system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit.
1214system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor
1215system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy
1216system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy
1217system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1218system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1219system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1220system.iocache.tags.tag_accesses 375534 # Number of tag accesses
1221system.iocache.tags.data_accesses 375534 # Number of data accesses

1241system.iocache.tags.replacements 41694 # number of replacements
1242system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use
1243system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1244system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
1245system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1246system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit.
1247system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor
1248system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy
1249system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy
1250system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1251system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1252system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1253system.iocache.tags.tag_accesses 375534 # Number of tag accesses
1254system.iocache.tags.data_accesses 375534 # Number of data accesses

1255system.iocache.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1222system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
1223system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
1224system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1225system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1226system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
1227system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
1228system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
1229system.iocache.overall_misses::total 41726 # number of overall misses
1230system.iocache.ReadReq_miss_latency::tsunami.ide 21854883 # number of ReadReq miss cycles
1231system.iocache.ReadReq_miss_latency::total 21854883 # number of ReadReq miss cycles
1232system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858321174 # number of WriteLineReq miss cycles
1233system.iocache.WriteLineReq_miss_latency::total 4858321174 # number of WriteLineReq miss cycles
1234system.iocache.demand_miss_latency::tsunami.ide 4880176057 # number of demand (read+write) miss cycles
1235system.iocache.demand_miss_latency::total 4880176057 # number of demand (read+write) miss cycles
1236system.iocache.overall_miss_latency::tsunami.ide 4880176057 # number of overall miss cycles
1237system.iocache.overall_miss_latency::total 4880176057 # number of overall miss cycles
1238system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
1239system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
1240system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1241system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1242system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
1243system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
1244system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
1245system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
1246system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1247system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1248system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1249system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1250system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1251system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1252system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1253system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1254system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862 # average ReadReq miss latency
1255system.iocache.ReadReq_avg_miss_latency::total 125602.775862 # average ReadReq miss latency
1256system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078 # average WriteLineReq miss latency
1257system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078 # average WriteLineReq miss latency
1258system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency
1259system.iocache.demand_avg_miss_latency::total 116957.677635 # average overall miss latency
1260system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency
1261system.iocache.overall_avg_miss_latency::total 116957.677635 # average overall miss latency
1262system.iocache.blocked_cycles::no_mshrs 1 # number of cycles access was blocked
1263system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1264system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked
1265system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1266system.iocache.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked
1267system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1268system.iocache.writebacks::writebacks 41520 # number of writebacks
1269system.iocache.writebacks::total 41520 # number of writebacks
1270system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
1271system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
1272system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1273system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1274system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
1275system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
1276system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
1277system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
1278system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13154883 # number of ReadReq MSHR miss cycles
1279system.iocache.ReadReq_mshr_miss_latency::total 13154883 # number of ReadReq MSHR miss cycles
1280system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778324656 # number of WriteLineReq MSHR miss cycles
1281system.iocache.WriteLineReq_mshr_miss_latency::total 2778324656 # number of WriteLineReq MSHR miss cycles
1282system.iocache.demand_mshr_miss_latency::tsunami.ide 2791479539 # number of demand (read+write) MSHR miss cycles
1283system.iocache.demand_mshr_miss_latency::total 2791479539 # number of demand (read+write) MSHR miss cycles
1284system.iocache.overall_mshr_miss_latency::tsunami.ide 2791479539 # number of overall MSHR miss cycles
1285system.iocache.overall_mshr_miss_latency::total 2791479539 # number of overall MSHR miss cycles
1286system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1287system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1288system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1289system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1290system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1291system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1292system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1293system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1294system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency
1295system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency
1296system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency
1297system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency
1298system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency
1299system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency
1300system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency
1301system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency

1256system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
1257system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
1258system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1259system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1260system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
1261system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
1262system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
1263system.iocache.overall_misses::total 41726 # number of overall misses
1264system.iocache.ReadReq_miss_latency::tsunami.ide 21854883 # number of ReadReq miss cycles
1265system.iocache.ReadReq_miss_latency::total 21854883 # number of ReadReq miss cycles
1266system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858321174 # number of WriteLineReq miss cycles
1267system.iocache.WriteLineReq_miss_latency::total 4858321174 # number of WriteLineReq miss cycles
1268system.iocache.demand_miss_latency::tsunami.ide 4880176057 # number of demand (read+write) miss cycles
1269system.iocache.demand_miss_latency::total 4880176057 # number of demand (read+write) miss cycles
1270system.iocache.overall_miss_latency::tsunami.ide 4880176057 # number of overall miss cycles
1271system.iocache.overall_miss_latency::total 4880176057 # number of overall miss cycles
1272system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
1273system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
1274system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1275system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1276system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
1277system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
1278system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
1279system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
1280system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1281system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1282system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1283system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1284system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1285system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1286system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1287system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1288system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862 # average ReadReq miss latency
1289system.iocache.ReadReq_avg_miss_latency::total 125602.775862 # average ReadReq miss latency
1290system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078 # average WriteLineReq miss latency
1291system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078 # average WriteLineReq miss latency
1292system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency
1293system.iocache.demand_avg_miss_latency::total 116957.677635 # average overall miss latency
1294system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency
1295system.iocache.overall_avg_miss_latency::total 116957.677635 # average overall miss latency
1296system.iocache.blocked_cycles::no_mshrs 1 # number of cycles access was blocked
1297system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1298system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked
1299system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1300system.iocache.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked
1301system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1302system.iocache.writebacks::writebacks 41520 # number of writebacks
1303system.iocache.writebacks::total 41520 # number of writebacks
1304system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
1305system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
1306system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1307system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1308system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
1309system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
1310system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
1311system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
1312system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13154883 # number of ReadReq MSHR miss cycles
1313system.iocache.ReadReq_mshr_miss_latency::total 13154883 # number of ReadReq MSHR miss cycles
1314system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778324656 # number of WriteLineReq MSHR miss cycles
1315system.iocache.WriteLineReq_mshr_miss_latency::total 2778324656 # number of WriteLineReq MSHR miss cycles
1316system.iocache.demand_mshr_miss_latency::tsunami.ide 2791479539 # number of demand (read+write) MSHR miss cycles
1317system.iocache.demand_mshr_miss_latency::total 2791479539 # number of demand (read+write) MSHR miss cycles
1318system.iocache.overall_mshr_miss_latency::tsunami.ide 2791479539 # number of overall MSHR miss cycles
1319system.iocache.overall_mshr_miss_latency::total 2791479539 # number of overall MSHR miss cycles
1320system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1321system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1322system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1323system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1324system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1325system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1326system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1327system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1328system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency
1329system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency
1330system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency
1331system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency
1332system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency
1333system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency
1334system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency
1335system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency

1336system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1302system.l2c.tags.replacements 341504 # number of replacements
1303system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use
1304system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks.
1305system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks.
1306system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks.
1307system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit.
1308system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor
1309system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor
1310system.l2c.tags.occ_blocks::cpu0.data 5040.815485 # Average occupied blocks per requestor
1311system.l2c.tags.occ_blocks::cpu1.inst 110.867276 # Average occupied blocks per requestor
1312system.l2c.tags.occ_blocks::cpu1.data 39.914491 # Average occupied blocks per requestor
1313system.l2c.tags.occ_percent::writebacks 0.841968 # Average percentage of cache occupancy
1314system.l2c.tags.occ_percent::cpu0.inst 0.073886 # Average percentage of cache occupancy
1315system.l2c.tags.occ_percent::cpu0.data 0.076917 # Average percentage of cache occupancy
1316system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy
1317system.l2c.tags.occ_percent::cpu1.data 0.000609 # Average percentage of cache occupancy
1318system.l2c.tags.occ_percent::total 0.995072 # Average percentage of cache occupancy
1319system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id
1320system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
1321system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id
1322system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id
1323system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id
1324system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id
1325system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id
1326system.l2c.tags.tag_accesses 35882279 # Number of tag accesses
1327system.l2c.tags.data_accesses 35882279 # Number of data accesses

1337system.l2c.tags.replacements 341504 # number of replacements
1338system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use
1339system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks.
1340system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks.
1341system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks.
1342system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit.
1343system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor
1344system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor
1345system.l2c.tags.occ_blocks::cpu0.data 5040.815485 # Average occupied blocks per requestor
1346system.l2c.tags.occ_blocks::cpu1.inst 110.867276 # Average occupied blocks per requestor
1347system.l2c.tags.occ_blocks::cpu1.data 39.914491 # Average occupied blocks per requestor
1348system.l2c.tags.occ_percent::writebacks 0.841968 # Average percentage of cache occupancy
1349system.l2c.tags.occ_percent::cpu0.inst 0.073886 # Average percentage of cache occupancy
1350system.l2c.tags.occ_percent::cpu0.data 0.076917 # Average percentage of cache occupancy
1351system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy
1352system.l2c.tags.occ_percent::cpu1.data 0.000609 # Average percentage of cache occupancy
1353system.l2c.tags.occ_percent::total 0.995072 # Average percentage of cache occupancy
1354system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id
1355system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
1356system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id
1357system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id
1358system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id
1359system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id
1360system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id
1361system.l2c.tags.tag_accesses 35882279 # Number of tag accesses
1362system.l2c.tags.data_accesses 35882279 # Number of data accesses

1363system.l2c.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1328system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits
1329system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits
1330system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits
1331system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits
1332system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits
1333system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits
1334system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits
1335system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits
1336system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
1337system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits
1338system.l2c.ReadExReq_hits::cpu0.data 126431 # number of ReadExReq hits
1339system.l2c.ReadExReq_hits::cpu1.data 47312 # number of ReadExReq hits
1340system.l2c.ReadExReq_hits::total 173743 # number of ReadExReq hits
1341system.l2c.ReadCleanReq_hits::cpu0.inst 685790 # number of ReadCleanReq hits
1342system.l2c.ReadCleanReq_hits::cpu1.inst 316251 # number of ReadCleanReq hits
1343system.l2c.ReadCleanReq_hits::total 1002041 # number of ReadCleanReq hits
1344system.l2c.ReadSharedReq_hits::cpu0.data 663459 # number of ReadSharedReq hits
1345system.l2c.ReadSharedReq_hits::cpu1.data 109055 # number of ReadSharedReq hits
1346system.l2c.ReadSharedReq_hits::total 772514 # number of ReadSharedReq hits
1347system.l2c.demand_hits::cpu0.inst 685790 # number of demand (read+write) hits
1348system.l2c.demand_hits::cpu0.data 789890 # number of demand (read+write) hits
1349system.l2c.demand_hits::cpu1.inst 316251 # number of demand (read+write) hits
1350system.l2c.demand_hits::cpu1.data 156367 # number of demand (read+write) hits
1351system.l2c.demand_hits::total 1948298 # number of demand (read+write) hits
1352system.l2c.overall_hits::cpu0.inst 685790 # number of overall hits
1353system.l2c.overall_hits::cpu0.data 789890 # number of overall hits
1354system.l2c.overall_hits::cpu1.inst 316251 # number of overall hits
1355system.l2c.overall_hits::cpu1.data 156367 # number of overall hits
1356system.l2c.overall_hits::total 1948298 # number of overall hits
1357system.l2c.UpgradeReq_misses::cpu0.data 2941 # number of UpgradeReq misses
1358system.l2c.UpgradeReq_misses::cpu1.data 1732 # number of UpgradeReq misses
1359system.l2c.UpgradeReq_misses::total 4673 # number of UpgradeReq misses
1360system.l2c.SCUpgradeReq_misses::cpu0.data 898 # number of SCUpgradeReq misses
1361system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses
1362system.l2c.SCUpgradeReq_misses::total 1795 # number of SCUpgradeReq misses
1363system.l2c.ReadExReq_misses::cpu0.data 115557 # number of ReadExReq misses
1364system.l2c.ReadExReq_misses::cpu1.data 6591 # number of ReadExReq misses
1365system.l2c.ReadExReq_misses::total 122148 # number of ReadExReq misses
1366system.l2c.ReadCleanReq_misses::cpu0.inst 12981 # number of ReadCleanReq misses
1367system.l2c.ReadCleanReq_misses::cpu1.inst 455 # number of ReadCleanReq misses
1368system.l2c.ReadCleanReq_misses::total 13436 # number of ReadCleanReq misses
1369system.l2c.ReadSharedReq_misses::cpu0.data 271641 # number of ReadSharedReq misses
1370system.l2c.ReadSharedReq_misses::cpu1.data 237 # number of ReadSharedReq misses
1371system.l2c.ReadSharedReq_misses::total 271878 # number of ReadSharedReq misses
1372system.l2c.demand_misses::cpu0.inst 12981 # number of demand (read+write) misses
1373system.l2c.demand_misses::cpu0.data 387198 # number of demand (read+write) misses
1374system.l2c.demand_misses::cpu1.inst 455 # number of demand (read+write) misses
1375system.l2c.demand_misses::cpu1.data 6828 # number of demand (read+write) misses
1376system.l2c.demand_misses::total 407462 # number of demand (read+write) misses
1377system.l2c.overall_misses::cpu0.inst 12981 # number of overall misses
1378system.l2c.overall_misses::cpu0.data 387198 # number of overall misses
1379system.l2c.overall_misses::cpu1.inst 455 # number of overall misses
1380system.l2c.overall_misses::cpu1.data 6828 # number of overall misses
1381system.l2c.overall_misses::total 407462 # number of overall misses
1382system.l2c.UpgradeReq_miss_latency::cpu0.data 1599000 # number of UpgradeReq miss cycles
1383system.l2c.UpgradeReq_miss_latency::cpu1.data 12643000 # number of UpgradeReq miss cycles
1384system.l2c.UpgradeReq_miss_latency::total 14242000 # number of UpgradeReq miss cycles
1385system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1259500 # number of SCUpgradeReq miss cycles
1386system.l2c.SCUpgradeReq_miss_latency::cpu1.data 178000 # number of SCUpgradeReq miss cycles
1387system.l2c.SCUpgradeReq_miss_latency::total 1437500 # number of SCUpgradeReq miss cycles
1388system.l2c.ReadExReq_miss_latency::cpu0.data 8901595500 # number of ReadExReq miss cycles
1389system.l2c.ReadExReq_miss_latency::cpu1.data 544185500 # number of ReadExReq miss cycles
1390system.l2c.ReadExReq_miss_latency::total 9445781000 # number of ReadExReq miss cycles
1391system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1065078500 # number of ReadCleanReq miss cycles
1392system.l2c.ReadCleanReq_miss_latency::cpu1.inst 37559000 # number of ReadCleanReq miss cycles
1393system.l2c.ReadCleanReq_miss_latency::total 1102637500 # number of ReadCleanReq miss cycles
1394system.l2c.ReadSharedReq_miss_latency::cpu0.data 19890941000 # number of ReadSharedReq miss cycles
1395system.l2c.ReadSharedReq_miss_latency::cpu1.data 19543500 # number of ReadSharedReq miss cycles
1396system.l2c.ReadSharedReq_miss_latency::total 19910484500 # number of ReadSharedReq miss cycles
1397system.l2c.demand_miss_latency::cpu0.inst 1065078500 # number of demand (read+write) miss cycles
1398system.l2c.demand_miss_latency::cpu0.data 28792536500 # number of demand (read+write) miss cycles
1399system.l2c.demand_miss_latency::cpu1.inst 37559000 # number of demand (read+write) miss cycles
1400system.l2c.demand_miss_latency::cpu1.data 563729000 # number of demand (read+write) miss cycles
1401system.l2c.demand_miss_latency::total 30458903000 # number of demand (read+write) miss cycles
1402system.l2c.overall_miss_latency::cpu0.inst 1065078500 # number of overall miss cycles
1403system.l2c.overall_miss_latency::cpu0.data 28792536500 # number of overall miss cycles
1404system.l2c.overall_miss_latency::cpu1.inst 37559000 # number of overall miss cycles
1405system.l2c.overall_miss_latency::cpu1.data 563729000 # number of overall miss cycles
1406system.l2c.overall_miss_latency::total 30458903000 # number of overall miss cycles
1407system.l2c.WritebackDirty_accesses::writebacks 792706 # number of WritebackDirty accesses(hits+misses)
1408system.l2c.WritebackDirty_accesses::total 792706 # number of WritebackDirty accesses(hits+misses)
1409system.l2c.WritebackClean_accesses::writebacks 747201 # number of WritebackClean accesses(hits+misses)
1410system.l2c.WritebackClean_accesses::total 747201 # number of WritebackClean accesses(hits+misses)
1411system.l2c.UpgradeReq_accesses::cpu0.data 3116 # number of UpgradeReq accesses(hits+misses)
1412system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses)
1413system.l2c.UpgradeReq_accesses::total 5382 # number of UpgradeReq accesses(hits+misses)
1414system.l2c.SCUpgradeReq_accesses::cpu0.data 931 # number of SCUpgradeReq accesses(hits+misses)
1415system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses)
1416system.l2c.SCUpgradeReq_accesses::total 1852 # number of SCUpgradeReq accesses(hits+misses)
1417system.l2c.ReadExReq_accesses::cpu0.data 241988 # number of ReadExReq accesses(hits+misses)
1418system.l2c.ReadExReq_accesses::cpu1.data 53903 # number of ReadExReq accesses(hits+misses)
1419system.l2c.ReadExReq_accesses::total 295891 # number of ReadExReq accesses(hits+misses)
1420system.l2c.ReadCleanReq_accesses::cpu0.inst 698771 # number of ReadCleanReq accesses(hits+misses)
1421system.l2c.ReadCleanReq_accesses::cpu1.inst 316706 # number of ReadCleanReq accesses(hits+misses)
1422system.l2c.ReadCleanReq_accesses::total 1015477 # number of ReadCleanReq accesses(hits+misses)
1423system.l2c.ReadSharedReq_accesses::cpu0.data 935100 # number of ReadSharedReq accesses(hits+misses)
1424system.l2c.ReadSharedReq_accesses::cpu1.data 109292 # number of ReadSharedReq accesses(hits+misses)
1425system.l2c.ReadSharedReq_accesses::total 1044392 # number of ReadSharedReq accesses(hits+misses)
1426system.l2c.demand_accesses::cpu0.inst 698771 # number of demand (read+write) accesses
1427system.l2c.demand_accesses::cpu0.data 1177088 # number of demand (read+write) accesses
1428system.l2c.demand_accesses::cpu1.inst 316706 # number of demand (read+write) accesses
1429system.l2c.demand_accesses::cpu1.data 163195 # number of demand (read+write) accesses
1430system.l2c.demand_accesses::total 2355760 # number of demand (read+write) accesses
1431system.l2c.overall_accesses::cpu0.inst 698771 # number of overall (read+write) accesses
1432system.l2c.overall_accesses::cpu0.data 1177088 # number of overall (read+write) accesses
1433system.l2c.overall_accesses::cpu1.inst 316706 # number of overall (read+write) accesses
1434system.l2c.overall_accesses::cpu1.data 163195 # number of overall (read+write) accesses
1435system.l2c.overall_accesses::total 2355760 # number of overall (read+write) accesses
1436system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943838 # miss rate for UpgradeReq accesses
1437system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764342 # miss rate for UpgradeReq accesses
1438system.l2c.UpgradeReq_miss_rate::total 0.868265 # miss rate for UpgradeReq accesses
1439system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.964554 # miss rate for SCUpgradeReq accesses
1440system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses
1441system.l2c.SCUpgradeReq_miss_rate::total 0.969222 # miss rate for SCUpgradeReq accesses
1442system.l2c.ReadExReq_miss_rate::cpu0.data 0.477532 # miss rate for ReadExReq accesses
1443system.l2c.ReadExReq_miss_rate::cpu1.data 0.122275 # miss rate for ReadExReq accesses
1444system.l2c.ReadExReq_miss_rate::total 0.412814 # miss rate for ReadExReq accesses
1445system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018577 # miss rate for ReadCleanReq accesses
1446system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001437 # miss rate for ReadCleanReq accesses
1447system.l2c.ReadCleanReq_miss_rate::total 0.013231 # miss rate for ReadCleanReq accesses
1448system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290494 # miss rate for ReadSharedReq accesses
1449system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002169 # miss rate for ReadSharedReq accesses
1450system.l2c.ReadSharedReq_miss_rate::total 0.260322 # miss rate for ReadSharedReq accesses
1451system.l2c.demand_miss_rate::cpu0.inst 0.018577 # miss rate for demand accesses
1452system.l2c.demand_miss_rate::cpu0.data 0.328946 # miss rate for demand accesses
1453system.l2c.demand_miss_rate::cpu1.inst 0.001437 # miss rate for demand accesses
1454system.l2c.demand_miss_rate::cpu1.data 0.041840 # miss rate for demand accesses
1455system.l2c.demand_miss_rate::total 0.172964 # miss rate for demand accesses
1456system.l2c.overall_miss_rate::cpu0.inst 0.018577 # miss rate for overall accesses
1457system.l2c.overall_miss_rate::cpu0.data 0.328946 # miss rate for overall accesses
1458system.l2c.overall_miss_rate::cpu1.inst 0.001437 # miss rate for overall accesses
1459system.l2c.overall_miss_rate::cpu1.data 0.041840 # miss rate for overall accesses
1460system.l2c.overall_miss_rate::total 0.172964 # miss rate for overall accesses
1461system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 543.692622 # average UpgradeReq miss latency
1462system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7299.653580 # average UpgradeReq miss latency
1463system.l2c.UpgradeReq_avg_miss_latency::total 3047.720950 # average UpgradeReq miss latency
1464system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1402.561247 # average SCUpgradeReq miss latency
1465system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 198.439242 # average SCUpgradeReq miss latency
1466system.l2c.SCUpgradeReq_avg_miss_latency::total 800.835655 # average SCUpgradeReq miss latency
1467system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77032.075080 # average ReadExReq miss latency
1468system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82564.937035 # average ReadExReq miss latency
1469system.l2c.ReadExReq_avg_miss_latency::total 77330.623506 # average ReadExReq miss latency
1470system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82049.033202 # average ReadCleanReq miss latency
1471system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82547.252747 # average ReadCleanReq miss latency
1472system.l2c.ReadCleanReq_avg_miss_latency::total 82065.905031 # average ReadCleanReq miss latency
1473system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73225.105930 # average ReadSharedReq miss latency
1474system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82462.025316 # average ReadSharedReq miss latency
1475system.l2c.ReadSharedReq_avg_miss_latency::total 73233.157887 # average ReadSharedReq miss latency
1476system.l2c.demand_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency
1477system.l2c.demand_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency
1478system.l2c.demand_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency
1479system.l2c.demand_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency
1480system.l2c.demand_avg_miss_latency::total 74752.745041 # average overall miss latency
1481system.l2c.overall_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency
1482system.l2c.overall_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency
1483system.l2c.overall_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency
1484system.l2c.overall_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency
1485system.l2c.overall_avg_miss_latency::total 74752.745041 # average overall miss latency
1486system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1487system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1488system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1489system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1490system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1491system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1492system.l2c.writebacks::writebacks 78937 # number of writebacks
1493system.l2c.writebacks::total 78937 # number of writebacks
1494system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
1495system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1496system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
1497system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
1498system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
1499system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
1500system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
1501system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
1502system.l2c.UpgradeReq_mshr_misses::cpu0.data 2941 # number of UpgradeReq MSHR misses
1503system.l2c.UpgradeReq_mshr_misses::cpu1.data 1732 # number of UpgradeReq MSHR misses
1504system.l2c.UpgradeReq_mshr_misses::total 4673 # number of UpgradeReq MSHR misses
1505system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 898 # number of SCUpgradeReq MSHR misses
1506system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses
1507system.l2c.SCUpgradeReq_mshr_misses::total 1795 # number of SCUpgradeReq MSHR misses
1508system.l2c.ReadExReq_mshr_misses::cpu0.data 115557 # number of ReadExReq MSHR misses
1509system.l2c.ReadExReq_mshr_misses::cpu1.data 6591 # number of ReadExReq MSHR misses
1510system.l2c.ReadExReq_mshr_misses::total 122148 # number of ReadExReq MSHR misses
1511system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12981 # number of ReadCleanReq MSHR misses
1512system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 444 # number of ReadCleanReq MSHR misses
1513system.l2c.ReadCleanReq_mshr_misses::total 13425 # number of ReadCleanReq MSHR misses
1514system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271641 # number of ReadSharedReq MSHR misses
1515system.l2c.ReadSharedReq_mshr_misses::cpu1.data 237 # number of ReadSharedReq MSHR misses
1516system.l2c.ReadSharedReq_mshr_misses::total 271878 # number of ReadSharedReq MSHR misses
1517system.l2c.demand_mshr_misses::cpu0.inst 12981 # number of demand (read+write) MSHR misses
1518system.l2c.demand_mshr_misses::cpu0.data 387198 # number of demand (read+write) MSHR misses
1519system.l2c.demand_mshr_misses::cpu1.inst 444 # number of demand (read+write) MSHR misses
1520system.l2c.demand_mshr_misses::cpu1.data 6828 # number of demand (read+write) MSHR misses
1521system.l2c.demand_mshr_misses::total 407451 # number of demand (read+write) MSHR misses
1522system.l2c.overall_mshr_misses::cpu0.inst 12981 # number of overall MSHR misses
1523system.l2c.overall_mshr_misses::cpu0.data 387198 # number of overall MSHR misses
1524system.l2c.overall_mshr_misses::cpu1.inst 444 # number of overall MSHR misses
1525system.l2c.overall_mshr_misses::cpu1.data 6828 # number of overall MSHR misses
1526system.l2c.overall_mshr_misses::total 407451 # number of overall MSHR misses
1527system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
1528system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
1529system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable
1530system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable
1531system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable
1532system.l2c.WriteReq_mshr_uncacheable::total 14058 # number of WriteReq MSHR uncacheable
1533system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses
1534system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses
1535system.l2c.overall_mshr_uncacheable_misses::total 21257 # number of overall MSHR uncacheable misses
1536system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 58492500 # number of UpgradeReq MSHR miss cycles
1537system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34311000 # number of UpgradeReq MSHR miss cycles
1538system.l2c.UpgradeReq_mshr_miss_latency::total 92803500 # number of UpgradeReq MSHR miss cycles
1539system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17536000 # number of SCUpgradeReq MSHR miss cycles
1540system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 17907500 # number of SCUpgradeReq MSHR miss cycles
1541system.l2c.SCUpgradeReq_mshr_miss_latency::total 35443500 # number of SCUpgradeReq MSHR miss cycles
1542system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7746025500 # number of ReadExReq MSHR miss cycles
1543system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 478275500 # number of ReadExReq MSHR miss cycles
1544system.l2c.ReadExReq_mshr_miss_latency::total 8224301000 # number of ReadExReq MSHR miss cycles
1545system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 935268500 # number of ReadCleanReq MSHR miss cycles
1546system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 32302501 # number of ReadCleanReq MSHR miss cycles
1547system.l2c.ReadCleanReq_mshr_miss_latency::total 967571001 # number of ReadCleanReq MSHR miss cycles
1548system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17174531000 # number of ReadSharedReq MSHR miss cycles
1549system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 17173500 # number of ReadSharedReq MSHR miss cycles
1550system.l2c.ReadSharedReq_mshr_miss_latency::total 17191704500 # number of ReadSharedReq MSHR miss cycles
1551system.l2c.demand_mshr_miss_latency::cpu0.inst 935268500 # number of demand (read+write) MSHR miss cycles
1552system.l2c.demand_mshr_miss_latency::cpu0.data 24920556500 # number of demand (read+write) MSHR miss cycles
1553system.l2c.demand_mshr_miss_latency::cpu1.inst 32302501 # number of demand (read+write) MSHR miss cycles
1554system.l2c.demand_mshr_miss_latency::cpu1.data 495449000 # number of demand (read+write) MSHR miss cycles
1555system.l2c.demand_mshr_miss_latency::total 26383576501 # number of demand (read+write) MSHR miss cycles
1556system.l2c.overall_mshr_miss_latency::cpu0.inst 935268500 # number of overall MSHR miss cycles
1557system.l2c.overall_mshr_miss_latency::cpu0.data 24920556500 # number of overall MSHR miss cycles
1558system.l2c.overall_mshr_miss_latency::cpu1.inst 32302501 # number of overall MSHR miss cycles
1559system.l2c.overall_mshr_miss_latency::cpu1.data 495449000 # number of overall MSHR miss cycles
1560system.l2c.overall_mshr_miss_latency::total 26383576501 # number of overall MSHR miss cycles
1561system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1489559500 # number of ReadReq MSHR uncacheable cycles
1562system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19061000 # number of ReadReq MSHR uncacheable cycles
1563system.l2c.ReadReq_mshr_uncacheable_latency::total 1508620500 # number of ReadReq MSHR uncacheable cycles
1564system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1489559500 # number of overall MSHR uncacheable cycles
1565system.l2c.overall_mshr_uncacheable_latency::cpu1.data 19061000 # number of overall MSHR uncacheable cycles
1566system.l2c.overall_mshr_uncacheable_latency::total 1508620500 # number of overall MSHR uncacheable cycles
1567system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1568system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1569system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943838 # mshr miss rate for UpgradeReq accesses
1570system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764342 # mshr miss rate for UpgradeReq accesses
1571system.l2c.UpgradeReq_mshr_miss_rate::total 0.868265 # mshr miss rate for UpgradeReq accesses
1572system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.964554 # mshr miss rate for SCUpgradeReq accesses
1573system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses
1574system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969222 # mshr miss rate for SCUpgradeReq accesses
1575system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477532 # mshr miss rate for ReadExReq accesses
1576system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122275 # mshr miss rate for ReadExReq accesses
1577system.l2c.ReadExReq_mshr_miss_rate::total 0.412814 # mshr miss rate for ReadExReq accesses
1578system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for ReadCleanReq accesses
1579system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for ReadCleanReq accesses
1580system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013220 # mshr miss rate for ReadCleanReq accesses
1581system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290494 # mshr miss rate for ReadSharedReq accesses
1582system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002169 # mshr miss rate for ReadSharedReq accesses
1583system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260322 # mshr miss rate for ReadSharedReq accesses
1584system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for demand accesses
1585system.l2c.demand_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for demand accesses
1586system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for demand accesses
1587system.l2c.demand_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for demand accesses
1588system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses
1589system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for overall accesses
1590system.l2c.overall_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for overall accesses
1591system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for overall accesses
1592system.l2c.overall_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for overall accesses
1593system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses
1594system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19888.643319 # average UpgradeReq mshr miss latency
1595system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19810.046189 # average UpgradeReq mshr miss latency
1596system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19859.512091 # average UpgradeReq mshr miss latency
1597system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19527.839644 # average SCUpgradeReq mshr miss latency
1598system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19963.768116 # average SCUpgradeReq mshr miss latency
1599system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19745.682451 # average SCUpgradeReq mshr miss latency
1600system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67032.075080 # average ReadExReq mshr miss latency
1601system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72564.937035 # average ReadExReq mshr miss latency
1602system.l2c.ReadExReq_avg_mshr_miss_latency::total 67330.623506 # average ReadExReq mshr miss latency
1603system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average ReadCleanReq mshr miss latency
1604system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average ReadCleanReq mshr miss latency
1605system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821 # average ReadCleanReq mshr miss latency
1606system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930 # average ReadSharedReq mshr miss latency
1607system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316 # average ReadSharedReq mshr miss latency
1608system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887 # average ReadSharedReq mshr miss latency
1609system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency
1610system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency
1611system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency
1612system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency
1613system.l2c.demand_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency
1614system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency
1615system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency
1616system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency
1617system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency
1618system.l2c.overall_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency
1619system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381 # average ReadReq mshr uncacheable latency
1620system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency
1621system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518 # average ReadReq mshr uncacheable latency
1622system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636 # average overall mshr uncacheable latency
1623system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency
1624system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency
1625system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter.
1626system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1627system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1628system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1629system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1630system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1364system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits
1365system.l2c.WritebackDirty_hits::total 792706 # number of WritebackDirty hits
1366system.l2c.WritebackClean_hits::writebacks 747201 # number of WritebackClean hits
1367system.l2c.WritebackClean_hits::total 747201 # number of WritebackClean hits
1368system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits
1369system.l2c.UpgradeReq_hits::cpu1.data 534 # number of UpgradeReq hits
1370system.l2c.UpgradeReq_hits::total 709 # number of UpgradeReq hits
1371system.l2c.SCUpgradeReq_hits::cpu0.data 33 # number of SCUpgradeReq hits
1372system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
1373system.l2c.SCUpgradeReq_hits::total 57 # number of SCUpgradeReq hits
1374system.l2c.ReadExReq_hits::cpu0.data 126431 # number of ReadExReq hits
1375system.l2c.ReadExReq_hits::cpu1.data 47312 # number of ReadExReq hits
1376system.l2c.ReadExReq_hits::total 173743 # number of ReadExReq hits
1377system.l2c.ReadCleanReq_hits::cpu0.inst 685790 # number of ReadCleanReq hits
1378system.l2c.ReadCleanReq_hits::cpu1.inst 316251 # number of ReadCleanReq hits
1379system.l2c.ReadCleanReq_hits::total 1002041 # number of ReadCleanReq hits
1380system.l2c.ReadSharedReq_hits::cpu0.data 663459 # number of ReadSharedReq hits
1381system.l2c.ReadSharedReq_hits::cpu1.data 109055 # number of ReadSharedReq hits
1382system.l2c.ReadSharedReq_hits::total 772514 # number of ReadSharedReq hits
1383system.l2c.demand_hits::cpu0.inst 685790 # number of demand (read+write) hits
1384system.l2c.demand_hits::cpu0.data 789890 # number of demand (read+write) hits
1385system.l2c.demand_hits::cpu1.inst 316251 # number of demand (read+write) hits
1386system.l2c.demand_hits::cpu1.data 156367 # number of demand (read+write) hits
1387system.l2c.demand_hits::total 1948298 # number of demand (read+write) hits
1388system.l2c.overall_hits::cpu0.inst 685790 # number of overall hits
1389system.l2c.overall_hits::cpu0.data 789890 # number of overall hits
1390system.l2c.overall_hits::cpu1.inst 316251 # number of overall hits
1391system.l2c.overall_hits::cpu1.data 156367 # number of overall hits
1392system.l2c.overall_hits::total 1948298 # number of overall hits
1393system.l2c.UpgradeReq_misses::cpu0.data 2941 # number of UpgradeReq misses
1394system.l2c.UpgradeReq_misses::cpu1.data 1732 # number of UpgradeReq misses
1395system.l2c.UpgradeReq_misses::total 4673 # number of UpgradeReq misses
1396system.l2c.SCUpgradeReq_misses::cpu0.data 898 # number of SCUpgradeReq misses
1397system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses
1398system.l2c.SCUpgradeReq_misses::total 1795 # number of SCUpgradeReq misses
1399system.l2c.ReadExReq_misses::cpu0.data 115557 # number of ReadExReq misses
1400system.l2c.ReadExReq_misses::cpu1.data 6591 # number of ReadExReq misses
1401system.l2c.ReadExReq_misses::total 122148 # number of ReadExReq misses
1402system.l2c.ReadCleanReq_misses::cpu0.inst 12981 # number of ReadCleanReq misses
1403system.l2c.ReadCleanReq_misses::cpu1.inst 455 # number of ReadCleanReq misses
1404system.l2c.ReadCleanReq_misses::total 13436 # number of ReadCleanReq misses
1405system.l2c.ReadSharedReq_misses::cpu0.data 271641 # number of ReadSharedReq misses
1406system.l2c.ReadSharedReq_misses::cpu1.data 237 # number of ReadSharedReq misses
1407system.l2c.ReadSharedReq_misses::total 271878 # number of ReadSharedReq misses
1408system.l2c.demand_misses::cpu0.inst 12981 # number of demand (read+write) misses
1409system.l2c.demand_misses::cpu0.data 387198 # number of demand (read+write) misses
1410system.l2c.demand_misses::cpu1.inst 455 # number of demand (read+write) misses
1411system.l2c.demand_misses::cpu1.data 6828 # number of demand (read+write) misses
1412system.l2c.demand_misses::total 407462 # number of demand (read+write) misses
1413system.l2c.overall_misses::cpu0.inst 12981 # number of overall misses
1414system.l2c.overall_misses::cpu0.data 387198 # number of overall misses
1415system.l2c.overall_misses::cpu1.inst 455 # number of overall misses
1416system.l2c.overall_misses::cpu1.data 6828 # number of overall misses
1417system.l2c.overall_misses::total 407462 # number of overall misses
1418system.l2c.UpgradeReq_miss_latency::cpu0.data 1599000 # number of UpgradeReq miss cycles
1419system.l2c.UpgradeReq_miss_latency::cpu1.data 12643000 # number of UpgradeReq miss cycles
1420system.l2c.UpgradeReq_miss_latency::total 14242000 # number of UpgradeReq miss cycles
1421system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1259500 # number of SCUpgradeReq miss cycles
1422system.l2c.SCUpgradeReq_miss_latency::cpu1.data 178000 # number of SCUpgradeReq miss cycles
1423system.l2c.SCUpgradeReq_miss_latency::total 1437500 # number of SCUpgradeReq miss cycles
1424system.l2c.ReadExReq_miss_latency::cpu0.data 8901595500 # number of ReadExReq miss cycles
1425system.l2c.ReadExReq_miss_latency::cpu1.data 544185500 # number of ReadExReq miss cycles
1426system.l2c.ReadExReq_miss_latency::total 9445781000 # number of ReadExReq miss cycles
1427system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1065078500 # number of ReadCleanReq miss cycles
1428system.l2c.ReadCleanReq_miss_latency::cpu1.inst 37559000 # number of ReadCleanReq miss cycles
1429system.l2c.ReadCleanReq_miss_latency::total 1102637500 # number of ReadCleanReq miss cycles
1430system.l2c.ReadSharedReq_miss_latency::cpu0.data 19890941000 # number of ReadSharedReq miss cycles
1431system.l2c.ReadSharedReq_miss_latency::cpu1.data 19543500 # number of ReadSharedReq miss cycles
1432system.l2c.ReadSharedReq_miss_latency::total 19910484500 # number of ReadSharedReq miss cycles
1433system.l2c.demand_miss_latency::cpu0.inst 1065078500 # number of demand (read+write) miss cycles
1434system.l2c.demand_miss_latency::cpu0.data 28792536500 # number of demand (read+write) miss cycles
1435system.l2c.demand_miss_latency::cpu1.inst 37559000 # number of demand (read+write) miss cycles
1436system.l2c.demand_miss_latency::cpu1.data 563729000 # number of demand (read+write) miss cycles
1437system.l2c.demand_miss_latency::total 30458903000 # number of demand (read+write) miss cycles
1438system.l2c.overall_miss_latency::cpu0.inst 1065078500 # number of overall miss cycles
1439system.l2c.overall_miss_latency::cpu0.data 28792536500 # number of overall miss cycles
1440system.l2c.overall_miss_latency::cpu1.inst 37559000 # number of overall miss cycles
1441system.l2c.overall_miss_latency::cpu1.data 563729000 # number of overall miss cycles
1442system.l2c.overall_miss_latency::total 30458903000 # number of overall miss cycles
1443system.l2c.WritebackDirty_accesses::writebacks 792706 # number of WritebackDirty accesses(hits+misses)
1444system.l2c.WritebackDirty_accesses::total 792706 # number of WritebackDirty accesses(hits+misses)
1445system.l2c.WritebackClean_accesses::writebacks 747201 # number of WritebackClean accesses(hits+misses)
1446system.l2c.WritebackClean_accesses::total 747201 # number of WritebackClean accesses(hits+misses)
1447system.l2c.UpgradeReq_accesses::cpu0.data 3116 # number of UpgradeReq accesses(hits+misses)
1448system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses)
1449system.l2c.UpgradeReq_accesses::total 5382 # number of UpgradeReq accesses(hits+misses)
1450system.l2c.SCUpgradeReq_accesses::cpu0.data 931 # number of SCUpgradeReq accesses(hits+misses)
1451system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses)
1452system.l2c.SCUpgradeReq_accesses::total 1852 # number of SCUpgradeReq accesses(hits+misses)
1453system.l2c.ReadExReq_accesses::cpu0.data 241988 # number of ReadExReq accesses(hits+misses)
1454system.l2c.ReadExReq_accesses::cpu1.data 53903 # number of ReadExReq accesses(hits+misses)
1455system.l2c.ReadExReq_accesses::total 295891 # number of ReadExReq accesses(hits+misses)
1456system.l2c.ReadCleanReq_accesses::cpu0.inst 698771 # number of ReadCleanReq accesses(hits+misses)
1457system.l2c.ReadCleanReq_accesses::cpu1.inst 316706 # number of ReadCleanReq accesses(hits+misses)
1458system.l2c.ReadCleanReq_accesses::total 1015477 # number of ReadCleanReq accesses(hits+misses)
1459system.l2c.ReadSharedReq_accesses::cpu0.data 935100 # number of ReadSharedReq accesses(hits+misses)
1460system.l2c.ReadSharedReq_accesses::cpu1.data 109292 # number of ReadSharedReq accesses(hits+misses)
1461system.l2c.ReadSharedReq_accesses::total 1044392 # number of ReadSharedReq accesses(hits+misses)
1462system.l2c.demand_accesses::cpu0.inst 698771 # number of demand (read+write) accesses
1463system.l2c.demand_accesses::cpu0.data 1177088 # number of demand (read+write) accesses
1464system.l2c.demand_accesses::cpu1.inst 316706 # number of demand (read+write) accesses
1465system.l2c.demand_accesses::cpu1.data 163195 # number of demand (read+write) accesses
1466system.l2c.demand_accesses::total 2355760 # number of demand (read+write) accesses
1467system.l2c.overall_accesses::cpu0.inst 698771 # number of overall (read+write) accesses
1468system.l2c.overall_accesses::cpu0.data 1177088 # number of overall (read+write) accesses
1469system.l2c.overall_accesses::cpu1.inst 316706 # number of overall (read+write) accesses
1470system.l2c.overall_accesses::cpu1.data 163195 # number of overall (read+write) accesses
1471system.l2c.overall_accesses::total 2355760 # number of overall (read+write) accesses
1472system.l2c.UpgradeReq_miss_rate::cpu0.data 0.943838 # miss rate for UpgradeReq accesses
1473system.l2c.UpgradeReq_miss_rate::cpu1.data 0.764342 # miss rate for UpgradeReq accesses
1474system.l2c.UpgradeReq_miss_rate::total 0.868265 # miss rate for UpgradeReq accesses
1475system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.964554 # miss rate for SCUpgradeReq accesses
1476system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses
1477system.l2c.SCUpgradeReq_miss_rate::total 0.969222 # miss rate for SCUpgradeReq accesses
1478system.l2c.ReadExReq_miss_rate::cpu0.data 0.477532 # miss rate for ReadExReq accesses
1479system.l2c.ReadExReq_miss_rate::cpu1.data 0.122275 # miss rate for ReadExReq accesses
1480system.l2c.ReadExReq_miss_rate::total 0.412814 # miss rate for ReadExReq accesses
1481system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018577 # miss rate for ReadCleanReq accesses
1482system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.001437 # miss rate for ReadCleanReq accesses
1483system.l2c.ReadCleanReq_miss_rate::total 0.013231 # miss rate for ReadCleanReq accesses
1484system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.290494 # miss rate for ReadSharedReq accesses
1485system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002169 # miss rate for ReadSharedReq accesses
1486system.l2c.ReadSharedReq_miss_rate::total 0.260322 # miss rate for ReadSharedReq accesses
1487system.l2c.demand_miss_rate::cpu0.inst 0.018577 # miss rate for demand accesses
1488system.l2c.demand_miss_rate::cpu0.data 0.328946 # miss rate for demand accesses
1489system.l2c.demand_miss_rate::cpu1.inst 0.001437 # miss rate for demand accesses
1490system.l2c.demand_miss_rate::cpu1.data 0.041840 # miss rate for demand accesses
1491system.l2c.demand_miss_rate::total 0.172964 # miss rate for demand accesses
1492system.l2c.overall_miss_rate::cpu0.inst 0.018577 # miss rate for overall accesses
1493system.l2c.overall_miss_rate::cpu0.data 0.328946 # miss rate for overall accesses
1494system.l2c.overall_miss_rate::cpu1.inst 0.001437 # miss rate for overall accesses
1495system.l2c.overall_miss_rate::cpu1.data 0.041840 # miss rate for overall accesses
1496system.l2c.overall_miss_rate::total 0.172964 # miss rate for overall accesses
1497system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 543.692622 # average UpgradeReq miss latency
1498system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7299.653580 # average UpgradeReq miss latency
1499system.l2c.UpgradeReq_avg_miss_latency::total 3047.720950 # average UpgradeReq miss latency
1500system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1402.561247 # average SCUpgradeReq miss latency
1501system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 198.439242 # average SCUpgradeReq miss latency
1502system.l2c.SCUpgradeReq_avg_miss_latency::total 800.835655 # average SCUpgradeReq miss latency
1503system.l2c.ReadExReq_avg_miss_latency::cpu0.data 77032.075080 # average ReadExReq miss latency
1504system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82564.937035 # average ReadExReq miss latency
1505system.l2c.ReadExReq_avg_miss_latency::total 77330.623506 # average ReadExReq miss latency
1506system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 82049.033202 # average ReadCleanReq miss latency
1507system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 82547.252747 # average ReadCleanReq miss latency
1508system.l2c.ReadCleanReq_avg_miss_latency::total 82065.905031 # average ReadCleanReq miss latency
1509system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73225.105930 # average ReadSharedReq miss latency
1510system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82462.025316 # average ReadSharedReq miss latency
1511system.l2c.ReadSharedReq_avg_miss_latency::total 73233.157887 # average ReadSharedReq miss latency
1512system.l2c.demand_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency
1513system.l2c.demand_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency
1514system.l2c.demand_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency
1515system.l2c.demand_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency
1516system.l2c.demand_avg_miss_latency::total 74752.745041 # average overall miss latency
1517system.l2c.overall_avg_miss_latency::cpu0.inst 82049.033202 # average overall miss latency
1518system.l2c.overall_avg_miss_latency::cpu0.data 74361.273819 # average overall miss latency
1519system.l2c.overall_avg_miss_latency::cpu1.inst 82547.252747 # average overall miss latency
1520system.l2c.overall_avg_miss_latency::cpu1.data 82561.364968 # average overall miss latency
1521system.l2c.overall_avg_miss_latency::total 74752.745041 # average overall miss latency
1522system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1523system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1524system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1525system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1526system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1527system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1528system.l2c.writebacks::writebacks 78937 # number of writebacks
1529system.l2c.writebacks::total 78937 # number of writebacks
1530system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
1531system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1532system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
1533system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
1534system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
1535system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
1536system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
1537system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
1538system.l2c.UpgradeReq_mshr_misses::cpu0.data 2941 # number of UpgradeReq MSHR misses
1539system.l2c.UpgradeReq_mshr_misses::cpu1.data 1732 # number of UpgradeReq MSHR misses
1540system.l2c.UpgradeReq_mshr_misses::total 4673 # number of UpgradeReq MSHR misses
1541system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 898 # number of SCUpgradeReq MSHR misses
1542system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses
1543system.l2c.SCUpgradeReq_mshr_misses::total 1795 # number of SCUpgradeReq MSHR misses
1544system.l2c.ReadExReq_mshr_misses::cpu0.data 115557 # number of ReadExReq MSHR misses
1545system.l2c.ReadExReq_mshr_misses::cpu1.data 6591 # number of ReadExReq MSHR misses
1546system.l2c.ReadExReq_mshr_misses::total 122148 # number of ReadExReq MSHR misses
1547system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12981 # number of ReadCleanReq MSHR misses
1548system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 444 # number of ReadCleanReq MSHR misses
1549system.l2c.ReadCleanReq_mshr_misses::total 13425 # number of ReadCleanReq MSHR misses
1550system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271641 # number of ReadSharedReq MSHR misses
1551system.l2c.ReadSharedReq_mshr_misses::cpu1.data 237 # number of ReadSharedReq MSHR misses
1552system.l2c.ReadSharedReq_mshr_misses::total 271878 # number of ReadSharedReq MSHR misses
1553system.l2c.demand_mshr_misses::cpu0.inst 12981 # number of demand (read+write) MSHR misses
1554system.l2c.demand_mshr_misses::cpu0.data 387198 # number of demand (read+write) MSHR misses
1555system.l2c.demand_mshr_misses::cpu1.inst 444 # number of demand (read+write) MSHR misses
1556system.l2c.demand_mshr_misses::cpu1.data 6828 # number of demand (read+write) MSHR misses
1557system.l2c.demand_mshr_misses::total 407451 # number of demand (read+write) MSHR misses
1558system.l2c.overall_mshr_misses::cpu0.inst 12981 # number of overall MSHR misses
1559system.l2c.overall_mshr_misses::cpu0.data 387198 # number of overall MSHR misses
1560system.l2c.overall_mshr_misses::cpu1.inst 444 # number of overall MSHR misses
1561system.l2c.overall_mshr_misses::cpu1.data 6828 # number of overall MSHR misses
1562system.l2c.overall_mshr_misses::total 407451 # number of overall MSHR misses
1563system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
1564system.l2c.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
1565system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable
1566system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable
1567system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable
1568system.l2c.WriteReq_mshr_uncacheable::total 14058 # number of WriteReq MSHR uncacheable
1569system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses
1570system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses
1571system.l2c.overall_mshr_uncacheable_misses::total 21257 # number of overall MSHR uncacheable misses
1572system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 58492500 # number of UpgradeReq MSHR miss cycles
1573system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34311000 # number of UpgradeReq MSHR miss cycles
1574system.l2c.UpgradeReq_mshr_miss_latency::total 92803500 # number of UpgradeReq MSHR miss cycles
1575system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17536000 # number of SCUpgradeReq MSHR miss cycles
1576system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 17907500 # number of SCUpgradeReq MSHR miss cycles
1577system.l2c.SCUpgradeReq_mshr_miss_latency::total 35443500 # number of SCUpgradeReq MSHR miss cycles
1578system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7746025500 # number of ReadExReq MSHR miss cycles
1579system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 478275500 # number of ReadExReq MSHR miss cycles
1580system.l2c.ReadExReq_mshr_miss_latency::total 8224301000 # number of ReadExReq MSHR miss cycles
1581system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 935268500 # number of ReadCleanReq MSHR miss cycles
1582system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 32302501 # number of ReadCleanReq MSHR miss cycles
1583system.l2c.ReadCleanReq_mshr_miss_latency::total 967571001 # number of ReadCleanReq MSHR miss cycles
1584system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17174531000 # number of ReadSharedReq MSHR miss cycles
1585system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 17173500 # number of ReadSharedReq MSHR miss cycles
1586system.l2c.ReadSharedReq_mshr_miss_latency::total 17191704500 # number of ReadSharedReq MSHR miss cycles
1587system.l2c.demand_mshr_miss_latency::cpu0.inst 935268500 # number of demand (read+write) MSHR miss cycles
1588system.l2c.demand_mshr_miss_latency::cpu0.data 24920556500 # number of demand (read+write) MSHR miss cycles
1589system.l2c.demand_mshr_miss_latency::cpu1.inst 32302501 # number of demand (read+write) MSHR miss cycles
1590system.l2c.demand_mshr_miss_latency::cpu1.data 495449000 # number of demand (read+write) MSHR miss cycles
1591system.l2c.demand_mshr_miss_latency::total 26383576501 # number of demand (read+write) MSHR miss cycles
1592system.l2c.overall_mshr_miss_latency::cpu0.inst 935268500 # number of overall MSHR miss cycles
1593system.l2c.overall_mshr_miss_latency::cpu0.data 24920556500 # number of overall MSHR miss cycles
1594system.l2c.overall_mshr_miss_latency::cpu1.inst 32302501 # number of overall MSHR miss cycles
1595system.l2c.overall_mshr_miss_latency::cpu1.data 495449000 # number of overall MSHR miss cycles
1596system.l2c.overall_mshr_miss_latency::total 26383576501 # number of overall MSHR miss cycles
1597system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1489559500 # number of ReadReq MSHR uncacheable cycles
1598system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 19061000 # number of ReadReq MSHR uncacheable cycles
1599system.l2c.ReadReq_mshr_uncacheable_latency::total 1508620500 # number of ReadReq MSHR uncacheable cycles
1600system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1489559500 # number of overall MSHR uncacheable cycles
1601system.l2c.overall_mshr_uncacheable_latency::cpu1.data 19061000 # number of overall MSHR uncacheable cycles
1602system.l2c.overall_mshr_uncacheable_latency::total 1508620500 # number of overall MSHR uncacheable cycles
1603system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1604system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1605system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943838 # mshr miss rate for UpgradeReq accesses
1606system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764342 # mshr miss rate for UpgradeReq accesses
1607system.l2c.UpgradeReq_mshr_miss_rate::total 0.868265 # mshr miss rate for UpgradeReq accesses
1608system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.964554 # mshr miss rate for SCUpgradeReq accesses
1609system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses
1610system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969222 # mshr miss rate for SCUpgradeReq accesses
1611system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477532 # mshr miss rate for ReadExReq accesses
1612system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122275 # mshr miss rate for ReadExReq accesses
1613system.l2c.ReadExReq_mshr_miss_rate::total 0.412814 # mshr miss rate for ReadExReq accesses
1614system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for ReadCleanReq accesses
1615system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for ReadCleanReq accesses
1616system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013220 # mshr miss rate for ReadCleanReq accesses
1617system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290494 # mshr miss rate for ReadSharedReq accesses
1618system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002169 # mshr miss rate for ReadSharedReq accesses
1619system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260322 # mshr miss rate for ReadSharedReq accesses
1620system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for demand accesses
1621system.l2c.demand_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for demand accesses
1622system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for demand accesses
1623system.l2c.demand_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for demand accesses
1624system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses
1625system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for overall accesses
1626system.l2c.overall_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for overall accesses
1627system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for overall accesses
1628system.l2c.overall_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for overall accesses
1629system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses
1630system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19888.643319 # average UpgradeReq mshr miss latency
1631system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19810.046189 # average UpgradeReq mshr miss latency
1632system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19859.512091 # average UpgradeReq mshr miss latency
1633system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19527.839644 # average SCUpgradeReq mshr miss latency
1634system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19963.768116 # average SCUpgradeReq mshr miss latency
1635system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19745.682451 # average SCUpgradeReq mshr miss latency
1636system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67032.075080 # average ReadExReq mshr miss latency
1637system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72564.937035 # average ReadExReq mshr miss latency
1638system.l2c.ReadExReq_avg_mshr_miss_latency::total 67330.623506 # average ReadExReq mshr miss latency
1639system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average ReadCleanReq mshr miss latency
1640system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average ReadCleanReq mshr miss latency
1641system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821 # average ReadCleanReq mshr miss latency
1642system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930 # average ReadSharedReq mshr miss latency
1643system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316 # average ReadSharedReq mshr miss latency
1644system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887 # average ReadSharedReq mshr miss latency
1645system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency
1646system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency
1647system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency
1648system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency
1649system.l2c.demand_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency
1650system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency
1651system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency
1652system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency
1653system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency
1654system.l2c.overall_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency
1655system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381 # average ReadReq mshr uncacheable latency
1656system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency
1657system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518 # average ReadReq mshr uncacheable latency
1658system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636 # average overall mshr uncacheable latency
1659system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency
1660system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency
1661system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter.
1662system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1663system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1664system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1665system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1666system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1667system.membus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1631system.membus.trans_dist::ReadReq 7199 # Transaction distribution
1632system.membus.trans_dist::ReadResp 292676 # Transaction distribution
1633system.membus.trans_dist::WriteReq 14058 # Transaction distribution
1634system.membus.trans_dist::WriteResp 14058 # Transaction distribution
1635system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution
1636system.membus.trans_dist::CleanEvict 261938 # Transaction distribution
1637system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution
1638system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution
1639system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
1640system.membus.trans_dist::ReadExReq 122469 # Transaction distribution
1641system.membus.trans_dist::ReadExResp 121633 # Transaction distribution
1642system.membus.trans_dist::ReadSharedReq 285477 # Transaction distribution
1643system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1644system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes)
1645system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182508 # Packet count per connected master and slave (bytes)
1646system.membus.pkt_count_system.l2c.mem_side::total 1225022 # Packet count per connected master and slave (bytes)
1647system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83435 # Packet count per connected master and slave (bytes)
1648system.membus.pkt_count_system.iocache.mem_side::total 83435 # Packet count per connected master and slave (bytes)
1649system.membus.pkt_count::total 1308457 # Packet count per connected master and slave (bytes)
1650system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes)
1651system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31079040 # Cumulative packet size per connected master and slave (bytes)
1652system.membus.pkt_size_system.l2c.mem_side::total 31160922 # Cumulative packet size per connected master and slave (bytes)
1653system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
1654system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
1655system.membus.pkt_size::total 33819162 # Cumulative packet size per connected master and slave (bytes)
1656system.membus.snoops 21640 # Total snoops (count)
1657system.membus.snoop_fanout::samples 498117 # Request fanout histogram
1658system.membus.snoop_fanout::mean 0.001313 # Request fanout histogram
1659system.membus.snoop_fanout::stdev 0.036211 # Request fanout histogram
1660system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1661system.membus.snoop_fanout::0 497463 99.87% 99.87% # Request fanout histogram
1662system.membus.snoop_fanout::1 654 0.13% 100.00% # Request fanout histogram
1663system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1664system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1665system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1666system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1667system.membus.snoop_fanout::total 498117 # Request fanout histogram
1668system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks)
1669system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1670system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks)
1671system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1672system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks)
1673system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1674system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks)
1675system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

1668system.membus.trans_dist::ReadReq 7199 # Transaction distribution
1669system.membus.trans_dist::ReadResp 292676 # Transaction distribution
1670system.membus.trans_dist::WriteReq 14058 # Transaction distribution
1671system.membus.trans_dist::WriteResp 14058 # Transaction distribution
1672system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution
1673system.membus.trans_dist::CleanEvict 261938 # Transaction distribution
1674system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution
1675system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution
1676system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
1677system.membus.trans_dist::ReadExReq 122469 # Transaction distribution
1678system.membus.trans_dist::ReadExResp 121633 # Transaction distribution
1679system.membus.trans_dist::ReadSharedReq 285477 # Transaction distribution
1680system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1681system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes)
1682system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182508 # Packet count per connected master and slave (bytes)
1683system.membus.pkt_count_system.l2c.mem_side::total 1225022 # Packet count per connected master and slave (bytes)
1684system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83435 # Packet count per connected master and slave (bytes)
1685system.membus.pkt_count_system.iocache.mem_side::total 83435 # Packet count per connected master and slave (bytes)
1686system.membus.pkt_count::total 1308457 # Packet count per connected master and slave (bytes)
1687system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes)
1688system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31079040 # Cumulative packet size per connected master and slave (bytes)
1689system.membus.pkt_size_system.l2c.mem_side::total 31160922 # Cumulative packet size per connected master and slave (bytes)
1690system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
1691system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
1692system.membus.pkt_size::total 33819162 # Cumulative packet size per connected master and slave (bytes)
1693system.membus.snoops 21640 # Total snoops (count)
1694system.membus.snoop_fanout::samples 498117 # Request fanout histogram
1695system.membus.snoop_fanout::mean 0.001313 # Request fanout histogram
1696system.membus.snoop_fanout::stdev 0.036211 # Request fanout histogram
1697system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1698system.membus.snoop_fanout::0 497463 99.87% 99.87% # Request fanout histogram
1699system.membus.snoop_fanout::1 654 0.13% 100.00% # Request fanout histogram
1700system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1701system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1702system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1703system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1704system.membus.snoop_fanout::total 498117 # Request fanout histogram
1705system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks)
1706system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1707system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks)
1708system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1709system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks)
1710system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1711system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks)
1712system.membus.respLayer2.utilization 0.0 # Layer utilization (%)

1713system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1676system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter.
1677system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1678system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1679system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter.
1680system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1681system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1714system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter.
1715system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1716system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1717system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter.
1718system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1719system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

1720system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1682system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution
1683system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution
1684system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution
1685system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution
1686system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution
1687system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution
1688system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution
1689system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution
1690system.toL2Bus.trans_dist::SCUpgradeReq 11299 # Transaction distribution
1691system.toL2Bus.trans_dist::UpgradeResp 27613 # Transaction distribution
1692system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
1693system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution
1694system.toL2Bus.trans_dist::ReadExReq 297840 # Transaction distribution
1695system.toL2Bus.trans_dist::ReadExResp 297840 # Transaction distribution
1696system.toL2Bus.trans_dist::ReadCleanReq 1015499 # Transaction distribution
1697system.toL2Bus.trans_dist::ReadSharedReq 1078979 # Transaction distribution
1698system.toL2Bus.trans_dist::InvalidateReq 227 # Transaction distribution
1699system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2095725 # Packet count per connected master and slave (bytes)
1700system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605435 # Packet count per connected master and slave (bytes)
1701system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949566 # Packet count per connected master and slave (bytes)
1702system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535407 # Packet count per connected master and slave (bytes)
1703system.toL2Bus.pkt_count::total 7186133 # Packet count per connected master and slave (bytes)
1704system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89403712 # Cumulative packet size per connected master and slave (bytes)
1705system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118812032 # Cumulative packet size per connected master and slave (bytes)
1706system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40502976 # Cumulative packet size per connected master and slave (bytes)
1707system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17791322 # Cumulative packet size per connected master and slave (bytes)
1708system.toL2Bus.pkt_size::total 266510042 # Cumulative packet size per connected master and slave (bytes)
1709system.toL2Bus.snoops 398828 # Total snoops (count)
1710system.toL2Bus.snoop_fanout::samples 2782920 # Request fanout histogram
1711system.toL2Bus.snoop_fanout::mean 0.138526 # Request fanout histogram
1712system.toL2Bus.snoop_fanout::stdev 0.345713 # Request fanout histogram
1713system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1714system.toL2Bus.snoop_fanout::0 2397661 86.16% 86.16% # Request fanout histogram
1715system.toL2Bus.snoop_fanout::1 385012 13.83% 99.99% # Request fanout histogram
1716system.toL2Bus.snoop_fanout::2 245 0.01% 100.00% # Request fanout histogram
1717system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
1718system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1719system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1720system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1721system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
1722system.toL2Bus.snoop_fanout::total 2782920 # Request fanout histogram
1723system.toL2Bus.reqLayer0.occupancy 4214914494 # Layer occupancy (ticks)
1724system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1725system.toL2Bus.snoopLayer0.occupancy 296383 # Layer occupancy (ticks)
1726system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1727system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks)
1728system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1729system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks)
1730system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1731system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks)
1732system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1733system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks)
1734system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

1721system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution
1722system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution
1723system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution
1724system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution
1725system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution
1726system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution
1727system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution
1728system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution
1729system.toL2Bus.trans_dist::SCUpgradeReq 11299 # Transaction distribution
1730system.toL2Bus.trans_dist::UpgradeResp 27613 # Transaction distribution
1731system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
1732system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution
1733system.toL2Bus.trans_dist::ReadExReq 297840 # Transaction distribution
1734system.toL2Bus.trans_dist::ReadExResp 297840 # Transaction distribution
1735system.toL2Bus.trans_dist::ReadCleanReq 1015499 # Transaction distribution
1736system.toL2Bus.trans_dist::ReadSharedReq 1078979 # Transaction distribution
1737system.toL2Bus.trans_dist::InvalidateReq 227 # Transaction distribution
1738system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2095725 # Packet count per connected master and slave (bytes)
1739system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605435 # Packet count per connected master and slave (bytes)
1740system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949566 # Packet count per connected master and slave (bytes)
1741system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535407 # Packet count per connected master and slave (bytes)
1742system.toL2Bus.pkt_count::total 7186133 # Packet count per connected master and slave (bytes)
1743system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89403712 # Cumulative packet size per connected master and slave (bytes)
1744system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118812032 # Cumulative packet size per connected master and slave (bytes)
1745system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40502976 # Cumulative packet size per connected master and slave (bytes)
1746system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17791322 # Cumulative packet size per connected master and slave (bytes)
1747system.toL2Bus.pkt_size::total 266510042 # Cumulative packet size per connected master and slave (bytes)
1748system.toL2Bus.snoops 398828 # Total snoops (count)
1749system.toL2Bus.snoop_fanout::samples 2782920 # Request fanout histogram
1750system.toL2Bus.snoop_fanout::mean 0.138526 # Request fanout histogram
1751system.toL2Bus.snoop_fanout::stdev 0.345713 # Request fanout histogram
1752system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1753system.toL2Bus.snoop_fanout::0 2397661 86.16% 86.16% # Request fanout histogram
1754system.toL2Bus.snoop_fanout::1 385012 13.83% 99.99% # Request fanout histogram
1755system.toL2Bus.snoop_fanout::2 245 0.01% 100.00% # Request fanout histogram
1756system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
1757system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
1758system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1759system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1760system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
1761system.toL2Bus.snoop_fanout::total 2782920 # Request fanout histogram
1762system.toL2Bus.reqLayer0.occupancy 4214914494 # Layer occupancy (ticks)
1763system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1764system.toL2Bus.snoopLayer0.occupancy 296383 # Layer occupancy (ticks)
1765system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1766system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks)
1767system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1768system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks)
1769system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1770system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks)
1771system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1772system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks)
1773system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)

1774system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1775system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1776system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1777system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states

1735system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1736system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1737system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1738system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1739system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1740system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1741system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1742system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1743system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1744system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1745system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1746system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1747system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1748system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1749system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1750system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1751system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1752system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1753system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1754system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1755system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1756system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1757system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1758system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1759system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1760system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1761system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1762system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1763system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1764system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1765system.tsunami.ethernet.droppedPackets 0 # number of packets dropped

1778system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1779system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1780system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1781system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1782system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1783system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1784system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1785system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1786system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1787system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1788system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1789system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1790system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1791system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1792system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1793system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1794system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1795system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1796system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1797system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1798system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1799system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1800system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1801system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1802system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1803system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1804system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1805system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1806system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1807system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1808system.tsunami.ethernet.droppedPackets 0 # number of packets dropped

1809system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1810system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1811system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1812system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1813system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1814system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1815system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1816system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1817system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1818system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1819system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1820system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1821system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1822system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1823system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1824system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1825system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1826system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1827system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1828system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1829system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1830system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states
1831system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1963612574000 # Cumulative time (in ticks) in various power states