Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

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stats.txt (11356:a80884911971)	stats.txt (11456:c0fb4435b80f)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.982593 # Number of seconds simulated 4sim_ticks 1982592736000 # Number of ticks simulated 5final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.982593 # Number of seconds simulated 4sim_ticks 1982592736000 # Number of ticks simulated 5final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 753764 # Simulator instruction rate (inst/s) 8host_op_rate 753764 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24497172234 # Simulator tick rate (ticks/s) 10host_mem_usage 320072 # Number of bytes of host memory used 11host_seconds 80.93 # Real time elapsed on the host	7host_inst_rate 1178528 # Simulator instruction rate (inst/s) 8host_op_rate 1178528 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38301918928 # Simulator tick rate (ticks/s) 10host_mem_usage 332884 # Number of bytes of host memory used 11host_seconds 51.76 # Real time elapsed on the host
12sim_insts 61003209 # Number of instructions simulated 13sim_ops 61003209 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26069824 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 800192 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 59328 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 859520 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7739392 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7739392 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 12503 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 385719 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 927 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 8177 # Number of read requests responded to by this memory 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 407341 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120928 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120928 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 403609 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12451380 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 29924 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 263961 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13149359 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 403609 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 29924 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 433533 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3903672 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3903672 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3903672 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 403609 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12451380 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 29924 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 263961 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17053031 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 407341 # Number of read requests accepted 54system.physmem.writeReqs 120928 # Number of write requests accepted 55system.physmem.readBursts 407341 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 120928 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26061824 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7737600 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26069824 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7739392 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25226 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25379 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25423 # Per bank write bursts 68system.physmem.perBankRdBursts::3 24855 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25157 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25423 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25497 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25338 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25239 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25589 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25733 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25917 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25947 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25572 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25277 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25644 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7850 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7778 # Per bank write bursts 83system.physmem.perBankWrBursts::2 7471 # Per bank write bursts 84system.physmem.perBankWrBursts::3 6886 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7104 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7345 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7431 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7144 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7161 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7315 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7729 # Per bank write bursts 92system.physmem.perBankWrBursts::11 8150 # Per bank write bursts 93system.physmem.perBankWrBursts::12 8256 # Per bank write bursts 94system.physmem.perBankWrBursts::13 7924 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7541 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7815 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 99system.physmem.totGap 1982585344500 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 407341 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 120928 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 407136 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1897 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 7397 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6003 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 7055 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6118 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 5968 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 6500 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 7074 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 6606 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8565 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8947 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7614 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7997 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 7153 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 7369 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6045 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 144 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 107 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 94 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 135 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 195 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 138 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 103 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 87 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 67562 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 500.272698 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 302.933598 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 404.928891 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 16219 24.01% 24.01% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12429 18.40% 42.40% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5206 7.71% 50.11% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3267 4.84% 54.94% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2499 3.70% 58.64% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 4251 6.29% 64.93% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1505 2.23% 67.16% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 2122 3.14% 70.30% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 20064 29.70% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 67562 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5401 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 75.393816 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2870.561720 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5398 99.94% 99.94% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 5401 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5401 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.384744 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.196926 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 20.269218 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 4796 88.80% 88.80% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 29 0.54% 89.34% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 16 0.30% 89.63% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 48 0.89% 90.52% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 211 3.91% 94.43% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 14 0.26% 94.69% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 16 0.30% 94.98% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 27 0.50% 95.48% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 197 3.65% 99.13% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 3 0.06% 99.19% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 2 0.04% 99.22% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 4 0.07% 99.30% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::128-135 6 0.11% 99.41% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::136-143 3 0.06% 99.46% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::144-151 1 0.02% 99.48% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::160-167 3 0.06% 99.54% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::168-175 4 0.07% 99.61% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::192-199 2 0.04% 99.74% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::208-215 9 0.17% 99.91% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::216-223 1 0.02% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::232-239 1 0.02% 99.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::total 5401 # Writes before turning the bus around for reads 260system.physmem.totQLat 2785960750 # Total ticks spent queuing 261system.physmem.totMemAccLat 10421260750 # Total ticks spent from burst creation until serviced by the DRAM 262system.physmem.totBusLat 2036080000 # Total ticks spent in databus transfers 263system.physmem.avgQLat 6841.48 # Average queueing delay per DRAM burst 264system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 265system.physmem.avgMemAccLat 25591.48 # Average memory access latency per DRAM burst 266system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s 267system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s 268system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s 269system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s 270system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 271system.physmem.busUtil 0.13 # Data bus utilization in percentage 272system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 273system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 274system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 275system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing 276system.physmem.readRowHits 363789 # Number of row buffer hits during reads 277system.physmem.writeRowHits 96765 # Number of row buffer hits during writes 278system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads 279system.physmem.writeRowHitRate 80.02 # Row buffer hit rate for writes 280system.physmem.avgGap 3752984.45 # Average gap between requests 281system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined 282system.physmem_0.actEnergy 243704160 # Energy for activate commands per rank (pJ) 283system.physmem_0.preEnergy 132973500 # Energy for precharge commands per rank (pJ) 284system.physmem_0.readEnergy 1577924400 # Energy for read commands per rank (pJ) 285system.physmem_0.writeEnergy 382378320 # Energy for write commands per rank (pJ) 286system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) 287system.physmem_0.actBackEnergy 72905362650 # Energy for active background per rank (pJ) 288system.physmem_0.preBackEnergy 1125601770750 # Energy for precharge background per rank (pJ) 289system.physmem_0.totalEnergy 1330337220900 # Total energy per rank (pJ) 290system.physmem_0.averagePower 671.009839 # Core power per rank (mW) 291system.physmem_0.memoryStateTime::IDLE 1872255893500 # Time in different power states 292system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states 293system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 294system.physmem_0.memoryStateTime::ACT 44130839000 # Time in different power states 295system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 296system.physmem_1.actEnergy 267064560 # Energy for activate commands per rank (pJ) 297system.physmem_1.preEnergy 145719750 # Energy for precharge commands per rank (pJ) 298system.physmem_1.readEnergy 1598360400 # Energy for read commands per rank (pJ) 299system.physmem_1.writeEnergy 401053680 # Energy for write commands per rank (pJ) 300system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) 301system.physmem_1.actBackEnergy 73884851505 # Energy for active background per rank (pJ) 302system.physmem_1.preBackEnergy 1124742561750 # Energy for precharge background per rank (pJ) 303system.physmem_1.totalEnergy 1330532718765 # Total energy per rank (pJ) 304system.physmem_1.averagePower 671.108451 # Core power per rank (mW) 305system.physmem_1.memoryStateTime::IDLE 1870830292750 # Time in different power states 306system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states 307system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 308system.physmem_1.memoryStateTime::ACT 45556426000 # Time in different power states 309system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 310system.cpu_clk_domain.clock 500 # Clock period in ticks 311system.cpu0.dtb.fetch_hits 0 # ITB hits 312system.cpu0.dtb.fetch_misses 0 # ITB misses 313system.cpu0.dtb.fetch_acv 0 # ITB acv 314system.cpu0.dtb.fetch_accesses 0 # ITB accesses 315system.cpu0.dtb.read_hits 7416468 # DTB read hits 316system.cpu0.dtb.read_misses 7442 # DTB read misses 317system.cpu0.dtb.read_acv 210 # DTB read access violations 318system.cpu0.dtb.read_accesses 490672 # DTB read accesses 319system.cpu0.dtb.write_hits 5004426 # DTB write hits 320system.cpu0.dtb.write_misses 812 # DTB write misses 321system.cpu0.dtb.write_acv 134 # DTB write access violations 322system.cpu0.dtb.write_accesses 187451 # DTB write accesses 323system.cpu0.dtb.data_hits 12420894 # DTB hits 324system.cpu0.dtb.data_misses 8254 # DTB misses 325system.cpu0.dtb.data_acv 344 # DTB access violations 326system.cpu0.dtb.data_accesses 678123 # DTB accesses 327system.cpu0.itb.fetch_hits 3482357 # ITB hits 328system.cpu0.itb.fetch_misses 3871 # ITB misses 329system.cpu0.itb.fetch_acv 184 # ITB acv 330system.cpu0.itb.fetch_accesses 3486228 # ITB accesses 331system.cpu0.itb.read_hits 0 # DTB read hits 332system.cpu0.itb.read_misses 0 # DTB read misses 333system.cpu0.itb.read_acv 0 # DTB read access violations 334system.cpu0.itb.read_accesses 0 # DTB read accesses 335system.cpu0.itb.write_hits 0 # DTB write hits 336system.cpu0.itb.write_misses 0 # DTB write misses 337system.cpu0.itb.write_acv 0 # DTB write access violations 338system.cpu0.itb.write_accesses 0 # DTB write accesses 339system.cpu0.itb.data_hits 0 # DTB hits 340system.cpu0.itb.data_misses 0 # DTB misses 341system.cpu0.itb.data_acv 0 # DTB access violations 342system.cpu0.itb.data_accesses 0 # DTB accesses 343system.cpu0.numCycles 3964851876 # number of cpu cycles simulated 344system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 345system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 346system.cpu0.kern.inst.arm 0 # number of arm instructions executed 347system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed 348system.cpu0.kern.inst.hwrei 162795 # number of hwrei instructions executed 349system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl 350system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl 351system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl 352system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl 353system.cpu0.kern.ipl_count::31 80935 58.06% 100.00% # number of times we switched to this ipl 354system.cpu0.kern.ipl_count::total 139406 # number of times we switched to this ipl 355system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl 356system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl 357system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl 358system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl 359system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl 360system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl 361system.cpu0.kern.ipl_ticks::0 1904797058500 96.08% 96.08% # number of cycles we spent at this ipl 362system.cpu0.kern.ipl_ticks::21 94101500 0.00% 96.09% # number of cycles we spent at this ipl 363system.cpu0.kern.ipl_ticks::22 790644500 0.04% 96.13% # number of cycles we spent at this ipl 364system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl 365system.cpu0.kern.ipl_ticks::31 76417629500 3.85% 100.00% # number of cycles we spent at this ipl 366system.cpu0.kern.ipl_ticks::total 1982425908000 # number of cycles we spent at this ipl 367system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl 368system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 369system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 370system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 371system.cpu0.kern.ipl_used::31 0.679348 # fraction of swpipl calls that actually changed the ipl 372system.cpu0.kern.ipl_used::total 0.810188 # fraction of swpipl calls that actually changed the ipl 373system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 374system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 375system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 376system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 377system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 378system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 379system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 380system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 381system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 382system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 383system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 384system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 385system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 386system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 387system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 388system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 389system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 390system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 391system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 392system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 393system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 394system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 395system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 396system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 397system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 398system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 399system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 400system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 401system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 402system.cpu0.kern.syscall::total 222 # number of syscalls executed 403system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 404system.cpu0.kern.callpal::wripir 524 0.36% 0.36% # number of callpals executed 405system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 406system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 407system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 408system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed 409system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 410system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 411system.cpu0.kern.callpal::swpipl 132536 89.80% 92.24% # number of callpals executed 412system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed 413system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed 414system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed 415system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed 416system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed 417system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed 418system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed 419system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed 420system.cpu0.kern.callpal::total 147596 # number of callpals executed 421system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches 422system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 423system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 424system.cpu0.kern.mode_good::kernel 1283 425system.cpu0.kern.mode_good::user 1283 426system.cpu0.kern.mode_good::idle 0 427system.cpu0.kern.mode_switch_good::kernel 0.186944 # fraction of useful protection mode switches 428system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 429system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 430system.cpu0.kern.mode_switch_good::total 0.315001 # fraction of useful protection mode switches 431system.cpu0.kern.mode_ticks::kernel 1977682468000 99.80% 99.80% # number of ticks spent at the given mode 432system.cpu0.kern.mode_ticks::user 3900182500 0.20% 100.00% # number of ticks spent at the given mode 433system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 434system.cpu0.kern.swap_context 3025 # number of times the context was actually changed 435system.cpu0.committedInsts 47316464 # Number of instructions committed 436system.cpu0.committedOps 47316464 # Number of ops (including micro ops) committed 437system.cpu0.num_int_alu_accesses 43886764 # Number of integer alu accesses 438system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses 439system.cpu0.num_func_calls 1185664 # number of times a function call or return occured 440system.cpu0.num_conditional_control_insts 5565449 # number of instructions that are conditional controls 441system.cpu0.num_int_insts 43886764 # number of integer instructions 442system.cpu0.num_fp_insts 206939 # number of float instructions 443system.cpu0.num_int_register_reads 60334858 # number of times the integer registers were read 444system.cpu0.num_int_register_writes 32718698 # number of times the integer registers were written 445system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read 446system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written 447system.cpu0.num_mem_refs 12460790 # number of memory refs 448system.cpu0.num_load_insts 7443408 # Number of load instructions 449system.cpu0.num_store_insts 5017382 # Number of store instructions 450system.cpu0.num_idle_cycles 3699967048.966084 # Number of idle cycles 451system.cpu0.num_busy_cycles 264884827.033916 # Number of busy cycles 452system.cpu0.not_idle_fraction 0.066808 # Percentage of non-idle cycles 453system.cpu0.idle_fraction 0.933192 # Percentage of idle cycles 454system.cpu0.Branches 7133745 # Number of branches fetched 455system.cpu0.op_class::No_OpClass 2703031 5.71% 5.71% # Class of executed instruction 456system.cpu0.op_class::IntAlu 31175440 65.88% 71.59% # Class of executed instruction 457system.cpu0.op_class::IntMult 51698 0.11% 71.70% # Class of executed instruction 458system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction 459system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction 460system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction 461system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction 462system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction 463system.cpu0.op_class::FloatDiv 1656 0.00% 71.75% # Class of executed instruction 464system.cpu0.op_class::FloatSqrt 0 0.00% 71.75% # Class of executed instruction 465system.cpu0.op_class::SimdAdd 0 0.00% 71.75% # Class of executed instruction 466system.cpu0.op_class::SimdAddAcc 0 0.00% 71.75% # Class of executed instruction 467system.cpu0.op_class::SimdAlu 0 0.00% 71.75% # Class of executed instruction 468system.cpu0.op_class::SimdCmp 0 0.00% 71.75% # Class of executed instruction 469system.cpu0.op_class::SimdCvt 0 0.00% 71.75% # Class of executed instruction 470system.cpu0.op_class::SimdMisc 0 0.00% 71.75% # Class of executed instruction 471system.cpu0.op_class::SimdMult 0 0.00% 71.75% # Class of executed instruction 472system.cpu0.op_class::SimdMultAcc 0 0.00% 71.75% # Class of executed instruction 473system.cpu0.op_class::SimdShift 0 0.00% 71.75% # Class of executed instruction 474system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.75% # Class of executed instruction 475system.cpu0.op_class::SimdSqrt 0 0.00% 71.75% # Class of executed instruction 476system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.75% # Class of executed instruction 477system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.75% # Class of executed instruction 478system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.75% # Class of executed instruction 479system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.75% # Class of executed instruction 480system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.75% # Class of executed instruction 481system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Class of executed instruction 482system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction 483system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction 484system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction 485system.cpu0.op_class::MemRead 7616501 16.09% 87.85% # Class of executed instruction 486system.cpu0.op_class::MemWrite 5023484 10.61% 98.46% # Class of executed instruction 487system.cpu0.op_class::IprAccess 727686 1.54% 100.00% # Class of executed instruction 488system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 489system.cpu0.op_class::total 47325062 # Class of executed instruction 490system.cpu0.dcache.tags.replacements 1172723 # number of replacements 491system.cpu0.dcache.tags.tagsinuse 505.333527 # Cycle average of tags in use 492system.cpu0.dcache.tags.total_refs 11236927 # Total number of references to valid blocks. 493system.cpu0.dcache.tags.sampled_refs 1173142 # Sample count of references to valid blocks. 494system.cpu0.dcache.tags.avg_refs 9.578488 # Average number of references to valid blocks. 495system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. 496system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333527 # Average occupied blocks per requestor 497system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy 498system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy 499system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id 500system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 501system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id 502system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id 503system.cpu0.dcache.tags.tag_accesses 50908342 # Number of tag accesses 504system.cpu0.dcache.tags.data_accesses 50908342 # Number of data accesses 505system.cpu0.dcache.ReadReq_hits::cpu0.data 6342787 # number of ReadReq hits 506system.cpu0.dcache.ReadReq_hits::total 6342787 # number of ReadReq hits 507system.cpu0.dcache.WriteReq_hits::cpu0.data 4601077 # number of WriteReq hits 508system.cpu0.dcache.WriteReq_hits::total 4601077 # number of WriteReq hits 509system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138129 # number of LoadLockedReq hits 510system.cpu0.dcache.LoadLockedReq_hits::total 138129 # number of LoadLockedReq hits 511system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145434 # number of StoreCondReq hits 512system.cpu0.dcache.StoreCondReq_hits::total 145434 # number of StoreCondReq hits 513system.cpu0.dcache.demand_hits::cpu0.data 10943864 # number of demand (read+write) hits 514system.cpu0.dcache.demand_hits::total 10943864 # number of demand (read+write) hits 515system.cpu0.dcache.overall_hits::cpu0.data 10943864 # number of overall hits 516system.cpu0.dcache.overall_hits::total 10943864 # number of overall hits 517system.cpu0.dcache.ReadReq_misses::cpu0.data 934179 # number of ReadReq misses 518system.cpu0.dcache.ReadReq_misses::total 934179 # number of ReadReq misses 519system.cpu0.dcache.WriteReq_misses::cpu0.data 249076 # number of WriteReq misses 520system.cpu0.dcache.WriteReq_misses::total 249076 # number of WriteReq misses 521system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses 522system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses 523system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses 524system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses 525system.cpu0.dcache.demand_misses::cpu0.data 1183255 # number of demand (read+write) misses 526system.cpu0.dcache.demand_misses::total 1183255 # number of demand (read+write) misses 527system.cpu0.dcache.overall_misses::cpu0.data 1183255 # number of overall misses 528system.cpu0.dcache.overall_misses::total 1183255 # number of overall misses 529system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42885164500 # number of ReadReq miss cycles 530system.cpu0.dcache.ReadReq_miss_latency::total 42885164500 # number of ReadReq miss cycles 531system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793601000 # number of WriteReq miss cycles 532system.cpu0.dcache.WriteReq_miss_latency::total 16793601000 # number of WriteReq miss cycles 533system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151515500 # number of LoadLockedReq miss cycles 534system.cpu0.dcache.LoadLockedReq_miss_latency::total 151515500 # number of LoadLockedReq miss cycles 535system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 94785500 # number of StoreCondReq miss cycles 536system.cpu0.dcache.StoreCondReq_miss_latency::total 94785500 # number of StoreCondReq miss cycles 537system.cpu0.dcache.demand_miss_latency::cpu0.data 59678765500 # number of demand (read+write) miss cycles 538system.cpu0.dcache.demand_miss_latency::total 59678765500 # number of demand (read+write) miss cycles 539system.cpu0.dcache.overall_miss_latency::cpu0.data 59678765500 # number of overall miss cycles 540system.cpu0.dcache.overall_miss_latency::total 59678765500 # number of overall miss cycles 541system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276966 # number of ReadReq accesses(hits+misses) 542system.cpu0.dcache.ReadReq_accesses::total 7276966 # number of ReadReq accesses(hits+misses) 543system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850153 # number of WriteReq accesses(hits+misses) 544system.cpu0.dcache.WriteReq_accesses::total 4850153 # number of WriteReq accesses(hits+misses) 545system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151707 # number of LoadLockedReq accesses(hits+misses) 546system.cpu0.dcache.LoadLockedReq_accesses::total 151707 # number of LoadLockedReq accesses(hits+misses) 547system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151173 # number of StoreCondReq accesses(hits+misses) 548system.cpu0.dcache.StoreCondReq_accesses::total 151173 # number of StoreCondReq accesses(hits+misses) 549system.cpu0.dcache.demand_accesses::cpu0.data 12127119 # number of demand (read+write) accesses 550system.cpu0.dcache.demand_accesses::total 12127119 # number of demand (read+write) accesses 551system.cpu0.dcache.overall_accesses::cpu0.data 12127119 # number of overall (read+write) accesses 552system.cpu0.dcache.overall_accesses::total 12127119 # number of overall (read+write) accesses 553system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128375 # miss rate for ReadReq accesses 554system.cpu0.dcache.ReadReq_miss_rate::total 0.128375 # miss rate for ReadReq accesses 555system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051354 # miss rate for WriteReq accesses 556system.cpu0.dcache.WriteReq_miss_rate::total 0.051354 # miss rate for WriteReq accesses 557system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089501 # miss rate for LoadLockedReq accesses 558system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089501 # miss rate for LoadLockedReq accesses 559system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037963 # miss rate for StoreCondReq accesses 560system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037963 # miss rate for StoreCondReq accesses 561system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097571 # miss rate for demand accesses 562system.cpu0.dcache.demand_miss_rate::total 0.097571 # miss rate for demand accesses 563system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097571 # miss rate for overall accesses 564system.cpu0.dcache.overall_miss_rate::total 0.097571 # miss rate for overall accesses 565system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.795700 # average ReadReq miss latency 566system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.795700 # average ReadReq miss latency 567system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67423.601632 # average WriteReq miss latency 568system.cpu0.dcache.WriteReq_avg_miss_latency::total 67423.601632 # average WriteReq miss latency 569system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11158.896745 # average LoadLockedReq miss latency 570system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11158.896745 # average LoadLockedReq miss latency 571system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16516.030667 # average StoreCondReq miss latency 572system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16516.030667 # average StoreCondReq miss latency 573system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency 574system.cpu0.dcache.demand_avg_miss_latency::total 50436.098305 # average overall miss latency 575system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency 576system.cpu0.dcache.overall_avg_miss_latency::total 50436.098305 # average overall miss latency 577system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 578system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 579system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 580system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 581system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 582system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	12sim_insts 61003209 # Number of instructions simulated 13sim_ops 61003209 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory 20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 26069824 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu0.inst 800192 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::cpu1.inst 59328 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 859520 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 7739392 # Number of bytes written to this memory 26system.physmem.bytes_written::total 7739392 # Number of bytes written to this memory 27system.physmem.num_reads::cpu0.inst 12503 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu0.data 385719 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.inst 927 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu1.data 8177 # Number of read requests responded to by this memory 31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 407341 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 120928 # Number of write requests responded to by this memory 34system.physmem.num_writes::total 120928 # Number of write requests responded to by this memory 35system.physmem.bw_read::cpu0.inst 403609 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu0.data 12451380 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.inst 29924 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu1.data 263961 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::total 13149359 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::cpu0.inst 403609 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu1.inst 29924 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 433533 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 3903672 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::total 3903672 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_total::writebacks 3903672 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu0.inst 403609 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu0.data 12451380 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.inst 29924 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu1.data 263961 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::total 17053031 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.readReqs 407341 # Number of read requests accepted 54system.physmem.writeReqs 120928 # Number of write requests accepted 55system.physmem.readBursts 407341 # Number of DRAM read bursts, including those serviced by the write queue 56system.physmem.writeBursts 120928 # Number of DRAM write bursts, including those merged in the write queue 57system.physmem.bytesReadDRAM 26061824 # Total number of bytes read from DRAM 58system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue 59system.physmem.bytesWritten 7737600 # Total number of bytes written to DRAM 60system.physmem.bytesReadSys 26069824 # Total read bytes from the system interface side 61system.physmem.bytesWrittenSys 7739392 # Total written bytes from the system interface side 62system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue 63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 64system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 65system.physmem.perBankRdBursts::0 25226 # Per bank write bursts 66system.physmem.perBankRdBursts::1 25379 # Per bank write bursts 67system.physmem.perBankRdBursts::2 25423 # Per bank write bursts 68system.physmem.perBankRdBursts::3 24855 # Per bank write bursts 69system.physmem.perBankRdBursts::4 25157 # Per bank write bursts 70system.physmem.perBankRdBursts::5 25423 # Per bank write bursts 71system.physmem.perBankRdBursts::6 25497 # Per bank write bursts 72system.physmem.perBankRdBursts::7 25338 # Per bank write bursts 73system.physmem.perBankRdBursts::8 25239 # Per bank write bursts 74system.physmem.perBankRdBursts::9 25589 # Per bank write bursts 75system.physmem.perBankRdBursts::10 25733 # Per bank write bursts 76system.physmem.perBankRdBursts::11 25917 # Per bank write bursts 77system.physmem.perBankRdBursts::12 25947 # Per bank write bursts 78system.physmem.perBankRdBursts::13 25572 # Per bank write bursts 79system.physmem.perBankRdBursts::14 25277 # Per bank write bursts 80system.physmem.perBankRdBursts::15 25644 # Per bank write bursts 81system.physmem.perBankWrBursts::0 7850 # Per bank write bursts 82system.physmem.perBankWrBursts::1 7778 # Per bank write bursts 83system.physmem.perBankWrBursts::2 7471 # Per bank write bursts 84system.physmem.perBankWrBursts::3 6886 # Per bank write bursts 85system.physmem.perBankWrBursts::4 7104 # Per bank write bursts 86system.physmem.perBankWrBursts::5 7345 # Per bank write bursts 87system.physmem.perBankWrBursts::6 7431 # Per bank write bursts 88system.physmem.perBankWrBursts::7 7144 # Per bank write bursts 89system.physmem.perBankWrBursts::8 7161 # Per bank write bursts 90system.physmem.perBankWrBursts::9 7315 # Per bank write bursts 91system.physmem.perBankWrBursts::10 7729 # Per bank write bursts 92system.physmem.perBankWrBursts::11 8150 # Per bank write bursts 93system.physmem.perBankWrBursts::12 8256 # Per bank write bursts 94system.physmem.perBankWrBursts::13 7924 # Per bank write bursts 95system.physmem.perBankWrBursts::14 7541 # Per bank write bursts 96system.physmem.perBankWrBursts::15 7815 # Per bank write bursts 97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 98system.physmem.numWrRetry 9 # Number of times write queue was full causing retry 99system.physmem.totGap 1982585344500 # Total gap between requests 100system.physmem.readPktSize::0 0 # Read request sizes (log2) 101system.physmem.readPktSize::1 0 # Read request sizes (log2) 102system.physmem.readPktSize::2 0 # Read request sizes (log2) 103system.physmem.readPktSize::3 0 # Read request sizes (log2) 104system.physmem.readPktSize::4 0 # Read request sizes (log2) 105system.physmem.readPktSize::5 0 # Read request sizes (log2) 106system.physmem.readPktSize::6 407341 # Read request sizes (log2) 107system.physmem.writePktSize::0 0 # Write request sizes (log2) 108system.physmem.writePktSize::1 0 # Write request sizes (log2) 109system.physmem.writePktSize::2 0 # Write request sizes (log2) 110system.physmem.writePktSize::3 0 # Write request sizes (log2) 111system.physmem.writePktSize::4 0 # Write request sizes (log2) 112system.physmem.writePktSize::5 0 # Write request sizes (log2) 113system.physmem.writePktSize::6 120928 # Write request sizes (log2) 114system.physmem.rdQLenPdf::0 407136 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::15 1897 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::17 7397 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::18 6003 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::19 7055 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::20 6118 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::21 5968 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::22 6500 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::23 7074 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::24 6606 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::25 8565 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::26 8947 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::27 7614 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::28 7997 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::29 7153 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::30 7369 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::31 6045 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::34 144 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::35 107 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::40 94 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::42 135 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::44 195 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::50 138 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::54 103 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::60 87 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see 210system.physmem.bytesPerActivate::samples 67562 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::mean 500.272698 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::gmean 302.933598 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::stdev 404.928891 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::0-127 16219 24.01% 24.01% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::128-255 12429 18.40% 42.40% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::256-383 5206 7.71% 50.11% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::384-511 3267 4.84% 54.94% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::512-639 2499 3.70% 58.64% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::640-767 4251 6.29% 64.93% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::768-895 1505 2.23% 67.16% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::896-1023 2122 3.14% 70.30% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1024-1151 20064 29.70% 100.00% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::total 67562 # Bytes accessed per row activation 224system.physmem.rdPerTurnAround::samples 5401 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::mean 75.393816 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::stdev 2870.561720 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::0-8191 5398 99.94% 99.94% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 5401 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 5401 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 22.384744 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.196926 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 20.269218 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-23 4796 88.80% 88.80% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-31 29 0.54% 89.34% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::32-39 16 0.30% 89.63% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::40-47 48 0.89% 90.52% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-55 211 3.91% 94.43% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::56-63 14 0.26% 94.69% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::64-71 16 0.30% 94.98% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::72-79 27 0.50% 95.48% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::80-87 197 3.65% 99.13% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::88-95 3 0.06% 99.19% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::96-103 2 0.04% 99.22% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::104-111 4 0.07% 99.30% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::128-135 6 0.11% 99.41% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::136-143 3 0.06% 99.46% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::144-151 1 0.02% 99.48% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::160-167 3 0.06% 99.54% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::168-175 4 0.07% 99.61% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::192-199 2 0.04% 99.74% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::208-215 9 0.17% 99.91% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::216-223 1 0.02% 99.93% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::232-239 1 0.02% 99.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::total 5401 # Writes before turning the bus around for reads 260system.physmem.totQLat 2785960750 # Total ticks spent queuing 261system.physmem.totMemAccLat 10421260750 # Total ticks spent from burst creation until serviced by the DRAM 262system.physmem.totBusLat 2036080000 # Total ticks spent in databus transfers 263system.physmem.avgQLat 6841.48 # Average queueing delay per DRAM burst 264system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 265system.physmem.avgMemAccLat 25591.48 # Average memory access latency per DRAM burst 266system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s 267system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s 268system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s 269system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s 270system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 271system.physmem.busUtil 0.13 # Data bus utilization in percentage 272system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 273system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 274system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 275system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing 276system.physmem.readRowHits 363789 # Number of row buffer hits during reads 277system.physmem.writeRowHits 96765 # Number of row buffer hits during writes 278system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads 279system.physmem.writeRowHitRate 80.02 # Row buffer hit rate for writes 280system.physmem.avgGap 3752984.45 # Average gap between requests 281system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined 282system.physmem_0.actEnergy 243704160 # Energy for activate commands per rank (pJ) 283system.physmem_0.preEnergy 132973500 # Energy for precharge commands per rank (pJ) 284system.physmem_0.readEnergy 1577924400 # Energy for read commands per rank (pJ) 285system.physmem_0.writeEnergy 382378320 # Energy for write commands per rank (pJ) 286system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) 287system.physmem_0.actBackEnergy 72905362650 # Energy for active background per rank (pJ) 288system.physmem_0.preBackEnergy 1125601770750 # Energy for precharge background per rank (pJ) 289system.physmem_0.totalEnergy 1330337220900 # Total energy per rank (pJ) 290system.physmem_0.averagePower 671.009839 # Core power per rank (mW) 291system.physmem_0.memoryStateTime::IDLE 1872255893500 # Time in different power states 292system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states 293system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 294system.physmem_0.memoryStateTime::ACT 44130839000 # Time in different power states 295system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 296system.physmem_1.actEnergy 267064560 # Energy for activate commands per rank (pJ) 297system.physmem_1.preEnergy 145719750 # Energy for precharge commands per rank (pJ) 298system.physmem_1.readEnergy 1598360400 # Energy for read commands per rank (pJ) 299system.physmem_1.writeEnergy 401053680 # Energy for write commands per rank (pJ) 300system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) 301system.physmem_1.actBackEnergy 73884851505 # Energy for active background per rank (pJ) 302system.physmem_1.preBackEnergy 1124742561750 # Energy for precharge background per rank (pJ) 303system.physmem_1.totalEnergy 1330532718765 # Total energy per rank (pJ) 304system.physmem_1.averagePower 671.108451 # Core power per rank (mW) 305system.physmem_1.memoryStateTime::IDLE 1870830292750 # Time in different power states 306system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states 307system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 308system.physmem_1.memoryStateTime::ACT 45556426000 # Time in different power states 309system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 310system.cpu_clk_domain.clock 500 # Clock period in ticks 311system.cpu0.dtb.fetch_hits 0 # ITB hits 312system.cpu0.dtb.fetch_misses 0 # ITB misses 313system.cpu0.dtb.fetch_acv 0 # ITB acv 314system.cpu0.dtb.fetch_accesses 0 # ITB accesses 315system.cpu0.dtb.read_hits 7416468 # DTB read hits 316system.cpu0.dtb.read_misses 7442 # DTB read misses 317system.cpu0.dtb.read_acv 210 # DTB read access violations 318system.cpu0.dtb.read_accesses 490672 # DTB read accesses 319system.cpu0.dtb.write_hits 5004426 # DTB write hits 320system.cpu0.dtb.write_misses 812 # DTB write misses 321system.cpu0.dtb.write_acv 134 # DTB write access violations 322system.cpu0.dtb.write_accesses 187451 # DTB write accesses 323system.cpu0.dtb.data_hits 12420894 # DTB hits 324system.cpu0.dtb.data_misses 8254 # DTB misses 325system.cpu0.dtb.data_acv 344 # DTB access violations 326system.cpu0.dtb.data_accesses 678123 # DTB accesses 327system.cpu0.itb.fetch_hits 3482357 # ITB hits 328system.cpu0.itb.fetch_misses 3871 # ITB misses 329system.cpu0.itb.fetch_acv 184 # ITB acv 330system.cpu0.itb.fetch_accesses 3486228 # ITB accesses 331system.cpu0.itb.read_hits 0 # DTB read hits 332system.cpu0.itb.read_misses 0 # DTB read misses 333system.cpu0.itb.read_acv 0 # DTB read access violations 334system.cpu0.itb.read_accesses 0 # DTB read accesses 335system.cpu0.itb.write_hits 0 # DTB write hits 336system.cpu0.itb.write_misses 0 # DTB write misses 337system.cpu0.itb.write_acv 0 # DTB write access violations 338system.cpu0.itb.write_accesses 0 # DTB write accesses 339system.cpu0.itb.data_hits 0 # DTB hits 340system.cpu0.itb.data_misses 0 # DTB misses 341system.cpu0.itb.data_acv 0 # DTB access violations 342system.cpu0.itb.data_accesses 0 # DTB accesses 343system.cpu0.numCycles 3964851876 # number of cpu cycles simulated 344system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 345system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 346system.cpu0.kern.inst.arm 0 # number of arm instructions executed 347system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed 348system.cpu0.kern.inst.hwrei 162795 # number of hwrei instructions executed 349system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl 350system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl 351system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl 352system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl 353system.cpu0.kern.ipl_count::31 80935 58.06% 100.00% # number of times we switched to this ipl 354system.cpu0.kern.ipl_count::total 139406 # number of times we switched to this ipl 355system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl 356system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl 357system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl 358system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl 359system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl 360system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl 361system.cpu0.kern.ipl_ticks::0 1904797058500 96.08% 96.08% # number of cycles we spent at this ipl 362system.cpu0.kern.ipl_ticks::21 94101500 0.00% 96.09% # number of cycles we spent at this ipl 363system.cpu0.kern.ipl_ticks::22 790644500 0.04% 96.13% # number of cycles we spent at this ipl 364system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl 365system.cpu0.kern.ipl_ticks::31 76417629500 3.85% 100.00% # number of cycles we spent at this ipl 366system.cpu0.kern.ipl_ticks::total 1982425908000 # number of cycles we spent at this ipl 367system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl 368system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 369system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 370system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 371system.cpu0.kern.ipl_used::31 0.679348 # fraction of swpipl calls that actually changed the ipl 372system.cpu0.kern.ipl_used::total 0.810188 # fraction of swpipl calls that actually changed the ipl 373system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed 374system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed 375system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed 376system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed 377system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed 378system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed 379system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed 380system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed 381system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed 382system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed 383system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed 384system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed 385system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed 386system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed 387system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed 388system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed 389system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed 390system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed 391system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed 392system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed 393system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed 394system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed 395system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed 396system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed 397system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed 398system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed 399system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed 400system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed 401system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed 402system.cpu0.kern.syscall::total 222 # number of syscalls executed 403system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 404system.cpu0.kern.callpal::wripir 524 0.36% 0.36% # number of callpals executed 405system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 406system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 407system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 408system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed 409system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed 410system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed 411system.cpu0.kern.callpal::swpipl 132536 89.80% 92.24% # number of callpals executed 412system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed 413system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed 414system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed 415system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed 416system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed 417system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed 418system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed 419system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed 420system.cpu0.kern.callpal::total 147596 # number of callpals executed 421system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches 422system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches 423system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 424system.cpu0.kern.mode_good::kernel 1283 425system.cpu0.kern.mode_good::user 1283 426system.cpu0.kern.mode_good::idle 0 427system.cpu0.kern.mode_switch_good::kernel 0.186944 # fraction of useful protection mode switches 428system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 429system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 430system.cpu0.kern.mode_switch_good::total 0.315001 # fraction of useful protection mode switches 431system.cpu0.kern.mode_ticks::kernel 1977682468000 99.80% 99.80% # number of ticks spent at the given mode 432system.cpu0.kern.mode_ticks::user 3900182500 0.20% 100.00% # number of ticks spent at the given mode 433system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 434system.cpu0.kern.swap_context 3025 # number of times the context was actually changed 435system.cpu0.committedInsts 47316464 # Number of instructions committed 436system.cpu0.committedOps 47316464 # Number of ops (including micro ops) committed 437system.cpu0.num_int_alu_accesses 43886764 # Number of integer alu accesses 438system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses 439system.cpu0.num_func_calls 1185664 # number of times a function call or return occured 440system.cpu0.num_conditional_control_insts 5565449 # number of instructions that are conditional controls 441system.cpu0.num_int_insts 43886764 # number of integer instructions 442system.cpu0.num_fp_insts 206939 # number of float instructions 443system.cpu0.num_int_register_reads 60334858 # number of times the integer registers were read 444system.cpu0.num_int_register_writes 32718698 # number of times the integer registers were written 445system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read 446system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written 447system.cpu0.num_mem_refs 12460790 # number of memory refs 448system.cpu0.num_load_insts 7443408 # Number of load instructions 449system.cpu0.num_store_insts 5017382 # Number of store instructions 450system.cpu0.num_idle_cycles 3699967048.966084 # Number of idle cycles 451system.cpu0.num_busy_cycles 264884827.033916 # Number of busy cycles 452system.cpu0.not_idle_fraction 0.066808 # Percentage of non-idle cycles 453system.cpu0.idle_fraction 0.933192 # Percentage of idle cycles 454system.cpu0.Branches 7133745 # Number of branches fetched 455system.cpu0.op_class::No_OpClass 2703031 5.71% 5.71% # Class of executed instruction 456system.cpu0.op_class::IntAlu 31175440 65.88% 71.59% # Class of executed instruction 457system.cpu0.op_class::IntMult 51698 0.11% 71.70% # Class of executed instruction 458system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction 459system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction 460system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction 461system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction 462system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction 463system.cpu0.op_class::FloatDiv 1656 0.00% 71.75% # Class of executed instruction 464system.cpu0.op_class::FloatSqrt 0 0.00% 71.75% # Class of executed instruction 465system.cpu0.op_class::SimdAdd 0 0.00% 71.75% # Class of executed instruction 466system.cpu0.op_class::SimdAddAcc 0 0.00% 71.75% # Class of executed instruction 467system.cpu0.op_class::SimdAlu 0 0.00% 71.75% # Class of executed instruction 468system.cpu0.op_class::SimdCmp 0 0.00% 71.75% # Class of executed instruction 469system.cpu0.op_class::SimdCvt 0 0.00% 71.75% # Class of executed instruction 470system.cpu0.op_class::SimdMisc 0 0.00% 71.75% # Class of executed instruction 471system.cpu0.op_class::SimdMult 0 0.00% 71.75% # Class of executed instruction 472system.cpu0.op_class::SimdMultAcc 0 0.00% 71.75% # Class of executed instruction 473system.cpu0.op_class::SimdShift 0 0.00% 71.75% # Class of executed instruction 474system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.75% # Class of executed instruction 475system.cpu0.op_class::SimdSqrt 0 0.00% 71.75% # Class of executed instruction 476system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.75% # Class of executed instruction 477system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.75% # Class of executed instruction 478system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.75% # Class of executed instruction 479system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.75% # Class of executed instruction 480system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.75% # Class of executed instruction 481system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Class of executed instruction 482system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction 483system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction 484system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction 485system.cpu0.op_class::MemRead 7616501 16.09% 87.85% # Class of executed instruction 486system.cpu0.op_class::MemWrite 5023484 10.61% 98.46% # Class of executed instruction 487system.cpu0.op_class::IprAccess 727686 1.54% 100.00% # Class of executed instruction 488system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 489system.cpu0.op_class::total 47325062 # Class of executed instruction 490system.cpu0.dcache.tags.replacements 1172723 # number of replacements 491system.cpu0.dcache.tags.tagsinuse 505.333527 # Cycle average of tags in use 492system.cpu0.dcache.tags.total_refs 11236927 # Total number of references to valid blocks. 493system.cpu0.dcache.tags.sampled_refs 1173142 # Sample count of references to valid blocks. 494system.cpu0.dcache.tags.avg_refs 9.578488 # Average number of references to valid blocks. 495system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. 496system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333527 # Average occupied blocks per requestor 497system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy 498system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy 499system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id 500system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 501system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id 502system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id 503system.cpu0.dcache.tags.tag_accesses 50908342 # Number of tag accesses 504system.cpu0.dcache.tags.data_accesses 50908342 # Number of data accesses 505system.cpu0.dcache.ReadReq_hits::cpu0.data 6342787 # number of ReadReq hits 506system.cpu0.dcache.ReadReq_hits::total 6342787 # number of ReadReq hits 507system.cpu0.dcache.WriteReq_hits::cpu0.data 4601077 # number of WriteReq hits 508system.cpu0.dcache.WriteReq_hits::total 4601077 # number of WriteReq hits 509system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138129 # number of LoadLockedReq hits 510system.cpu0.dcache.LoadLockedReq_hits::total 138129 # number of LoadLockedReq hits 511system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145434 # number of StoreCondReq hits 512system.cpu0.dcache.StoreCondReq_hits::total 145434 # number of StoreCondReq hits 513system.cpu0.dcache.demand_hits::cpu0.data 10943864 # number of demand (read+write) hits 514system.cpu0.dcache.demand_hits::total 10943864 # number of demand (read+write) hits 515system.cpu0.dcache.overall_hits::cpu0.data 10943864 # number of overall hits 516system.cpu0.dcache.overall_hits::total 10943864 # number of overall hits 517system.cpu0.dcache.ReadReq_misses::cpu0.data 934179 # number of ReadReq misses 518system.cpu0.dcache.ReadReq_misses::total 934179 # number of ReadReq misses 519system.cpu0.dcache.WriteReq_misses::cpu0.data 249076 # number of WriteReq misses 520system.cpu0.dcache.WriteReq_misses::total 249076 # number of WriteReq misses 521system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses 522system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses 523system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses 524system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses 525system.cpu0.dcache.demand_misses::cpu0.data 1183255 # number of demand (read+write) misses 526system.cpu0.dcache.demand_misses::total 1183255 # number of demand (read+write) misses 527system.cpu0.dcache.overall_misses::cpu0.data 1183255 # number of overall misses 528system.cpu0.dcache.overall_misses::total 1183255 # number of overall misses 529system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42885164500 # number of ReadReq miss cycles 530system.cpu0.dcache.ReadReq_miss_latency::total 42885164500 # number of ReadReq miss cycles 531system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793601000 # number of WriteReq miss cycles 532system.cpu0.dcache.WriteReq_miss_latency::total 16793601000 # number of WriteReq miss cycles 533system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151515500 # number of LoadLockedReq miss cycles 534system.cpu0.dcache.LoadLockedReq_miss_latency::total 151515500 # number of LoadLockedReq miss cycles 535system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 94785500 # number of StoreCondReq miss cycles 536system.cpu0.dcache.StoreCondReq_miss_latency::total 94785500 # number of StoreCondReq miss cycles 537system.cpu0.dcache.demand_miss_latency::cpu0.data 59678765500 # number of demand (read+write) miss cycles 538system.cpu0.dcache.demand_miss_latency::total 59678765500 # number of demand (read+write) miss cycles 539system.cpu0.dcache.overall_miss_latency::cpu0.data 59678765500 # number of overall miss cycles 540system.cpu0.dcache.overall_miss_latency::total 59678765500 # number of overall miss cycles 541system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276966 # number of ReadReq accesses(hits+misses) 542system.cpu0.dcache.ReadReq_accesses::total 7276966 # number of ReadReq accesses(hits+misses) 543system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850153 # number of WriteReq accesses(hits+misses) 544system.cpu0.dcache.WriteReq_accesses::total 4850153 # number of WriteReq accesses(hits+misses) 545system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151707 # number of LoadLockedReq accesses(hits+misses) 546system.cpu0.dcache.LoadLockedReq_accesses::total 151707 # number of LoadLockedReq accesses(hits+misses) 547system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151173 # number of StoreCondReq accesses(hits+misses) 548system.cpu0.dcache.StoreCondReq_accesses::total 151173 # number of StoreCondReq accesses(hits+misses) 549system.cpu0.dcache.demand_accesses::cpu0.data 12127119 # number of demand (read+write) accesses 550system.cpu0.dcache.demand_accesses::total 12127119 # number of demand (read+write) accesses 551system.cpu0.dcache.overall_accesses::cpu0.data 12127119 # number of overall (read+write) accesses 552system.cpu0.dcache.overall_accesses::total 12127119 # number of overall (read+write) accesses 553system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128375 # miss rate for ReadReq accesses 554system.cpu0.dcache.ReadReq_miss_rate::total 0.128375 # miss rate for ReadReq accesses 555system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051354 # miss rate for WriteReq accesses 556system.cpu0.dcache.WriteReq_miss_rate::total 0.051354 # miss rate for WriteReq accesses 557system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089501 # miss rate for LoadLockedReq accesses 558system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089501 # miss rate for LoadLockedReq accesses 559system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037963 # miss rate for StoreCondReq accesses 560system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037963 # miss rate for StoreCondReq accesses 561system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097571 # miss rate for demand accesses 562system.cpu0.dcache.demand_miss_rate::total 0.097571 # miss rate for demand accesses 563system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097571 # miss rate for overall accesses 564system.cpu0.dcache.overall_miss_rate::total 0.097571 # miss rate for overall accesses 565system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.795700 # average ReadReq miss latency 566system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.795700 # average ReadReq miss latency 567system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67423.601632 # average WriteReq miss latency 568system.cpu0.dcache.WriteReq_avg_miss_latency::total 67423.601632 # average WriteReq miss latency 569system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11158.896745 # average LoadLockedReq miss latency 570system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11158.896745 # average LoadLockedReq miss latency 571system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16516.030667 # average StoreCondReq miss latency 572system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16516.030667 # average StoreCondReq miss latency 573system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency 574system.cpu0.dcache.demand_avg_miss_latency::total 50436.098305 # average overall miss latency 575system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency 576system.cpu0.dcache.overall_avg_miss_latency::total 50436.098305 # average overall miss latency 577system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 578system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 579system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 580system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 581system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 582system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
583system.cpu0.dcache.fast_writes 0 # number of fast writes performed 584system.cpu0.dcache.cache_copies 0 # number of cache copies performed
585system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks 586system.cpu0.dcache.writebacks::total 672790 # number of writebacks 587system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses 588system.cpu0.dcache.ReadReq_mshr_misses::total 934179 # number of ReadReq MSHR misses 589system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249076 # number of WriteReq MSHR misses 590system.cpu0.dcache.WriteReq_mshr_misses::total 249076 # number of WriteReq MSHR misses 591system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses 592system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses 593system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5739 # number of StoreCondReq MSHR misses 594system.cpu0.dcache.StoreCondReq_mshr_misses::total 5739 # number of StoreCondReq MSHR misses 595system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183255 # number of demand (read+write) MSHR misses 596system.cpu0.dcache.demand_mshr_misses::total 1183255 # number of demand (read+write) MSHR misses 597system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183255 # number of overall MSHR misses 598system.cpu0.dcache.overall_mshr_misses::total 1183255 # number of overall MSHR misses 599system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7083 # number of ReadReq MSHR uncacheable 600system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7083 # number of ReadReq MSHR uncacheable 601system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10783 # number of WriteReq MSHR uncacheable 602system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10783 # number of WriteReq MSHR uncacheable 603system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17866 # number of overall MSHR uncacheable misses 604system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17866 # number of overall MSHR uncacheable misses 605system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41950985500 # number of ReadReq MSHR miss cycles 606system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41950985500 # number of ReadReq MSHR miss cycles 607system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544525000 # number of WriteReq MSHR miss cycles 608system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544525000 # number of WriteReq MSHR miss cycles 609system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137937500 # number of LoadLockedReq MSHR miss cycles 610system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137937500 # number of LoadLockedReq MSHR miss cycles 611system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89046500 # number of StoreCondReq MSHR miss cycles 612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89046500 # number of StoreCondReq MSHR miss cycles 613system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58495510500 # number of demand (read+write) MSHR miss cycles 614system.cpu0.dcache.demand_mshr_miss_latency::total 58495510500 # number of demand (read+write) MSHR miss cycles 615system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 # number of overall MSHR miss cycles 616system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles 617system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles 618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles	583system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks 584system.cpu0.dcache.writebacks::total 672790 # number of writebacks 585system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses 586system.cpu0.dcache.ReadReq_mshr_misses::total 934179 # number of ReadReq MSHR misses 587system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249076 # number of WriteReq MSHR misses 588system.cpu0.dcache.WriteReq_mshr_misses::total 249076 # number of WriteReq MSHR misses 589system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses 590system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses 591system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5739 # number of StoreCondReq MSHR misses 592system.cpu0.dcache.StoreCondReq_mshr_misses::total 5739 # number of StoreCondReq MSHR misses 593system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183255 # number of demand (read+write) MSHR misses 594system.cpu0.dcache.demand_mshr_misses::total 1183255 # number of demand (read+write) MSHR misses 595system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183255 # number of overall MSHR misses 596system.cpu0.dcache.overall_mshr_misses::total 1183255 # number of overall MSHR misses 597system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7083 # number of ReadReq MSHR uncacheable 598system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7083 # number of ReadReq MSHR uncacheable 599system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10783 # number of WriteReq MSHR uncacheable 600system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10783 # number of WriteReq MSHR uncacheable 601system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17866 # number of overall MSHR uncacheable misses 602system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17866 # number of overall MSHR uncacheable misses 603system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41950985500 # number of ReadReq MSHR miss cycles 604system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41950985500 # number of ReadReq MSHR miss cycles 605system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544525000 # number of WriteReq MSHR miss cycles 606system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544525000 # number of WriteReq MSHR miss cycles 607system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137937500 # number of LoadLockedReq MSHR miss cycles 608system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137937500 # number of LoadLockedReq MSHR miss cycles 609system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89046500 # number of StoreCondReq MSHR miss cycles 610system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89046500 # number of StoreCondReq MSHR miss cycles 611system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58495510500 # number of demand (read+write) MSHR miss cycles 612system.cpu0.dcache.demand_mshr_miss_latency::total 58495510500 # number of demand (read+write) MSHR miss cycles 613system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 # number of overall MSHR miss cycles 614system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles 615system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles 616system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles
619system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451870500 # number of WriteReq MSHR uncacheable cycles 620system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451870500 # number of WriteReq MSHR uncacheable cycles 621system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4018772500 # number of overall MSHR uncacheable cycles 622system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4018772500 # number of overall MSHR uncacheable cycles	617system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566902000 # number of overall MSHR uncacheable cycles 618system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566902000 # number of overall MSHR uncacheable cycles
623system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses 624system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses 625system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses 626system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051354 # mshr miss rate for WriteReq accesses 627system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089501 # mshr miss rate for LoadLockedReq accesses 628system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089501 # mshr miss rate for LoadLockedReq accesses 629system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses 630system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses 631system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for demand accesses 632system.cpu0.dcache.demand_mshr_miss_rate::total 0.097571 # mshr miss rate for demand accesses 633system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for overall accesses 634system.cpu0.dcache.overall_mshr_miss_rate::total 0.097571 # mshr miss rate for overall accesses 635system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.795700 # average ReadReq mshr miss latency 636system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.795700 # average ReadReq mshr miss latency 637system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66423.601632 # average WriteReq mshr miss latency 638system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66423.601632 # average WriteReq mshr miss latency 639system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10158.896745 # average LoadLockedReq mshr miss latency 640system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10158.896745 # average LoadLockedReq mshr miss latency 641system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15516.030667 # average StoreCondReq mshr miss latency 642system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15516.030667 # average StoreCondReq mshr miss latency 643system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency 644system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency 645system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency 646system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency 647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency 648system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency	619system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses 620system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses 621system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses 622system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051354 # mshr miss rate for WriteReq accesses 623system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089501 # mshr miss rate for LoadLockedReq accesses 624system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089501 # mshr miss rate for LoadLockedReq accesses 625system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses 626system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses 627system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for demand accesses 628system.cpu0.dcache.demand_mshr_miss_rate::total 0.097571 # mshr miss rate for demand accesses 629system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for overall accesses 630system.cpu0.dcache.overall_mshr_miss_rate::total 0.097571 # mshr miss rate for overall accesses 631system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.795700 # average ReadReq mshr miss latency 632system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.795700 # average ReadReq mshr miss latency 633system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66423.601632 # average WriteReq mshr miss latency 634system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66423.601632 # average WriteReq mshr miss latency 635system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10158.896745 # average LoadLockedReq mshr miss latency 636system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10158.896745 # average LoadLockedReq mshr miss latency 637system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15516.030667 # average StoreCondReq mshr miss latency 638system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15516.030667 # average StoreCondReq mshr miss latency 639system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency 640system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency 641system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency 642system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency 643system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency 644system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency
649system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925 # average WriteReq mshr uncacheable latency 650system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925 # average WriteReq mshr uncacheable latency 651system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914 # average overall mshr uncacheable latency 652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914 # average overall mshr uncacheable latency 653system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate	645system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306 # average overall mshr uncacheable latency 646system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306 # average overall mshr uncacheable latency
654system.cpu0.icache.tags.replacements 686545 # number of replacements 655system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use 656system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks. 657system.cpu0.icache.tags.sampled_refs 687057 # Sample count of references to valid blocks. 658system.cpu0.icache.tags.avg_refs 67.880661 # Average number of references to valid blocks. 659system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. 660system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490868 # Average occupied blocks per requestor 661system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy 662system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy 663system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 664system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id 665system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id 666system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 667system.cpu0.icache.tags.tag_accesses 48012241 # Number of tag accesses 668system.cpu0.icache.tags.data_accesses 48012241 # Number of data accesses 669system.cpu0.icache.ReadReq_hits::cpu0.inst 46637883 # number of ReadReq hits 670system.cpu0.icache.ReadReq_hits::total 46637883 # number of ReadReq hits 671system.cpu0.icache.demand_hits::cpu0.inst 46637883 # number of demand (read+write) hits 672system.cpu0.icache.demand_hits::total 46637883 # number of demand (read+write) hits 673system.cpu0.icache.overall_hits::cpu0.inst 46637883 # number of overall hits 674system.cpu0.icache.overall_hits::total 46637883 # number of overall hits 675system.cpu0.icache.ReadReq_misses::cpu0.inst 687179 # number of ReadReq misses 676system.cpu0.icache.ReadReq_misses::total 687179 # number of ReadReq misses 677system.cpu0.icache.demand_misses::cpu0.inst 687179 # number of demand (read+write) misses 678system.cpu0.icache.demand_misses::total 687179 # number of demand (read+write) misses 679system.cpu0.icache.overall_misses::cpu0.inst 687179 # number of overall misses 680system.cpu0.icache.overall_misses::total 687179 # number of overall misses 681system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10623000500 # number of ReadReq miss cycles 682system.cpu0.icache.ReadReq_miss_latency::total 10623000500 # number of ReadReq miss cycles 683system.cpu0.icache.demand_miss_latency::cpu0.inst 10623000500 # number of demand (read+write) miss cycles 684system.cpu0.icache.demand_miss_latency::total 10623000500 # number of demand (read+write) miss cycles 685system.cpu0.icache.overall_miss_latency::cpu0.inst 10623000500 # number of overall miss cycles 686system.cpu0.icache.overall_miss_latency::total 10623000500 # number of overall miss cycles 687system.cpu0.icache.ReadReq_accesses::cpu0.inst 47325062 # number of ReadReq accesses(hits+misses) 688system.cpu0.icache.ReadReq_accesses::total 47325062 # number of ReadReq accesses(hits+misses) 689system.cpu0.icache.demand_accesses::cpu0.inst 47325062 # number of demand (read+write) accesses 690system.cpu0.icache.demand_accesses::total 47325062 # number of demand (read+write) accesses 691system.cpu0.icache.overall_accesses::cpu0.inst 47325062 # number of overall (read+write) accesses 692system.cpu0.icache.overall_accesses::total 47325062 # number of overall (read+write) accesses 693system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses 694system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses 695system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses 696system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses 697system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses 698system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses 699system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15458.854971 # average ReadReq miss latency 700system.cpu0.icache.ReadReq_avg_miss_latency::total 15458.854971 # average ReadReq miss latency 701system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency 702system.cpu0.icache.demand_avg_miss_latency::total 15458.854971 # average overall miss latency 703system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency 704system.cpu0.icache.overall_avg_miss_latency::total 15458.854971 # average overall miss latency 705system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 706system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 707system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 708system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 709system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 710system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	647system.cpu0.icache.tags.replacements 686545 # number of replacements 648system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use 649system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks. 650system.cpu0.icache.tags.sampled_refs 687057 # Sample count of references to valid blocks. 651system.cpu0.icache.tags.avg_refs 67.880661 # Average number of references to valid blocks. 652system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. 653system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490868 # Average occupied blocks per requestor 654system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy 655system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy 656system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 657system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id 658system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id 659system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 660system.cpu0.icache.tags.tag_accesses 48012241 # Number of tag accesses 661system.cpu0.icache.tags.data_accesses 48012241 # Number of data accesses 662system.cpu0.icache.ReadReq_hits::cpu0.inst 46637883 # number of ReadReq hits 663system.cpu0.icache.ReadReq_hits::total 46637883 # number of ReadReq hits 664system.cpu0.icache.demand_hits::cpu0.inst 46637883 # number of demand (read+write) hits 665system.cpu0.icache.demand_hits::total 46637883 # number of demand (read+write) hits 666system.cpu0.icache.overall_hits::cpu0.inst 46637883 # number of overall hits 667system.cpu0.icache.overall_hits::total 46637883 # number of overall hits 668system.cpu0.icache.ReadReq_misses::cpu0.inst 687179 # number of ReadReq misses 669system.cpu0.icache.ReadReq_misses::total 687179 # number of ReadReq misses 670system.cpu0.icache.demand_misses::cpu0.inst 687179 # number of demand (read+write) misses 671system.cpu0.icache.demand_misses::total 687179 # number of demand (read+write) misses 672system.cpu0.icache.overall_misses::cpu0.inst 687179 # number of overall misses 673system.cpu0.icache.overall_misses::total 687179 # number of overall misses 674system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10623000500 # number of ReadReq miss cycles 675system.cpu0.icache.ReadReq_miss_latency::total 10623000500 # number of ReadReq miss cycles 676system.cpu0.icache.demand_miss_latency::cpu0.inst 10623000500 # number of demand (read+write) miss cycles 677system.cpu0.icache.demand_miss_latency::total 10623000500 # number of demand (read+write) miss cycles 678system.cpu0.icache.overall_miss_latency::cpu0.inst 10623000500 # number of overall miss cycles 679system.cpu0.icache.overall_miss_latency::total 10623000500 # number of overall miss cycles 680system.cpu0.icache.ReadReq_accesses::cpu0.inst 47325062 # number of ReadReq accesses(hits+misses) 681system.cpu0.icache.ReadReq_accesses::total 47325062 # number of ReadReq accesses(hits+misses) 682system.cpu0.icache.demand_accesses::cpu0.inst 47325062 # number of demand (read+write) accesses 683system.cpu0.icache.demand_accesses::total 47325062 # number of demand (read+write) accesses 684system.cpu0.icache.overall_accesses::cpu0.inst 47325062 # number of overall (read+write) accesses 685system.cpu0.icache.overall_accesses::total 47325062 # number of overall (read+write) accesses 686system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses 687system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses 688system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses 689system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses 690system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses 691system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses 692system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15458.854971 # average ReadReq miss latency 693system.cpu0.icache.ReadReq_avg_miss_latency::total 15458.854971 # average ReadReq miss latency 694system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency 695system.cpu0.icache.demand_avg_miss_latency::total 15458.854971 # average overall miss latency 696system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency 697system.cpu0.icache.overall_avg_miss_latency::total 15458.854971 # average overall miss latency 698system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 699system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 700system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 701system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 702system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 703system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
711system.cpu0.icache.fast_writes 0 # number of fast writes performed 712system.cpu0.icache.cache_copies 0 # number of cache copies performed
713system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks 714system.cpu0.icache.writebacks::total 686545 # number of writebacks 715system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses 716system.cpu0.icache.ReadReq_mshr_misses::total 687179 # number of ReadReq MSHR misses 717system.cpu0.icache.demand_mshr_misses::cpu0.inst 687179 # number of demand (read+write) MSHR misses 718system.cpu0.icache.demand_mshr_misses::total 687179 # number of demand (read+write) MSHR misses 719system.cpu0.icache.overall_mshr_misses::cpu0.inst 687179 # number of overall MSHR misses 720system.cpu0.icache.overall_mshr_misses::total 687179 # number of overall MSHR misses 721system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9935821500 # number of ReadReq MSHR miss cycles 722system.cpu0.icache.ReadReq_mshr_miss_latency::total 9935821500 # number of ReadReq MSHR miss cycles 723system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9935821500 # number of demand (read+write) MSHR miss cycles 724system.cpu0.icache.demand_mshr_miss_latency::total 9935821500 # number of demand (read+write) MSHR miss cycles 725system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9935821500 # number of overall MSHR miss cycles 726system.cpu0.icache.overall_mshr_miss_latency::total 9935821500 # number of overall MSHR miss cycles 727system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses 728system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses 729system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses 730system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses 731system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses 732system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses 733system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average ReadReq mshr miss latency 734system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14458.854971 # average ReadReq mshr miss latency 735system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency 736system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency 737system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency 738system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency	704system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks 705system.cpu0.icache.writebacks::total 686545 # number of writebacks 706system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses 707system.cpu0.icache.ReadReq_mshr_misses::total 687179 # number of ReadReq MSHR misses 708system.cpu0.icache.demand_mshr_misses::cpu0.inst 687179 # number of demand (read+write) MSHR misses 709system.cpu0.icache.demand_mshr_misses::total 687179 # number of demand (read+write) MSHR misses 710system.cpu0.icache.overall_mshr_misses::cpu0.inst 687179 # number of overall MSHR misses 711system.cpu0.icache.overall_mshr_misses::total 687179 # number of overall MSHR misses 712system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9935821500 # number of ReadReq MSHR miss cycles 713system.cpu0.icache.ReadReq_mshr_miss_latency::total 9935821500 # number of ReadReq MSHR miss cycles 714system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9935821500 # number of demand (read+write) MSHR miss cycles 715system.cpu0.icache.demand_mshr_miss_latency::total 9935821500 # number of demand (read+write) MSHR miss cycles 716system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9935821500 # number of overall MSHR miss cycles 717system.cpu0.icache.overall_mshr_miss_latency::total 9935821500 # number of overall MSHR miss cycles 718system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses 719system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses 720system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses 721system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses 722system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses 723system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses 724system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average ReadReq mshr miss latency 725system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14458.854971 # average ReadReq mshr miss latency 726system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency 727system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency 728system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency 729system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency
739system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
740system.cpu1.dtb.fetch_hits 0 # ITB hits 741system.cpu1.dtb.fetch_misses 0 # ITB misses 742system.cpu1.dtb.fetch_acv 0 # ITB acv 743system.cpu1.dtb.fetch_accesses 0 # ITB accesses 744system.cpu1.dtb.read_hits 2511191 # DTB read hits 745system.cpu1.dtb.read_misses 2993 # DTB read misses 746system.cpu1.dtb.read_acv 0 # DTB read access violations 747system.cpu1.dtb.read_accesses 239364 # DTB read accesses 748system.cpu1.dtb.write_hits 1830032 # DTB write hits 749system.cpu1.dtb.write_misses 342 # DTB write misses 750system.cpu1.dtb.write_acv 29 # DTB write access violations 751system.cpu1.dtb.write_accesses 105248 # DTB write accesses 752system.cpu1.dtb.data_hits 4341223 # DTB hits 753system.cpu1.dtb.data_misses 3335 # DTB misses 754system.cpu1.dtb.data_acv 29 # DTB access violations 755system.cpu1.dtb.data_accesses 344612 # DTB accesses 756system.cpu1.itb.fetch_hits 1990291 # ITB hits 757system.cpu1.itb.fetch_misses 1216 # ITB misses 758system.cpu1.itb.fetch_acv 0 # ITB acv 759system.cpu1.itb.fetch_accesses 1991507 # ITB accesses 760system.cpu1.itb.read_hits 0 # DTB read hits 761system.cpu1.itb.read_misses 0 # DTB read misses 762system.cpu1.itb.read_acv 0 # DTB read access violations 763system.cpu1.itb.read_accesses 0 # DTB read accesses 764system.cpu1.itb.write_hits 0 # DTB write hits 765system.cpu1.itb.write_misses 0 # DTB write misses 766system.cpu1.itb.write_acv 0 # DTB write access violations 767system.cpu1.itb.write_accesses 0 # DTB write accesses 768system.cpu1.itb.data_hits 0 # DTB hits 769system.cpu1.itb.data_misses 0 # DTB misses 770system.cpu1.itb.data_acv 0 # DTB access violations 771system.cpu1.itb.data_accesses 0 # DTB accesses 772system.cpu1.numCycles 3965185472 # number of cpu cycles simulated 773system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 774system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 775system.cpu1.kern.inst.arm 0 # number of arm instructions executed 776system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed 777system.cpu1.kern.inst.hwrei 81049 # number of hwrei instructions executed 778system.cpu1.kern.ipl_count::0 27547 38.53% 38.53% # number of times we switched to this ipl 779system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl 780system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl 781system.cpu1.kern.ipl_count::31 41462 57.99% 100.00% # number of times we switched to this ipl 782system.cpu1.kern.ipl_count::total 71504 # number of times we switched to this ipl 783system.cpu1.kern.ipl_good::0 26679 48.22% 48.22% # number of times we switched to this ipl from a different ipl 784system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl 785system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl 786system.cpu1.kern.ipl_good::31 26155 47.27% 100.00% # number of times we switched to this ipl from a different ipl 787system.cpu1.kern.ipl_good::total 55329 # number of times we switched to this ipl from a different ipl 788system.cpu1.kern.ipl_ticks::0 1912239584500 96.45% 96.45% # number of cycles we spent at this ipl 789system.cpu1.kern.ipl_ticks::22 731206500 0.04% 96.49% # number of cycles we spent at this ipl 790system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl 791system.cpu1.kern.ipl_ticks::31 69246698500 3.49% 100.00% # number of cycles we spent at this ipl 792system.cpu1.kern.ipl_ticks::total 1982591999000 # number of cycles we spent at this ipl 793system.cpu1.kern.ipl_used::0 0.968490 # fraction of swpipl calls that actually changed the ipl 794system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 795system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 796system.cpu1.kern.ipl_used::31 0.630819 # fraction of swpipl calls that actually changed the ipl 797system.cpu1.kern.ipl_used::total 0.773789 # fraction of swpipl calls that actually changed the ipl 798system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 799system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 800system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 801system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 802system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 803system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 804system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 805system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 806system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 807system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 808system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 809system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 810system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 811system.cpu1.kern.syscall::total 104 # number of syscalls executed 812system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 813system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed 814system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 815system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 816system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed 817system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed 818system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed 819system.cpu1.kern.callpal::swpipl 65182 88.12% 91.52% # number of callpals executed 820system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed 821system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed 822system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed 823system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed 824system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # number of callpals executed 825system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed 826system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 827system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 828system.cpu1.kern.callpal::total 73972 # number of callpals executed 829system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches 830system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 831system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches 832system.cpu1.kern.mode_good::kernel 912 833system.cpu1.kern.mode_good::user 464 834system.cpu1.kern.mode_good::idle 448 835system.cpu1.kern.mode_switch_good::kernel 0.431206 # fraction of useful protection mode switches 836system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 837system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches 838system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches 839system.cpu1.kern.mode_ticks::kernel 19469811000 0.98% 0.98% # number of ticks spent at the given mode 840system.cpu1.kern.mode_ticks::user 1729387000 0.09% 1.07% # number of ticks spent at the given mode 841system.cpu1.kern.mode_ticks::idle 1961392799000 98.93% 100.00% # number of ticks spent at the given mode 842system.cpu1.kern.swap_context 2067 # number of times the context was actually changed 843system.cpu1.committedInsts 13686745 # Number of instructions committed 844system.cpu1.committedOps 13686745 # Number of ops (including micro ops) committed 845system.cpu1.num_int_alu_accesses 12624358 # Number of integer alu accesses 846system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses 847system.cpu1.num_func_calls 430170 # number of times a function call or return occured 848system.cpu1.num_conditional_control_insts 1359717 # number of instructions that are conditional controls 849system.cpu1.num_int_insts 12624358 # number of integer instructions 850system.cpu1.num_fp_insts 178612 # number of float instructions 851system.cpu1.num_int_register_reads 17383561 # number of times the integer registers were read 852system.cpu1.num_int_register_writes 9260404 # number of times the integer registers were written 853system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read 854system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written 855system.cpu1.num_mem_refs 4365379 # number of memory refs 856system.cpu1.num_load_insts 2525846 # Number of load instructions 857system.cpu1.num_store_insts 1839533 # Number of store instructions 858system.cpu1.num_idle_cycles 3912234287.998026 # Number of idle cycles 859system.cpu1.num_busy_cycles 52951184.001973 # Number of busy cycles 860system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles 861system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles 862system.cpu1.Branches 1950147 # Number of branches fetched 863system.cpu1.op_class::No_OpClass 733822 5.36% 5.36% # Class of executed instruction 864system.cpu1.op_class::IntAlu 8101444 59.18% 64.54% # Class of executed instruction 865system.cpu1.op_class::IntMult 23186 0.17% 64.71% # Class of executed instruction 866system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction 867system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction 868system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction 869system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction 870system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction 871system.cpu1.op_class::FloatDiv 1986 0.01% 64.83% # Class of executed instruction 872system.cpu1.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction 873system.cpu1.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction 874system.cpu1.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction 875system.cpu1.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction 876system.cpu1.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction 877system.cpu1.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction 878system.cpu1.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction 879system.cpu1.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction 880system.cpu1.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction 881system.cpu1.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction 882system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction 883system.cpu1.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction 884system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction 885system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction 886system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction 887system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction 888system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction 889system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Class of executed instruction 890system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction 891system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction 892system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction 893system.cpu1.op_class::MemRead 2600523 19.00% 83.82% # Class of executed instruction 894system.cpu1.op_class::MemWrite 1840557 13.44% 97.27% # Class of executed instruction 895system.cpu1.op_class::IprAccess 374219 2.73% 100.00% # Class of executed instruction 896system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 897system.cpu1.op_class::total 13690109 # Class of executed instruction 898system.cpu1.dcache.tags.replacements 173692 # number of replacements 899system.cpu1.dcache.tags.tagsinuse 481.984896 # Cycle average of tags in use 900system.cpu1.dcache.tags.total_refs 4164965 # Total number of references to valid blocks. 901system.cpu1.dcache.tags.sampled_refs 174204 # Sample count of references to valid blocks. 902system.cpu1.dcache.tags.avg_refs 23.908550 # Average number of references to valid blocks. 903system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. 904system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.984896 # Average occupied blocks per requestor 905system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941377 # Average percentage of cache occupancy 906system.cpu1.dcache.tags.occ_percent::total 0.941377 # Average percentage of cache occupancy 907system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 908system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 909system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 910system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 911system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 912system.cpu1.dcache.tags.tag_accesses 17608650 # Number of tag accesses 913system.cpu1.dcache.tags.data_accesses 17608650 # Number of data accesses 914system.cpu1.dcache.ReadReq_hits::cpu1.data 2339562 # number of ReadReq hits 915system.cpu1.dcache.ReadReq_hits::total 2339562 # number of ReadReq hits 916system.cpu1.dcache.WriteReq_hits::cpu1.data 1707213 # number of WriteReq hits 917system.cpu1.dcache.WriteReq_hits::total 1707213 # number of WriteReq hits 918system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50427 # number of LoadLockedReq hits 919system.cpu1.dcache.LoadLockedReq_hits::total 50427 # number of LoadLockedReq hits 920system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53080 # number of StoreCondReq hits 921system.cpu1.dcache.StoreCondReq_hits::total 53080 # number of StoreCondReq hits 922system.cpu1.dcache.demand_hits::cpu1.data 4046775 # number of demand (read+write) hits 923system.cpu1.dcache.demand_hits::total 4046775 # number of demand (read+write) hits 924system.cpu1.dcache.overall_hits::cpu1.data 4046775 # number of overall hits 925system.cpu1.dcache.overall_hits::total 4046775 # number of overall hits 926system.cpu1.dcache.ReadReq_misses::cpu1.data 123491 # number of ReadReq misses 927system.cpu1.dcache.ReadReq_misses::total 123491 # number of ReadReq misses 928system.cpu1.dcache.WriteReq_misses::cpu1.data 65586 # number of WriteReq misses 929system.cpu1.dcache.WriteReq_misses::total 65586 # number of WriteReq misses 930system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9255 # number of LoadLockedReq misses 931system.cpu1.dcache.LoadLockedReq_misses::total 9255 # number of LoadLockedReq misses 932system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6109 # number of StoreCondReq misses 933system.cpu1.dcache.StoreCondReq_misses::total 6109 # number of StoreCondReq misses 934system.cpu1.dcache.demand_misses::cpu1.data 189077 # number of demand (read+write) misses 935system.cpu1.dcache.demand_misses::total 189077 # number of demand (read+write) misses 936system.cpu1.dcache.overall_misses::cpu1.data 189077 # number of overall misses 937system.cpu1.dcache.overall_misses::total 189077 # number of overall misses 938system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1555586500 # number of ReadReq miss cycles 939system.cpu1.dcache.ReadReq_miss_latency::total 1555586500 # number of ReadReq miss cycles 940system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1871475500 # number of WriteReq miss cycles 941system.cpu1.dcache.WriteReq_miss_latency::total 1871475500 # number of WriteReq miss cycles 942system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84845000 # number of LoadLockedReq miss cycles 943system.cpu1.dcache.LoadLockedReq_miss_latency::total 84845000 # number of LoadLockedReq miss cycles 944system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 96965500 # number of StoreCondReq miss cycles 945system.cpu1.dcache.StoreCondReq_miss_latency::total 96965500 # number of StoreCondReq miss cycles 946system.cpu1.dcache.demand_miss_latency::cpu1.data 3427062000 # number of demand (read+write) miss cycles 947system.cpu1.dcache.demand_miss_latency::total 3427062000 # number of demand (read+write) miss cycles 948system.cpu1.dcache.overall_miss_latency::cpu1.data 3427062000 # number of overall miss cycles 949system.cpu1.dcache.overall_miss_latency::total 3427062000 # number of overall miss cycles 950system.cpu1.dcache.ReadReq_accesses::cpu1.data 2463053 # number of ReadReq accesses(hits+misses) 951system.cpu1.dcache.ReadReq_accesses::total 2463053 # number of ReadReq accesses(hits+misses) 952system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772799 # number of WriteReq accesses(hits+misses) 953system.cpu1.dcache.WriteReq_accesses::total 1772799 # number of WriteReq accesses(hits+misses) 954system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59682 # number of LoadLockedReq accesses(hits+misses) 955system.cpu1.dcache.LoadLockedReq_accesses::total 59682 # number of LoadLockedReq accesses(hits+misses) 956system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59189 # number of StoreCondReq accesses(hits+misses) 957system.cpu1.dcache.StoreCondReq_accesses::total 59189 # number of StoreCondReq accesses(hits+misses) 958system.cpu1.dcache.demand_accesses::cpu1.data 4235852 # number of demand (read+write) accesses 959system.cpu1.dcache.demand_accesses::total 4235852 # number of demand (read+write) accesses 960system.cpu1.dcache.overall_accesses::cpu1.data 4235852 # number of overall (read+write) accesses 961system.cpu1.dcache.overall_accesses::total 4235852 # number of overall (read+write) accesses 962system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050137 # miss rate for ReadReq accesses 963system.cpu1.dcache.ReadReq_miss_rate::total 0.050137 # miss rate for ReadReq accesses 964system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036996 # miss rate for WriteReq accesses 965system.cpu1.dcache.WriteReq_miss_rate::total 0.036996 # miss rate for WriteReq accesses 966system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155072 # miss rate for LoadLockedReq accesses 967system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155072 # miss rate for LoadLockedReq accesses 968system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103212 # miss rate for StoreCondReq accesses 969system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103212 # miss rate for StoreCondReq accesses 970system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044637 # miss rate for demand accesses 971system.cpu1.dcache.demand_miss_rate::total 0.044637 # miss rate for demand accesses 972system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044637 # miss rate for overall accesses 973system.cpu1.dcache.overall_miss_rate::total 0.044637 # miss rate for overall accesses 974system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12596.760088 # average ReadReq miss latency 975system.cpu1.dcache.ReadReq_avg_miss_latency::total 12596.760088 # average ReadReq miss latency 976system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28534.679657 # average WriteReq miss latency 977system.cpu1.dcache.WriteReq_avg_miss_latency::total 28534.679657 # average WriteReq miss latency 978system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9167.477039 # average LoadLockedReq miss latency 979system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9167.477039 # average LoadLockedReq miss latency 980system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15872.565068 # average StoreCondReq miss latency 981system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15872.565068 # average StoreCondReq miss latency 982system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency 983system.cpu1.dcache.demand_avg_miss_latency::total 18125.218826 # average overall miss latency 984system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency 985system.cpu1.dcache.overall_avg_miss_latency::total 18125.218826 # average overall miss latency 986system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 987system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 988system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 989system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 990system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 991system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	730system.cpu1.dtb.fetch_hits 0 # ITB hits 731system.cpu1.dtb.fetch_misses 0 # ITB misses 732system.cpu1.dtb.fetch_acv 0 # ITB acv 733system.cpu1.dtb.fetch_accesses 0 # ITB accesses 734system.cpu1.dtb.read_hits 2511191 # DTB read hits 735system.cpu1.dtb.read_misses 2993 # DTB read misses 736system.cpu1.dtb.read_acv 0 # DTB read access violations 737system.cpu1.dtb.read_accesses 239364 # DTB read accesses 738system.cpu1.dtb.write_hits 1830032 # DTB write hits 739system.cpu1.dtb.write_misses 342 # DTB write misses 740system.cpu1.dtb.write_acv 29 # DTB write access violations 741system.cpu1.dtb.write_accesses 105248 # DTB write accesses 742system.cpu1.dtb.data_hits 4341223 # DTB hits 743system.cpu1.dtb.data_misses 3335 # DTB misses 744system.cpu1.dtb.data_acv 29 # DTB access violations 745system.cpu1.dtb.data_accesses 344612 # DTB accesses 746system.cpu1.itb.fetch_hits 1990291 # ITB hits 747system.cpu1.itb.fetch_misses 1216 # ITB misses 748system.cpu1.itb.fetch_acv 0 # ITB acv 749system.cpu1.itb.fetch_accesses 1991507 # ITB accesses 750system.cpu1.itb.read_hits 0 # DTB read hits 751system.cpu1.itb.read_misses 0 # DTB read misses 752system.cpu1.itb.read_acv 0 # DTB read access violations 753system.cpu1.itb.read_accesses 0 # DTB read accesses 754system.cpu1.itb.write_hits 0 # DTB write hits 755system.cpu1.itb.write_misses 0 # DTB write misses 756system.cpu1.itb.write_acv 0 # DTB write access violations 757system.cpu1.itb.write_accesses 0 # DTB write accesses 758system.cpu1.itb.data_hits 0 # DTB hits 759system.cpu1.itb.data_misses 0 # DTB misses 760system.cpu1.itb.data_acv 0 # DTB access violations 761system.cpu1.itb.data_accesses 0 # DTB accesses 762system.cpu1.numCycles 3965185472 # number of cpu cycles simulated 763system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 764system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 765system.cpu1.kern.inst.arm 0 # number of arm instructions executed 766system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed 767system.cpu1.kern.inst.hwrei 81049 # number of hwrei instructions executed 768system.cpu1.kern.ipl_count::0 27547 38.53% 38.53% # number of times we switched to this ipl 769system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl 770system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl 771system.cpu1.kern.ipl_count::31 41462 57.99% 100.00% # number of times we switched to this ipl 772system.cpu1.kern.ipl_count::total 71504 # number of times we switched to this ipl 773system.cpu1.kern.ipl_good::0 26679 48.22% 48.22% # number of times we switched to this ipl from a different ipl 774system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl 775system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl 776system.cpu1.kern.ipl_good::31 26155 47.27% 100.00% # number of times we switched to this ipl from a different ipl 777system.cpu1.kern.ipl_good::total 55329 # number of times we switched to this ipl from a different ipl 778system.cpu1.kern.ipl_ticks::0 1912239584500 96.45% 96.45% # number of cycles we spent at this ipl 779system.cpu1.kern.ipl_ticks::22 731206500 0.04% 96.49% # number of cycles we spent at this ipl 780system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl 781system.cpu1.kern.ipl_ticks::31 69246698500 3.49% 100.00% # number of cycles we spent at this ipl 782system.cpu1.kern.ipl_ticks::total 1982591999000 # number of cycles we spent at this ipl 783system.cpu1.kern.ipl_used::0 0.968490 # fraction of swpipl calls that actually changed the ipl 784system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 785system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 786system.cpu1.kern.ipl_used::31 0.630819 # fraction of swpipl calls that actually changed the ipl 787system.cpu1.kern.ipl_used::total 0.773789 # fraction of swpipl calls that actually changed the ipl 788system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed 789system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed 790system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed 791system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed 792system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed 793system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed 794system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed 795system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed 796system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed 797system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed 798system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed 799system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed 800system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed 801system.cpu1.kern.syscall::total 104 # number of syscalls executed 802system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 803system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed 804system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 805system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed 806system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed 807system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed 808system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed 809system.cpu1.kern.callpal::swpipl 65182 88.12% 91.52% # number of callpals executed 810system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed 811system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed 812system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed 813system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed 814system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # number of callpals executed 815system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed 816system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed 817system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 818system.cpu1.kern.callpal::total 73972 # number of callpals executed 819system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches 820system.cpu1.kern.mode_switch::user 464 # number of protection mode switches 821system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches 822system.cpu1.kern.mode_good::kernel 912 823system.cpu1.kern.mode_good::user 464 824system.cpu1.kern.mode_good::idle 448 825system.cpu1.kern.mode_switch_good::kernel 0.431206 # fraction of useful protection mode switches 826system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 827system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches 828system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches 829system.cpu1.kern.mode_ticks::kernel 19469811000 0.98% 0.98% # number of ticks spent at the given mode 830system.cpu1.kern.mode_ticks::user 1729387000 0.09% 1.07% # number of ticks spent at the given mode 831system.cpu1.kern.mode_ticks::idle 1961392799000 98.93% 100.00% # number of ticks spent at the given mode 832system.cpu1.kern.swap_context 2067 # number of times the context was actually changed 833system.cpu1.committedInsts 13686745 # Number of instructions committed 834system.cpu1.committedOps 13686745 # Number of ops (including micro ops) committed 835system.cpu1.num_int_alu_accesses 12624358 # Number of integer alu accesses 836system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses 837system.cpu1.num_func_calls 430170 # number of times a function call or return occured 838system.cpu1.num_conditional_control_insts 1359717 # number of instructions that are conditional controls 839system.cpu1.num_int_insts 12624358 # number of integer instructions 840system.cpu1.num_fp_insts 178612 # number of float instructions 841system.cpu1.num_int_register_reads 17383561 # number of times the integer registers were read 842system.cpu1.num_int_register_writes 9260404 # number of times the integer registers were written 843system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read 844system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written 845system.cpu1.num_mem_refs 4365379 # number of memory refs 846system.cpu1.num_load_insts 2525846 # Number of load instructions 847system.cpu1.num_store_insts 1839533 # Number of store instructions 848system.cpu1.num_idle_cycles 3912234287.998026 # Number of idle cycles 849system.cpu1.num_busy_cycles 52951184.001973 # Number of busy cycles 850system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles 851system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles 852system.cpu1.Branches 1950147 # Number of branches fetched 853system.cpu1.op_class::No_OpClass 733822 5.36% 5.36% # Class of executed instruction 854system.cpu1.op_class::IntAlu 8101444 59.18% 64.54% # Class of executed instruction 855system.cpu1.op_class::IntMult 23186 0.17% 64.71% # Class of executed instruction 856system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction 857system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction 858system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction 859system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction 860system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction 861system.cpu1.op_class::FloatDiv 1986 0.01% 64.83% # Class of executed instruction 862system.cpu1.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction 863system.cpu1.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction 864system.cpu1.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction 865system.cpu1.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction 866system.cpu1.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction 867system.cpu1.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction 868system.cpu1.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction 869system.cpu1.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction 870system.cpu1.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction 871system.cpu1.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction 872system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction 873system.cpu1.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction 874system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction 875system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction 876system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction 877system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction 878system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction 879system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Class of executed instruction 880system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction 881system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction 882system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction 883system.cpu1.op_class::MemRead 2600523 19.00% 83.82% # Class of executed instruction 884system.cpu1.op_class::MemWrite 1840557 13.44% 97.27% # Class of executed instruction 885system.cpu1.op_class::IprAccess 374219 2.73% 100.00% # Class of executed instruction 886system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 887system.cpu1.op_class::total 13690109 # Class of executed instruction 888system.cpu1.dcache.tags.replacements 173692 # number of replacements 889system.cpu1.dcache.tags.tagsinuse 481.984896 # Cycle average of tags in use 890system.cpu1.dcache.tags.total_refs 4164965 # Total number of references to valid blocks. 891system.cpu1.dcache.tags.sampled_refs 174204 # Sample count of references to valid blocks. 892system.cpu1.dcache.tags.avg_refs 23.908550 # Average number of references to valid blocks. 893system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. 894system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.984896 # Average occupied blocks per requestor 895system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941377 # Average percentage of cache occupancy 896system.cpu1.dcache.tags.occ_percent::total 0.941377 # Average percentage of cache occupancy 897system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 898system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 899system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 900system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 901system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 902system.cpu1.dcache.tags.tag_accesses 17608650 # Number of tag accesses 903system.cpu1.dcache.tags.data_accesses 17608650 # Number of data accesses 904system.cpu1.dcache.ReadReq_hits::cpu1.data 2339562 # number of ReadReq hits 905system.cpu1.dcache.ReadReq_hits::total 2339562 # number of ReadReq hits 906system.cpu1.dcache.WriteReq_hits::cpu1.data 1707213 # number of WriteReq hits 907system.cpu1.dcache.WriteReq_hits::total 1707213 # number of WriteReq hits 908system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50427 # number of LoadLockedReq hits 909system.cpu1.dcache.LoadLockedReq_hits::total 50427 # number of LoadLockedReq hits 910system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53080 # number of StoreCondReq hits 911system.cpu1.dcache.StoreCondReq_hits::total 53080 # number of StoreCondReq hits 912system.cpu1.dcache.demand_hits::cpu1.data 4046775 # number of demand (read+write) hits 913system.cpu1.dcache.demand_hits::total 4046775 # number of demand (read+write) hits 914system.cpu1.dcache.overall_hits::cpu1.data 4046775 # number of overall hits 915system.cpu1.dcache.overall_hits::total 4046775 # number of overall hits 916system.cpu1.dcache.ReadReq_misses::cpu1.data 123491 # number of ReadReq misses 917system.cpu1.dcache.ReadReq_misses::total 123491 # number of ReadReq misses 918system.cpu1.dcache.WriteReq_misses::cpu1.data 65586 # number of WriteReq misses 919system.cpu1.dcache.WriteReq_misses::total 65586 # number of WriteReq misses 920system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9255 # number of LoadLockedReq misses 921system.cpu1.dcache.LoadLockedReq_misses::total 9255 # number of LoadLockedReq misses 922system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6109 # number of StoreCondReq misses 923system.cpu1.dcache.StoreCondReq_misses::total 6109 # number of StoreCondReq misses 924system.cpu1.dcache.demand_misses::cpu1.data 189077 # number of demand (read+write) misses 925system.cpu1.dcache.demand_misses::total 189077 # number of demand (read+write) misses 926system.cpu1.dcache.overall_misses::cpu1.data 189077 # number of overall misses 927system.cpu1.dcache.overall_misses::total 189077 # number of overall misses 928system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1555586500 # number of ReadReq miss cycles 929system.cpu1.dcache.ReadReq_miss_latency::total 1555586500 # number of ReadReq miss cycles 930system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1871475500 # number of WriteReq miss cycles 931system.cpu1.dcache.WriteReq_miss_latency::total 1871475500 # number of WriteReq miss cycles 932system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84845000 # number of LoadLockedReq miss cycles 933system.cpu1.dcache.LoadLockedReq_miss_latency::total 84845000 # number of LoadLockedReq miss cycles 934system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 96965500 # number of StoreCondReq miss cycles 935system.cpu1.dcache.StoreCondReq_miss_latency::total 96965500 # number of StoreCondReq miss cycles 936system.cpu1.dcache.demand_miss_latency::cpu1.data 3427062000 # number of demand (read+write) miss cycles 937system.cpu1.dcache.demand_miss_latency::total 3427062000 # number of demand (read+write) miss cycles 938system.cpu1.dcache.overall_miss_latency::cpu1.data 3427062000 # number of overall miss cycles 939system.cpu1.dcache.overall_miss_latency::total 3427062000 # number of overall miss cycles 940system.cpu1.dcache.ReadReq_accesses::cpu1.data 2463053 # number of ReadReq accesses(hits+misses) 941system.cpu1.dcache.ReadReq_accesses::total 2463053 # number of ReadReq accesses(hits+misses) 942system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772799 # number of WriteReq accesses(hits+misses) 943system.cpu1.dcache.WriteReq_accesses::total 1772799 # number of WriteReq accesses(hits+misses) 944system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59682 # number of LoadLockedReq accesses(hits+misses) 945system.cpu1.dcache.LoadLockedReq_accesses::total 59682 # number of LoadLockedReq accesses(hits+misses) 946system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59189 # number of StoreCondReq accesses(hits+misses) 947system.cpu1.dcache.StoreCondReq_accesses::total 59189 # number of StoreCondReq accesses(hits+misses) 948system.cpu1.dcache.demand_accesses::cpu1.data 4235852 # number of demand (read+write) accesses 949system.cpu1.dcache.demand_accesses::total 4235852 # number of demand (read+write) accesses 950system.cpu1.dcache.overall_accesses::cpu1.data 4235852 # number of overall (read+write) accesses 951system.cpu1.dcache.overall_accesses::total 4235852 # number of overall (read+write) accesses 952system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050137 # miss rate for ReadReq accesses 953system.cpu1.dcache.ReadReq_miss_rate::total 0.050137 # miss rate for ReadReq accesses 954system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036996 # miss rate for WriteReq accesses 955system.cpu1.dcache.WriteReq_miss_rate::total 0.036996 # miss rate for WriteReq accesses 956system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155072 # miss rate for LoadLockedReq accesses 957system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155072 # miss rate for LoadLockedReq accesses 958system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103212 # miss rate for StoreCondReq accesses 959system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103212 # miss rate for StoreCondReq accesses 960system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044637 # miss rate for demand accesses 961system.cpu1.dcache.demand_miss_rate::total 0.044637 # miss rate for demand accesses 962system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044637 # miss rate for overall accesses 963system.cpu1.dcache.overall_miss_rate::total 0.044637 # miss rate for overall accesses 964system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12596.760088 # average ReadReq miss latency 965system.cpu1.dcache.ReadReq_avg_miss_latency::total 12596.760088 # average ReadReq miss latency 966system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28534.679657 # average WriteReq miss latency 967system.cpu1.dcache.WriteReq_avg_miss_latency::total 28534.679657 # average WriteReq miss latency 968system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9167.477039 # average LoadLockedReq miss latency 969system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9167.477039 # average LoadLockedReq miss latency 970system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15872.565068 # average StoreCondReq miss latency 971system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15872.565068 # average StoreCondReq miss latency 972system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency 973system.cpu1.dcache.demand_avg_miss_latency::total 18125.218826 # average overall miss latency 974system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency 975system.cpu1.dcache.overall_avg_miss_latency::total 18125.218826 # average overall miss latency 976system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 977system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 978system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 979system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 980system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 981system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
992system.cpu1.dcache.fast_writes 0 # number of fast writes performed 993system.cpu1.dcache.cache_copies 0 # number of cache copies performed
994system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks 995system.cpu1.dcache.writebacks::total 119726 # number of writebacks 996system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses 997system.cpu1.dcache.ReadReq_mshr_misses::total 123491 # number of ReadReq MSHR misses 998system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65586 # number of WriteReq MSHR misses 999system.cpu1.dcache.WriteReq_mshr_misses::total 65586 # number of WriteReq MSHR misses 1000system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9255 # number of LoadLockedReq MSHR misses 1001system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9255 # number of LoadLockedReq MSHR misses 1002system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6109 # number of StoreCondReq MSHR misses 1003system.cpu1.dcache.StoreCondReq_mshr_misses::total 6109 # number of StoreCondReq MSHR misses 1004system.cpu1.dcache.demand_mshr_misses::cpu1.data 189077 # number of demand (read+write) MSHR misses 1005system.cpu1.dcache.demand_mshr_misses::total 189077 # number of demand (read+write) MSHR misses 1006system.cpu1.dcache.overall_mshr_misses::cpu1.data 189077 # number of overall MSHR misses 1007system.cpu1.dcache.overall_mshr_misses::total 189077 # number of overall MSHR misses 1008system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable 1009system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable 1010system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable 1011system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3348 # number of WriteReq MSHR uncacheable 1012system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses 1013system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3466 # number of overall MSHR uncacheable misses 1014system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432095500 # number of ReadReq MSHR miss cycles 1015system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432095500 # number of ReadReq MSHR miss cycles 1016system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1805889500 # number of WriteReq MSHR miss cycles 1017system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805889500 # number of WriteReq MSHR miss cycles 1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75590000 # number of LoadLockedReq MSHR miss cycles 1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75590000 # number of LoadLockedReq MSHR miss cycles 1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90856500 # number of StoreCondReq MSHR miss cycles 1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90856500 # number of StoreCondReq MSHR miss cycles 1022system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237985000 # number of demand (read+write) MSHR miss cycles 1023system.cpu1.dcache.demand_mshr_miss_latency::total 3237985000 # number of demand (read+write) MSHR miss cycles 1024system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 # number of overall MSHR miss cycles 1025system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles 1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles 1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles	982system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks 983system.cpu1.dcache.writebacks::total 119726 # number of writebacks 984system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses 985system.cpu1.dcache.ReadReq_mshr_misses::total 123491 # number of ReadReq MSHR misses 986system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65586 # number of WriteReq MSHR misses 987system.cpu1.dcache.WriteReq_mshr_misses::total 65586 # number of WriteReq MSHR misses 988system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9255 # number of LoadLockedReq MSHR misses 989system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9255 # number of LoadLockedReq MSHR misses 990system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6109 # number of StoreCondReq MSHR misses 991system.cpu1.dcache.StoreCondReq_mshr_misses::total 6109 # number of StoreCondReq MSHR misses 992system.cpu1.dcache.demand_mshr_misses::cpu1.data 189077 # number of demand (read+write) MSHR misses 993system.cpu1.dcache.demand_mshr_misses::total 189077 # number of demand (read+write) MSHR misses 994system.cpu1.dcache.overall_mshr_misses::cpu1.data 189077 # number of overall MSHR misses 995system.cpu1.dcache.overall_mshr_misses::total 189077 # number of overall MSHR misses 996system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable 997system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable 998system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable 999system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3348 # number of WriteReq MSHR uncacheable 1000system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses 1001system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3466 # number of overall MSHR uncacheable misses 1002system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432095500 # number of ReadReq MSHR miss cycles 1003system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432095500 # number of ReadReq MSHR miss cycles 1004system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1805889500 # number of WriteReq MSHR miss cycles 1005system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805889500 # number of WriteReq MSHR miss cycles 1006system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75590000 # number of LoadLockedReq MSHR miss cycles 1007system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75590000 # number of LoadLockedReq MSHR miss cycles 1008system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90856500 # number of StoreCondReq MSHR miss cycles 1009system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90856500 # number of StoreCondReq MSHR miss cycles 1010system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237985000 # number of demand (read+write) MSHR miss cycles 1011system.cpu1.dcache.demand_mshr_miss_latency::total 3237985000 # number of demand (read+write) MSHR miss cycles 1012system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 # number of overall MSHR miss cycles 1013system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles 1014system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles 1015system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles
1028system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles 1029system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles 1030system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles 1031system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles	1016system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 25051000 # number of overall MSHR uncacheable cycles 1017system.cpu1.dcache.overall_mshr_uncacheable_latency::total 25051000 # number of overall MSHR uncacheable cycles
1032system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses 1033system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses 1034system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses 1035system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses 1036system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses 1037system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses 1038system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses 1039system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses 1040system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses 1041system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses 1042system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses 1043system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses 1044system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11596.760088 # average ReadReq mshr miss latency 1045system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11596.760088 # average ReadReq mshr miss latency 1046system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27534.679657 # average WriteReq mshr miss latency 1047system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27534.679657 # average WriteReq mshr miss latency 1048system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8167.477039 # average LoadLockedReq mshr miss latency 1049system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8167.477039 # average LoadLockedReq mshr miss latency 1050system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency 1051system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency 1052system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency 1053system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency 1054system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency 1055system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency 1056system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency 1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency	1018system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses 1019system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses 1020system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses 1021system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses 1022system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses 1023system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses 1024system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses 1025system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses 1026system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses 1027system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses 1028system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses 1029system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses 1030system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11596.760088 # average ReadReq mshr miss latency 1031system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11596.760088 # average ReadReq mshr miss latency 1032system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27534.679657 # average WriteReq mshr miss latency 1033system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27534.679657 # average WriteReq mshr miss latency 1034system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8167.477039 # average LoadLockedReq mshr miss latency 1035system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8167.477039 # average LoadLockedReq mshr miss latency 1036system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency 1037system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency 1038system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency 1039system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency 1040system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency 1041system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency 1042system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency 1043system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency
1058system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency 1059system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency 1060system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency 1061system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency 1062system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate	1044system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7227.639931 # average overall mshr uncacheable latency 1045system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7227.639931 # average overall mshr uncacheable latency
1063system.cpu1.icache.tags.replacements 331529 # number of replacements 1064system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use 1065system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks. 1066system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks. 1067system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks. 1068system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. 1069system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor 1070system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy 1071system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy 1072system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1073system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 1074system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 1075system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id 1076system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id 1077system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1078system.cpu1.icache.tags.tag_accesses 14022191 # Number of tag accesses 1079system.cpu1.icache.tags.data_accesses 14022191 # Number of data accesses 1080system.cpu1.icache.ReadReq_hits::cpu1.inst 13358029 # number of ReadReq hits 1081system.cpu1.icache.ReadReq_hits::total 13358029 # number of ReadReq hits 1082system.cpu1.icache.demand_hits::cpu1.inst 13358029 # number of demand (read+write) hits 1083system.cpu1.icache.demand_hits::total 13358029 # number of demand (read+write) hits 1084system.cpu1.icache.overall_hits::cpu1.inst 13358029 # number of overall hits 1085system.cpu1.icache.overall_hits::total 13358029 # number of overall hits 1086system.cpu1.icache.ReadReq_misses::cpu1.inst 332081 # number of ReadReq misses 1087system.cpu1.icache.ReadReq_misses::total 332081 # number of ReadReq misses 1088system.cpu1.icache.demand_misses::cpu1.inst 332081 # number of demand (read+write) misses 1089system.cpu1.icache.demand_misses::total 332081 # number of demand (read+write) misses 1090system.cpu1.icache.overall_misses::cpu1.inst 332081 # number of overall misses 1091system.cpu1.icache.overall_misses::total 332081 # number of overall misses 1092system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4540351000 # number of ReadReq miss cycles 1093system.cpu1.icache.ReadReq_miss_latency::total 4540351000 # number of ReadReq miss cycles 1094system.cpu1.icache.demand_miss_latency::cpu1.inst 4540351000 # number of demand (read+write) miss cycles 1095system.cpu1.icache.demand_miss_latency::total 4540351000 # number of demand (read+write) miss cycles 1096system.cpu1.icache.overall_miss_latency::cpu1.inst 4540351000 # number of overall miss cycles 1097system.cpu1.icache.overall_miss_latency::total 4540351000 # number of overall miss cycles 1098system.cpu1.icache.ReadReq_accesses::cpu1.inst 13690110 # number of ReadReq accesses(hits+misses) 1099system.cpu1.icache.ReadReq_accesses::total 13690110 # number of ReadReq accesses(hits+misses) 1100system.cpu1.icache.demand_accesses::cpu1.inst 13690110 # number of demand (read+write) accesses 1101system.cpu1.icache.demand_accesses::total 13690110 # number of demand (read+write) accesses 1102system.cpu1.icache.overall_accesses::cpu1.inst 13690110 # number of overall (read+write) accesses 1103system.cpu1.icache.overall_accesses::total 13690110 # number of overall (read+write) accesses 1104system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024257 # miss rate for ReadReq accesses 1105system.cpu1.icache.ReadReq_miss_rate::total 0.024257 # miss rate for ReadReq accesses 1106system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024257 # miss rate for demand accesses 1107system.cpu1.icache.demand_miss_rate::total 0.024257 # miss rate for demand accesses 1108system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024257 # miss rate for overall accesses 1109system.cpu1.icache.overall_miss_rate::total 0.024257 # miss rate for overall accesses 1110system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13672.420283 # average ReadReq miss latency 1111system.cpu1.icache.ReadReq_avg_miss_latency::total 13672.420283 # average ReadReq miss latency 1112system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency 1113system.cpu1.icache.demand_avg_miss_latency::total 13672.420283 # average overall miss latency 1114system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency 1115system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency 1116system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1117system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1118system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1119system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1120system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1121system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	1046system.cpu1.icache.tags.replacements 331529 # number of replacements 1047system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use 1048system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks. 1049system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks. 1050system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks. 1051system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. 1052system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor 1053system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy 1054system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy 1055system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1056system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id 1057system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 1058system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id 1059system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id 1060system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1061system.cpu1.icache.tags.tag_accesses 14022191 # Number of tag accesses 1062system.cpu1.icache.tags.data_accesses 14022191 # Number of data accesses 1063system.cpu1.icache.ReadReq_hits::cpu1.inst 13358029 # number of ReadReq hits 1064system.cpu1.icache.ReadReq_hits::total 13358029 # number of ReadReq hits 1065system.cpu1.icache.demand_hits::cpu1.inst 13358029 # number of demand (read+write) hits 1066system.cpu1.icache.demand_hits::total 13358029 # number of demand (read+write) hits 1067system.cpu1.icache.overall_hits::cpu1.inst 13358029 # number of overall hits 1068system.cpu1.icache.overall_hits::total 13358029 # number of overall hits 1069system.cpu1.icache.ReadReq_misses::cpu1.inst 332081 # number of ReadReq misses 1070system.cpu1.icache.ReadReq_misses::total 332081 # number of ReadReq misses 1071system.cpu1.icache.demand_misses::cpu1.inst 332081 # number of demand (read+write) misses 1072system.cpu1.icache.demand_misses::total 332081 # number of demand (read+write) misses 1073system.cpu1.icache.overall_misses::cpu1.inst 332081 # number of overall misses 1074system.cpu1.icache.overall_misses::total 332081 # number of overall misses 1075system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4540351000 # number of ReadReq miss cycles 1076system.cpu1.icache.ReadReq_miss_latency::total 4540351000 # number of ReadReq miss cycles 1077system.cpu1.icache.demand_miss_latency::cpu1.inst 4540351000 # number of demand (read+write) miss cycles 1078system.cpu1.icache.demand_miss_latency::total 4540351000 # number of demand (read+write) miss cycles 1079system.cpu1.icache.overall_miss_latency::cpu1.inst 4540351000 # number of overall miss cycles 1080system.cpu1.icache.overall_miss_latency::total 4540351000 # number of overall miss cycles 1081system.cpu1.icache.ReadReq_accesses::cpu1.inst 13690110 # number of ReadReq accesses(hits+misses) 1082system.cpu1.icache.ReadReq_accesses::total 13690110 # number of ReadReq accesses(hits+misses) 1083system.cpu1.icache.demand_accesses::cpu1.inst 13690110 # number of demand (read+write) accesses 1084system.cpu1.icache.demand_accesses::total 13690110 # number of demand (read+write) accesses 1085system.cpu1.icache.overall_accesses::cpu1.inst 13690110 # number of overall (read+write) accesses 1086system.cpu1.icache.overall_accesses::total 13690110 # number of overall (read+write) accesses 1087system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024257 # miss rate for ReadReq accesses 1088system.cpu1.icache.ReadReq_miss_rate::total 0.024257 # miss rate for ReadReq accesses 1089system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024257 # miss rate for demand accesses 1090system.cpu1.icache.demand_miss_rate::total 0.024257 # miss rate for demand accesses 1091system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024257 # miss rate for overall accesses 1092system.cpu1.icache.overall_miss_rate::total 0.024257 # miss rate for overall accesses 1093system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13672.420283 # average ReadReq miss latency 1094system.cpu1.icache.ReadReq_avg_miss_latency::total 13672.420283 # average ReadReq miss latency 1095system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency 1096system.cpu1.icache.demand_avg_miss_latency::total 13672.420283 # average overall miss latency 1097system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency 1098system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency 1099system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1100system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1101system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1102system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1103system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1104system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1122system.cpu1.icache.fast_writes 0 # number of fast writes performed 1123system.cpu1.icache.cache_copies 0 # number of cache copies performed
1124system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks 1125system.cpu1.icache.writebacks::total 331529 # number of writebacks 1126system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses 1127system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses 1128system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses 1129system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses 1130system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses 1131system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses 1132system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4208270000 # number of ReadReq MSHR miss cycles 1133system.cpu1.icache.ReadReq_mshr_miss_latency::total 4208270000 # number of ReadReq MSHR miss cycles 1134system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4208270000 # number of demand (read+write) MSHR miss cycles 1135system.cpu1.icache.demand_mshr_miss_latency::total 4208270000 # number of demand (read+write) MSHR miss cycles 1136system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4208270000 # number of overall MSHR miss cycles 1137system.cpu1.icache.overall_mshr_miss_latency::total 4208270000 # number of overall MSHR miss cycles 1138system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for ReadReq accesses 1139system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024257 # mshr miss rate for ReadReq accesses 1140system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for demand accesses 1141system.cpu1.icache.demand_mshr_miss_rate::total 0.024257 # mshr miss rate for demand accesses 1142system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses 1143system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses 1144system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency 1145system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency 1146system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency 1147system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency 1148system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency 1149system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency	1105system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks 1106system.cpu1.icache.writebacks::total 331529 # number of writebacks 1107system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses 1108system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses 1109system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses 1110system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses 1111system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses 1112system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses 1113system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4208270000 # number of ReadReq MSHR miss cycles 1114system.cpu1.icache.ReadReq_mshr_miss_latency::total 4208270000 # number of ReadReq MSHR miss cycles 1115system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4208270000 # number of demand (read+write) MSHR miss cycles 1116system.cpu1.icache.demand_mshr_miss_latency::total 4208270000 # number of demand (read+write) MSHR miss cycles 1117system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4208270000 # number of overall MSHR miss cycles 1118system.cpu1.icache.overall_mshr_miss_latency::total 4208270000 # number of overall MSHR miss cycles 1119system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for ReadReq accesses 1120system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024257 # mshr miss rate for ReadReq accesses 1121system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for demand accesses 1122system.cpu1.icache.demand_mshr_miss_rate::total 0.024257 # mshr miss rate for demand accesses 1123system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses 1124system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses 1125system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency 1126system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency 1127system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency 1128system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency 1129system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency 1130system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
1150system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1151system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1152system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1153system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1154system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1155system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1156system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1157system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1158system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1159system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1160system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1161system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1162system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1163system.iobus.trans_dist::ReadReq 7376 # Transaction distribution 1164system.iobus.trans_dist::ReadResp 7376 # Transaction distribution 1165system.iobus.trans_dist::WriteReq 55683 # Transaction distribution 1166system.iobus.trans_dist::WriteResp 55683 # Transaction distribution 1167system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14050 # Packet count per connected master and slave (bytes) 1168system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1169system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 188 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18150 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1176system.iobus.pkt_count_system.bridge.master::total 42664 # Packet count per connected master and slave (bytes) 1177system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 1178system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 1179system.iobus.pkt_count::total 126118 # Packet count per connected master and slave (bytes) 1180system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56200 # Cumulative packet size per connected master and slave (bytes) 1181system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1182system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1183system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1184system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 171 # Cumulative packet size per connected master and slave (bytes) 1185system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9075 # Cumulative packet size per connected master and slave (bytes) 1186system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) 1187system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1188system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1189system.iobus.pkt_size_system.bridge.master::total 82454 # Cumulative packet size per connected master and slave (bytes) 1190system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 1191system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 1192system.iobus.pkt_size::total 2744078 # Cumulative packet size per connected master and slave (bytes) 1193system.iobus.reqLayer0.occupancy 15116500 # Layer occupancy (ticks) 1194system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1195system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) 1196system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1197system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1198system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1199system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1200system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1201system.iobus.reqLayer22.occupancy 183000 # Layer occupancy (ticks) 1202system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1203system.iobus.reqLayer23.occupancy 15844000 # Layer occupancy (ticks) 1204system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1205system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) 1206system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1207system.iobus.reqLayer25.occupancy 6055500 # Layer occupancy (ticks) 1208system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1209system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) 1210system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1211system.iobus.reqLayer27.occupancy 215674412 # Layer occupancy (ticks) 1212system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1213system.iobus.respLayer0.occupancy 28533000 # Layer occupancy (ticks) 1214system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1215system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) 1216system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1217system.iocache.tags.replacements 41695 # number of replacements 1218system.iocache.tags.tagsinuse 0.566860 # Cycle average of tags in use 1219system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1220system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 1221system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1222system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. 1223system.iocache.tags.occ_blocks::tsunami.ide 0.566860 # Average occupied blocks per requestor 1224system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy 1225system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy 1226system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1227system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1228system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1229system.iocache.tags.tag_accesses 375543 # Number of tag accesses 1230system.iocache.tags.data_accesses 375543 # Number of data accesses 1231system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 1232system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 1233system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1234system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses	1131system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1132system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1133system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1134system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1135system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1136system.disk0.dma_write_txs 395 # Number of DMA write transactions. 1137system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1138system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1139system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1140system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1141system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1142system.disk2.dma_write_txs 1 # Number of DMA write transactions. 1143system.iobus.trans_dist::ReadReq 7376 # Transaction distribution 1144system.iobus.trans_dist::ReadResp 7376 # Transaction distribution 1145system.iobus.trans_dist::WriteReq 55683 # Transaction distribution 1146system.iobus.trans_dist::WriteResp 55683 # Transaction distribution 1147system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14050 # Packet count per connected master and slave (bytes) 1148system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) 1149system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 1150system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 1151system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 188 # Packet count per connected master and slave (bytes) 1152system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18150 # Packet count per connected master and slave (bytes) 1153system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) 1154system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 1155system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 1156system.iobus.pkt_count_system.bridge.master::total 42664 # Packet count per connected master and slave (bytes) 1157system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) 1158system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) 1159system.iobus.pkt_count::total 126118 # Packet count per connected master and slave (bytes) 1160system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56200 # Cumulative packet size per connected master and slave (bytes) 1161system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) 1162system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 1163system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 1164system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 171 # Cumulative packet size per connected master and slave (bytes) 1165system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9075 # Cumulative packet size per connected master and slave (bytes) 1166system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) 1167system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 1168system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 1169system.iobus.pkt_size_system.bridge.master::total 82454 # Cumulative packet size per connected master and slave (bytes) 1170system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) 1171system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) 1172system.iobus.pkt_size::total 2744078 # Cumulative packet size per connected master and slave (bytes) 1173system.iobus.reqLayer0.occupancy 15116500 # Layer occupancy (ticks) 1174system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1175system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) 1176system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1177system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 1178system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1179system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 1180system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1181system.iobus.reqLayer22.occupancy 183000 # Layer occupancy (ticks) 1182system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1183system.iobus.reqLayer23.occupancy 15844000 # Layer occupancy (ticks) 1184system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1185system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) 1186system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1187system.iobus.reqLayer25.occupancy 6055500 # Layer occupancy (ticks) 1188system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1189system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) 1190system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1191system.iobus.reqLayer27.occupancy 215674412 # Layer occupancy (ticks) 1192system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1193system.iobus.respLayer0.occupancy 28533000 # Layer occupancy (ticks) 1194system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1195system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) 1196system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1197system.iocache.tags.replacements 41695 # number of replacements 1198system.iocache.tags.tagsinuse 0.566860 # Cycle average of tags in use 1199system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1200system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 1201system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1202system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. 1203system.iocache.tags.occ_blocks::tsunami.ide 0.566860 # Average occupied blocks per requestor 1204system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy 1205system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy 1206system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1207system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1208system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1209system.iocache.tags.tag_accesses 375543 # Number of tag accesses 1210system.iocache.tags.data_accesses 375543 # Number of data accesses 1211system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 1212system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 1213system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 1214system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1235system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses 1236system.iocache.demand_misses::total 175 # number of demand (read+write) misses 1237system.iocache.overall_misses::tsunami.ide 175 # number of overall misses 1238system.iocache.overall_misses::total 175 # number of overall misses	1215system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 1216system.iocache.demand_misses::total 41727 # number of demand (read+write) misses 1217system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses 1218system.iocache.overall_misses::total 41727 # number of overall misses
1239system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles 1240system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles 1241system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles 1242system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles	1219system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles 1220system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles 1221system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles 1222system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles
1243system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles 1244system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles 1245system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles 1246system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles	1223system.iocache.demand_miss_latency::tsunami.ide 5267103412 # number of demand (read+write) miss cycles 1224system.iocache.demand_miss_latency::total 5267103412 # number of demand (read+write) miss cycles 1225system.iocache.overall_miss_latency::tsunami.ide 5267103412 # number of overall miss cycles 1226system.iocache.overall_miss_latency::total 5267103412 # number of overall miss cycles
1247system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 1248system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 1249system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1250system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)	1227system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) 1228system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 1229system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 1230system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1251system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses 1252system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses 1253system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses 1254system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses	1231system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 1232system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 1233system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 1234system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
1255system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1256system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1257system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1258system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1259system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1260system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1261system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1262system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1263system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency 1264system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency 1265system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency 1266system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency	1235system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1236system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1237system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 1238system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1239system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1240system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1241system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1242system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1243system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency 1244system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency 1245system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency 1246system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency
1267system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency 1268system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency 1269system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency 1270system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency	1247system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency 1248system.iocache.demand_avg_miss_latency::total 126227.704172 # average overall miss latency 1249system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency 1250system.iocache.overall_avg_miss_latency::total 126227.704172 # average overall miss latency
1271system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1272system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1273system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1274system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1275system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1276system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	1251system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1252system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1253system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1254system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1255system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1256system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1277system.iocache.fast_writes 0 # number of fast writes performed 1278system.iocache.cache_copies 0 # number of cache copies performed
1279system.iocache.writebacks::writebacks 41520 # number of writebacks 1280system.iocache.writebacks::total 41520 # number of writebacks 1281system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 1282system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 1283system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1284system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses	1257system.iocache.writebacks::writebacks 41520 # number of writebacks 1258system.iocache.writebacks::total 41520 # number of writebacks 1259system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses 1260system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses 1261system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 1262system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1285system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses 1286system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses 1287system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses 1288system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses	1263system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses 1264system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses 1265system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses 1266system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
1289system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles 1290system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles 1291system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles 1292system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles	1267system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles 1268system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles 1269system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles 1270system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles
1293system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles 1294system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles 1295system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles 1296system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles	1271system.iocache.demand_mshr_miss_latency::tsunami.ide 3178946624 # number of demand (read+write) MSHR miss cycles 1272system.iocache.demand_mshr_miss_latency::total 3178946624 # number of demand (read+write) MSHR miss cycles 1273system.iocache.overall_mshr_miss_latency::tsunami.ide 3178946624 # number of overall MSHR miss cycles 1274system.iocache.overall_mshr_miss_latency::total 3178946624 # number of overall MSHR miss cycles
1297system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1298system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1299system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1300system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1301system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1302system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1303system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1304system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1305system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency 1306system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency 1307system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency 1308system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency	1275system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 1276system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1277system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 1278system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1279system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 1280system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1281system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 1282system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1283system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency 1284system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency 1285system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency 1286system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency
1309system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency 1310system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency 1311system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency 1312system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency 1313system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate	1287system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency 1288system.iocache.demand_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency 1289system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency 1290system.iocache.overall_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency
1314system.l2c.tags.replacements 342136 # number of replacements 1315system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use 1316system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks. 1317system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks. 1318system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks. 1319system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. 1320system.l2c.tags.occ_blocks::writebacks 54851.977847 # Average occupied blocks per requestor 1321system.l2c.tags.occ_blocks::cpu0.inst 4799.733629 # Average occupied blocks per requestor 1322system.l2c.tags.occ_blocks::cpu0.data 5353.675533 # Average occupied blocks per requestor 1323system.l2c.tags.occ_blocks::cpu1.inst 118.645951 # Average occupied blocks per requestor 1324system.l2c.tags.occ_blocks::cpu1.data 39.333789 # Average occupied blocks per requestor 1325system.l2c.tags.occ_percent::writebacks 0.836975 # Average percentage of cache occupancy 1326system.l2c.tags.occ_percent::cpu0.inst 0.073238 # Average percentage of cache occupancy 1327system.l2c.tags.occ_percent::cpu0.data 0.081691 # Average percentage of cache occupancy 1328system.l2c.tags.occ_percent::cpu1.inst 0.001810 # Average percentage of cache occupancy 1329system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy 1330system.l2c.tags.occ_percent::total 0.994314 # Average percentage of cache occupancy 1331system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id 1332system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 1333system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id 1334system.l2c.tags.age_task_id_blocks_1024::2 5377 # Occupied blocks per task id 1335system.l2c.tags.age_task_id_blocks_1024::3 6298 # Occupied blocks per task id 1336system.l2c.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id 1337system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id 1338system.l2c.tags.tag_accesses 35906899 # Number of tag accesses 1339system.l2c.tags.data_accesses 35906899 # Number of data accesses 1340system.l2c.WritebackDirty_hits::writebacks 792516 # number of WritebackDirty hits 1341system.l2c.WritebackDirty_hits::total 792516 # number of WritebackDirty hits 1342system.l2c.WritebackClean_hits::writebacks 746948 # number of WritebackClean hits 1343system.l2c.WritebackClean_hits::total 746948 # number of WritebackClean hits 1344system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits 1345system.l2c.UpgradeReq_hits::cpu1.data 548 # number of UpgradeReq hits 1346system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits 1347system.l2c.SCUpgradeReq_hits::cpu0.data 41 # number of SCUpgradeReq hits 1348system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 1349system.l2c.SCUpgradeReq_hits::total 65 # number of SCUpgradeReq hits 1350system.l2c.ReadExReq_hits::cpu0.data 124124 # number of ReadExReq hits 1351system.l2c.ReadExReq_hits::cpu1.data 48553 # number of ReadExReq hits 1352system.l2c.ReadExReq_hits::total 172677 # number of ReadExReq hits 1353system.l2c.ReadCleanReq_hits::cpu0.inst 674650 # number of ReadCleanReq hits 1354system.l2c.ReadCleanReq_hits::cpu1.inst 331142 # number of ReadCleanReq hits 1355system.l2c.ReadCleanReq_hits::total 1005792 # number of ReadCleanReq hits 1356system.l2c.ReadSharedReq_hits::cpu0.data 659425 # number of ReadSharedReq hits 1357system.l2c.ReadSharedReq_hits::cpu1.data 113738 # number of ReadSharedReq hits 1358system.l2c.ReadSharedReq_hits::total 773163 # number of ReadSharedReq hits 1359system.l2c.demand_hits::cpu0.inst 674650 # number of demand (read+write) hits 1360system.l2c.demand_hits::cpu0.data 783549 # number of demand (read+write) hits 1361system.l2c.demand_hits::cpu1.inst 331142 # number of demand (read+write) hits 1362system.l2c.demand_hits::cpu1.data 162291 # number of demand (read+write) hits 1363system.l2c.demand_hits::total 1951632 # number of demand (read+write) hits 1364system.l2c.overall_hits::cpu0.inst 674650 # number of overall hits 1365system.l2c.overall_hits::cpu0.data 783549 # number of overall hits 1366system.l2c.overall_hits::cpu1.inst 331142 # number of overall hits 1367system.l2c.overall_hits::cpu1.data 162291 # number of overall hits 1368system.l2c.overall_hits::total 1951632 # number of overall hits 1369system.l2c.UpgradeReq_misses::cpu0.data 2972 # number of UpgradeReq misses 1370system.l2c.UpgradeReq_misses::cpu1.data 1812 # number of UpgradeReq misses 1371system.l2c.UpgradeReq_misses::total 4784 # number of UpgradeReq misses 1372system.l2c.SCUpgradeReq_misses::cpu0.data 926 # number of SCUpgradeReq misses 1373system.l2c.SCUpgradeReq_misses::cpu1.data 930 # number of SCUpgradeReq misses 1374system.l2c.SCUpgradeReq_misses::total 1856 # number of SCUpgradeReq misses 1375system.l2c.ReadExReq_misses::cpu0.data 114970 # number of ReadExReq misses 1376system.l2c.ReadExReq_misses::cpu1.data 7877 # number of ReadExReq misses 1377system.l2c.ReadExReq_misses::total 122847 # number of ReadExReq misses 1378system.l2c.ReadCleanReq_misses::cpu0.inst 12503 # number of ReadCleanReq misses 1379system.l2c.ReadCleanReq_misses::cpu1.inst 938 # number of ReadCleanReq misses 1380system.l2c.ReadCleanReq_misses::total 13441 # number of ReadCleanReq misses 1381system.l2c.ReadSharedReq_misses::cpu0.data 271537 # number of ReadSharedReq misses 1382system.l2c.ReadSharedReq_misses::cpu1.data 338 # number of ReadSharedReq misses 1383system.l2c.ReadSharedReq_misses::total 271875 # number of ReadSharedReq misses 1384system.l2c.demand_misses::cpu0.inst 12503 # number of demand (read+write) misses 1385system.l2c.demand_misses::cpu0.data 386507 # number of demand (read+write) misses 1386system.l2c.demand_misses::cpu1.inst 938 # number of demand (read+write) misses 1387system.l2c.demand_misses::cpu1.data 8215 # number of demand (read+write) misses 1388system.l2c.demand_misses::total 408163 # number of demand (read+write) misses 1389system.l2c.overall_misses::cpu0.inst 12503 # number of overall misses 1390system.l2c.overall_misses::cpu0.data 386507 # number of overall misses 1391system.l2c.overall_misses::cpu1.inst 938 # number of overall misses 1392system.l2c.overall_misses::cpu1.data 8215 # number of overall misses 1393system.l2c.overall_misses::total 408163 # number of overall misses 1394system.l2c.UpgradeReq_miss_latency::cpu0.data 3623500 # number of UpgradeReq miss cycles 1395system.l2c.UpgradeReq_miss_latency::cpu1.data 35439500 # number of UpgradeReq miss cycles 1396system.l2c.UpgradeReq_miss_latency::total 39063000 # number of UpgradeReq miss cycles 1397system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3369500 # number of SCUpgradeReq miss cycles 1398system.l2c.SCUpgradeReq_miss_latency::cpu1.data 943000 # number of SCUpgradeReq miss cycles 1399system.l2c.SCUpgradeReq_miss_latency::total 4312500 # number of SCUpgradeReq miss cycles 1400system.l2c.ReadExReq_miss_latency::cpu0.data 14618383500 # number of ReadExReq miss cycles 1401system.l2c.ReadExReq_miss_latency::cpu1.data 1037446500 # number of ReadExReq miss cycles 1402system.l2c.ReadExReq_miss_latency::total 15655830000 # number of ReadExReq miss cycles 1403system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1639795500 # number of ReadCleanReq miss cycles 1404system.l2c.ReadCleanReq_miss_latency::cpu1.inst 123119500 # number of ReadCleanReq miss cycles 1405system.l2c.ReadCleanReq_miss_latency::total 1762915000 # number of ReadCleanReq miss cycles 1406system.l2c.ReadSharedReq_miss_latency::cpu0.data 33668278500 # number of ReadSharedReq miss cycles 1407system.l2c.ReadSharedReq_miss_latency::cpu1.data 42563000 # number of ReadSharedReq miss cycles 1408system.l2c.ReadSharedReq_miss_latency::total 33710841500 # number of ReadSharedReq miss cycles 1409system.l2c.demand_miss_latency::cpu0.inst 1639795500 # number of demand (read+write) miss cycles 1410system.l2c.demand_miss_latency::cpu0.data 48286662000 # number of demand (read+write) miss cycles 1411system.l2c.demand_miss_latency::cpu1.inst 123119500 # number of demand (read+write) miss cycles 1412system.l2c.demand_miss_latency::cpu1.data 1080009500 # number of demand (read+write) miss cycles 1413system.l2c.demand_miss_latency::total 51129586500 # number of demand (read+write) miss cycles 1414system.l2c.overall_miss_latency::cpu0.inst 1639795500 # number of overall miss cycles 1415system.l2c.overall_miss_latency::cpu0.data 48286662000 # number of overall miss cycles 1416system.l2c.overall_miss_latency::cpu1.inst 123119500 # number of overall miss cycles 1417system.l2c.overall_miss_latency::cpu1.data 1080009500 # number of overall miss cycles 1418system.l2c.overall_miss_latency::total 51129586500 # number of overall miss cycles 1419system.l2c.WritebackDirty_accesses::writebacks 792516 # number of WritebackDirty accesses(hits+misses) 1420system.l2c.WritebackDirty_accesses::total 792516 # number of WritebackDirty accesses(hits+misses) 1421system.l2c.WritebackClean_accesses::writebacks 746948 # number of WritebackClean accesses(hits+misses) 1422system.l2c.WritebackClean_accesses::total 746948 # number of WritebackClean accesses(hits+misses) 1423system.l2c.UpgradeReq_accesses::cpu0.data 3155 # number of UpgradeReq accesses(hits+misses) 1424system.l2c.UpgradeReq_accesses::cpu1.data 2360 # number of UpgradeReq accesses(hits+misses) 1425system.l2c.UpgradeReq_accesses::total 5515 # number of UpgradeReq accesses(hits+misses) 1426system.l2c.SCUpgradeReq_accesses::cpu0.data 967 # number of SCUpgradeReq accesses(hits+misses) 1427system.l2c.SCUpgradeReq_accesses::cpu1.data 954 # number of SCUpgradeReq accesses(hits+misses) 1428system.l2c.SCUpgradeReq_accesses::total 1921 # number of SCUpgradeReq accesses(hits+misses) 1429system.l2c.ReadExReq_accesses::cpu0.data 239094 # number of ReadExReq accesses(hits+misses) 1430system.l2c.ReadExReq_accesses::cpu1.data 56430 # number of ReadExReq accesses(hits+misses) 1431system.l2c.ReadExReq_accesses::total 295524 # number of ReadExReq accesses(hits+misses) 1432system.l2c.ReadCleanReq_accesses::cpu0.inst 687153 # number of ReadCleanReq accesses(hits+misses) 1433system.l2c.ReadCleanReq_accesses::cpu1.inst 332080 # number of ReadCleanReq accesses(hits+misses) 1434system.l2c.ReadCleanReq_accesses::total 1019233 # number of ReadCleanReq accesses(hits+misses) 1435system.l2c.ReadSharedReq_accesses::cpu0.data 930962 # number of ReadSharedReq accesses(hits+misses) 1436system.l2c.ReadSharedReq_accesses::cpu1.data 114076 # number of ReadSharedReq accesses(hits+misses) 1437system.l2c.ReadSharedReq_accesses::total 1045038 # number of ReadSharedReq accesses(hits+misses) 1438system.l2c.demand_accesses::cpu0.inst 687153 # number of demand (read+write) accesses 1439system.l2c.demand_accesses::cpu0.data 1170056 # number of demand (read+write) accesses 1440system.l2c.demand_accesses::cpu1.inst 332080 # number of demand (read+write) accesses 1441system.l2c.demand_accesses::cpu1.data 170506 # number of demand (read+write) accesses 1442system.l2c.demand_accesses::total 2359795 # number of demand (read+write) accesses 1443system.l2c.overall_accesses::cpu0.inst 687153 # number of overall (read+write) accesses 1444system.l2c.overall_accesses::cpu0.data 1170056 # number of overall (read+write) accesses 1445system.l2c.overall_accesses::cpu1.inst 332080 # number of overall (read+write) accesses 1446system.l2c.overall_accesses::cpu1.data 170506 # number of overall (read+write) accesses 1447system.l2c.overall_accesses::total 2359795 # number of overall (read+write) accesses 1448system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941997 # miss rate for UpgradeReq accesses 1449system.l2c.UpgradeReq_miss_rate::cpu1.data 0.767797 # miss rate for UpgradeReq accesses 1450system.l2c.UpgradeReq_miss_rate::total 0.867452 # miss rate for UpgradeReq accesses 1451system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.957601 # miss rate for SCUpgradeReq accesses 1452system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974843 # miss rate for SCUpgradeReq accesses 1453system.l2c.SCUpgradeReq_miss_rate::total 0.966163 # miss rate for SCUpgradeReq accesses 1454system.l2c.ReadExReq_miss_rate::cpu0.data 0.480857 # miss rate for ReadExReq accesses 1455system.l2c.ReadExReq_miss_rate::cpu1.data 0.139589 # miss rate for ReadExReq accesses 1456system.l2c.ReadExReq_miss_rate::total 0.415692 # miss rate for ReadExReq accesses 1457system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018195 # miss rate for ReadCleanReq accesses 1458system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002825 # miss rate for ReadCleanReq accesses 1459system.l2c.ReadCleanReq_miss_rate::total 0.013187 # miss rate for ReadCleanReq accesses 1460system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291674 # miss rate for ReadSharedReq accesses 1461system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002963 # miss rate for ReadSharedReq accesses 1462system.l2c.ReadSharedReq_miss_rate::total 0.260158 # miss rate for ReadSharedReq accesses 1463system.l2c.demand_miss_rate::cpu0.inst 0.018195 # miss rate for demand accesses 1464system.l2c.demand_miss_rate::cpu0.data 0.330332 # miss rate for demand accesses 1465system.l2c.demand_miss_rate::cpu1.inst 0.002825 # miss rate for demand accesses 1466system.l2c.demand_miss_rate::cpu1.data 0.048180 # miss rate for demand accesses 1467system.l2c.demand_miss_rate::total 0.172965 # miss rate for demand accesses 1468system.l2c.overall_miss_rate::cpu0.inst 0.018195 # miss rate for overall accesses 1469system.l2c.overall_miss_rate::cpu0.data 0.330332 # miss rate for overall accesses 1470system.l2c.overall_miss_rate::cpu1.inst 0.002825 # miss rate for overall accesses 1471system.l2c.overall_miss_rate::cpu1.data 0.048180 # miss rate for overall accesses 1472system.l2c.overall_miss_rate::total 0.172965 # miss rate for overall accesses 1473system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1219.212651 # average UpgradeReq miss latency 1474system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19558.222958 # average UpgradeReq miss latency 1475system.l2c.UpgradeReq_avg_miss_latency::total 8165.342809 # average UpgradeReq miss latency 1476system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3638.768898 # average SCUpgradeReq miss latency 1477system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1013.978495 # average SCUpgradeReq miss latency 1478system.l2c.SCUpgradeReq_avg_miss_latency::total 2323.545259 # average SCUpgradeReq miss latency 1479system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127149.547708 # average ReadExReq miss latency 1480system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131705.789006 # average ReadExReq miss latency 1481system.l2c.ReadExReq_avg_miss_latency::total 127441.695768 # average ReadExReq miss latency 1482system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131152.163481 # average ReadCleanReq miss latency 1483system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131257.462687 # average ReadCleanReq miss latency 1484system.l2c.ReadCleanReq_avg_miss_latency::total 131159.511941 # average ReadCleanReq miss latency 1485system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123991.494713 # average ReadSharedReq miss latency 1486system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 125926.035503 # average ReadSharedReq miss latency 1487system.l2c.ReadSharedReq_avg_miss_latency::total 123993.899770 # average ReadSharedReq miss latency 1488system.l2c.demand_avg_miss_latency::cpu0.inst 131152.163481 # average overall miss latency 1489system.l2c.demand_avg_miss_latency::cpu0.data 124930.886116 # average overall miss latency 1490system.l2c.demand_avg_miss_latency::cpu1.inst 131257.462687 # average overall miss latency 1491system.l2c.demand_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency 1492system.l2c.demand_avg_miss_latency::total 125267.568349 # average overall miss latency 1493system.l2c.overall_avg_miss_latency::cpu0.inst 131152.163481 # average overall miss latency 1494system.l2c.overall_avg_miss_latency::cpu0.data 124930.886116 # average overall miss latency 1495system.l2c.overall_avg_miss_latency::cpu1.inst 131257.462687 # average overall miss latency 1496system.l2c.overall_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency 1497system.l2c.overall_avg_miss_latency::total 125267.568349 # average overall miss latency 1498system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1499system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1500system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1501system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1502system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1503system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	1291system.l2c.tags.replacements 342136 # number of replacements 1292system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use 1293system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks. 1294system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks. 1295system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks. 1296system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. 1297system.l2c.tags.occ_blocks::writebacks 54851.977847 # Average occupied blocks per requestor 1298system.l2c.tags.occ_blocks::cpu0.inst 4799.733629 # Average occupied blocks per requestor 1299system.l2c.tags.occ_blocks::cpu0.data 5353.675533 # Average occupied blocks per requestor 1300system.l2c.tags.occ_blocks::cpu1.inst 118.645951 # Average occupied blocks per requestor 1301system.l2c.tags.occ_blocks::cpu1.data 39.333789 # Average occupied blocks per requestor 1302system.l2c.tags.occ_percent::writebacks 0.836975 # Average percentage of cache occupancy 1303system.l2c.tags.occ_percent::cpu0.inst 0.073238 # Average percentage of cache occupancy 1304system.l2c.tags.occ_percent::cpu0.data 0.081691 # Average percentage of cache occupancy 1305system.l2c.tags.occ_percent::cpu1.inst 0.001810 # Average percentage of cache occupancy 1306system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy 1307system.l2c.tags.occ_percent::total 0.994314 # Average percentage of cache occupancy 1308system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id 1309system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 1310system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id 1311system.l2c.tags.age_task_id_blocks_1024::2 5377 # Occupied blocks per task id 1312system.l2c.tags.age_task_id_blocks_1024::3 6298 # Occupied blocks per task id 1313system.l2c.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id 1314system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id 1315system.l2c.tags.tag_accesses 35906899 # Number of tag accesses 1316system.l2c.tags.data_accesses 35906899 # Number of data accesses 1317system.l2c.WritebackDirty_hits::writebacks 792516 # number of WritebackDirty hits 1318system.l2c.WritebackDirty_hits::total 792516 # number of WritebackDirty hits 1319system.l2c.WritebackClean_hits::writebacks 746948 # number of WritebackClean hits 1320system.l2c.WritebackClean_hits::total 746948 # number of WritebackClean hits 1321system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits 1322system.l2c.UpgradeReq_hits::cpu1.data 548 # number of UpgradeReq hits 1323system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits 1324system.l2c.SCUpgradeReq_hits::cpu0.data 41 # number of SCUpgradeReq hits 1325system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits 1326system.l2c.SCUpgradeReq_hits::total 65 # number of SCUpgradeReq hits 1327system.l2c.ReadExReq_hits::cpu0.data 124124 # number of ReadExReq hits 1328system.l2c.ReadExReq_hits::cpu1.data 48553 # number of ReadExReq hits 1329system.l2c.ReadExReq_hits::total 172677 # number of ReadExReq hits 1330system.l2c.ReadCleanReq_hits::cpu0.inst 674650 # number of ReadCleanReq hits 1331system.l2c.ReadCleanReq_hits::cpu1.inst 331142 # number of ReadCleanReq hits 1332system.l2c.ReadCleanReq_hits::total 1005792 # number of ReadCleanReq hits 1333system.l2c.ReadSharedReq_hits::cpu0.data 659425 # number of ReadSharedReq hits 1334system.l2c.ReadSharedReq_hits::cpu1.data 113738 # number of ReadSharedReq hits 1335system.l2c.ReadSharedReq_hits::total 773163 # number of ReadSharedReq hits 1336system.l2c.demand_hits::cpu0.inst 674650 # number of demand (read+write) hits 1337system.l2c.demand_hits::cpu0.data 783549 # number of demand (read+write) hits 1338system.l2c.demand_hits::cpu1.inst 331142 # number of demand (read+write) hits 1339system.l2c.demand_hits::cpu1.data 162291 # number of demand (read+write) hits 1340system.l2c.demand_hits::total 1951632 # number of demand (read+write) hits 1341system.l2c.overall_hits::cpu0.inst 674650 # number of overall hits 1342system.l2c.overall_hits::cpu0.data 783549 # number of overall hits 1343system.l2c.overall_hits::cpu1.inst 331142 # number of overall hits 1344system.l2c.overall_hits::cpu1.data 162291 # number of overall hits 1345system.l2c.overall_hits::total 1951632 # number of overall hits 1346system.l2c.UpgradeReq_misses::cpu0.data 2972 # number of UpgradeReq misses 1347system.l2c.UpgradeReq_misses::cpu1.data 1812 # number of UpgradeReq misses 1348system.l2c.UpgradeReq_misses::total 4784 # number of UpgradeReq misses 1349system.l2c.SCUpgradeReq_misses::cpu0.data 926 # number of SCUpgradeReq misses 1350system.l2c.SCUpgradeReq_misses::cpu1.data 930 # number of SCUpgradeReq misses 1351system.l2c.SCUpgradeReq_misses::total 1856 # number of SCUpgradeReq misses 1352system.l2c.ReadExReq_misses::cpu0.data 114970 # number of ReadExReq misses 1353system.l2c.ReadExReq_misses::cpu1.data 7877 # number of ReadExReq misses 1354system.l2c.ReadExReq_misses::total 122847 # number of ReadExReq misses 1355system.l2c.ReadCleanReq_misses::cpu0.inst 12503 # number of ReadCleanReq misses 1356system.l2c.ReadCleanReq_misses::cpu1.inst 938 # number of ReadCleanReq misses 1357system.l2c.ReadCleanReq_misses::total 13441 # number of ReadCleanReq misses 1358system.l2c.ReadSharedReq_misses::cpu0.data 271537 # number of ReadSharedReq misses 1359system.l2c.ReadSharedReq_misses::cpu1.data 338 # number of ReadSharedReq misses 1360system.l2c.ReadSharedReq_misses::total 271875 # number of ReadSharedReq misses 1361system.l2c.demand_misses::cpu0.inst 12503 # number of demand (read+write) misses 1362system.l2c.demand_misses::cpu0.data 386507 # number of demand (read+write) misses 1363system.l2c.demand_misses::cpu1.inst 938 # number of demand (read+write) misses 1364system.l2c.demand_misses::cpu1.data 8215 # number of demand (read+write) misses 1365system.l2c.demand_misses::total 408163 # number of demand (read+write) misses 1366system.l2c.overall_misses::cpu0.inst 12503 # number of overall misses 1367system.l2c.overall_misses::cpu0.data 386507 # number of overall misses 1368system.l2c.overall_misses::cpu1.inst 938 # number of overall misses 1369system.l2c.overall_misses::cpu1.data 8215 # number of overall misses 1370system.l2c.overall_misses::total 408163 # number of overall misses 1371system.l2c.UpgradeReq_miss_latency::cpu0.data 3623500 # number of UpgradeReq miss cycles 1372system.l2c.UpgradeReq_miss_latency::cpu1.data 35439500 # number of UpgradeReq miss cycles 1373system.l2c.UpgradeReq_miss_latency::total 39063000 # number of UpgradeReq miss cycles 1374system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3369500 # number of SCUpgradeReq miss cycles 1375system.l2c.SCUpgradeReq_miss_latency::cpu1.data 943000 # number of SCUpgradeReq miss cycles 1376system.l2c.SCUpgradeReq_miss_latency::total 4312500 # number of SCUpgradeReq miss cycles 1377system.l2c.ReadExReq_miss_latency::cpu0.data 14618383500 # number of ReadExReq miss cycles 1378system.l2c.ReadExReq_miss_latency::cpu1.data 1037446500 # number of ReadExReq miss cycles 1379system.l2c.ReadExReq_miss_latency::total 15655830000 # number of ReadExReq miss cycles 1380system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1639795500 # number of ReadCleanReq miss cycles 1381system.l2c.ReadCleanReq_miss_latency::cpu1.inst 123119500 # number of ReadCleanReq miss cycles 1382system.l2c.ReadCleanReq_miss_latency::total 1762915000 # number of ReadCleanReq miss cycles 1383system.l2c.ReadSharedReq_miss_latency::cpu0.data 33668278500 # number of ReadSharedReq miss cycles 1384system.l2c.ReadSharedReq_miss_latency::cpu1.data 42563000 # number of ReadSharedReq miss cycles 1385system.l2c.ReadSharedReq_miss_latency::total 33710841500 # number of ReadSharedReq miss cycles 1386system.l2c.demand_miss_latency::cpu0.inst 1639795500 # number of demand (read+write) miss cycles 1387system.l2c.demand_miss_latency::cpu0.data 48286662000 # number of demand (read+write) miss cycles 1388system.l2c.demand_miss_latency::cpu1.inst 123119500 # number of demand (read+write) miss cycles 1389system.l2c.demand_miss_latency::cpu1.data 1080009500 # number of demand (read+write) miss cycles 1390system.l2c.demand_miss_latency::total 51129586500 # number of demand (read+write) miss cycles 1391system.l2c.overall_miss_latency::cpu0.inst 1639795500 # number of overall miss cycles 1392system.l2c.overall_miss_latency::cpu0.data 48286662000 # number of overall miss cycles 1393system.l2c.overall_miss_latency::cpu1.inst 123119500 # number of overall miss cycles 1394system.l2c.overall_miss_latency::cpu1.data 1080009500 # number of overall miss cycles 1395system.l2c.overall_miss_latency::total 51129586500 # number of overall miss cycles 1396system.l2c.WritebackDirty_accesses::writebacks 792516 # number of WritebackDirty accesses(hits+misses) 1397system.l2c.WritebackDirty_accesses::total 792516 # number of WritebackDirty accesses(hits+misses) 1398system.l2c.WritebackClean_accesses::writebacks 746948 # number of WritebackClean accesses(hits+misses) 1399system.l2c.WritebackClean_accesses::total 746948 # number of WritebackClean accesses(hits+misses) 1400system.l2c.UpgradeReq_accesses::cpu0.data 3155 # number of UpgradeReq accesses(hits+misses) 1401system.l2c.UpgradeReq_accesses::cpu1.data 2360 # number of UpgradeReq accesses(hits+misses) 1402system.l2c.UpgradeReq_accesses::total 5515 # number of UpgradeReq accesses(hits+misses) 1403system.l2c.SCUpgradeReq_accesses::cpu0.data 967 # number of SCUpgradeReq accesses(hits+misses) 1404system.l2c.SCUpgradeReq_accesses::cpu1.data 954 # number of SCUpgradeReq accesses(hits+misses) 1405system.l2c.SCUpgradeReq_accesses::total 1921 # number of SCUpgradeReq accesses(hits+misses) 1406system.l2c.ReadExReq_accesses::cpu0.data 239094 # number of ReadExReq accesses(hits+misses) 1407system.l2c.ReadExReq_accesses::cpu1.data 56430 # number of ReadExReq accesses(hits+misses) 1408system.l2c.ReadExReq_accesses::total 295524 # number of ReadExReq accesses(hits+misses) 1409system.l2c.ReadCleanReq_accesses::cpu0.inst 687153 # number of ReadCleanReq accesses(hits+misses) 1410system.l2c.ReadCleanReq_accesses::cpu1.inst 332080 # number of ReadCleanReq accesses(hits+misses) 1411system.l2c.ReadCleanReq_accesses::total 1019233 # number of ReadCleanReq accesses(hits+misses) 1412system.l2c.ReadSharedReq_accesses::cpu0.data 930962 # number of ReadSharedReq accesses(hits+misses) 1413system.l2c.ReadSharedReq_accesses::cpu1.data 114076 # number of ReadSharedReq accesses(hits+misses) 1414system.l2c.ReadSharedReq_accesses::total 1045038 # number of ReadSharedReq accesses(hits+misses) 1415system.l2c.demand_accesses::cpu0.inst 687153 # number of demand (read+write) accesses 1416system.l2c.demand_accesses::cpu0.data 1170056 # number of demand (read+write) accesses 1417system.l2c.demand_accesses::cpu1.inst 332080 # number of demand (read+write) accesses 1418system.l2c.demand_accesses::cpu1.data 170506 # number of demand (read+write) accesses 1419system.l2c.demand_accesses::total 2359795 # number of demand (read+write) accesses 1420system.l2c.overall_accesses::cpu0.inst 687153 # number of overall (read+write) accesses 1421system.l2c.overall_accesses::cpu0.data 1170056 # number of overall (read+write) accesses 1422system.l2c.overall_accesses::cpu1.inst 332080 # number of overall (read+write) accesses 1423system.l2c.overall_accesses::cpu1.data 170506 # number of overall (read+write) accesses 1424system.l2c.overall_accesses::total 2359795 # number of overall (read+write) accesses 1425system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941997 # miss rate for UpgradeReq accesses 1426system.l2c.UpgradeReq_miss_rate::cpu1.data 0.767797 # miss rate for UpgradeReq accesses 1427system.l2c.UpgradeReq_miss_rate::total 0.867452 # miss rate for UpgradeReq accesses 1428system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.957601 # miss rate for SCUpgradeReq accesses 1429system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974843 # miss rate for SCUpgradeReq accesses 1430system.l2c.SCUpgradeReq_miss_rate::total 0.966163 # miss rate for SCUpgradeReq accesses 1431system.l2c.ReadExReq_miss_rate::cpu0.data 0.480857 # miss rate for ReadExReq accesses 1432system.l2c.ReadExReq_miss_rate::cpu1.data 0.139589 # miss rate for ReadExReq accesses 1433system.l2c.ReadExReq_miss_rate::total 0.415692 # miss rate for ReadExReq accesses 1434system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018195 # miss rate for ReadCleanReq accesses 1435system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002825 # miss rate for ReadCleanReq accesses 1436system.l2c.ReadCleanReq_miss_rate::total 0.013187 # miss rate for ReadCleanReq accesses 1437system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291674 # miss rate for ReadSharedReq accesses 1438system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002963 # miss rate for ReadSharedReq accesses 1439system.l2c.ReadSharedReq_miss_rate::total 0.260158 # miss rate for ReadSharedReq accesses 1440system.l2c.demand_miss_rate::cpu0.inst 0.018195 # miss rate for demand accesses 1441system.l2c.demand_miss_rate::cpu0.data 0.330332 # miss rate for demand accesses 1442system.l2c.demand_miss_rate::cpu1.inst 0.002825 # miss rate for demand accesses 1443system.l2c.demand_miss_rate::cpu1.data 0.048180 # miss rate for demand accesses 1444system.l2c.demand_miss_rate::total 0.172965 # miss rate for demand accesses 1445system.l2c.overall_miss_rate::cpu0.inst 0.018195 # miss rate for overall accesses 1446system.l2c.overall_miss_rate::cpu0.data 0.330332 # miss rate for overall accesses 1447system.l2c.overall_miss_rate::cpu1.inst 0.002825 # miss rate for overall accesses 1448system.l2c.overall_miss_rate::cpu1.data 0.048180 # miss rate for overall accesses 1449system.l2c.overall_miss_rate::total 0.172965 # miss rate for overall accesses 1450system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1219.212651 # average UpgradeReq miss latency 1451system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19558.222958 # average UpgradeReq miss latency 1452system.l2c.UpgradeReq_avg_miss_latency::total 8165.342809 # average UpgradeReq miss latency 1453system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3638.768898 # average SCUpgradeReq miss latency 1454system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1013.978495 # average SCUpgradeReq miss latency 1455system.l2c.SCUpgradeReq_avg_miss_latency::total 2323.545259 # average SCUpgradeReq miss latency 1456system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127149.547708 # average ReadExReq miss latency 1457system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131705.789006 # average ReadExReq miss latency 1458system.l2c.ReadExReq_avg_miss_latency::total 127441.695768 # average ReadExReq miss latency 1459system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131152.163481 # average ReadCleanReq miss latency 1460system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131257.462687 # average ReadCleanReq miss latency 1461system.l2c.ReadCleanReq_avg_miss_latency::total 131159.511941 # average ReadCleanReq miss latency 1462system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123991.494713 # average ReadSharedReq miss latency 1463system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 125926.035503 # average ReadSharedReq miss latency 1464system.l2c.ReadSharedReq_avg_miss_latency::total 123993.899770 # average ReadSharedReq miss latency 1465system.l2c.demand_avg_miss_latency::cpu0.inst 131152.163481 # average overall miss latency 1466system.l2c.demand_avg_miss_latency::cpu0.data 124930.886116 # average overall miss latency 1467system.l2c.demand_avg_miss_latency::cpu1.inst 131257.462687 # average overall miss latency 1468system.l2c.demand_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency 1469system.l2c.demand_avg_miss_latency::total 125267.568349 # average overall miss latency 1470system.l2c.overall_avg_miss_latency::cpu0.inst 131152.163481 # average overall miss latency 1471system.l2c.overall_avg_miss_latency::cpu0.data 124930.886116 # average overall miss latency 1472system.l2c.overall_avg_miss_latency::cpu1.inst 131257.462687 # average overall miss latency 1473system.l2c.overall_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency 1474system.l2c.overall_avg_miss_latency::total 125267.568349 # average overall miss latency 1475system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1476system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1477system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1478system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1479system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1480system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1504system.l2c.fast_writes 0 # number of fast writes performed 1505system.l2c.cache_copies 0 # number of cache copies performed