Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.962613 # Number of seconds simulated
4sim_ticks 1962612686500 # Number of ticks simulated
5final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1051716 # Simulator instruction rate (inst/s)
8host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 33894179183 # Simulator tick rate (ticks/s)
10host_mem_usage 374244 # Number of bytes of host memory used
11host_seconds 57.90 # Real time elapsed on the host

7host_inst_rate 1118839 # Simulator instruction rate (inst/s)
8host_op_rate 1118839 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 36057415911 # Simulator tick rate (ticks/s)
10host_mem_usage 319640 # Number of bytes of host memory used
11host_seconds 54.43 # Real time elapsed on the host

12sim_insts 60898638 # Number of instructions simulated
13sim_ops 60898638 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 406851 # Number of read requests accepted
54system.physmem.writeReqs 161902 # Number of write requests accepted
55system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue
59system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 25141 # Per bank write bursts
66system.physmem.perBankRdBursts::1 25398 # Per bank write bursts
67system.physmem.perBankRdBursts::2 25524 # Per bank write bursts
68system.physmem.perBankRdBursts::3 24918 # Per bank write bursts
69system.physmem.perBankRdBursts::4 25169 # Per bank write bursts
70system.physmem.perBankRdBursts::5 25258 # Per bank write bursts
71system.physmem.perBankRdBursts::6 25808 # Per bank write bursts
72system.physmem.perBankRdBursts::7 25541 # Per bank write bursts
73system.physmem.perBankRdBursts::8 25675 # Per bank write bursts
74system.physmem.perBankRdBursts::9 25330 # Per bank write bursts
75system.physmem.perBankRdBursts::10 25284 # Per bank write bursts
76system.physmem.perBankRdBursts::11 25615 # Per bank write bursts
77system.physmem.perBankRdBursts::12 25647 # Per bank write bursts
78system.physmem.perBankRdBursts::13 25653 # Per bank write bursts
79system.physmem.perBankRdBursts::14 25754 # Per bank write bursts
80system.physmem.perBankRdBursts::15 25033 # Per bank write bursts
81system.physmem.perBankWrBursts::0 8965 # Per bank write bursts
82system.physmem.perBankWrBursts::1 8625 # Per bank write bursts
83system.physmem.perBankWrBursts::2 8456 # Per bank write bursts
84system.physmem.perBankWrBursts::3 7799 # Per bank write bursts
85system.physmem.perBankWrBursts::4 8065 # Per bank write bursts
86system.physmem.perBankWrBursts::5 8041 # Per bank write bursts
87system.physmem.perBankWrBursts::6 8610 # Per bank write bursts
88system.physmem.perBankWrBursts::7 8172 # Per bank write bursts
89system.physmem.perBankWrBursts::8 8465 # Per bank write bursts
90system.physmem.perBankWrBursts::9 8053 # Per bank write bursts
91system.physmem.perBankWrBursts::10 8222 # Per bank write bursts
92system.physmem.perBankWrBursts::11 8481 # Per bank write bursts
93system.physmem.perBankWrBursts::12 8850 # Per bank write bursts
94system.physmem.perBankWrBursts::13 9510 # Per bank write bursts
95system.physmem.perBankWrBursts::14 9309 # Per bank write bursts
96system.physmem.perBankWrBursts::15 8651 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 56 # Number of times write queue was full causing retry
99system.physmem.totGap 1962566141500 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 406851 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 161902 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
146system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads
274system.physmem.totQLat 2137457500 # Total ticks spent queuing
275system.physmem.totMemAccLat 9763982500 # Total ticks spent from burst creation until serviced by the DRAM
276system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers
277system.physmem.avgQLat 5254.99 # Average queueing delay per DRAM burst
278system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
279system.physmem.avgMemAccLat 24004.99 # Average memory access latency per DRAM burst
280system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s
281system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s
282system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s
283system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s
284system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
285system.physmem.busUtil 0.14 # Data bus utilization in percentage
286system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
287system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
288system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
289system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing
290system.physmem.readRowHits 364433 # Number of row buffer hits during reads
291system.physmem.writeRowHits 110956 # Number of row buffer hits during writes
292system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads
293system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes
294system.physmem.avgGap 3450647.54 # Average gap between requests
295system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined
296system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ)
297system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ)
298system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ)
299system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ)
300system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ)
301system.physmem_0.actBackEnergy 66287824245 # Energy for active background per rank (pJ)
302system.physmem_0.preBackEnergy 1119418910250 # Energy for precharge background per rank (pJ)
303system.physmem_0.totalEnergy 1316300550720 # Total energy per rank (pJ)
304system.physmem_0.averagePower 670.688732 # Core power per rank (mW)
305system.physmem_0.memoryStateTime::IDLE 1862013796212 # Time in different power states
306system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states
307system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
308system.physmem_0.memoryStateTime::ACT 35060565038 # Time in different power states
309system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
310system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ)
311system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ)
312system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ)
313system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ)
314system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ)
315system.physmem_1.actBackEnergy 66523575105 # Energy for active background per rank (pJ)
316system.physmem_1.preBackEnergy 1119212111250 # Energy for precharge background per rank (pJ)
317system.physmem_1.totalEnergy 1316364135975 # Total energy per rank (pJ)
318system.physmem_1.averagePower 670.721130 # Core power per rank (mW)
319system.physmem_1.memoryStateTime::IDLE 1861673236216 # Time in different power states
320system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states
321system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
322system.physmem_1.memoryStateTime::ACT 35401125034 # Time in different power states
323system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
324system.cpu_clk_domain.clock 500 # Clock period in ticks
325system.cpu0.dtb.fetch_hits 0 # ITB hits
326system.cpu0.dtb.fetch_misses 0 # ITB misses
327system.cpu0.dtb.fetch_acv 0 # ITB acv
328system.cpu0.dtb.fetch_accesses 0 # ITB accesses
329system.cpu0.dtb.read_hits 7492205 # DTB read hits
330system.cpu0.dtb.read_misses 7443 # DTB read misses
331system.cpu0.dtb.read_acv 210 # DTB read access violations
332system.cpu0.dtb.read_accesses 490673 # DTB read accesses
333system.cpu0.dtb.write_hits 5067323 # DTB write hits
334system.cpu0.dtb.write_misses 813 # DTB write misses
335system.cpu0.dtb.write_acv 134 # DTB write access violations
336system.cpu0.dtb.write_accesses 187452 # DTB write accesses
337system.cpu0.dtb.data_hits 12559528 # DTB hits
338system.cpu0.dtb.data_misses 8256 # DTB misses
339system.cpu0.dtb.data_acv 344 # DTB access violations
340system.cpu0.dtb.data_accesses 678125 # DTB accesses
341system.cpu0.itb.fetch_hits 3501951 # ITB hits
342system.cpu0.itb.fetch_misses 3871 # ITB misses
343system.cpu0.itb.fetch_acv 184 # ITB acv
344system.cpu0.itb.fetch_accesses 3505822 # ITB accesses
345system.cpu0.itb.read_hits 0 # DTB read hits
346system.cpu0.itb.read_misses 0 # DTB read misses
347system.cpu0.itb.read_acv 0 # DTB read access violations
348system.cpu0.itb.read_accesses 0 # DTB read accesses
349system.cpu0.itb.write_hits 0 # DTB write hits
350system.cpu0.itb.write_misses 0 # DTB write misses
351system.cpu0.itb.write_acv 0 # DTB write access violations
352system.cpu0.itb.write_accesses 0 # DTB write accesses
353system.cpu0.itb.data_hits 0 # DTB hits
354system.cpu0.itb.data_misses 0 # DTB misses
355system.cpu0.itb.data_acv 0 # DTB access violations
356system.cpu0.itb.data_accesses 0 # DTB accesses
357system.cpu0.numCycles 3923838766 # number of cpu cycles simulated
358system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
359system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
360system.cpu0.committedInsts 47743384 # Number of instructions committed
361system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed
362system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses
363system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses
364system.cpu0.num_func_calls 1202353 # number of times a function call or return occured
365system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls
366system.cpu0.num_int_insts 44279734 # number of integer instructions
367system.cpu0.num_fp_insts 210698 # number of float instructions
368system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read
369system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written
370system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read
371system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written
372system.cpu0.num_mem_refs 12599731 # number of memory refs
373system.cpu0.num_load_insts 7519361 # Number of load instructions
374system.cpu0.num_store_insts 5080370 # Number of store instructions
375system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles
376system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles
377system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles
378system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles
379system.cpu0.Branches 7198745 # Number of branches fetched
380system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction
381system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction
382system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction
383system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction
384system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction
385system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction
386system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction
387system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction
388system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction
389system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction
390system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction
391system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction
392system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction
393system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction
394system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction
395system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction
396system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction
397system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction
398system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction
399system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction
400system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction
401system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction
402system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction
403system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction
404system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction
405system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction
406system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction
407system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction
408system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction
409system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction
410system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction
411system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction
412system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction
413system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
414system.cpu0.op_class::total 47751984 # Class of executed instruction
415system.cpu0.kern.inst.arm 0 # number of arm instructions executed
416system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed
417system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed
418system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl
419system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
420system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl
421system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl
422system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl
423system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl
424system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl
425system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
426system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
427system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl
428system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl
429system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl
430system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl
431system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl
432system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl
433system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl
434system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl
435system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl
436system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl
437system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
438system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
439system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
440system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl
441system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl
442system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
443system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
444system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
445system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
446system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
447system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
448system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
449system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
450system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
451system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
452system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
453system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
454system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
455system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
456system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
457system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
458system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
459system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
460system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
461system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
462system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
463system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
464system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
465system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
466system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
467system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
468system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
469system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
470system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
471system.cpu0.kern.syscall::total 222 # number of syscalls executed
472system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
473system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed
474system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
475system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
476system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
477system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed
478system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
479system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
480system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed
481system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed
482system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
483system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed
484system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
485system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed
486system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed
487system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
488system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
489system.cpu0.kern.callpal::total 149812 # number of callpals executed
490system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches
491system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
492system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
493system.cpu0.kern.mode_good::kernel 1282
494system.cpu0.kern.mode_good::user 1282
495system.cpu0.kern.mode_good::idle 0
496system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches
497system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
498system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
499system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches
500system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode
501system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode
502system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
503system.cpu0.kern.swap_context 3068 # number of times the context was actually changed
504system.cpu0.dcache.tags.replacements 1180939 # number of replacements
505system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use
506system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks.
507system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks.
508system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks.
509system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit.
510system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor
511system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy
512system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy
513system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id
514system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id
515system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id
516system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id
517system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses
518system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses
519system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits
520system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits
521system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits
522system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits
523system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits
524system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits
525system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits
526system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits
527system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits
528system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits
529system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits
530system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits
531system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses
532system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses
533system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses
534system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses
535system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses
536system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses
537system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses
538system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses
539system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses
540system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses
541system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses
542system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses
543system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles
544system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles
545system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906402435 # number of WriteReq miss cycles
546system.cpu0.dcache.WriteReq_miss_latency::total 10906402435 # number of WriteReq miss cycles
547system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles
548system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles
549system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles
550system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles
551system.cpu0.dcache.demand_miss_latency::cpu0.data 39966793434 # number of demand (read+write) miss cycles
552system.cpu0.dcache.demand_miss_latency::total 39966793434 # number of demand (read+write) miss cycles
553system.cpu0.dcache.overall_miss_latency::cpu0.data 39966793434 # number of overall miss cycles
554system.cpu0.dcache.overall_miss_latency::total 39966793434 # number of overall miss cycles
555system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses)
556system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses)
557system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses)
558system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses)
559system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses)
560system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses)
561system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses)
562system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses)
563system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses
564system.cpu0.dcache.demand_accesses::total 12261297 # number of demand (read+write) accesses
565system.cpu0.dcache.overall_accesses::cpu0.data 12261297 # number of overall (read+write) accesses
566system.cpu0.dcache.overall_accesses::total 12261297 # number of overall (read+write) accesses
567system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127696 # miss rate for ReadReq accesses
568system.cpu0.dcache.ReadReq_miss_rate::total 0.127696 # miss rate for ReadReq accesses
569system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051247 # miss rate for WriteReq accesses
570system.cpu0.dcache.WriteReq_miss_rate::total 0.051247 # miss rate for WriteReq accesses
571system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088684 # miss rate for LoadLockedReq accesses
572system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088684 # miss rate for LoadLockedReq accesses
573system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses
574system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses
575system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses
576system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses
577system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses
578system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses
579system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency
580system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency
581system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232 # average WriteReq miss latency
582system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232 # average WriteReq miss latency
583system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency
584system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency
585system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency
586system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency
587system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
588system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101 # average overall miss latency
589system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
590system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101 # average overall miss latency
591system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
592system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
593system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
594system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
595system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
596system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
597system.cpu0.dcache.fast_writes 0 # number of fast writes performed
598system.cpu0.dcache.cache_copies 0 # number of cache copies performed
599system.cpu0.dcache.writebacks::writebacks 679102 # number of writebacks
600system.cpu0.dcache.writebacks::total 679102 # number of writebacks
601system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938638 # number of ReadReq MSHR misses
602system.cpu0.dcache.ReadReq_mshr_misses::total 938638 # number of ReadReq MSHR misses
603system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251661 # number of WriteReq MSHR misses
604system.cpu0.dcache.WriteReq_mshr_misses::total 251661 # number of WriteReq MSHR misses
605system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses
606system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses
607system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses
608system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses
609system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses
610system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses
611system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses
612system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses

613system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
614system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable
615system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable
616system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10834 # number of WriteReq MSHR uncacheable
617system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses
618system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17944 # number of overall MSHR uncacheable misses

613system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles
614system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles
615system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
616system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles
617system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles
618system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles
619system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles
620system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles
621system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003535066 # number of demand (read+write) MSHR miss cycles
622system.cpu0.dcache.demand_mshr_miss_latency::total 38003535066 # number of demand (read+write) MSHR miss cycles
623system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003535066 # number of overall MSHR miss cycles
624system.cpu0.dcache.overall_mshr_miss_latency::total 38003535066 # number of overall MSHR miss cycles
625system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles
626system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles
627system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles
628system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles
629system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles
630system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles
631system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses
632system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses
633system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses
634system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses
635system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses
636system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses
637system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses
638system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses
639system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses
640system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses
641system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses
642system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses
643system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency
644system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency
645system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497 # average WriteReq mshr miss latency
646system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497 # average WriteReq mshr miss latency
647system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency
648system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency
649system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency
650system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency
651system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
652system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
653system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
654system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency

619system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles
620system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles
621system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
622system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles
623system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles
624system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles
625system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles
626system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles
627system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003535066 # number of demand (read+write) MSHR miss cycles
628system.cpu0.dcache.demand_mshr_miss_latency::total 38003535066 # number of demand (read+write) MSHR miss cycles
629system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003535066 # number of overall MSHR miss cycles
630system.cpu0.dcache.overall_mshr_miss_latency::total 38003535066 # number of overall MSHR miss cycles
631system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles
632system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles
633system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles
634system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles
635system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles
636system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles
637system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses
638system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses
639system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses
640system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses
641system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses
642system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses
643system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses
644system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses
645system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses
646system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses
647system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses
648system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses
649system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency
650system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency
651system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.210497 # average WriteReq mshr miss latency
652system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.210497 # average WriteReq mshr miss latency
653system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency
654system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency
655system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency
656system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency
657system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
658system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
659system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
660system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency

655system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
656system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
657system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
658system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
659system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
660system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

661system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899 # average ReadReq mshr uncacheable latency
662system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899 # average ReadReq mshr uncacheable latency
663system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 211730.893483 # average WriteReq mshr uncacheable latency
664system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483 # average WriteReq mshr uncacheable latency
665system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210003.817432 # average overall mshr uncacheable latency
666system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432 # average overall mshr uncacheable latency

661system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
662system.cpu0.icache.tags.replacements 698758 # number of replacements
663system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use
664system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks.
665system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks.
666system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks.
667system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit.
668system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor
669system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992492 # Average percentage of cache occupancy
670system.cpu0.icache.tags.occ_percent::total 0.992492 # Average percentage of cache occupancy
671system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
672system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id
673system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id
674system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
675system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses
676system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses
677system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits
678system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits
679system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits
680system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits
681system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits
682system.cpu0.icache.overall_hits::total 47052596 # number of overall hits
683system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses
684system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses
685system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses
686system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses
687system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses
688system.cpu0.icache.overall_misses::total 699388 # number of overall misses
689system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles
690system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles
691system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles
692system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles
693system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles
694system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles
695system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses)
696system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses)
697system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses
698system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses
699system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses
700system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses
701system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses
702system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses
703system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses
704system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses
705system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses
706system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses
707system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency
708system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency
709system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency
710system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency
711system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency
712system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency
713system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
714system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
715system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
716system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
717system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
718system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
719system.cpu0.icache.fast_writes 0 # number of fast writes performed
720system.cpu0.icache.cache_copies 0 # number of cache copies performed
721system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses
722system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses
723system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses
724system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses
725system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses
726system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses
727system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles
728system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles
729system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles
730system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles
731system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles
732system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles
733system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses
734system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses
735system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses
736system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses
737system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses
738system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses
739system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency
740system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency
741system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency
742system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency
743system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency
744system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency
745system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
746system.cpu1.dtb.fetch_hits 0 # ITB hits
747system.cpu1.dtb.fetch_misses 0 # ITB misses
748system.cpu1.dtb.fetch_acv 0 # ITB acv
749system.cpu1.dtb.fetch_accesses 0 # ITB accesses
750system.cpu1.dtb.read_hits 2419579 # DTB read hits
751system.cpu1.dtb.read_misses 2992 # DTB read misses
752system.cpu1.dtb.read_acv 0 # DTB read access violations
753system.cpu1.dtb.read_accesses 239363 # DTB read accesses
754system.cpu1.dtb.write_hits 1757217 # DTB write hits
755system.cpu1.dtb.write_misses 341 # DTB write misses
756system.cpu1.dtb.write_acv 29 # DTB write access violations
757system.cpu1.dtb.write_accesses 105247 # DTB write accesses
758system.cpu1.dtb.data_hits 4176796 # DTB hits
759system.cpu1.dtb.data_misses 3333 # DTB misses
760system.cpu1.dtb.data_acv 29 # DTB access violations
761system.cpu1.dtb.data_accesses 344610 # DTB accesses
762system.cpu1.itb.fetch_hits 1964101 # ITB hits
763system.cpu1.itb.fetch_misses 1216 # ITB misses
764system.cpu1.itb.fetch_acv 0 # ITB acv
765system.cpu1.itb.fetch_accesses 1965317 # ITB accesses
766system.cpu1.itb.read_hits 0 # DTB read hits
767system.cpu1.itb.read_misses 0 # DTB read misses
768system.cpu1.itb.read_acv 0 # DTB read access violations
769system.cpu1.itb.read_accesses 0 # DTB read accesses
770system.cpu1.itb.write_hits 0 # DTB write hits
771system.cpu1.itb.write_misses 0 # DTB write misses
772system.cpu1.itb.write_acv 0 # DTB write access violations
773system.cpu1.itb.write_accesses 0 # DTB write accesses
774system.cpu1.itb.data_hits 0 # DTB hits
775system.cpu1.itb.data_misses 0 # DTB misses
776system.cpu1.itb.data_acv 0 # DTB access violations
777system.cpu1.itb.data_accesses 0 # DTB accesses
778system.cpu1.numCycles 3925225373 # number of cpu cycles simulated
779system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
780system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
781system.cpu1.committedInsts 13155254 # Number of instructions committed
782system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed
783system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses
784system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses
785system.cpu1.num_func_calls 411301 # number of times a function call or return occured
786system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls
787system.cpu1.num_int_insts 12132982 # number of integer instructions
788system.cpu1.num_fp_insts 173111 # number of float instructions
789system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read
790system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written
791system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read
792system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written
793system.cpu1.num_mem_refs 4200357 # number of memory refs
794system.cpu1.num_load_insts 2433886 # Number of load instructions
795system.cpu1.num_store_insts 1766471 # Number of store instructions
796system.cpu1.num_idle_cycles 3876126901.998025 # Number of idle cycles
797system.cpu1.num_busy_cycles 49098471.001975 # Number of busy cycles
798system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles
799system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles
800system.cpu1.Branches 1871330 # Number of branches fetched
801system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction
802system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction
803system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction
804system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction
805system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction
806system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction
807system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction
808system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction
809system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction
810system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction
811system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction
812system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction
813system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction
814system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction
815system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction
816system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction
817system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction
818system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction
819system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction
820system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction
821system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction
822system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction
823system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction
824system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction
825system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction
826system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction
827system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction
828system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction
829system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction
830system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction
831system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction
832system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction
833system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction
834system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
835system.cpu1.op_class::total 13158616 # Class of executed instruction
836system.cpu1.kern.inst.arm 0 # number of arm instructions executed
837system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
838system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed
839system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl
840system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl
841system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl
842system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl
843system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl
844system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl
845system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl
846system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl
847system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl
848system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl
849system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl
850system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl
851system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl
852system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl
853system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl
854system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl
855system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
856system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
857system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl
858system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl
859system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
860system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
861system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
862system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
863system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
864system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
865system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
866system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
867system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
868system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
869system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
870system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
871system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
872system.cpu1.kern.syscall::total 104 # number of syscalls executed
873system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
874system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed
875system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
876system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
877system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed
878system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
879system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
880system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed
881system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed
882system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed
883system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed
884system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed
885system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed
886system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
887system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
888system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
889system.cpu1.kern.callpal::total 71473 # number of callpals executed
890system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches
891system.cpu1.kern.mode_switch::user 463 # number of protection mode switches
892system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches
893system.cpu1.kern.mode_good::kernel 890
894system.cpu1.kern.mode_good::user 463
895system.cpu1.kern.mode_good::idle 427
896system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches
897system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
898system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches
899system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches
900system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode
901system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode
902system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode
903system.cpu1.kern.swap_context 1998 # number of times the context was actually changed
904system.cpu1.dcache.tags.replacements 166165 # number of replacements
905system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use
906system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks.
907system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks.
908system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks.
909system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit.
910system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor
911system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy
912system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy
913system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
914system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
915system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
916system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
917system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
918system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses
919system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses
920system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits
921system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits
922system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits
923system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits
924system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits
925system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits
926system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits
927system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits
928system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits
929system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits
930system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits
931system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits
932system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses
933system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses
934system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses
935system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses
936system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses
937system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses
938system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses
939system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses
940system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses
941system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses
942system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses
943system.cpu1.dcache.overall_misses::total 180698 # number of overall misses
944system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles
945system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles
946system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles
947system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles
948system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81193500 # number of LoadLockedReq miss cycles
949system.cpu1.dcache.LoadLockedReq_miss_latency::total 81193500 # number of LoadLockedReq miss cycles
950system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles
951system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles
952system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles
953system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles
954system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles
955system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles
956system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses)
957system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses)
958system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses)
959system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses)
960system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses)
961system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses)
962system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses)
963system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses)
964system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses
965system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses
966system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses
967system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses
968system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses
969system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses
970system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses
971system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses
972system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses
973system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses
974system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses
975system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses
976system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses
977system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses
978system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses
979system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses
980system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency
981system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency
982system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency
983system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency
984system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.537133 # average LoadLockedReq miss latency
985system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.537133 # average LoadLockedReq miss latency
986system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency
987system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency
988system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency
989system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency
990system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency
991system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency
992system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
993system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
994system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
995system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
996system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
997system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
998system.cpu1.dcache.fast_writes 0 # number of fast writes performed
999system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1000system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks
1001system.cpu1.dcache.writebacks::total 114146 # number of writebacks
1002system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses
1003system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses
1004system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses
1005system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses
1006system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses
1007system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses
1008system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses
1009system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses
1010system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses
1011system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses
1012system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses
1013system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses

667system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
668system.cpu0.icache.tags.replacements 698758 # number of replacements
669system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use
670system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks.
671system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks.
672system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks.
673system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit.
674system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor
675system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992492 # Average percentage of cache occupancy
676system.cpu0.icache.tags.occ_percent::total 0.992492 # Average percentage of cache occupancy
677system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
678system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id
679system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id
680system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
681system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses
682system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses
683system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits
684system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits
685system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits
686system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits
687system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits
688system.cpu0.icache.overall_hits::total 47052596 # number of overall hits
689system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses
690system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses
691system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses
692system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses
693system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses
694system.cpu0.icache.overall_misses::total 699388 # number of overall misses
695system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles
696system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles
697system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles
698system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles
699system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles
700system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles
701system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses)
702system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses)
703system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses
704system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses
705system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses
706system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses
707system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses
708system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses
709system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses
710system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses
711system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses
712system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses
713system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency
714system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency
715system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency
716system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency
717system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency
718system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency
719system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
720system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
721system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
722system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
723system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
724system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
725system.cpu0.icache.fast_writes 0 # number of fast writes performed
726system.cpu0.icache.cache_copies 0 # number of cache copies performed
727system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses
728system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses
729system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses
730system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses
731system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses
732system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses
733system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles
734system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles
735system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles
736system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles
737system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles
738system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles
739system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses
740system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses
741system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses
742system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses
743system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses
744system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses
745system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency
746system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency
747system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency
748system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency
749system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency
750system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency
751system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
752system.cpu1.dtb.fetch_hits 0 # ITB hits
753system.cpu1.dtb.fetch_misses 0 # ITB misses
754system.cpu1.dtb.fetch_acv 0 # ITB acv
755system.cpu1.dtb.fetch_accesses 0 # ITB accesses
756system.cpu1.dtb.read_hits 2419579 # DTB read hits
757system.cpu1.dtb.read_misses 2992 # DTB read misses
758system.cpu1.dtb.read_acv 0 # DTB read access violations
759system.cpu1.dtb.read_accesses 239363 # DTB read accesses
760system.cpu1.dtb.write_hits 1757217 # DTB write hits
761system.cpu1.dtb.write_misses 341 # DTB write misses
762system.cpu1.dtb.write_acv 29 # DTB write access violations
763system.cpu1.dtb.write_accesses 105247 # DTB write accesses
764system.cpu1.dtb.data_hits 4176796 # DTB hits
765system.cpu1.dtb.data_misses 3333 # DTB misses
766system.cpu1.dtb.data_acv 29 # DTB access violations
767system.cpu1.dtb.data_accesses 344610 # DTB accesses
768system.cpu1.itb.fetch_hits 1964101 # ITB hits
769system.cpu1.itb.fetch_misses 1216 # ITB misses
770system.cpu1.itb.fetch_acv 0 # ITB acv
771system.cpu1.itb.fetch_accesses 1965317 # ITB accesses
772system.cpu1.itb.read_hits 0 # DTB read hits
773system.cpu1.itb.read_misses 0 # DTB read misses
774system.cpu1.itb.read_acv 0 # DTB read access violations
775system.cpu1.itb.read_accesses 0 # DTB read accesses
776system.cpu1.itb.write_hits 0 # DTB write hits
777system.cpu1.itb.write_misses 0 # DTB write misses
778system.cpu1.itb.write_acv 0 # DTB write access violations
779system.cpu1.itb.write_accesses 0 # DTB write accesses
780system.cpu1.itb.data_hits 0 # DTB hits
781system.cpu1.itb.data_misses 0 # DTB misses
782system.cpu1.itb.data_acv 0 # DTB access violations
783system.cpu1.itb.data_accesses 0 # DTB accesses
784system.cpu1.numCycles 3925225373 # number of cpu cycles simulated
785system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
786system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
787system.cpu1.committedInsts 13155254 # Number of instructions committed
788system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed
789system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses
790system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses
791system.cpu1.num_func_calls 411301 # number of times a function call or return occured
792system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls
793system.cpu1.num_int_insts 12132982 # number of integer instructions
794system.cpu1.num_fp_insts 173111 # number of float instructions
795system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read
796system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written
797system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read
798system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written
799system.cpu1.num_mem_refs 4200357 # number of memory refs
800system.cpu1.num_load_insts 2433886 # Number of load instructions
801system.cpu1.num_store_insts 1766471 # Number of store instructions
802system.cpu1.num_idle_cycles 3876126901.998025 # Number of idle cycles
803system.cpu1.num_busy_cycles 49098471.001975 # Number of busy cycles
804system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles
805system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles
806system.cpu1.Branches 1871330 # Number of branches fetched
807system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction
808system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction
809system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction
810system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction
811system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction
812system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction
813system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction
814system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction
815system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction
816system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction
817system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction
818system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction
819system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction
820system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction
821system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction
822system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction
823system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction
824system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction
825system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction
826system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction
827system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction
828system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction
829system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction
830system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction
831system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction
832system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction
833system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction
834system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction
835system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction
836system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction
837system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction
838system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction
839system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction
840system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
841system.cpu1.op_class::total 13158616 # Class of executed instruction
842system.cpu1.kern.inst.arm 0 # number of arm instructions executed
843system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed
844system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed
845system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl
846system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl
847system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl
848system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl
849system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl
850system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl
851system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl
852system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl
853system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl
854system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl
855system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl
856system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl
857system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl
858system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl
859system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl
860system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl
861system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
862system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
863system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl
864system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl
865system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
866system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
867system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
868system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
869system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
870system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
871system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
872system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
873system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
874system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
875system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
876system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
877system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
878system.cpu1.kern.syscall::total 104 # number of syscalls executed
879system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
880system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed
881system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
882system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
883system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed
884system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
885system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
886system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed
887system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed
888system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed
889system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed
890system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed
891system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed
892system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
893system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
894system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
895system.cpu1.kern.callpal::total 71473 # number of callpals executed
896system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches
897system.cpu1.kern.mode_switch::user 463 # number of protection mode switches
898system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches
899system.cpu1.kern.mode_good::kernel 890
900system.cpu1.kern.mode_good::user 463
901system.cpu1.kern.mode_good::idle 427
902system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches
903system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
904system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches
905system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches
906system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode
907system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode
908system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode
909system.cpu1.kern.swap_context 1998 # number of times the context was actually changed
910system.cpu1.dcache.tags.replacements 166165 # number of replacements
911system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use
912system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks.
913system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks.
914system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks.
915system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit.
916system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor
917system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy
918system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy
919system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
920system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
921system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
922system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
923system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
924system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses
925system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses
926system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits
927system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits
928system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits
929system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits
930system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits
931system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits
932system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits
933system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits
934system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits
935system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits
936system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits
937system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits
938system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses
939system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses
940system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses
941system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses
942system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses
943system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses
944system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses
945system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses
946system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses
947system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses
948system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses
949system.cpu1.dcache.overall_misses::total 180698 # number of overall misses
950system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles
951system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles
952system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles
953system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles
954system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81193500 # number of LoadLockedReq miss cycles
955system.cpu1.dcache.LoadLockedReq_miss_latency::total 81193500 # number of LoadLockedReq miss cycles
956system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles
957system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles
958system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles
959system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles
960system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles
961system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles
962system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses)
963system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses)
964system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses)
965system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses)
966system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses)
967system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses)
968system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses)
969system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses)
970system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses
971system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses
972system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses
973system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses
974system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses
975system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses
976system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses
977system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses
978system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses
979system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses
980system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses
981system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses
982system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses
983system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses
984system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses
985system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses
986system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency
987system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency
988system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency
989system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency
990system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.537133 # average LoadLockedReq miss latency
991system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.537133 # average LoadLockedReq miss latency
992system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency
993system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency
994system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency
995system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency
996system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency
997system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency
998system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
999system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1000system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1001system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1002system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1003system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1004system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1005system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1006system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks
1007system.cpu1.dcache.writebacks::total 114146 # number of writebacks
1008system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses
1009system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses
1010system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses
1011system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses
1012system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses
1013system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses
1014system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses
1015system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses
1016system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses
1017system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses
1018system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses
1019system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses

1020system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
1021system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable
1022system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3218 # number of WriteReq MSHR uncacheable
1023system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3218 # number of WriteReq MSHR uncacheable
1024system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3307 # number of overall MSHR uncacheable misses
1025system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3307 # number of overall MSHR uncacheable misses

1014system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles
1015system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles
1016system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles
1017system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles
1018system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles
1019system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles
1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles
1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles
1022system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles
1023system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles
1024system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles
1025system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles
1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18866000 # number of ReadReq MSHR uncacheable cycles
1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18866000 # number of ReadReq MSHR uncacheable cycles
1028system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716370000 # number of WriteReq MSHR uncacheable cycles
1029system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716370000 # number of WriteReq MSHR uncacheable cycles
1030system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735236000 # number of overall MSHR uncacheable cycles
1031system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735236000 # number of overall MSHR uncacheable cycles
1032system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses
1033system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses
1034system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses
1035system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses
1036system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses
1037system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses
1038system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses
1039system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses
1040system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses
1041system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses
1042system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses
1043system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses
1044system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency
1045system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency
1046system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency
1047system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency
1048system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency
1049system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency
1050system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency
1051system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency
1052system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
1053system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
1054system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
1055system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency

1026system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles
1027system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles
1028system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles
1029system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles
1030system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67822500 # number of LoadLockedReq MSHR miss cycles
1031system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67822500 # number of LoadLockedReq MSHR miss cycles
1032system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles
1033system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles
1034system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles
1035system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles
1036system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles
1037system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles
1038system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18866000 # number of ReadReq MSHR uncacheable cycles
1039system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18866000 # number of ReadReq MSHR uncacheable cycles
1040system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716370000 # number of WriteReq MSHR uncacheable cycles
1041system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716370000 # number of WriteReq MSHR uncacheable cycles
1042system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735236000 # number of overall MSHR uncacheable cycles
1043system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735236000 # number of overall MSHR uncacheable cycles
1044system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses
1045system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses
1046system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses
1047system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses
1048system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses
1049system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses
1050system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses
1051system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses
1052system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses
1053system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses
1054system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses
1055system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses
1056system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency
1057system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency
1058system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency
1059system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency
1060system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.537133 # average LoadLockedReq mshr miss latency
1061system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.537133 # average LoadLockedReq mshr miss latency
1062system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency
1063system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency
1064system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
1065system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
1066system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
1067system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency

1056system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1058system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1059system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1060system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1061system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

1068system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 211977.528090 # average ReadReq mshr uncacheable latency
1069system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211977.528090 # average ReadReq mshr uncacheable latency
1070system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 222613.424487 # average WriteReq mshr uncacheable latency
1071system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 222613.424487 # average WriteReq mshr uncacheable latency
1072system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 222327.184760 # average overall mshr uncacheable latency
1073system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760 # average overall mshr uncacheable latency

1062system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1063system.cpu1.icache.tags.replacements 315648 # number of replacements
1064system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use
1065system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks.
1066system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks.
1067system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks.
1068system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit.
1069system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor
1070system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy
1071system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy
1072system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1073system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
1074system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
1075system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
1076system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
1077system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1078system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses
1079system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses
1080system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits
1081system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits
1082system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits
1083system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits
1084system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits
1085system.cpu1.icache.overall_hits::total 12842415 # number of overall hits
1086system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses
1087system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses
1088system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses
1089system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses
1090system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses
1091system.cpu1.icache.overall_misses::total 316202 # number of overall misses
1092system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles
1093system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles
1094system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles
1095system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles
1096system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles
1097system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles
1098system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses)
1099system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses)
1100system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses
1101system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses
1102system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses
1103system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses
1104system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses
1105system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses
1106system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses
1107system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses
1108system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses
1109system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses
1110system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency
1111system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency
1112system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency
1113system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency
1114system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency
1115system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency
1116system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1117system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1118system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1119system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1120system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1121system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1122system.cpu1.icache.fast_writes 0 # number of fast writes performed
1123system.cpu1.icache.cache_copies 0 # number of cache copies performed
1124system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses
1125system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses
1126system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses
1127system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses
1128system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses
1129system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses
1130system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles
1131system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles
1132system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles
1133system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles
1134system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles
1135system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles
1136system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses
1137system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses
1138system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses
1139system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses
1140system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses
1141system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses
1142system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency
1143system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency
1144system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency
1145system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency
1146system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency
1147system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency
1148system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1149system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1150system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1151system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1152system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1153system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1154system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1155system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1156system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1157system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1158system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1159system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1160system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1161system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
1162system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
1163system.iobus.trans_dist::WriteReq 55604 # Transaction distribution
1164system.iobus.trans_dist::WriteResp 14052 # Transaction distribution
1165system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1166system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes)
1167system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1168system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1169system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1170system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1171system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1172system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
1173system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1174system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1175system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1176system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1177system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1178system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes)
1179system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
1180system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
1181system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes)
1182system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes)
1183system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
1184system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1185system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1186system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1187system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1188system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
1189system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1190system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1191system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1192system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1193system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1194system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes)
1195system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
1196system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
1197system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes)
1198system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks)
1199system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1200system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1201system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1202system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1203system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1204system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1205system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1206system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1207system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1208system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1209system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1210system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
1211system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1212system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1213system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1214system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1215system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1216system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1217system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1218system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1219system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1220system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks)
1221system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1222system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1223system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1224system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks)
1225system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1226system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks)
1227system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1228system.iocache.tags.replacements 41694 # number of replacements
1229system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use
1230system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1231system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
1232system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1233system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit.
1234system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor
1235system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy
1236system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy
1237system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1238system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1239system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1240system.iocache.tags.tag_accesses 375534 # Number of tag accesses
1241system.iocache.tags.data_accesses 375534 # Number of data accesses
1242system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
1243system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
1244system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
1245system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
1246system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
1247system.iocache.demand_misses::total 174 # number of demand (read+write) misses
1248system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
1249system.iocache.overall_misses::total 174 # number of overall misses
1250system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles
1251system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles
1252system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles
1253system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles
1254system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles
1255system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles
1256system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles
1257system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles
1258system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
1259system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
1260system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
1261system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
1262system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
1263system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
1264system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
1265system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
1266system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1267system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1268system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
1269system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1270system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1271system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1272system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1273system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1274system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency
1275system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency
1276system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency
1277system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency
1278system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency
1279system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency
1280system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency
1281system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency
1282system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked
1283system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1284system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked
1285system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1286system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked
1287system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1288system.iocache.fast_writes 0 # number of fast writes performed
1289system.iocache.cache_copies 0 # number of cache copies performed
1290system.iocache.writebacks::writebacks 41520 # number of writebacks
1291system.iocache.writebacks::total 41520 # number of writebacks
1292system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
1293system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
1294system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
1295system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
1296system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses
1297system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
1298system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses
1299system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses
1300system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles
1301system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles
1302system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles
1303system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles
1304system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles
1305system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles
1306system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles
1307system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles
1308system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1309system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1310system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1311system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1312system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1313system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1314system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1315system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1316system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency
1317system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency
1318system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency
1319system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency
1320system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency
1321system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency
1322system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency
1323system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency
1324system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1325system.l2c.tags.replacements 341367 # number of replacements
1326system.l2c.tags.tagsinuse 65207.739779 # Cycle average of tags in use
1327system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks.
1328system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks.
1329system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks.
1330system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit.
1331system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor
1332system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor
1333system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor
1334system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor
1335system.l2c.tags.occ_blocks::cpu1.data 38.745274 # Average occupied blocks per requestor
1336system.l2c.tags.occ_percent::writebacks 0.842038 # Average percentage of cache occupancy
1337system.l2c.tags.occ_percent::cpu0.inst 0.074069 # Average percentage of cache occupancy
1338system.l2c.tags.occ_percent::cpu0.data 0.076558 # Average percentage of cache occupancy
1339system.l2c.tags.occ_percent::cpu1.inst 0.001735 # Average percentage of cache occupancy
1340system.l2c.tags.occ_percent::cpu1.data 0.000591 # Average percentage of cache occupancy
1341system.l2c.tags.occ_percent::total 0.994991 # Average percentage of cache occupancy
1342system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id
1343system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
1344system.l2c.tags.age_task_id_blocks_1024::1 1104 # Occupied blocks per task id
1345system.l2c.tags.age_task_id_blocks_1024::2 5014 # Occupied blocks per task id
1346system.l2c.tags.age_task_id_blocks_1024::3 6093 # Occupied blocks per task id
1347system.l2c.tags.age_task_id_blocks_1024::4 52607 # Occupied blocks per task id
1348system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id
1349system.l2c.tags.tag_accesses 25960355 # Number of tag accesses
1350system.l2c.tags.data_accesses 25960355 # Number of data accesses
1351system.l2c.ReadReq_hits::cpu0.inst 686297 # number of ReadReq hits
1352system.l2c.ReadReq_hits::cpu0.data 664438 # number of ReadReq hits
1353system.l2c.ReadReq_hits::cpu1.inst 315744 # number of ReadReq hits
1354system.l2c.ReadReq_hits::cpu1.data 108706 # number of ReadReq hits
1355system.l2c.ReadReq_hits::total 1775185 # number of ReadReq hits
1356system.l2c.Writeback_hits::writebacks 793248 # number of Writeback hits
1357system.l2c.Writeback_hits::total 793248 # number of Writeback hits
1358system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits
1359system.l2c.UpgradeReq_hits::cpu1.data 524 # number of UpgradeReq hits
1360system.l2c.UpgradeReq_hits::total 707 # number of UpgradeReq hits
1361system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits
1362system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
1363system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits
1364system.l2c.ReadExReq_hits::cpu0.data 126541 # number of ReadExReq hits
1365system.l2c.ReadExReq_hits::cpu1.data 47234 # number of ReadExReq hits
1366system.l2c.ReadExReq_hits::total 173775 # number of ReadExReq hits
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1431system.l2c.Writeback_accesses::total 793248 # number of Writeback accesses(hits+misses)
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1457system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768142 # miss rate for UpgradeReq accesses
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1476system.l2c.ReadReq_avg_miss_latency::cpu0.data 72526.787686 # average ReadReq miss latency
1477system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81764.223195 # average ReadReq miss latency
1478system.l2c.ReadReq_avg_miss_latency::cpu1.data 79026.709402 # average ReadReq miss latency
1479system.l2c.ReadReq_avg_miss_latency::total 72914.086343 # average ReadReq miss latency
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1481system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7642.901498 # average UpgradeReq miss latency
1482system.l2c.UpgradeReq_avg_miss_latency::total 3181.116756 # average UpgradeReq miss latency
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1484system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 207.351171 # average SCUpgradeReq miss latency
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1487system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81969.151009 # average ReadExReq miss latency
1488system.l2c.ReadExReq_avg_miss_latency::total 76368.034848 # average ReadExReq miss latency
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1491system.l2c.demand_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency
1492system.l2c.demand_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency
1493system.l2c.demand_avg_miss_latency::total 73949.695537 # average overall miss latency
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1495system.l2c.overall_avg_miss_latency::cpu0.data 73578.388617 # average overall miss latency
1496system.l2c.overall_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency
1497system.l2c.overall_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency
1498system.l2c.overall_avg_miss_latency::total 73949.695537 # average overall miss latency
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1501system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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1511system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
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1514system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
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1517system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
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1524system.l2c.UpgradeReq_mshr_misses::cpu1.data 1736 # number of UpgradeReq MSHR misses
1525system.l2c.UpgradeReq_mshr_misses::total 4685 # number of UpgradeReq MSHR misses
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1527system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses
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1075system.cpu1.icache.tags.replacements 315648 # number of replacements
1076system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use
1077system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks.
1078system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks.
1079system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks.
1080system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit.
1081system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor
1082system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy
1083system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy
1084system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1085system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
1086system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
1087system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
1088system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
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1091system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses
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1116system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses
1117system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses
1118system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses
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1121system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses
1122system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency
1123system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency
1124system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency
1125system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency
1126system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency
1127system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency
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1131system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1132system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1133system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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1145system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles
1146system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles
1147system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles
1148system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses
1149system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses
1150system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses
1151system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses
1152system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses
1153system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses
1154system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency
1155system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency
1156system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency
1157system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency
1158system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency
1159system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency
1160system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1161system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1162system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1163system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1164system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1165system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1166system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1167system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1168system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1169system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1170system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1171system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1172system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1173system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
1174system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
1175system.iobus.trans_dist::WriteReq 55604 # Transaction distribution
1176system.iobus.trans_dist::WriteResp 14052 # Transaction distribution
1177system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1178system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes)
1179system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1180system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1181system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1182system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1183system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1184system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
1185system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1186system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1187system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1188system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1189system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1190system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes)
1191system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
1192system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
1193system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes)
1194system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes)
1195system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
1196system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1197system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1198system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1199system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1200system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
1201system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1202system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1203system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1204system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1205system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1206system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes)
1207system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
1208system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
1209system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes)
1210system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks)
1211system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1212system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1213system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1214system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1215system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1216system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1217system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1218system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1219system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1220system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1221system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1222system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
1223system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1224system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1225system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1226system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1227system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1228system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1229system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1230system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1231system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1232system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks)
1233system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1234system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1235system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1236system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks)
1237system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1238system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks)
1239system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1240system.iocache.tags.replacements 41694 # number of replacements
1241system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use
1242system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1243system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
1244system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1245system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit.
1246system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor
1247system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy
1248system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy
1249system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1250system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1251system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1252system.iocache.tags.tag_accesses 375534 # Number of tag accesses
1253system.iocache.tags.data_accesses 375534 # Number of data accesses
1254system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
1255system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
1256system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
1257system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
1258system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
1259system.iocache.demand_misses::total 174 # number of demand (read+write) misses
1260system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
1261system.iocache.overall_misses::total 174 # number of overall misses
1262system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles
1263system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles
1264system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles
1265system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles
1266system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles
1267system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles
1268system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles
1269system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles
1270system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
1271system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
1272system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
1273system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
1274system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
1275system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
1276system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
1277system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
1278system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1279system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1280system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
1281system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1282system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1283system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1284system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1285system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1286system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency
1287system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency
1288system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency
1289system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency
1290system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency
1291system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency
1292system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency
1293system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency
1294system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked
1295system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1296system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked
1297system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1298system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked
1299system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1300system.iocache.fast_writes 0 # number of fast writes performed
1301system.iocache.cache_copies 0 # number of cache copies performed
1302system.iocache.writebacks::writebacks 41520 # number of writebacks
1303system.iocache.writebacks::total 41520 # number of writebacks
1304system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
1305system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
1306system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
1307system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
1308system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses
1309system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
1310system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses
1311system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses
1312system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles
1313system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles
1314system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles
1315system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles
1316system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles
1317system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles
1318system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles
1319system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles
1320system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1321system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1322system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1323system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1324system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1325system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1326system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1327system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1328system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency
1329system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency
1330system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency
1331system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency
1332system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency
1333system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency
1334system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency
1335system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency
1336system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1337system.l2c.tags.replacements 341367 # number of replacements
1338system.l2c.tags.tagsinuse 65207.739779 # Cycle average of tags in use
1339system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks.
1340system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks.
1341system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks.
1342system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit.
1343system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor
1344system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor
1345system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor
1346system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor
1347system.l2c.tags.occ_blocks::cpu1.data 38.745274 # Average occupied blocks per requestor
1348system.l2c.tags.occ_percent::writebacks 0.842038 # Average percentage of cache occupancy
1349system.l2c.tags.occ_percent::cpu0.inst 0.074069 # Average percentage of cache occupancy
1350system.l2c.tags.occ_percent::cpu0.data 0.076558 # Average percentage of cache occupancy
1351system.l2c.tags.occ_percent::cpu1.inst 0.001735 # Average percentage of cache occupancy
1352system.l2c.tags.occ_percent::cpu1.data 0.000591 # Average percentage of cache occupancy
1353system.l2c.tags.occ_percent::total 0.994991 # Average percentage of cache occupancy
1354system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id
1355system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
1356system.l2c.tags.age_task_id_blocks_1024::1 1104 # Occupied blocks per task id
1357system.l2c.tags.age_task_id_blocks_1024::2 5014 # Occupied blocks per task id
1358system.l2c.tags.age_task_id_blocks_1024::3 6093 # Occupied blocks per task id
1359system.l2c.tags.age_task_id_blocks_1024::4 52607 # Occupied blocks per task id
1360system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id
1361system.l2c.tags.tag_accesses 25960355 # Number of tag accesses
1362system.l2c.tags.data_accesses 25960355 # Number of data accesses
1363system.l2c.ReadReq_hits::cpu0.inst 686297 # number of ReadReq hits
1364system.l2c.ReadReq_hits::cpu0.data 664438 # number of ReadReq hits
1365system.l2c.ReadReq_hits::cpu1.inst 315744 # number of ReadReq hits
1366system.l2c.ReadReq_hits::cpu1.data 108706 # number of ReadReq hits
1367system.l2c.ReadReq_hits::total 1775185 # number of ReadReq hits
1368system.l2c.Writeback_hits::writebacks 793248 # number of Writeback hits
1369system.l2c.Writeback_hits::total 793248 # number of Writeback hits
1370system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits
1371system.l2c.UpgradeReq_hits::cpu1.data 524 # number of UpgradeReq hits
1372system.l2c.UpgradeReq_hits::total 707 # number of UpgradeReq hits
1373system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits
1374system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
1375system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits
1376system.l2c.ReadExReq_hits::cpu0.data 126541 # number of ReadExReq hits
1377system.l2c.ReadExReq_hits::cpu1.data 47234 # number of ReadExReq hits
1378system.l2c.ReadExReq_hits::total 173775 # number of ReadExReq hits
1379system.l2c.demand_hits::cpu0.inst 686297 # number of demand (read+write) hits
1380system.l2c.demand_hits::cpu0.data 790979 # number of demand (read+write) hits
1381system.l2c.demand_hits::cpu1.inst 315744 # number of demand (read+write) hits
1382system.l2c.demand_hits::cpu1.data 155940 # number of demand (read+write) hits
1383system.l2c.demand_hits::total 1948960 # number of demand (read+write) hits
1384system.l2c.overall_hits::cpu0.inst 686297 # number of overall hits
1385system.l2c.overall_hits::cpu0.data 790979 # number of overall hits
1386system.l2c.overall_hits::cpu1.inst 315744 # number of overall hits
1387system.l2c.overall_hits::cpu1.data 155940 # number of overall hits
1388system.l2c.overall_hits::total 1948960 # number of overall hits
1389system.l2c.ReadReq_misses::cpu0.inst 13070 # number of ReadReq misses
1390system.l2c.ReadReq_misses::cpu0.data 271636 # number of ReadReq misses
1391system.l2c.ReadReq_misses::cpu1.inst 457 # number of ReadReq misses
1392system.l2c.ReadReq_misses::cpu1.data 234 # number of ReadReq misses
1393system.l2c.ReadReq_misses::total 285397 # number of ReadReq misses
1394system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses
1395system.l2c.UpgradeReq_misses::cpu1.data 1736 # number of UpgradeReq misses
1396system.l2c.UpgradeReq_misses::total 4685 # number of UpgradeReq misses
1397system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses
1398system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses
1399system.l2c.SCUpgradeReq_misses::total 1789 # number of SCUpgradeReq misses
1400system.l2c.ReadExReq_misses::cpu0.data 115627 # number of ReadExReq misses
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1581system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses
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1608system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency
1609system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency
1610system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777 # average ReadExReq mshr miss latency
1611system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency
1612system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554 # average ReadExReq mshr miss latency
1613system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency
1614system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency
1615system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
1616system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
1617system.l2c.demand_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
1618system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency
1619system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency
1620system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
1621system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
1622system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency

1563system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles
1564system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles
1565system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles
1566system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles
1567system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles
1568system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles
1569system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles
1570system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles
1571system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15769892 # number of SCUpgradeReq MSHR miss cycles
1572system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15706897 # number of SCUpgradeReq MSHR miss cycles
1573system.l2c.SCUpgradeReq_mshr_miss_latency::total 31476789 # number of SCUpgradeReq MSHR miss cycles
1574system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347146989 # number of ReadExReq MSHR miss cycles
1575system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457723764 # number of ReadExReq MSHR miss cycles
1576system.l2c.ReadExReq_mshr_miss_latency::total 7804870753 # number of ReadExReq MSHR miss cycles
1577system.l2c.demand_mshr_miss_latency::cpu0.inst 888765750 # number of demand (read+write) MSHR miss cycles
1578system.l2c.demand_mshr_miss_latency::cpu0.data 23652214489 # number of demand (read+write) MSHR miss cycles
1579system.l2c.demand_mshr_miss_latency::cpu1.inst 31138500 # number of demand (read+write) MSHR miss cycles
1580system.l2c.demand_mshr_miss_latency::cpu1.data 473285514 # number of demand (read+write) MSHR miss cycles
1581system.l2c.demand_mshr_miss_latency::total 25045404253 # number of demand (read+write) MSHR miss cycles
1582system.l2c.overall_mshr_miss_latency::cpu0.inst 888765750 # number of overall MSHR miss cycles
1583system.l2c.overall_mshr_miss_latency::cpu0.data 23652214489 # number of overall MSHR miss cycles
1584system.l2c.overall_mshr_miss_latency::cpu1.inst 31138500 # number of overall MSHR miss cycles
1585system.l2c.overall_mshr_miss_latency::cpu1.data 473285514 # number of overall MSHR miss cycles
1586system.l2c.overall_mshr_miss_latency::total 25045404253 # number of overall MSHR miss cycles
1587system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1374876000 # number of ReadReq MSHR uncacheable cycles
1588system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17620000 # number of ReadReq MSHR uncacheable cycles
1589system.l2c.ReadReq_mshr_uncacheable_latency::total 1392496000 # number of ReadReq MSHR uncacheable cycles
1590system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153050500 # number of WriteReq MSHR uncacheable cycles
1591system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674536000 # number of WriteReq MSHR uncacheable cycles
1592system.l2c.WriteReq_mshr_uncacheable_latency::total 2827586500 # number of WriteReq MSHR uncacheable cycles
1593system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527926500 # number of overall MSHR uncacheable cycles
1594system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156000 # number of overall MSHR uncacheable cycles
1595system.l2c.overall_mshr_uncacheable_latency::total 4220082500 # number of overall MSHR uncacheable cycles
1596system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for ReadReq accesses
1597system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290186 # mshr miss rate for ReadReq accesses
1598system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for ReadReq accesses
1599system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002148 # mshr miss rate for ReadReq accesses
1600system.l2c.ReadReq_mshr_miss_rate::total 0.138498 # mshr miss rate for ReadReq accesses
1601system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941571 # mshr miss rate for UpgradeReq accesses
1602system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses
1603system.l2c.UpgradeReq_mshr_miss_rate::total 0.868880 # mshr miss rate for UpgradeReq accesses
1604system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961207 # mshr miss rate for SCUpgradeReq accesses
1605system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses
1606system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967550 # mshr miss rate for SCUpgradeReq accesses
1607system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477466 # mshr miss rate for ReadExReq accesses
1608system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122420 # mshr miss rate for ReadExReq accesses
1609system.l2c.ReadExReq_mshr_miss_rate::total 0.412904 # mshr miss rate for ReadExReq accesses
1610system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for demand accesses
1611system.l2c.demand_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for demand accesses
1612system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for demand accesses
1613system.l2c.demand_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for demand accesses
1614system.l2c.demand_mshr_miss_rate::total 0.172964 # mshr miss rate for demand accesses
1615system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for overall accesses
1616system.l2c.overall_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for overall accesses
1617system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for overall accesses
1618system.l2c.overall_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for overall accesses
1619system.l2c.overall_mshr_miss_rate::total 0.172964 # mshr miss rate for overall accesses
1620system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average ReadReq mshr miss latency
1621system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251 # average ReadReq mshr miss latency
1622system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average ReadReq mshr miss latency
1623system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128 # average ReadReq mshr miss latency
1624system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811 # average ReadReq mshr miss latency
1625system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875 # average UpgradeReq mshr miss latency
1626system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency
1627system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency
1628system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency
1629system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency
1630system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency
1631system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.793777 # average ReadExReq mshr miss latency
1632system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency
1633system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.284554 # average ReadExReq mshr miss latency
1634system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency
1635system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency
1636system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
1637system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
1638system.l2c.demand_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
1639system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency
1640system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.327333 # average overall mshr miss latency
1641system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
1642system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
1643system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency

1623system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1624system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1625system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1626system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1627system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1628system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1629system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1630system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1631system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency

1644system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193372.151899 # average ReadReq mshr uncacheable latency
1645system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197977.528090 # average ReadReq mshr uncacheable latency
1646system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193429.087373 # average ReadReq mshr uncacheable latency
1647system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 198730.893483 # average WriteReq mshr uncacheable latency
1648system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 209613.424487 # average WriteReq mshr uncacheable latency
1649system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 201223.064332 # average WriteReq mshr uncacheable latency
1650system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 196607.584708 # average overall mshr uncacheable latency
1651system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 209300.272150 # average overall mshr uncacheable latency
1652system.l2c.overall_avg_mshr_uncacheable_latency::total 198582.772575 # average overall mshr uncacheable latency

1632system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1633system.membus.trans_dist::ReadReq 292759 # Transaction distribution
1634system.membus.trans_dist::ReadResp 292759 # Transaction distribution
1635system.membus.trans_dist::WriteReq 14052 # Transaction distribution
1636system.membus.trans_dist::WriteResp 14052 # Transaction distribution
1637system.membus.trans_dist::Writeback 120350 # Transaction distribution
1638system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
1639system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1640system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution
1641system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution
1642system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution
1643system.membus.trans_dist::ReadExReq 122543 # Transaction distribution
1644system.membus.trans_dist::ReadExResp 121713 # Transaction distribution
1645system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes)
1646system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes)
1647system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes)
1648system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes)
1649system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes)
1650system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes)
1651system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes)
1652system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes)
1653system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes)
1654system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes)
1655system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
1656system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes)
1657system.membus.snoops 21558 # Total snoops (count)

1653system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1654system.membus.trans_dist::ReadReq 292759 # Transaction distribution
1655system.membus.trans_dist::ReadResp 292759 # Transaction distribution
1656system.membus.trans_dist::WriteReq 14052 # Transaction distribution
1657system.membus.trans_dist::WriteResp 14052 # Transaction distribution
1658system.membus.trans_dist::Writeback 120350 # Transaction distribution
1659system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
1660system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1661system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution
1662system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution
1663system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution
1664system.membus.trans_dist::ReadExReq 122543 # Transaction distribution
1665system.membus.trans_dist::ReadExResp 121713 # Transaction distribution
1666system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes)
1667system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes)
1668system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes)
1669system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes)
1670system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes)
1671system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes)
1672system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes)
1673system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes)
1674system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes)
1675system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes)
1676system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
1677system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes)
1678system.membus.snoops 21558 # Total snoops (count)

1658system.membus.snoop_fanout::samples 597341 # Request fanout histogram

1679system.membus.snoop_fanout::samples 618592 # Request fanout histogram

1659system.membus.snoop_fanout::mean 1 # Request fanout histogram
1660system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1661system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1662system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1680system.membus.snoop_fanout::mean 1 # Request fanout histogram
1681system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1682system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1683system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1663system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram

1684system.membus.snoop_fanout::1 618592 100.00% 100.00% # Request fanout histogram

1664system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1665system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1666system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1667system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1685system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1686system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1687system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1688system.membus.snoop_fanout::max_value 1 # Request fanout histogram

1668system.membus.snoop_fanout::total 597341 # Request fanout histogram

1689system.membus.snoop_fanout::total 618592 # Request fanout histogram

1669system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks)
1670system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1671system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks)
1672system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1673system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks)
1674system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1675system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks)
1676system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1677system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution
1678system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution
1679system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution
1680system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution
1681system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution
1682system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution
1683system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution
1684system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution
1685system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution
1686system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution
1687system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution
1688system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes)
1689system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes)
1690system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes)
1691system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes)
1692system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes)
1693system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes)
1694system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes)
1695system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes)
1696system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes)
1697system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes)
1698system.toL2Bus.snoops 98552 # Total snoops (count)

1690system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks)
1691system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1692system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks)
1693system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1694system.membus.respLayer1.occupancy 2189522277 # Layer occupancy (ticks)
1695system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1696system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks)
1697system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1698system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution
1699system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution
1700system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution
1701system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution
1702system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution
1703system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution
1704system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution
1705system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution
1706system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution
1707system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution
1708system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution
1709system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes)
1710system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes)
1711system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes)
1712system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes)
1713system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes)
1714system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes)
1715system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes)
1716system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes)
1717system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes)
1718system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes)
1719system.toL2Bus.snoops 98552 # Total snoops (count)

1699system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram
1700system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram
1701system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram

1720system.toL2Bus.snoop_fanout::samples 3276706 # Request fanout histogram
1721system.toL2Bus.snoop_fanout::mean 3.012746 # Request fanout histogram
1722system.toL2Bus.snoop_fanout::stdev 0.112175 # Request fanout histogram

1702system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1703system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1704system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1705system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram

1723system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1724system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1725system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1726system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram

1706system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram
1707system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram

1727system.toL2Bus.snoop_fanout::3 3234942 98.73% 98.73% # Request fanout histogram
1728system.toL2Bus.snoop_fanout::4 41764 1.27% 100.00% # Request fanout histogram

1708system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1709system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1710system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram

1729system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1730system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1731system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram

1711system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram

1732system.toL2Bus.snoop_fanout::total 3276706 # Request fanout histogram