1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.961841 # Number of seconds simulated
4sim_ticks 1961841175000 # Number of ticks simulated
5final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1272238 # Simulator instruction rate (inst/s)
8host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 42053157352 # Simulator tick rate (ticks/s)
10host_mem_usage 308880 # Number of bytes of host memory used
11host_seconds 46.65 # Real time elapsed on the host
12sim_insts 59351715 # Number of instructions simulated
13sim_ops 59351715 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 24914752 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.inst 32192 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.data 287808 # Number of bytes read from this memory
19system.physmem.bytes_read::total 28716928 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu0.inst 831360 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::cpu1.inst 32192 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 7746368 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7746368 # Number of bytes written to this memory
25system.physmem.num_reads::cpu0.inst 12990 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu0.data 389293 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu1.inst 503 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.data 4497 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 448702 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 121037 # Number of write requests responded to by this memory
32system.physmem.num_writes::total 121037 # Number of write requests responded to by this memory
33system.physmem.bw_read::cpu0.inst 423765 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu0.data 12699678 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::tsunami.ide 1351188 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu1.inst 16409 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.data 146703 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::total 14637744 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::cpu0.inst 423765 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu1.inst 16409 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 440174 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 3948519 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 3948519 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 3948519 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu0.inst 423765 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu0.data 12699678 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::tsunami.ide 1351188 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller
52system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller
53system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
54system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
55system.physmem.bytesRead 28716928 # Total number of bytes read from memory
56system.physmem.bytesWritten 7746368 # Total number of bytes written to memory
57system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize()
58system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize()
59system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
60system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed
61system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::2 28314 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::3 28019 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::4 27858 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::5 28118 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::6 27836 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::7 27466 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::8 27905 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::9 27953 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::10 27826 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::11 28040 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::12 28428 # Track reads on a per bank basis
74system.physmem.perBankRdReqs::13 28581 # Track reads on a per bank basis
75system.physmem.perBankRdReqs::14 28092 # Track reads on a per bank basis
76system.physmem.perBankRdReqs::15 28236 # Track reads on a per bank basis
77system.physmem.perBankWrReqs::0 7663 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::1 7614 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::2 7774 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::3 7534 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::4 7350 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::5 7579 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::6 7314 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::7 6876 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::8 7222 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::9 7326 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::10 7279 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::11 7591 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::12 7943 # Track writes on a per bank basis
90system.physmem.perBankWrReqs::13 8207 # Track writes on a per bank basis
91system.physmem.perBankWrReqs::14 7875 # Track writes on a per bank basis
92system.physmem.perBankWrReqs::15 7890 # Track writes on a per bank basis
93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
94system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
95system.physmem.totGap 1961833946000 # Total gap between requests
96system.physmem.readPktSize::0 0 # Categorize read packet sizes
97system.physmem.readPktSize::1 0 # Categorize read packet sizes
98system.physmem.readPktSize::2 0 # Categorize read packet sizes
99system.physmem.readPktSize::3 0 # Categorize read packet sizes
100system.physmem.readPktSize::4 0 # Categorize read packet sizes
101system.physmem.readPktSize::5 0 # Categorize read packet sizes
102system.physmem.readPktSize::6 448702 # Categorize read packet sizes
103system.physmem.writePktSize::0 0 # Categorize write packet sizes
104system.physmem.writePktSize::1 0 # Categorize write packet sizes
105system.physmem.writePktSize::2 0 # Categorize write packet sizes
106system.physmem.writePktSize::3 0 # Categorize write packet sizes
107system.physmem.writePktSize::4 0 # Categorize write packet sizes
108system.physmem.writePktSize::5 0 # Categorize write packet sizes
109system.physmem.writePktSize::6 121037 # Categorize write packet sizes
110system.physmem.rdQLenPdf::0 407897 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::1 7065 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::2 5297 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::3 3282 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::4 3277 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::5 2995 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::6 1539 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::7 1507 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::8 1468 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::9 1448 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::10 1445 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::11 1437 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::12 1400 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::13 2065 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::14 2339 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::15 2218 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::16 1196 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::18 219 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
142system.physmem.wrQLenPdf::0 3809 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::1 3916 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::2 4987 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::3 5260 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::4 5261 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::5 5262 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::6 5262 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::7 5262 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::8 5262 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::9 5263 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::10 5263 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::11 5262 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::12 5262 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::13 5262 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::14 5262 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::15 5262 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::16 5262 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::17 5262 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::18 5262 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::19 5262 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::20 5262 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::22 5262 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::23 1454 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::24 1347 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::25 276 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
174system.physmem.bytesPerActivate::samples 39515 # Bytes accessed per row activation
175system.physmem.bytesPerActivate::mean 922.589599 # Bytes accessed per row activation
176system.physmem.bytesPerActivate::gmean 226.543369 # Bytes accessed per row activation
177system.physmem.bytesPerActivate::stdev 2381.494153 # Bytes accessed per row activation
178system.physmem.bytesPerActivate::64-67 13878 35.12% 35.12% # Bytes accessed per row activation
179system.physmem.bytesPerActivate::128-131 6056 15.33% 50.45% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::192-195 3741 9.47% 59.91% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::256-259 2391 6.05% 65.96% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::320-323 1744 4.41% 70.38% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::384-387 1425 3.61% 73.98% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::448-451 1039 2.63% 76.61% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::512-515 750 1.90% 78.51% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::576-579 668 1.69% 80.20% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::640-643 592 1.50% 81.70% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::704-707 528 1.34% 83.04% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::768-771 459 1.16% 84.20% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::832-835 301 0.76% 84.96% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::896-899 245 0.62% 85.58% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::960-963 187 0.47% 86.05% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::1024-1027 264 0.67% 86.72% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1088-1091 137 0.35% 87.07% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1152-1155 111 0.28% 87.35% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1216-1219 92 0.23% 87.58% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1280-1283 96 0.24% 87.82% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1344-1347 88 0.22% 88.05% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1408-1411 105 0.27% 88.31% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1472-1475 1100 2.78% 91.10% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1536-1539 187 0.47% 91.57% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1600-1603 132 0.33% 91.90% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1664-1667 88 0.22% 92.13% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1728-1731 54 0.14% 92.26% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1792-1795 43 0.11% 92.37% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::1856-1859 23 0.06% 92.43% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::1920-1923 21 0.05% 92.48% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1984-1987 20 0.05% 92.53% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::2048-2051 29 0.07% 92.61% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::2112-2115 19 0.05% 92.66% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2176-2179 11 0.03% 92.68% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2240-2243 14 0.04% 92.72% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2304-2307 4 0.01% 92.73% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::2368-2371 9 0.02% 92.75% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::2432-2435 6 0.02% 92.77% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::2496-2499 1 0.00% 92.77% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.78% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::2624-2627 5 0.01% 92.79% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::2688-2691 3 0.01% 92.80% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::2752-2755 1 0.00% 92.80% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::2816-2819 6 0.02% 92.82% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::2880-2883 5 0.01% 92.83% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::2944-2947 2 0.01% 92.83% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::3072-3075 2 0.01% 92.84% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.84% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.85% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.85% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3328-3331 4 0.01% 92.86% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3392-3395 4 0.01% 92.87% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::3456-3459 2 0.01% 92.88% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.88% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.89% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.89% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::3840-3843 1 0.00% 92.89% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::3968-3971 3 0.01% 92.90% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::4032-4035 2 0.01% 92.91% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.91% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::4160-4163 3 0.01% 92.92% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::4224-4227 2 0.01% 92.92% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.92% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4352-4355 4 0.01% 92.93% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.94% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4480-4483 2 0.01% 92.94% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.94% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4672-4675 1 0.00% 92.95% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::4736-4739 1 0.00% 92.95% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.95% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.95% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::4928-4931 1 0.00% 92.96% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.96% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::5760-5763 2 0.01% 92.96% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::6144-6147 3 0.01% 92.97% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.97% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::6784-6787 1 0.00% 92.98% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.98% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::7168-7171 2 0.01% 92.98% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.99% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.99% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::7360-7363 1 0.00% 93.00% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::7552-7555 1 0.00% 93.00% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::7616-7619 2 0.01% 93.00% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::7680-7683 2 0.01% 93.01% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::7744-7747 1 0.00% 93.01% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::7808-7811 1 0.00% 93.01% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::7936-7939 2 0.01% 93.02% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::8000-8003 3 0.01% 93.03% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::8128-8131 6 0.02% 93.04% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::8192-8195 2432 6.15% 99.20% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::8256-8259 1 0.00% 99.20% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::8384-8387 2 0.01% 99.20% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::12352-12355 1 0.00% 99.21% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.21% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::13056-13059 1 0.00% 99.21% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::13696-13699 1 0.00% 99.21% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.22% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.22% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::14272-14275 3 0.01% 99.23% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::14400-14403 1 0.00% 99.23% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::14528-14531 2 0.01% 99.23% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.24% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.24% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::15104-15107 2 0.01% 99.24% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::15296-15299 2 0.01% 99.25% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::15360-15363 16 0.04% 99.29% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::15488-15491 2 0.01% 99.29% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.30% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::16384-16387 242 0.61% 99.91% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::16448-16451 10 0.03% 99.93% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::16512-16515 6 0.02% 99.95% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::16576-16579 1 0.00% 99.95% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::16640-16643 6 0.02% 99.97% # Bytes accessed per row activation
292system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.98% # Bytes accessed per row activation
293system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation
294system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation
295system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.99% # Bytes accessed per row activation
296system.physmem.bytesPerActivate::17024-17027 4 0.01% 100.00% # Bytes accessed per row activation
297system.physmem.bytesPerActivate::17984-17987 1 0.00% 100.00% # Bytes accessed per row activation
298system.physmem.bytesPerActivate::total 39515 # Bytes accessed per row activation
299system.physmem.totQLat 3750140000 # Total cycles spent in queuing delays
300system.physmem.totMemAccLat 12006448750 # Sum of mem lat for all requests
301system.physmem.totBusLat 2243145000 # Total cycles spent in databus access
302system.physmem.totBankLat 6013163750 # Total cycles spent in bank access
303system.physmem.avgQLat 8359.11 # Average queueing delay per request
304system.physmem.avgBankLat 13403.42 # Average bank access latency per request
305system.physmem.avgBusLat 5000.00 # Average bus latency per request
306system.physmem.avgMemAccLat 26762.53 # Average memory access latency
307system.physmem.avgRdBW 14.64 # Average achieved read bandwidth in MB/s
308system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s
309system.physmem.avgConsumedRdBW 14.64 # Average consumed read bandwidth in MB/s
310system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s
311system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
312system.physmem.busUtil 0.15 # Data bus utilization in percentage
313system.physmem.avgRdQLen 0.01 # Average read queue length over time
314system.physmem.avgWrQLen 6.90 # Average write queue length over time
315system.physmem.readRowHits 433153 # Number of row buffer hits during reads
316system.physmem.writeRowHits 96987 # Number of row buffer hits during writes
317system.physmem.readRowHitRate 96.55 # Row buffer hit rate for reads
318system.physmem.writeRowHitRate 80.13 # Row buffer hit rate for writes
319system.physmem.avgGap 3443390.65 # Average gap between requests
320system.membus.throughput 18639952 # Throughput (bytes/s)
321system.membus.trans_dist::ReadReq 292620 # Transaction distribution
322system.membus.trans_dist::ReadResp 292620 # Transaction distribution
323system.membus.trans_dist::WriteReq 12397 # Transaction distribution
324system.membus.trans_dist::WriteResp 12397 # Transaction distribution
325system.membus.trans_dist::Writeback 121037 # Transaction distribution
326system.membus.trans_dist::UpgradeReq 4186 # Transaction distribution
327system.membus.trans_dist::SCUpgradeReq 858 # Transaction distribution
328system.membus.trans_dist::UpgradeResp 3168 # Transaction distribution
329system.membus.trans_dist::ReadExReq 163944 # Transaction distribution
330system.membus.trans_dist::ReadExResp 163855 # Transaction distribution
331system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39192 # Packet count per connected master and slave (bytes)
332system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 # Packet count per connected master and slave (bytes)
333system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes)
334system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes)
335system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes)
336system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes)
337system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes)
338system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes)
339system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes)
340system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes)
341system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes)
342system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes)
343system.membus.data_through_bus 36531890 # Total data (bytes)
344system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes)
345system.membus.reqLayer0.occupancy 39129000 # Layer occupancy (ticks)
346system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
347system.membus.reqLayer1.occupancy 1559666750 # Layer occupancy (ticks)
348system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
349system.membus.respLayer1.occupancy 3812357322 # Layer occupancy (ticks)
350system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
351system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks)
352system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
353system.l2c.tags.replacements 341780 # number of replacements
354system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use
355system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks.
356system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks.
357system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks.
358system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit.
359system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor
360system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor
361system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor
362system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor
363system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor
364system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy
365system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy
366system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy
367system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy
368system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy
369system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy
370system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits
371system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits
372system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits
373system.l2c.ReadReq_hits::cpu1.data 28709 # number of ReadReq hits
374system.l2c.ReadReq_hits::total 1793292 # number of ReadReq hits
375system.l2c.Writeback_hits::writebacks 820882 # number of Writeback hits
376system.l2c.Writeback_hits::total 820882 # number of Writeback hits
377system.l2c.UpgradeReq_hits::cpu0.data 160 # number of UpgradeReq hits
378system.l2c.UpgradeReq_hits::cpu1.data 41 # number of UpgradeReq hits
379system.l2c.UpgradeReq_hits::total 201 # number of UpgradeReq hits
380system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits
381system.l2c.SCUpgradeReq_hits::cpu1.data 18 # number of SCUpgradeReq hits
382system.l2c.SCUpgradeReq_hits::total 36 # number of SCUpgradeReq hits
383system.l2c.ReadExReq_hits::cpu0.data 176285 # number of ReadExReq hits
384system.l2c.ReadExReq_hits::cpu1.data 7535 # number of ReadExReq hits
385system.l2c.ReadExReq_hits::total 183820 # number of ReadExReq hits
386system.l2c.demand_hits::cpu0.inst 908184 # number of demand (read+write) hits
387system.l2c.demand_hits::cpu0.data 953017 # number of demand (read+write) hits
388system.l2c.demand_hits::cpu1.inst 79667 # number of demand (read+write) hits
389system.l2c.demand_hits::cpu1.data 36244 # number of demand (read+write) hits
390system.l2c.demand_hits::total 1977112 # number of demand (read+write) hits
391system.l2c.overall_hits::cpu0.inst 908184 # number of overall hits
392system.l2c.overall_hits::cpu0.data 953017 # number of overall hits
393system.l2c.overall_hits::cpu1.inst 79667 # number of overall hits
394system.l2c.overall_hits::cpu1.data 36244 # number of overall hits
395system.l2c.overall_hits::total 1977112 # number of overall hits
396system.l2c.ReadReq_misses::cpu0.inst 12993 # number of ReadReq misses
397system.l2c.ReadReq_misses::cpu0.data 271572 # number of ReadReq misses
398system.l2c.ReadReq_misses::cpu1.inst 511 # number of ReadReq misses
399system.l2c.ReadReq_misses::cpu1.data 178 # number of ReadReq misses
400system.l2c.ReadReq_misses::total 285254 # number of ReadReq misses
401system.l2c.UpgradeReq_misses::cpu0.data 2440 # number of UpgradeReq misses
402system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses
403system.l2c.UpgradeReq_misses::total 2923 # number of UpgradeReq misses
404system.l2c.SCUpgradeReq_misses::cpu0.data 33 # number of SCUpgradeReq misses
405system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses
406system.l2c.SCUpgradeReq_misses::total 106 # number of SCUpgradeReq misses
407system.l2c.ReadExReq_misses::cpu0.data 118111 # number of ReadExReq misses
408system.l2c.ReadExReq_misses::cpu1.data 4331 # number of ReadExReq misses
409system.l2c.ReadExReq_misses::total 122442 # number of ReadExReq misses
410system.l2c.demand_misses::cpu0.inst 12993 # number of demand (read+write) misses
411system.l2c.demand_misses::cpu0.data 389683 # number of demand (read+write) misses
412system.l2c.demand_misses::cpu1.inst 511 # number of demand (read+write) misses
413system.l2c.demand_misses::cpu1.data 4509 # number of demand (read+write) misses
414system.l2c.demand_misses::total 407696 # number of demand (read+write) misses
415system.l2c.overall_misses::cpu0.inst 12993 # number of overall misses
416system.l2c.overall_misses::cpu0.data 389683 # number of overall misses
417system.l2c.overall_misses::cpu1.inst 511 # number of overall misses
418system.l2c.overall_misses::cpu1.data 4509 # number of overall misses
419system.l2c.overall_misses::total 407696 # number of overall misses
420system.l2c.ReadReq_miss_latency::cpu0.inst 1030661993 # number of ReadReq miss cycles
421system.l2c.ReadReq_miss_latency::cpu0.data 16900238244 # number of ReadReq miss cycles
422system.l2c.ReadReq_miss_latency::cpu1.inst 41124000 # number of ReadReq miss cycles
423system.l2c.ReadReq_miss_latency::cpu1.data 15490750 # number of ReadReq miss cycles
424system.l2c.ReadReq_miss_latency::total 17987514987 # number of ReadReq miss cycles
425system.l2c.UpgradeReq_miss_latency::cpu0.data 1078963 # number of UpgradeReq miss cycles
426system.l2c.UpgradeReq_miss_latency::cpu1.data 302487 # number of UpgradeReq miss cycles
427system.l2c.UpgradeReq_miss_latency::total 1381450 # number of UpgradeReq miss cycles
428system.l2c.SCUpgradeReq_miss_latency::cpu0.data 69997 # number of SCUpgradeReq miss cycles
429system.l2c.SCUpgradeReq_miss_latency::cpu1.data 92496 # number of SCUpgradeReq miss cycles
430system.l2c.SCUpgradeReq_miss_latency::total 162493 # number of SCUpgradeReq miss cycles
431system.l2c.ReadExReq_miss_latency::cpu0.data 7866556623 # number of ReadExReq miss cycles
432system.l2c.ReadExReq_miss_latency::cpu1.data 326108488 # number of ReadExReq miss cycles
433system.l2c.ReadExReq_miss_latency::total 8192665111 # number of ReadExReq miss cycles
434system.l2c.demand_miss_latency::cpu0.inst 1030661993 # number of demand (read+write) miss cycles
435system.l2c.demand_miss_latency::cpu0.data 24766794867 # number of demand (read+write) miss cycles
436system.l2c.demand_miss_latency::cpu1.inst 41124000 # number of demand (read+write) miss cycles
437system.l2c.demand_miss_latency::cpu1.data 341599238 # number of demand (read+write) miss cycles
438system.l2c.demand_miss_latency::total 26180180098 # number of demand (read+write) miss cycles
439system.l2c.overall_miss_latency::cpu0.inst 1030661993 # number of overall miss cycles
440system.l2c.overall_miss_latency::cpu0.data 24766794867 # number of overall miss cycles
441system.l2c.overall_miss_latency::cpu1.inst 41124000 # number of overall miss cycles
442system.l2c.overall_miss_latency::cpu1.data 341599238 # number of overall miss cycles
443system.l2c.overall_miss_latency::total 26180180098 # number of overall miss cycles
444system.l2c.ReadReq_accesses::cpu0.inst 921177 # number of ReadReq accesses(hits+misses)
445system.l2c.ReadReq_accesses::cpu0.data 1048304 # number of ReadReq accesses(hits+misses)
446system.l2c.ReadReq_accesses::cpu1.inst 80178 # number of ReadReq accesses(hits+misses)
447system.l2c.ReadReq_accesses::cpu1.data 28887 # number of ReadReq accesses(hits+misses)
448system.l2c.ReadReq_accesses::total 2078546 # number of ReadReq accesses(hits+misses)
449system.l2c.Writeback_accesses::writebacks 820882 # number of Writeback accesses(hits+misses)
450system.l2c.Writeback_accesses::total 820882 # number of Writeback accesses(hits+misses)
451system.l2c.UpgradeReq_accesses::cpu0.data 2600 # number of UpgradeReq accesses(hits+misses)
452system.l2c.UpgradeReq_accesses::cpu1.data 524 # number of UpgradeReq accesses(hits+misses)
453system.l2c.UpgradeReq_accesses::total 3124 # number of UpgradeReq accesses(hits+misses)
454system.l2c.SCUpgradeReq_accesses::cpu0.data 51 # number of SCUpgradeReq accesses(hits+misses)
455system.l2c.SCUpgradeReq_accesses::cpu1.data 91 # number of SCUpgradeReq accesses(hits+misses)
456system.l2c.SCUpgradeReq_accesses::total 142 # number of SCUpgradeReq accesses(hits+misses)
457system.l2c.ReadExReq_accesses::cpu0.data 294396 # number of ReadExReq accesses(hits+misses)
458system.l2c.ReadExReq_accesses::cpu1.data 11866 # number of ReadExReq accesses(hits+misses)
459system.l2c.ReadExReq_accesses::total 306262 # number of ReadExReq accesses(hits+misses)
460system.l2c.demand_accesses::cpu0.inst 921177 # number of demand (read+write) accesses
461system.l2c.demand_accesses::cpu0.data 1342700 # number of demand (read+write) accesses
462system.l2c.demand_accesses::cpu1.inst 80178 # number of demand (read+write) accesses
463system.l2c.demand_accesses::cpu1.data 40753 # number of demand (read+write) accesses
464system.l2c.demand_accesses::total 2384808 # number of demand (read+write) accesses
465system.l2c.overall_accesses::cpu0.inst 921177 # number of overall (read+write) accesses
466system.l2c.overall_accesses::cpu0.data 1342700 # number of overall (read+write) accesses
467system.l2c.overall_accesses::cpu1.inst 80178 # number of overall (read+write) accesses
468system.l2c.overall_accesses::cpu1.data 40753 # number of overall (read+write) accesses
469system.l2c.overall_accesses::total 2384808 # number of overall (read+write) accesses
470system.l2c.ReadReq_miss_rate::cpu0.inst 0.014105 # miss rate for ReadReq accesses
471system.l2c.ReadReq_miss_rate::cpu0.data 0.259058 # miss rate for ReadReq accesses
472system.l2c.ReadReq_miss_rate::cpu1.inst 0.006373 # miss rate for ReadReq accesses
473system.l2c.ReadReq_miss_rate::cpu1.data 0.006162 # miss rate for ReadReq accesses
474system.l2c.ReadReq_miss_rate::total 0.137237 # miss rate for ReadReq accesses
475system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938462 # miss rate for UpgradeReq accesses
476system.l2c.UpgradeReq_miss_rate::cpu1.data 0.921756 # miss rate for UpgradeReq accesses
477system.l2c.UpgradeReq_miss_rate::total 0.935659 # miss rate for UpgradeReq accesses
478system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.647059 # miss rate for SCUpgradeReq accesses
479system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.802198 # miss rate for SCUpgradeReq accesses
480system.l2c.SCUpgradeReq_miss_rate::total 0.746479 # miss rate for SCUpgradeReq accesses
481system.l2c.ReadExReq_miss_rate::cpu0.data 0.401198 # miss rate for ReadExReq accesses
482system.l2c.ReadExReq_miss_rate::cpu1.data 0.364992 # miss rate for ReadExReq accesses
483system.l2c.ReadExReq_miss_rate::total 0.399795 # miss rate for ReadExReq accesses
484system.l2c.demand_miss_rate::cpu0.inst 0.014105 # miss rate for demand accesses
485system.l2c.demand_miss_rate::cpu0.data 0.290223 # miss rate for demand accesses
486system.l2c.demand_miss_rate::cpu1.inst 0.006373 # miss rate for demand accesses
487system.l2c.demand_miss_rate::cpu1.data 0.110642 # miss rate for demand accesses
488system.l2c.demand_miss_rate::total 0.170955 # miss rate for demand accesses
489system.l2c.overall_miss_rate::cpu0.inst 0.014105 # miss rate for overall accesses
490system.l2c.overall_miss_rate::cpu0.data 0.290223 # miss rate for overall accesses
491system.l2c.overall_miss_rate::cpu1.inst 0.006373 # miss rate for overall accesses
492system.l2c.overall_miss_rate::cpu1.data 0.110642 # miss rate for overall accesses
493system.l2c.overall_miss_rate::total 0.170955 # miss rate for overall accesses
494system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79324.404910 # average ReadReq miss latency
495system.l2c.ReadReq_avg_miss_latency::cpu0.data 62231.151385 # average ReadReq miss latency
496system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80477.495108 # average ReadReq miss latency
497system.l2c.ReadReq_avg_miss_latency::cpu1.data 87026.685393 # average ReadReq miss latency
498system.l2c.ReadReq_avg_miss_latency::total 63057.888713 # average ReadReq miss latency
499system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 442.197951 # average UpgradeReq miss latency
500system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 626.267081 # average UpgradeReq miss latency
501system.l2c.UpgradeReq_avg_miss_latency::total 472.613753 # average UpgradeReq miss latency
502system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2121.121212 # average SCUpgradeReq miss latency
503system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1267.068493 # average SCUpgradeReq miss latency
504system.l2c.SCUpgradeReq_avg_miss_latency::total 1532.952830 # average SCUpgradeReq miss latency
505system.l2c.ReadExReq_avg_miss_latency::cpu0.data 66603.082041 # average ReadExReq miss latency
506system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75296.349111 # average ReadExReq miss latency
507system.l2c.ReadExReq_avg_miss_latency::total 66910.578976 # average ReadExReq miss latency
508system.l2c.demand_avg_miss_latency::cpu0.inst 79324.404910 # average overall miss latency
509system.l2c.demand_avg_miss_latency::cpu0.data 63556.262057 # average overall miss latency
510system.l2c.demand_avg_miss_latency::cpu1.inst 80477.495108 # average overall miss latency
511system.l2c.demand_avg_miss_latency::cpu1.data 75759.422932 # average overall miss latency
512system.l2c.demand_avg_miss_latency::total 64214.954520 # average overall miss latency
513system.l2c.overall_avg_miss_latency::cpu0.inst 79324.404910 # average overall miss latency
514system.l2c.overall_avg_miss_latency::cpu0.data 63556.262057 # average overall miss latency
515system.l2c.overall_avg_miss_latency::cpu1.inst 80477.495108 # average overall miss latency
516system.l2c.overall_avg_miss_latency::cpu1.data 75759.422932 # average overall miss latency
517system.l2c.overall_avg_miss_latency::total 64214.954520 # average overall miss latency
518system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
519system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
520system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
521system.l2c.blocked::no_targets 0 # number of cycles access was blocked
522system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
523system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
524system.l2c.fast_writes 0 # number of fast writes performed
525system.l2c.cache_copies 0 # number of cache copies performed
526system.l2c.writebacks::writebacks 79517 # number of writebacks
527system.l2c.writebacks::total 79517 # number of writebacks
528system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits
529system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
530system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
531system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
532system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
533system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
534system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
535system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
536system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
537system.l2c.ReadReq_mshr_misses::cpu0.inst 12990 # number of ReadReq MSHR misses
538system.l2c.ReadReq_mshr_misses::cpu0.data 271572 # number of ReadReq MSHR misses
539system.l2c.ReadReq_mshr_misses::cpu1.inst 503 # number of ReadReq MSHR misses
540system.l2c.ReadReq_mshr_misses::cpu1.data 178 # number of ReadReq MSHR misses
541system.l2c.ReadReq_mshr_misses::total 285243 # number of ReadReq MSHR misses
542system.l2c.UpgradeReq_mshr_misses::cpu0.data 2440 # number of UpgradeReq MSHR misses
543system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses
544system.l2c.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses
545system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 33 # number of SCUpgradeReq MSHR misses
546system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 73 # number of SCUpgradeReq MSHR misses
547system.l2c.SCUpgradeReq_mshr_misses::total 106 # number of SCUpgradeReq MSHR misses
548system.l2c.ReadExReq_mshr_misses::cpu0.data 118111 # number of ReadExReq MSHR misses
549system.l2c.ReadExReq_mshr_misses::cpu1.data 4331 # number of ReadExReq MSHR misses
550system.l2c.ReadExReq_mshr_misses::total 122442 # number of ReadExReq MSHR misses
551system.l2c.demand_mshr_misses::cpu0.inst 12990 # number of demand (read+write) MSHR misses
552system.l2c.demand_mshr_misses::cpu0.data 389683 # number of demand (read+write) MSHR misses
553system.l2c.demand_mshr_misses::cpu1.inst 503 # number of demand (read+write) MSHR misses
554system.l2c.demand_mshr_misses::cpu1.data 4509 # number of demand (read+write) MSHR misses
555system.l2c.demand_mshr_misses::total 407685 # number of demand (read+write) MSHR misses
556system.l2c.overall_mshr_misses::cpu0.inst 12990 # number of overall MSHR misses
557system.l2c.overall_mshr_misses::cpu0.data 389683 # number of overall MSHR misses
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559system.l2c.overall_mshr_misses::cpu1.data 4509 # number of overall MSHR misses
560system.l2c.overall_mshr_misses::total 407685 # number of overall MSHR misses
561system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 866381257 # number of ReadReq MSHR miss cycles
562system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13503893756 # number of ReadReq MSHR miss cycles
563system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 34165000 # number of ReadReq MSHR miss cycles
564system.l2c.ReadReq_mshr_miss_latency::cpu1.data 13232750 # number of ReadReq MSHR miss cycles
565system.l2c.ReadReq_mshr_miss_latency::total 14417672763 # number of ReadReq MSHR miss cycles
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567system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4864483 # number of UpgradeReq MSHR miss cycles
568system.l2c.UpgradeReq_mshr_miss_latency::total 29421420 # number of UpgradeReq MSHR miss cycles
569system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 330033 # number of SCUpgradeReq MSHR miss cycles
570system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 730073 # number of SCUpgradeReq MSHR miss cycles
571system.l2c.SCUpgradeReq_mshr_miss_latency::total 1060106 # number of SCUpgradeReq MSHR miss cycles
572system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6385916377 # number of ReadExReq MSHR miss cycles
573system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 270944012 # number of ReadExReq MSHR miss cycles
574system.l2c.ReadExReq_mshr_miss_latency::total 6656860389 # number of ReadExReq MSHR miss cycles
575system.l2c.demand_mshr_miss_latency::cpu0.inst 866381257 # number of demand (read+write) MSHR miss cycles
576system.l2c.demand_mshr_miss_latency::cpu0.data 19889810133 # number of demand (read+write) MSHR miss cycles
577system.l2c.demand_mshr_miss_latency::cpu1.inst 34165000 # number of demand (read+write) MSHR miss cycles
578system.l2c.demand_mshr_miss_latency::cpu1.data 284176762 # number of demand (read+write) MSHR miss cycles
579system.l2c.demand_mshr_miss_latency::total 21074533152 # number of demand (read+write) MSHR miss cycles
580system.l2c.overall_mshr_miss_latency::cpu0.inst 866381257 # number of overall MSHR miss cycles
581system.l2c.overall_mshr_miss_latency::cpu0.data 19889810133 # number of overall MSHR miss cycles
582system.l2c.overall_mshr_miss_latency::cpu1.inst 34165000 # number of overall MSHR miss cycles
583system.l2c.overall_mshr_miss_latency::cpu1.data 284176762 # number of overall MSHR miss cycles
584system.l2c.overall_mshr_miss_latency::total 21074533152 # number of overall MSHR miss cycles
585system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373141500 # number of ReadReq MSHR uncacheable cycles
586system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17611000 # number of ReadReq MSHR uncacheable cycles
587system.l2c.ReadReq_mshr_uncacheable_latency::total 1390752500 # number of ReadReq MSHR uncacheable cycles
588system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1974248000 # number of WriteReq MSHR uncacheable cycles
589system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 499178500 # number of WriteReq MSHR uncacheable cycles
590system.l2c.WriteReq_mshr_uncacheable_latency::total 2473426500 # number of WriteReq MSHR uncacheable cycles
591system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3347389500 # number of overall MSHR uncacheable cycles
592system.l2c.overall_mshr_uncacheable_latency::cpu1.data 516789500 # number of overall MSHR uncacheable cycles
593system.l2c.overall_mshr_uncacheable_latency::total 3864179000 # number of overall MSHR uncacheable cycles
594system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for ReadReq accesses
595system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.259058 # mshr miss rate for ReadReq accesses
596system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for ReadReq accesses
597system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.006162 # mshr miss rate for ReadReq accesses
598system.l2c.ReadReq_mshr_miss_rate::total 0.137232 # mshr miss rate for ReadReq accesses
599system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938462 # mshr miss rate for UpgradeReq accesses
600system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.921756 # mshr miss rate for UpgradeReq accesses
601system.l2c.UpgradeReq_mshr_miss_rate::total 0.935659 # mshr miss rate for UpgradeReq accesses
602system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.647059 # mshr miss rate for SCUpgradeReq accesses
603system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.802198 # mshr miss rate for SCUpgradeReq accesses
604system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746479 # mshr miss rate for SCUpgradeReq accesses
605system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.401198 # mshr miss rate for ReadExReq accesses
606system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.364992 # mshr miss rate for ReadExReq accesses
607system.l2c.ReadExReq_mshr_miss_rate::total 0.399795 # mshr miss rate for ReadExReq accesses
608system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for demand accesses
609system.l2c.demand_mshr_miss_rate::cpu0.data 0.290223 # mshr miss rate for demand accesses
610system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for demand accesses
611system.l2c.demand_mshr_miss_rate::cpu1.data 0.110642 # mshr miss rate for demand accesses
612system.l2c.demand_mshr_miss_rate::total 0.170951 # mshr miss rate for demand accesses
613system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014102 # mshr miss rate for overall accesses
614system.l2c.overall_mshr_miss_rate::cpu0.data 0.290223 # mshr miss rate for overall accesses
615system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006274 # mshr miss rate for overall accesses
616system.l2c.overall_mshr_miss_rate::cpu1.data 0.110642 # mshr miss rate for overall accesses
617system.l2c.overall_mshr_miss_rate::total 0.170951 # mshr miss rate for overall accesses
618system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average ReadReq mshr miss latency
619system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49724.911832 # average ReadReq mshr miss latency
620system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average ReadReq mshr miss latency
621system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74341.292135 # average ReadReq mshr miss latency
622system.l2c.ReadReq_avg_mshr_miss_latency::total 50545.229026 # average ReadReq mshr miss latency
623system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.318443 # average UpgradeReq mshr miss latency
624system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10071.393375 # average UpgradeReq mshr miss latency
625system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10065.487513 # average UpgradeReq mshr miss latency
626system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
627system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
628system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
629system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54067.075692 # average ReadExReq mshr miss latency
630system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62559.226968 # average ReadExReq mshr miss latency
631system.l2c.ReadExReq_avg_mshr_miss_latency::total 54367.458789 # average ReadExReq mshr miss latency
632system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency
633system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency
634system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency
635system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency
636system.l2c.demand_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency
637system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66696.016705 # average overall mshr miss latency
638system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51041.000334 # average overall mshr miss latency
639system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67922.465209 # average overall mshr miss latency
640system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63024.342870 # average overall mshr miss latency
641system.l2c.overall_avg_mshr_miss_latency::total 51693.177703 # average overall mshr miss latency
642system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
643system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
644system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
645system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
646system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
647system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
648system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
649system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
650system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
651system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
652system.iocache.tags.replacements 41698 # number of replacements
653system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use
654system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
655system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks.
656system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
657system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit.
658system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor
659system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy
660system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy
661system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses
662system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
663system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
664system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
665system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses
666system.iocache.demand_misses::total 41730 # number of demand (read+write) misses
667system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses
668system.iocache.overall_misses::total 41730 # number of overall misses
669system.iocache.ReadReq_miss_latency::tsunami.ide 21912883 # number of ReadReq miss cycles
670system.iocache.ReadReq_miss_latency::total 21912883 # number of ReadReq miss cycles
671system.iocache.WriteReq_miss_latency::tsunami.ide 10439154521 # number of WriteReq miss cycles
672system.iocache.WriteReq_miss_latency::total 10439154521 # number of WriteReq miss cycles
673system.iocache.demand_miss_latency::tsunami.ide 10461067404 # number of demand (read+write) miss cycles
674system.iocache.demand_miss_latency::total 10461067404 # number of demand (read+write) miss cycles
675system.iocache.overall_miss_latency::tsunami.ide 10461067404 # number of overall miss cycles
676system.iocache.overall_miss_latency::total 10461067404 # number of overall miss cycles
677system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses)
678system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
679system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
680system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
681system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses
682system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses
683system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses
684system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses
685system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
686system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
687system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
688system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
689system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
690system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
691system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
692system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
693system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123106.084270 # average ReadReq miss latency
694system.iocache.ReadReq_avg_miss_latency::total 123106.084270 # average ReadReq miss latency
695system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251231.096482 # average WriteReq miss latency
696system.iocache.WriteReq_avg_miss_latency::total 251231.096482 # average WriteReq miss latency
697system.iocache.demand_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency
698system.iocache.demand_avg_miss_latency::total 250684.577139 # average overall miss latency
699system.iocache.overall_avg_miss_latency::tsunami.ide 250684.577139 # average overall miss latency
700system.iocache.overall_avg_miss_latency::total 250684.577139 # average overall miss latency
701system.iocache.blocked_cycles::no_mshrs 274830 # number of cycles access was blocked
702system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
703system.iocache.blocked::no_mshrs 27442 # number of cycles access was blocked
704system.iocache.blocked::no_targets 0 # number of cycles access was blocked
705system.iocache.avg_blocked_cycles::no_mshrs 10.014941 # average number of cycles each access was blocked
706system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
707system.iocache.fast_writes 0 # number of fast writes performed
708system.iocache.cache_copies 0 # number of cache copies performed
709system.iocache.writebacks::writebacks 41520 # number of writebacks
710system.iocache.writebacks::total 41520 # number of writebacks
711system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses
712system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses
713system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
714system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
715system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses
716system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses
717system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses
718system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses
719system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12655383 # number of ReadReq MSHR miss cycles
720system.iocache.ReadReq_mshr_miss_latency::total 12655383 # number of ReadReq MSHR miss cycles
721system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8277077521 # number of WriteReq MSHR miss cycles
722system.iocache.WriteReq_mshr_miss_latency::total 8277077521 # number of WriteReq MSHR miss cycles
723system.iocache.demand_mshr_miss_latency::tsunami.ide 8289732904 # number of demand (read+write) MSHR miss cycles
724system.iocache.demand_mshr_miss_latency::total 8289732904 # number of demand (read+write) MSHR miss cycles
725system.iocache.overall_mshr_miss_latency::tsunami.ide 8289732904 # number of overall MSHR miss cycles
726system.iocache.overall_mshr_miss_latency::total 8289732904 # number of overall MSHR miss cycles
727system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
728system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
729system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
730system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
731system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
732system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
733system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
734system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
735system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71097.657303 # average ReadReq mshr miss latency
736system.iocache.ReadReq_avg_mshr_miss_latency::total 71097.657303 # average ReadReq mshr miss latency
737system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199198.053547 # average WriteReq mshr miss latency
738system.iocache.WriteReq_avg_mshr_miss_latency::total 199198.053547 # average WriteReq mshr miss latency
739system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency
740system.iocache.demand_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency
741system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198651.639204 # average overall mshr miss latency
742system.iocache.overall_avg_mshr_miss_latency::total 198651.639204 # average overall mshr miss latency
743system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
744system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
745system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
746system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
747system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
748system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
749system.disk0.dma_write_txs 395 # Number of DMA write transactions.
750system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
751system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
752system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
753system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
754system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
755system.disk2.dma_write_txs 1 # Number of DMA write transactions.
756system.cpu0.dtb.fetch_hits 0 # ITB hits
757system.cpu0.dtb.fetch_misses 0 # ITB misses
758system.cpu0.dtb.fetch_acv 0 # ITB acv
759system.cpu0.dtb.fetch_accesses 0 # ITB accesses
760system.cpu0.dtb.read_hits 8725663 # DTB read hits
761system.cpu0.dtb.read_misses 7765 # DTB read misses
762system.cpu0.dtb.read_acv 210 # DTB read access violations
763system.cpu0.dtb.read_accesses 524069 # DTB read accesses
764system.cpu0.dtb.write_hits 6139453 # DTB write hits
765system.cpu0.dtb.write_misses 910 # DTB write misses
766system.cpu0.dtb.write_acv 133 # DTB write access violations
767system.cpu0.dtb.write_accesses 202595 # DTB write accesses
768system.cpu0.dtb.data_hits 14865116 # DTB hits
769system.cpu0.dtb.data_misses 8675 # DTB misses
770system.cpu0.dtb.data_acv 343 # DTB access violations
771system.cpu0.dtb.data_accesses 726664 # DTB accesses
772system.cpu0.itb.fetch_hits 4015307 # ITB hits
773system.cpu0.itb.fetch_misses 3984 # ITB misses
774system.cpu0.itb.fetch_acv 184 # ITB acv
775system.cpu0.itb.fetch_accesses 4019291 # ITB accesses
776system.cpu0.itb.read_hits 0 # DTB read hits
777system.cpu0.itb.read_misses 0 # DTB read misses
778system.cpu0.itb.read_acv 0 # DTB read access violations
779system.cpu0.itb.read_accesses 0 # DTB read accesses
780system.cpu0.itb.write_hits 0 # DTB write hits
781system.cpu0.itb.write_misses 0 # DTB write misses
782system.cpu0.itb.write_acv 0 # DTB write access violations
783system.cpu0.itb.write_accesses 0 # DTB write accesses
784system.cpu0.itb.data_hits 0 # DTB hits
785system.cpu0.itb.data_misses 0 # DTB misses
786system.cpu0.itb.data_acv 0 # DTB access violations
787system.cpu0.itb.data_accesses 0 # DTB accesses
788system.cpu0.numCycles 3923682350 # number of cpu cycles simulated
789system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
790system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
791system.cpu0.committedInsts 54601969 # Number of instructions committed
792system.cpu0.committedOps 54601969 # Number of ops (including micro ops) committed
793system.cpu0.num_int_alu_accesses 50544405 # Number of integer alu accesses
794system.cpu0.num_fp_alu_accesses 297630 # Number of float alu accesses
795system.cpu0.num_func_calls 1438477 # number of times a function call or return occured
796system.cpu0.num_conditional_control_insts 6291508 # number of instructions that are conditional controls
797system.cpu0.num_int_insts 50544405 # number of integer instructions
798system.cpu0.num_fp_insts 297630 # number of float instructions
799system.cpu0.num_int_register_reads 69247284 # number of times the integer registers were read
800system.cpu0.num_int_register_writes 37427910 # number of times the integer registers were written
801system.cpu0.num_fp_register_reads 145753 # number of times the floating registers were read
802system.cpu0.num_fp_register_writes 148838 # number of times the floating registers were written
803system.cpu0.num_mem_refs 14912078 # number of memory refs
804system.cpu0.num_load_insts 8757685 # Number of load instructions
805system.cpu0.num_store_insts 6154393 # Number of store instructions
806system.cpu0.num_idle_cycles 3674902109.498127 # Number of idle cycles
807system.cpu0.num_busy_cycles 248780240.501873 # Number of busy cycles
808system.cpu0.not_idle_fraction 0.063405 # Percentage of non-idle cycles
809system.cpu0.idle_fraction 0.936595 # Percentage of idle cycles
810system.cpu0.kern.inst.arm 0 # number of arm instructions executed
811system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed
812system.cpu0.kern.inst.hwrei 204697 # number of hwrei instructions executed
813system.cpu0.kern.ipl_count::0 73289 40.68% 40.68% # number of times we switched to this ipl
814system.cpu0.kern.ipl_count::21 131 0.07% 40.75% # number of times we switched to this ipl
815system.cpu0.kern.ipl_count::22 1975 1.10% 41.85% # number of times we switched to this ipl
816system.cpu0.kern.ipl_count::30 6 0.00% 41.85% # number of times we switched to this ipl
817system.cpu0.kern.ipl_count::31 104766 58.15% 100.00% # number of times we switched to this ipl
818system.cpu0.kern.ipl_count::total 180167 # number of times we switched to this ipl
819system.cpu0.kern.ipl_good::0 71920 49.28% 49.28% # number of times we switched to this ipl from a different ipl
820system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl
821system.cpu0.kern.ipl_good::22 1975 1.35% 50.72% # number of times we switched to this ipl from a different ipl
822system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
823system.cpu0.kern.ipl_good::31 71914 49.27% 100.00% # number of times we switched to this ipl from a different ipl
824system.cpu0.kern.ipl_good::total 145946 # number of times we switched to this ipl from a different ipl
825system.cpu0.kern.ipl_ticks::0 1899196330000 96.81% 96.81% # number of cycles we spent at this ipl
826system.cpu0.kern.ipl_ticks::21 95025500 0.00% 96.81% # number of cycles we spent at this ipl
827system.cpu0.kern.ipl_ticks::22 769055500 0.04% 96.85% # number of cycles we spent at this ipl
828system.cpu0.kern.ipl_ticks::30 5164500 0.00% 96.85% # number of cycles we spent at this ipl
829system.cpu0.kern.ipl_ticks::31 61774827500 3.15% 100.00% # number of cycles we spent at this ipl
830system.cpu0.kern.ipl_ticks::total 1961840403000 # number of cycles we spent at this ipl
831system.cpu0.kern.ipl_used::0 0.981321 # fraction of swpipl calls that actually changed the ipl
832system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
833system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
834system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
835system.cpu0.kern.ipl_used::31 0.686425 # fraction of swpipl calls that actually changed the ipl
836system.cpu0.kern.ipl_used::total 0.810060 # fraction of swpipl calls that actually changed the ipl
837system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
838system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
839system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
840system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
841system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
842system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
843system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
844system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed

--- 15 unchanged lines hidden (view full) ---

860system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
861system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
862system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
863system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
864system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
865system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
866system.cpu0.kern.syscall::total 234 # number of syscalls executed
867system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
868system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed
869system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
870system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
871system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
872system.cpu0.kern.callpal::swpctx 3942 2.08% 2.13% # number of callpals executed
873system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed
874system.cpu0.kern.callpal::wrent 7 0.00% 2.16% # number of callpals executed
875system.cpu0.kern.callpal::swpipl 173212 91.45% 93.61% # number of callpals executed
876system.cpu0.kern.callpal::rdps 6702 3.54% 97.15% # number of callpals executed
877system.cpu0.kern.callpal::wrkgp 1 0.00% 97.15% # number of callpals executed
878system.cpu0.kern.callpal::wrusp 4 0.00% 97.16% # number of callpals executed
879system.cpu0.kern.callpal::rdusp 9 0.00% 97.16% # number of callpals executed
880system.cpu0.kern.callpal::whami 2 0.00% 97.16% # number of callpals executed
881system.cpu0.kern.callpal::rti 4842 2.56% 99.72% # number of callpals executed
882system.cpu0.kern.callpal::callsys 394 0.21% 99.93% # number of callpals executed
883system.cpu0.kern.callpal::imb 139 0.07% 100.00% # number of callpals executed
884system.cpu0.kern.callpal::total 189397 # number of callpals executed
885system.cpu0.kern.mode_switch::kernel 7440 # number of protection mode switches
886system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches
887system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
888system.cpu0.kern.mode_good::kernel 1368
889system.cpu0.kern.mode_good::user 1369
890system.cpu0.kern.mode_good::idle 0
891system.cpu0.kern.mode_switch_good::kernel 0.183871 # fraction of useful protection mode switches
892system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
893system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
894system.cpu0.kern.mode_switch_good::total 0.310705 # fraction of useful protection mode switches
895system.cpu0.kern.mode_ticks::kernel 1958025785500 99.81% 99.81% # number of ticks spent at the given mode
896system.cpu0.kern.mode_ticks::user 3814613000 0.19% 100.00% # number of ticks spent at the given mode
897system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
898system.cpu0.kern.swap_context 3943 # number of times the context was actually changed
899system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
900system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
901system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
902system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
903system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
904system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
905system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
906system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

922system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
923system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
924system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
925system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
926system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
927system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
928system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
929system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
930system.toL2Bus.throughput 105075557 # Throughput (bytes/s)
931system.toL2Bus.trans_dist::ReadReq 2099191 # Transaction distribution
932system.toL2Bus.trans_dist::ReadResp 2099176 # Transaction distribution
933system.toL2Bus.trans_dist::WriteReq 12397 # Transaction distribution
934system.toL2Bus.trans_dist::WriteResp 12397 # Transaction distribution
935system.toL2Bus.trans_dist::Writeback 820882 # Transaction distribution
936system.toL2Bus.trans_dist::UpgradeReq 4248 # Transaction distribution
937system.toL2Bus.trans_dist::SCUpgradeReq 894 # Transaction distribution
938system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution
939system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution
940system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution
941system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes)
942system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes)
943system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes)
944system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes)
945system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes)
946system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes)
947system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes)
948system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes)
949system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes)
950system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes)
951system.toL2Bus.data_through_bus 205232754 # Total data (bytes)
952system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes)
953system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks)
954system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
955system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks)
956system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
957system.toL2Bus.respLayer0.occupancy 4148559004 # Layer occupancy (ticks)
958system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
959system.toL2Bus.respLayer1.occupancy 6195378103 # Layer occupancy (ticks)
960system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
961system.toL2Bus.respLayer2.occupancy 360929992 # Layer occupancy (ticks)
962system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
963system.toL2Bus.respLayer3.occupancy 206344318 # Layer occupancy (ticks)
964system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
965system.iobus.throughput 1391673 # Throughput (bytes/s)
966system.iobus.trans_dist::ReadReq 7377 # Transaction distribution
967system.iobus.trans_dist::ReadResp 7377 # Transaction distribution
968system.iobus.trans_dist::WriteReq 53949 # Transaction distribution
969system.iobus.trans_dist::WriteResp 53949 # Transaction distribution
970system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes)
971system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
972system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
973system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
974system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
975system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
976system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
977system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
978system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
979system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
980system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
981system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
982system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes)
983system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes)
984system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes)
985system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes)
986system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes)
987system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
988system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
989system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
990system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
991system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
992system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
993system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
994system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
995system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
996system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
997system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
998system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes)
999system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes)
1000system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes)
1001system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes)
1002system.iobus.data_through_bus 2730242 # Total data (bytes)
1003system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks)
1004system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1005system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1006system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1007system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1008system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1009system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1010system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1011system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)

--- 5 unchanged lines hidden (view full) ---

1017system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1018system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1019system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1020system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1021system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1022system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1023system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1024system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1025system.iobus.reqLayer29.occupancy 378297154 # Layer occupancy (ticks)
1026system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1027system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1028system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1029system.iobus.respLayer0.occupancy 26795000 # Layer occupancy (ticks)
1030system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1031system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks)
1032system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1033system.cpu0.icache.tags.replacements 920572 # number of replacements
1034system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use
1035system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks.
1036system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks.
1037system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks.
1038system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit.
1039system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor
1040system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy
1041system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy
1042system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits
1043system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits
1044system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits
1045system.cpu0.icache.demand_hits::total 53689788 # number of demand (read+write) hits
1046system.cpu0.icache.overall_hits::cpu0.inst 53689788 # number of overall hits
1047system.cpu0.icache.overall_hits::total 53689788 # number of overall hits
1048system.cpu0.icache.ReadReq_misses::cpu0.inst 921200 # number of ReadReq misses
1049system.cpu0.icache.ReadReq_misses::total 921200 # number of ReadReq misses
1050system.cpu0.icache.demand_misses::cpu0.inst 921200 # number of demand (read+write) misses
1051system.cpu0.icache.demand_misses::total 921200 # number of demand (read+write) misses
1052system.cpu0.icache.overall_misses::cpu0.inst 921200 # number of overall misses
1053system.cpu0.icache.overall_misses::total 921200 # number of overall misses
1054system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12937764004 # number of ReadReq miss cycles
1055system.cpu0.icache.ReadReq_miss_latency::total 12937764004 # number of ReadReq miss cycles
1056system.cpu0.icache.demand_miss_latency::cpu0.inst 12937764004 # number of demand (read+write) miss cycles
1057system.cpu0.icache.demand_miss_latency::total 12937764004 # number of demand (read+write) miss cycles
1058system.cpu0.icache.overall_miss_latency::cpu0.inst 12937764004 # number of overall miss cycles
1059system.cpu0.icache.overall_miss_latency::total 12937764004 # number of overall miss cycles
1060system.cpu0.icache.ReadReq_accesses::cpu0.inst 54610988 # number of ReadReq accesses(hits+misses)
1061system.cpu0.icache.ReadReq_accesses::total 54610988 # number of ReadReq accesses(hits+misses)
1062system.cpu0.icache.demand_accesses::cpu0.inst 54610988 # number of demand (read+write) accesses
1063system.cpu0.icache.demand_accesses::total 54610988 # number of demand (read+write) accesses
1064system.cpu0.icache.overall_accesses::cpu0.inst 54610988 # number of overall (read+write) accesses
1065system.cpu0.icache.overall_accesses::total 54610988 # number of overall (read+write) accesses
1066system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016868 # miss rate for ReadReq accesses
1067system.cpu0.icache.ReadReq_miss_rate::total 0.016868 # miss rate for ReadReq accesses
1068system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016868 # miss rate for demand accesses
1069system.cpu0.icache.demand_miss_rate::total 0.016868 # miss rate for demand accesses
1070system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016868 # miss rate for overall accesses
1071system.cpu0.icache.overall_miss_rate::total 0.016868 # miss rate for overall accesses
1072system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14044.468089 # average ReadReq miss latency
1073system.cpu0.icache.ReadReq_avg_miss_latency::total 14044.468089 # average ReadReq miss latency
1074system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency
1075system.cpu0.icache.demand_avg_miss_latency::total 14044.468089 # average overall miss latency
1076system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14044.468089 # average overall miss latency
1077system.cpu0.icache.overall_avg_miss_latency::total 14044.468089 # average overall miss latency
1078system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1079system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1080system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1081system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1082system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1083system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1084system.cpu0.icache.fast_writes 0 # number of fast writes performed
1085system.cpu0.icache.cache_copies 0 # number of cache copies performed
1086system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 921200 # number of ReadReq MSHR misses
1087system.cpu0.icache.ReadReq_mshr_misses::total 921200 # number of ReadReq MSHR misses
1088system.cpu0.icache.demand_mshr_misses::cpu0.inst 921200 # number of demand (read+write) MSHR misses
1089system.cpu0.icache.demand_mshr_misses::total 921200 # number of demand (read+write) MSHR misses
1090system.cpu0.icache.overall_mshr_misses::cpu0.inst 921200 # number of overall MSHR misses
1091system.cpu0.icache.overall_mshr_misses::total 921200 # number of overall MSHR misses
1092system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11089045996 # number of ReadReq MSHR miss cycles
1093system.cpu0.icache.ReadReq_mshr_miss_latency::total 11089045996 # number of ReadReq MSHR miss cycles
1094system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11089045996 # number of demand (read+write) MSHR miss cycles
1095system.cpu0.icache.demand_mshr_miss_latency::total 11089045996 # number of demand (read+write) MSHR miss cycles
1096system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11089045996 # number of overall MSHR miss cycles
1097system.cpu0.icache.overall_mshr_miss_latency::total 11089045996 # number of overall MSHR miss cycles
1098system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for ReadReq accesses
1099system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016868 # mshr miss rate for ReadReq accesses
1100system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for demand accesses
1101system.cpu0.icache.demand_mshr_miss_rate::total 0.016868 # mshr miss rate for demand accesses
1102system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016868 # mshr miss rate for overall accesses
1103system.cpu0.icache.overall_mshr_miss_rate::total 0.016868 # mshr miss rate for overall accesses
1104system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average ReadReq mshr miss latency
1105system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12037.609635 # average ReadReq mshr miss latency
1106system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency
1107system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency
1108system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency
1109system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency
1110system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1111system.cpu0.dcache.tags.replacements 1349865 # number of replacements
1112system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use
1113system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks.
1114system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks.
1115system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks.
1116system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit.
1117system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor
1118system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy
1119system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy
1120system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits
1121system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits
1122system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits
1123system.cpu0.dcache.WriteReq_hits::total 5646858 # number of WriteReq hits
1124system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177791 # number of LoadLockedReq hits
1125system.cpu0.dcache.LoadLockedReq_hits::total 177791 # number of LoadLockedReq hits
1126system.cpu0.dcache.StoreCondReq_hits::cpu0.data 193304 # number of StoreCondReq hits
1127system.cpu0.dcache.StoreCondReq_hits::total 193304 # number of StoreCondReq hits
1128system.cpu0.dcache.demand_hits::cpu0.data 13154053 # number of demand (read+write) hits
1129system.cpu0.dcache.demand_hits::total 13154053 # number of demand (read+write) hits
1130system.cpu0.dcache.overall_hits::cpu0.data 13154053 # number of overall hits
1131system.cpu0.dcache.overall_hits::total 13154053 # number of overall hits
1132system.cpu0.dcache.ReadReq_misses::cpu0.data 1040730 # number of ReadReq misses
1133system.cpu0.dcache.ReadReq_misses::total 1040730 # number of ReadReq misses
1134system.cpu0.dcache.WriteReq_misses::cpu0.data 297940 # number of WriteReq misses
1135system.cpu0.dcache.WriteReq_misses::total 297940 # number of WriteReq misses
1136system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16884 # number of LoadLockedReq misses
1137system.cpu0.dcache.LoadLockedReq_misses::total 16884 # number of LoadLockedReq misses
1138system.cpu0.dcache.StoreCondReq_misses::cpu0.data 399 # number of StoreCondReq misses
1139system.cpu0.dcache.StoreCondReq_misses::total 399 # number of StoreCondReq misses
1140system.cpu0.dcache.demand_misses::cpu0.data 1338670 # number of demand (read+write) misses
1141system.cpu0.dcache.demand_misses::total 1338670 # number of demand (read+write) misses
1142system.cpu0.dcache.overall_misses::cpu0.data 1338670 # number of overall misses
1143system.cpu0.dcache.overall_misses::total 1338670 # number of overall misses
1144system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27787431256 # number of ReadReq miss cycles
1145system.cpu0.dcache.ReadReq_miss_latency::total 27787431256 # number of ReadReq miss cycles
1146system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10644315314 # number of WriteReq miss cycles
1147system.cpu0.dcache.WriteReq_miss_latency::total 10644315314 # number of WriteReq miss cycles
1148system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 223091000 # number of LoadLockedReq miss cycles
1149system.cpu0.dcache.LoadLockedReq_miss_latency::total 223091000 # number of LoadLockedReq miss cycles
1150system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2495533 # number of StoreCondReq miss cycles
1151system.cpu0.dcache.StoreCondReq_miss_latency::total 2495533 # number of StoreCondReq miss cycles
1152system.cpu0.dcache.demand_miss_latency::cpu0.data 38431746570 # number of demand (read+write) miss cycles
1153system.cpu0.dcache.demand_miss_latency::total 38431746570 # number of demand (read+write) miss cycles
1154system.cpu0.dcache.overall_miss_latency::cpu0.data 38431746570 # number of overall miss cycles
1155system.cpu0.dcache.overall_miss_latency::total 38431746570 # number of overall miss cycles
1156system.cpu0.dcache.ReadReq_accesses::cpu0.data 8547925 # number of ReadReq accesses(hits+misses)
1157system.cpu0.dcache.ReadReq_accesses::total 8547925 # number of ReadReq accesses(hits+misses)
1158system.cpu0.dcache.WriteReq_accesses::cpu0.data 5944798 # number of WriteReq accesses(hits+misses)
1159system.cpu0.dcache.WriteReq_accesses::total 5944798 # number of WriteReq accesses(hits+misses)
1160system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194675 # number of LoadLockedReq accesses(hits+misses)
1161system.cpu0.dcache.LoadLockedReq_accesses::total 194675 # number of LoadLockedReq accesses(hits+misses)
1162system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 193703 # number of StoreCondReq accesses(hits+misses)
1163system.cpu0.dcache.StoreCondReq_accesses::total 193703 # number of StoreCondReq accesses(hits+misses)
1164system.cpu0.dcache.demand_accesses::cpu0.data 14492723 # number of demand (read+write) accesses
1165system.cpu0.dcache.demand_accesses::total 14492723 # number of demand (read+write) accesses
1166system.cpu0.dcache.overall_accesses::cpu0.data 14492723 # number of overall (read+write) accesses
1167system.cpu0.dcache.overall_accesses::total 14492723 # number of overall (read+write) accesses
1168system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.121752 # miss rate for ReadReq accesses
1169system.cpu0.dcache.ReadReq_miss_rate::total 0.121752 # miss rate for ReadReq accesses
1170system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050118 # miss rate for WriteReq accesses
1171system.cpu0.dcache.WriteReq_miss_rate::total 0.050118 # miss rate for WriteReq accesses
1172system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086729 # miss rate for LoadLockedReq accesses
1173system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086729 # miss rate for LoadLockedReq accesses
1174system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002060 # miss rate for StoreCondReq accesses
1175system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002060 # miss rate for StoreCondReq accesses
1176system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092368 # miss rate for demand accesses
1177system.cpu0.dcache.demand_miss_rate::total 0.092368 # miss rate for demand accesses
1178system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092368 # miss rate for overall accesses
1179system.cpu0.dcache.overall_miss_rate::total 0.092368 # miss rate for overall accesses
1180system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26699.942594 # average ReadReq miss latency
1181system.cpu0.dcache.ReadReq_avg_miss_latency::total 26699.942594 # average ReadReq miss latency
1182system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35726.372135 # average WriteReq miss latency
1183system.cpu0.dcache.WriteReq_avg_miss_latency::total 35726.372135 # average WriteReq miss latency
1184system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13213.160389 # average LoadLockedReq miss latency
1185system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13213.160389 # average LoadLockedReq miss latency
1186system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6254.468672 # average StoreCondReq miss latency
1187system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6254.468672 # average StoreCondReq miss latency
1188system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency
1189system.cpu0.dcache.demand_avg_miss_latency::total 28708.902545 # average overall miss latency
1190system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 28708.902545 # average overall miss latency
1191system.cpu0.dcache.overall_avg_miss_latency::total 28708.902545 # average overall miss latency
1192system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1193system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1194system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1195system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1196system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1197system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1198system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1199system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1200system.cpu0.dcache.writebacks::writebacks 798646 # number of writebacks
1201system.cpu0.dcache.writebacks::total 798646 # number of writebacks
1202system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1040730 # number of ReadReq MSHR misses
1203system.cpu0.dcache.ReadReq_mshr_misses::total 1040730 # number of ReadReq MSHR misses
1204system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297940 # number of WriteReq MSHR misses
1205system.cpu0.dcache.WriteReq_mshr_misses::total 297940 # number of WriteReq MSHR misses
1206system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16884 # number of LoadLockedReq MSHR misses
1207system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16884 # number of LoadLockedReq MSHR misses
1208system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 399 # number of StoreCondReq MSHR misses
1209system.cpu0.dcache.StoreCondReq_mshr_misses::total 399 # number of StoreCondReq MSHR misses
1210system.cpu0.dcache.demand_mshr_misses::cpu0.data 1338670 # number of demand (read+write) MSHR misses
1211system.cpu0.dcache.demand_mshr_misses::total 1338670 # number of demand (read+write) MSHR misses
1212system.cpu0.dcache.overall_mshr_misses::cpu0.data 1338670 # number of overall MSHR misses
1213system.cpu0.dcache.overall_mshr_misses::total 1338670 # number of overall MSHR misses
1214system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25571734744 # number of ReadReq MSHR miss cycles
1215system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25571734744 # number of ReadReq MSHR miss cycles
1216system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9990567686 # number of WriteReq MSHR miss cycles
1217system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9990567686 # number of WriteReq MSHR miss cycles
1218system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 189290000 # number of LoadLockedReq MSHR miss cycles
1219system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 189290000 # number of LoadLockedReq MSHR miss cycles
1220system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1697467 # number of StoreCondReq MSHR miss cycles
1221system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1697467 # number of StoreCondReq MSHR miss cycles
1222system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35562302430 # number of demand (read+write) MSHR miss cycles
1223system.cpu0.dcache.demand_mshr_miss_latency::total 35562302430 # number of demand (read+write) MSHR miss cycles
1224system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35562302430 # number of overall MSHR miss cycles
1225system.cpu0.dcache.overall_mshr_miss_latency::total 35562302430 # number of overall MSHR miss cycles
1226system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465580500 # number of ReadReq MSHR uncacheable cycles
1227system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465580500 # number of ReadReq MSHR uncacheable cycles
1228system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2094321000 # number of WriteReq MSHR uncacheable cycles
1229system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2094321000 # number of WriteReq MSHR uncacheable cycles
1230system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3559901500 # number of overall MSHR uncacheable cycles
1231system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3559901500 # number of overall MSHR uncacheable cycles
1232system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.121752 # mshr miss rate for ReadReq accesses
1233system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.121752 # mshr miss rate for ReadReq accesses
1234system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050118 # mshr miss rate for WriteReq accesses
1235system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050118 # mshr miss rate for WriteReq accesses
1236system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086729 # mshr miss rate for LoadLockedReq accesses
1237system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086729 # mshr miss rate for LoadLockedReq accesses
1238system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002060 # mshr miss rate for StoreCondReq accesses
1239system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002060 # mshr miss rate for StoreCondReq accesses
1240system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for demand accesses
1241system.cpu0.dcache.demand_mshr_miss_rate::total 0.092368 # mshr miss rate for demand accesses
1242system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092368 # mshr miss rate for overall accesses
1243system.cpu0.dcache.overall_mshr_miss_rate::total 0.092368 # mshr miss rate for overall accesses
1244system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24570.959561 # average ReadReq mshr miss latency
1245system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24570.959561 # average ReadReq mshr miss latency
1246system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33532.146358 # average WriteReq mshr miss latency
1247system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33532.146358 # average WriteReq mshr miss latency
1248system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11211.205875 # average LoadLockedReq mshr miss latency
1249system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11211.205875 # average LoadLockedReq mshr miss latency
1250system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4254.303258 # average StoreCondReq mshr miss latency
1251system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4254.303258 # average StoreCondReq mshr miss latency
1252system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency
1253system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency
1254system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26565.398814 # average overall mshr miss latency
1255system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26565.398814 # average overall mshr miss latency
1256system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1257system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1258system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1259system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1260system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1261system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1262system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1263system.cpu1.dtb.fetch_hits 0 # ITB hits
1264system.cpu1.dtb.fetch_misses 0 # ITB misses
1265system.cpu1.dtb.fetch_acv 0 # ITB acv
1266system.cpu1.dtb.fetch_accesses 0 # ITB accesses
1267system.cpu1.dtb.read_hits 957039 # DTB read hits
1268system.cpu1.dtb.read_misses 2620 # DTB read misses
1269system.cpu1.dtb.read_acv 0 # DTB read access violations
1270system.cpu1.dtb.read_accesses 205337 # DTB read accesses
1271system.cpu1.dtb.write_hits 556340 # DTB write hits
1272system.cpu1.dtb.write_misses 235 # DTB write misses
1273system.cpu1.dtb.write_acv 24 # DTB write access violations
1274system.cpu1.dtb.write_accesses 89739 # DTB write accesses
1275system.cpu1.dtb.data_hits 1513379 # DTB hits
1276system.cpu1.dtb.data_misses 2855 # DTB misses
1277system.cpu1.dtb.data_acv 24 # DTB access violations
1278system.cpu1.dtb.data_accesses 295076 # DTB accesses
1279system.cpu1.itb.fetch_hits 1320031 # ITB hits
1280system.cpu1.itb.fetch_misses 1064 # ITB misses
1281system.cpu1.itb.fetch_acv 0 # ITB acv
1282system.cpu1.itb.fetch_accesses 1321095 # ITB accesses
1283system.cpu1.itb.read_hits 0 # DTB read hits
1284system.cpu1.itb.read_misses 0 # DTB read misses
1285system.cpu1.itb.read_acv 0 # DTB read access violations
1286system.cpu1.itb.read_accesses 0 # DTB read accesses
1287system.cpu1.itb.write_hits 0 # DTB write hits
1288system.cpu1.itb.write_misses 0 # DTB write misses
1289system.cpu1.itb.write_acv 0 # DTB write access violations
1290system.cpu1.itb.write_accesses 0 # DTB write accesses
1291system.cpu1.itb.data_hits 0 # DTB hits
1292system.cpu1.itb.data_misses 0 # DTB misses
1293system.cpu1.itb.data_acv 0 # DTB access violations
1294system.cpu1.itb.data_accesses 0 # DTB accesses
1295system.cpu1.numCycles 3921887017 # number of cpu cycles simulated
1296system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1297system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1298system.cpu1.committedInsts 4749746 # Number of instructions committed
1299system.cpu1.committedOps 4749746 # Number of ops (including micro ops) committed
1300system.cpu1.num_int_alu_accesses 4446088 # Number of integer alu accesses
1301system.cpu1.num_fp_alu_accesses 30301 # Number of float alu accesses
1302system.cpu1.num_func_calls 145582 # number of times a function call or return occured
1303system.cpu1.num_conditional_control_insts 455512 # number of instructions that are conditional controls
1304system.cpu1.num_int_insts 4446088 # number of integer instructions
1305system.cpu1.num_fp_insts 30301 # number of float instructions
1306system.cpu1.num_int_register_reads 6169769 # number of times the integer registers were read
1307system.cpu1.num_int_register_writes 3384887 # number of times the integer registers were written
1308system.cpu1.num_fp_register_reads 19629 # number of times the floating registers were read
1309system.cpu1.num_fp_register_writes 19442 # number of times the floating registers were written
1310system.cpu1.num_mem_refs 1521715 # number of memory refs
1311system.cpu1.num_load_insts 962201 # Number of load instructions
1312system.cpu1.num_store_insts 559514 # Number of store instructions
1313system.cpu1.num_idle_cycles 3904242469.193159 # Number of idle cycles
1314system.cpu1.num_busy_cycles 17644547.806841 # Number of busy cycles
1315system.cpu1.not_idle_fraction 0.004499 # Percentage of non-idle cycles
1316system.cpu1.idle_fraction 0.995501 # Percentage of idle cycles
1317system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1318system.cpu1.kern.inst.quiesce 2329 # number of quiesce instructions executed
1319system.cpu1.kern.inst.hwrei 33659 # number of hwrei instructions executed
1320system.cpu1.kern.ipl_count::0 8392 30.97% 30.97% # number of times we switched to this ipl
1321system.cpu1.kern.ipl_count::22 1970 7.27% 38.24% # number of times we switched to this ipl
1322system.cpu1.kern.ipl_count::30 88 0.32% 38.57% # number of times we switched to this ipl
1323system.cpu1.kern.ipl_count::31 16645 61.43% 100.00% # number of times we switched to this ipl
1324system.cpu1.kern.ipl_count::total 27095 # number of times we switched to this ipl
1325system.cpu1.kern.ipl_good::0 8384 44.74% 44.74% # number of times we switched to this ipl from a different ipl
1326system.cpu1.kern.ipl_good::22 1970 10.51% 55.26% # number of times we switched to this ipl from a different ipl
1327system.cpu1.kern.ipl_good::30 88 0.47% 55.73% # number of times we switched to this ipl from a different ipl
1328system.cpu1.kern.ipl_good::31 8296 44.27% 100.00% # number of times we switched to this ipl from a different ipl
1329system.cpu1.kern.ipl_good::total 18738 # number of times we switched to this ipl from a different ipl
1330system.cpu1.kern.ipl_ticks::0 1917649813500 97.79% 97.79% # number of cycles we spent at this ipl
1331system.cpu1.kern.ipl_ticks::22 700167000 0.04% 97.83% # number of cycles we spent at this ipl
1332system.cpu1.kern.ipl_ticks::30 60318500 0.00% 97.83% # number of cycles we spent at this ipl
1333system.cpu1.kern.ipl_ticks::31 42533179500 2.17% 100.00% # number of cycles we spent at this ipl
1334system.cpu1.kern.ipl_ticks::total 1960943478500 # number of cycles we spent at this ipl
1335system.cpu1.kern.ipl_used::0 0.999047 # fraction of swpipl calls that actually changed the ipl
1336system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1337system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
1338system.cpu1.kern.ipl_used::31 0.498408 # fraction of swpipl calls that actually changed the ipl
1339system.cpu1.kern.ipl_used::total 0.691567 # fraction of swpipl calls that actually changed the ipl
1340system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
1341system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
1342system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
1343system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
1344system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
1345system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
1346system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
1347system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
1348system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
1349system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
1350system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
1351system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
1352system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
1353system.cpu1.kern.syscall::total 92 # number of syscalls executed
1354system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
1355system.cpu1.kern.callpal::wripir 6 0.02% 0.03% # number of callpals executed
1356system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
1357system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
1358system.cpu1.kern.callpal::swpctx 283 1.02% 1.06% # number of callpals executed
1359system.cpu1.kern.callpal::tbi 3 0.01% 1.07% # number of callpals executed
1360system.cpu1.kern.callpal::wrent 7 0.03% 1.09% # number of callpals executed
1361system.cpu1.kern.callpal::swpipl 22604 81.73% 82.82% # number of callpals executed
1362system.cpu1.kern.callpal::rdps 2147 7.76% 90.59% # number of callpals executed
1363system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed
1364system.cpu1.kern.callpal::wrusp 3 0.01% 90.60% # number of callpals executed
1365system.cpu1.kern.callpal::whami 3 0.01% 90.61% # number of callpals executed
1366system.cpu1.kern.callpal::rti 2432 8.79% 99.41% # number of callpals executed
1367system.cpu1.kern.callpal::callsys 121 0.44% 99.84% # number of callpals executed
1368system.cpu1.kern.callpal::imb 42 0.15% 100.00% # number of callpals executed
1369system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
1370system.cpu1.kern.callpal::total 27656 # number of callpals executed
1371system.cpu1.kern.mode_switch::kernel 652 # number of protection mode switches
1372system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
1373system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches
1374system.cpu1.kern.mode_good::kernel 379
1375system.cpu1.kern.mode_good::user 367
1376system.cpu1.kern.mode_good::idle 12
1377system.cpu1.kern.mode_switch_good::kernel 0.581288 # fraction of useful protection mode switches
1378system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1379system.cpu1.kern.mode_switch_good::idle 0.005811 # fraction of useful protection mode switches
1380system.cpu1.kern.mode_switch_good::total 0.245785 # fraction of useful protection mode switches
1381system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # number of ticks spent at the given mode
1382system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode
1383system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode
1384system.cpu1.kern.swap_context 284 # number of times the context was actually changed
1385system.cpu1.icache.tags.replacements 79630 # number of replacements
1386system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use
1387system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks.
1388system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks.
1389system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks.
1390system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit.
1391system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor
1392system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy
1393system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy
1394system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits
1395system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits
1396system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits
1397system.cpu1.icache.demand_hits::total 4672446 # number of demand (read+write) hits
1398system.cpu1.icache.overall_hits::cpu1.inst 4672446 # number of overall hits
1399system.cpu1.icache.overall_hits::total 4672446 # number of overall hits
1400system.cpu1.icache.ReadReq_misses::cpu1.inst 80179 # number of ReadReq misses
1401system.cpu1.icache.ReadReq_misses::total 80179 # number of ReadReq misses
1402system.cpu1.icache.demand_misses::cpu1.inst 80179 # number of demand (read+write) misses
1403system.cpu1.icache.demand_misses::total 80179 # number of demand (read+write) misses
1404system.cpu1.icache.overall_misses::cpu1.inst 80179 # number of overall misses
1405system.cpu1.icache.overall_misses::total 80179 # number of overall misses
1406system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1082064992 # number of ReadReq miss cycles
1407system.cpu1.icache.ReadReq_miss_latency::total 1082064992 # number of ReadReq miss cycles
1408system.cpu1.icache.demand_miss_latency::cpu1.inst 1082064992 # number of demand (read+write) miss cycles
1409system.cpu1.icache.demand_miss_latency::total 1082064992 # number of demand (read+write) miss cycles
1410system.cpu1.icache.overall_miss_latency::cpu1.inst 1082064992 # number of overall miss cycles
1411system.cpu1.icache.overall_miss_latency::total 1082064992 # number of overall miss cycles
1412system.cpu1.icache.ReadReq_accesses::cpu1.inst 4752625 # number of ReadReq accesses(hits+misses)
1413system.cpu1.icache.ReadReq_accesses::total 4752625 # number of ReadReq accesses(hits+misses)
1414system.cpu1.icache.demand_accesses::cpu1.inst 4752625 # number of demand (read+write) accesses
1415system.cpu1.icache.demand_accesses::total 4752625 # number of demand (read+write) accesses
1416system.cpu1.icache.overall_accesses::cpu1.inst 4752625 # number of overall (read+write) accesses
1417system.cpu1.icache.overall_accesses::total 4752625 # number of overall (read+write) accesses
1418system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016870 # miss rate for ReadReq accesses
1419system.cpu1.icache.ReadReq_miss_rate::total 0.016870 # miss rate for ReadReq accesses
1420system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016870 # miss rate for demand accesses
1421system.cpu1.icache.demand_miss_rate::total 0.016870 # miss rate for demand accesses
1422system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016870 # miss rate for overall accesses
1423system.cpu1.icache.overall_miss_rate::total 0.016870 # miss rate for overall accesses
1424system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13495.615959 # average ReadReq miss latency
1425system.cpu1.icache.ReadReq_avg_miss_latency::total 13495.615959 # average ReadReq miss latency
1426system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency
1427system.cpu1.icache.demand_avg_miss_latency::total 13495.615959 # average overall miss latency
1428system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13495.615959 # average overall miss latency
1429system.cpu1.icache.overall_avg_miss_latency::total 13495.615959 # average overall miss latency
1430system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1431system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1432system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1433system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1434system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1435system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1436system.cpu1.icache.fast_writes 0 # number of fast writes performed
1437system.cpu1.icache.cache_copies 0 # number of cache copies performed
1438system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 80179 # number of ReadReq MSHR misses
1439system.cpu1.icache.ReadReq_mshr_misses::total 80179 # number of ReadReq MSHR misses
1440system.cpu1.icache.demand_mshr_misses::cpu1.inst 80179 # number of demand (read+write) MSHR misses
1441system.cpu1.icache.demand_mshr_misses::total 80179 # number of demand (read+write) MSHR misses
1442system.cpu1.icache.overall_mshr_misses::cpu1.inst 80179 # number of overall MSHR misses
1443system.cpu1.icache.overall_mshr_misses::total 80179 # number of overall MSHR misses
1444system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 921458008 # number of ReadReq MSHR miss cycles
1445system.cpu1.icache.ReadReq_mshr_miss_latency::total 921458008 # number of ReadReq MSHR miss cycles
1446system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 921458008 # number of demand (read+write) MSHR miss cycles
1447system.cpu1.icache.demand_mshr_miss_latency::total 921458008 # number of demand (read+write) MSHR miss cycles
1448system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 921458008 # number of overall MSHR miss cycles
1449system.cpu1.icache.overall_mshr_miss_latency::total 921458008 # number of overall MSHR miss cycles
1450system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for ReadReq accesses
1451system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016870 # mshr miss rate for ReadReq accesses
1452system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for demand accesses
1453system.cpu1.icache.demand_mshr_miss_rate::total 0.016870 # mshr miss rate for demand accesses
1454system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016870 # mshr miss rate for overall accesses
1455system.cpu1.icache.overall_mshr_miss_rate::total 0.016870 # mshr miss rate for overall accesses
1456system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average ReadReq mshr miss latency
1457system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11492.510608 # average ReadReq mshr miss latency
1458system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency
1459system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency
1460system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency
1461system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency
1462system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1463system.cpu1.dcache.tags.replacements 40890 # number of replacements
1464system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use
1465system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks.
1466system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks.
1467system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks.
1468system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit.
1469system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor
1470system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy
1471system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy
1472system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits
1473system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits
1474system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits
1475system.cpu1.dcache.WriteReq_hits::total 531046 # number of WriteReq hits
1476system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 9250 # number of LoadLockedReq hits
1477system.cpu1.dcache.LoadLockedReq_hits::total 9250 # number of LoadLockedReq hits
1478system.cpu1.dcache.StoreCondReq_hits::cpu1.data 9554 # number of StoreCondReq hits
1479system.cpu1.dcache.StoreCondReq_hits::total 9554 # number of StoreCondReq hits
1480system.cpu1.dcache.demand_hits::cpu1.data 1448467 # number of demand (read+write) hits
1481system.cpu1.dcache.demand_hits::total 1448467 # number of demand (read+write) hits
1482system.cpu1.dcache.overall_hits::cpu1.data 1448467 # number of overall hits
1483system.cpu1.dcache.overall_hits::total 1448467 # number of overall hits
1484system.cpu1.dcache.ReadReq_misses::cpu1.data 31971 # number of ReadReq misses
1485system.cpu1.dcache.ReadReq_misses::total 31971 # number of ReadReq misses
1486system.cpu1.dcache.WriteReq_misses::cpu1.data 13337 # number of WriteReq misses
1487system.cpu1.dcache.WriteReq_misses::total 13337 # number of WriteReq misses
1488system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 850 # number of LoadLockedReq misses
1489system.cpu1.dcache.LoadLockedReq_misses::total 850 # number of LoadLockedReq misses
1490system.cpu1.dcache.StoreCondReq_misses::cpu1.data 495 # number of StoreCondReq misses
1491system.cpu1.dcache.StoreCondReq_misses::total 495 # number of StoreCondReq misses
1492system.cpu1.dcache.demand_misses::cpu1.data 45308 # number of demand (read+write) misses
1493system.cpu1.dcache.demand_misses::total 45308 # number of demand (read+write) misses
1494system.cpu1.dcache.overall_misses::cpu1.data 45308 # number of overall misses
1495system.cpu1.dcache.overall_misses::total 45308 # number of overall misses
1496system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 398942000 # number of ReadReq miss cycles
1497system.cpu1.dcache.ReadReq_miss_latency::total 398942000 # number of ReadReq miss cycles
1498system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 455916495 # number of WriteReq miss cycles
1499system.cpu1.dcache.WriteReq_miss_latency::total 455916495 # number of WriteReq miss cycles
1500system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 9380250 # number of LoadLockedReq miss cycles
1501system.cpu1.dcache.LoadLockedReq_miss_latency::total 9380250 # number of LoadLockedReq miss cycles
1502system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3699073 # number of StoreCondReq miss cycles
1503system.cpu1.dcache.StoreCondReq_miss_latency::total 3699073 # number of StoreCondReq miss cycles
1504system.cpu1.dcache.demand_miss_latency::cpu1.data 854858495 # number of demand (read+write) miss cycles
1505system.cpu1.dcache.demand_miss_latency::total 854858495 # number of demand (read+write) miss cycles
1506system.cpu1.dcache.overall_miss_latency::cpu1.data 854858495 # number of overall miss cycles
1507system.cpu1.dcache.overall_miss_latency::total 854858495 # number of overall miss cycles
1508system.cpu1.dcache.ReadReq_accesses::cpu1.data 949392 # number of ReadReq accesses(hits+misses)
1509system.cpu1.dcache.ReadReq_accesses::total 949392 # number of ReadReq accesses(hits+misses)
1510system.cpu1.dcache.WriteReq_accesses::cpu1.data 544383 # number of WriteReq accesses(hits+misses)
1511system.cpu1.dcache.WriteReq_accesses::total 544383 # number of WriteReq accesses(hits+misses)
1512system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 10100 # number of LoadLockedReq accesses(hits+misses)
1513system.cpu1.dcache.LoadLockedReq_accesses::total 10100 # number of LoadLockedReq accesses(hits+misses)
1514system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 10049 # number of StoreCondReq accesses(hits+misses)
1515system.cpu1.dcache.StoreCondReq_accesses::total 10049 # number of StoreCondReq accesses(hits+misses)
1516system.cpu1.dcache.demand_accesses::cpu1.data 1493775 # number of demand (read+write) accesses
1517system.cpu1.dcache.demand_accesses::total 1493775 # number of demand (read+write) accesses
1518system.cpu1.dcache.overall_accesses::cpu1.data 1493775 # number of overall (read+write) accesses
1519system.cpu1.dcache.overall_accesses::total 1493775 # number of overall (read+write) accesses
1520system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033675 # miss rate for ReadReq accesses
1521system.cpu1.dcache.ReadReq_miss_rate::total 0.033675 # miss rate for ReadReq accesses
1522system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.024499 # miss rate for WriteReq accesses
1523system.cpu1.dcache.WriteReq_miss_rate::total 0.024499 # miss rate for WriteReq accesses
1524system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.084158 # miss rate for LoadLockedReq accesses
1525system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.084158 # miss rate for LoadLockedReq accesses
1526system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.049259 # miss rate for StoreCondReq accesses
1527system.cpu1.dcache.StoreCondReq_miss_rate::total 0.049259 # miss rate for StoreCondReq accesses
1528system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030331 # miss rate for demand accesses
1529system.cpu1.dcache.demand_miss_rate::total 0.030331 # miss rate for demand accesses
1530system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030331 # miss rate for overall accesses
1531system.cpu1.dcache.overall_miss_rate::total 0.030331 # miss rate for overall accesses
1532system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12478.245910 # average ReadReq miss latency
1533system.cpu1.dcache.ReadReq_avg_miss_latency::total 12478.245910 # average ReadReq miss latency
1534system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34184.336432 # average WriteReq miss latency
1535system.cpu1.dcache.WriteReq_avg_miss_latency::total 34184.336432 # average WriteReq miss latency
1536system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11035.588235 # average LoadLockedReq miss latency
1537system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11035.588235 # average LoadLockedReq miss latency
1538system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7472.874747 # average StoreCondReq miss latency
1539system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7472.874747 # average StoreCondReq miss latency
1540system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency
1541system.cpu1.dcache.demand_avg_miss_latency::total 18867.716408 # average overall miss latency
1542system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18867.716408 # average overall miss latency
1543system.cpu1.dcache.overall_avg_miss_latency::total 18867.716408 # average overall miss latency
1544system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1545system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1546system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1547system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1548system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1549system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1550system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1551system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1552system.cpu1.dcache.writebacks::writebacks 22236 # number of writebacks
1553system.cpu1.dcache.writebacks::total 22236 # number of writebacks
1554system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 31971 # number of ReadReq MSHR misses
1555system.cpu1.dcache.ReadReq_mshr_misses::total 31971 # number of ReadReq MSHR misses
1556system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 13337 # number of WriteReq MSHR misses
1557system.cpu1.dcache.WriteReq_mshr_misses::total 13337 # number of WriteReq MSHR misses
1558system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 850 # number of LoadLockedReq MSHR misses
1559system.cpu1.dcache.LoadLockedReq_mshr_misses::total 850 # number of LoadLockedReq MSHR misses
1560system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 495 # number of StoreCondReq MSHR misses
1561system.cpu1.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses
1562system.cpu1.dcache.demand_mshr_misses::cpu1.data 45308 # number of demand (read+write) MSHR misses
1563system.cpu1.dcache.demand_mshr_misses::total 45308 # number of demand (read+write) MSHR misses
1564system.cpu1.dcache.overall_mshr_misses::cpu1.data 45308 # number of overall MSHR misses
1565system.cpu1.dcache.overall_mshr_misses::total 45308 # number of overall MSHR misses
1566system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 334917000 # number of ReadReq MSHR miss cycles
1567system.cpu1.dcache.ReadReq_mshr_miss_latency::total 334917000 # number of ReadReq MSHR miss cycles
1568system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 427133505 # number of WriteReq MSHR miss cycles
1569system.cpu1.dcache.WriteReq_mshr_miss_latency::total 427133505 # number of WriteReq MSHR miss cycles
1570system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 7677750 # number of LoadLockedReq MSHR miss cycles
1571system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 7677750 # number of LoadLockedReq MSHR miss cycles
1572system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2708927 # number of StoreCondReq MSHR miss cycles
1573system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2708927 # number of StoreCondReq MSHR miss cycles
1574system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 762050505 # number of demand (read+write) MSHR miss cycles
1575system.cpu1.dcache.demand_mshr_miss_latency::total 762050505 # number of demand (read+write) MSHR miss cycles
1576system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 762050505 # number of overall MSHR miss cycles
1577system.cpu1.dcache.overall_mshr_miss_latency::total 762050505 # number of overall MSHR miss cycles
1578system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles
1579system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles
1580system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 527878500 # number of WriteReq MSHR uncacheable cycles
1581system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 527878500 # number of WriteReq MSHR uncacheable cycles
1582system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 546646500 # number of overall MSHR uncacheable cycles
1583system.cpu1.dcache.overall_mshr_uncacheable_latency::total 546646500 # number of overall MSHR uncacheable cycles
1584system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033675 # mshr miss rate for ReadReq accesses
1585system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033675 # mshr miss rate for ReadReq accesses
1586system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024499 # mshr miss rate for WriteReq accesses
1587system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.024499 # mshr miss rate for WriteReq accesses
1588system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.084158 # mshr miss rate for LoadLockedReq accesses
1589system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.084158 # mshr miss rate for LoadLockedReq accesses
1590system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for StoreCondReq accesses
1591system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.049259 # mshr miss rate for StoreCondReq accesses
1592system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for demand accesses
1593system.cpu1.dcache.demand_mshr_miss_rate::total 0.030331 # mshr miss rate for demand accesses
1594system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030331 # mshr miss rate for overall accesses
1595system.cpu1.dcache.overall_mshr_miss_rate::total 0.030331 # mshr miss rate for overall accesses
1596system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10475.649808 # average ReadReq mshr miss latency
1597system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10475.649808 # average ReadReq mshr miss latency
1598system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32026.205668 # average WriteReq mshr miss latency
1599system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32026.205668 # average WriteReq mshr miss latency
1600system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9032.647059 # average LoadLockedReq mshr miss latency
1601system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9032.647059 # average LoadLockedReq mshr miss latency
1602system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5472.579798 # average StoreCondReq mshr miss latency
1603system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5472.579798 # average StoreCondReq mshr miss latency
1604system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency
1605system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency
1606system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16819.336651 # average overall mshr miss latency
1607system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16819.336651 # average overall mshr miss latency
1608system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1609system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1610system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1611system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1612system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1613system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1614system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1615
1616---------- End Simulation Statistics ----------