1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.982593 # Number of seconds simulated
4sim_ticks 1982592736000 # Number of ticks simulated
5final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 753764 # Simulator instruction rate (inst/s)
8host_op_rate 753764 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 24497172234 # Simulator tick rate (ticks/s)
10host_mem_usage 320072 # Number of bytes of host memory used
11host_seconds 80.93 # Real time elapsed on the host
12sim_insts 61003209 # Number of instructions simulated
13sim_ops 61003209 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory
--- 555 unchanged lines hidden (view full) ---
575system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency
576system.cpu0.dcache.overall_avg_miss_latency::total 50436.098305 # average overall miss latency
577system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
578system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
579system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
580system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
581system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
582system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
583system.cpu0.dcache.fast_writes 0 # number of fast writes performed
584system.cpu0.dcache.cache_copies 0 # number of cache copies performed
585system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks
586system.cpu0.dcache.writebacks::total 672790 # number of writebacks
587system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses
588system.cpu0.dcache.ReadReq_mshr_misses::total 934179 # number of ReadReq MSHR misses
589system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249076 # number of WriteReq MSHR misses
590system.cpu0.dcache.WriteReq_mshr_misses::total 249076 # number of WriteReq MSHR misses
591system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses
592system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses
--- 18 unchanged lines hidden (view full) ---
611system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89046500 # number of StoreCondReq MSHR miss cycles
612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89046500 # number of StoreCondReq MSHR miss cycles
613system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58495510500 # number of demand (read+write) MSHR miss cycles
614system.cpu0.dcache.demand_mshr_miss_latency::total 58495510500 # number of demand (read+write) MSHR miss cycles
615system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 # number of overall MSHR miss cycles
616system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles
617system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles
618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles
619system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451870500 # number of WriteReq MSHR uncacheable cycles
620system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451870500 # number of WriteReq MSHR uncacheable cycles
621system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4018772500 # number of overall MSHR uncacheable cycles
622system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4018772500 # number of overall MSHR uncacheable cycles
623system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses
624system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses
625system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses
626system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051354 # mshr miss rate for WriteReq accesses
627system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089501 # mshr miss rate for LoadLockedReq accesses
628system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089501 # mshr miss rate for LoadLockedReq accesses
629system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses
630system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses
--- 10 unchanged lines hidden (view full) ---
641system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15516.030667 # average StoreCondReq mshr miss latency
642system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15516.030667 # average StoreCondReq mshr miss latency
643system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency
644system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency
645system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency
646system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency
647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency
648system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency
649system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925 # average WriteReq mshr uncacheable latency
650system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925 # average WriteReq mshr uncacheable latency
651system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914 # average overall mshr uncacheable latency
652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914 # average overall mshr uncacheable latency
653system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
654system.cpu0.icache.tags.replacements 686545 # number of replacements
655system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use
656system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks.
657system.cpu0.icache.tags.sampled_refs 687057 # Sample count of references to valid blocks.
658system.cpu0.icache.tags.avg_refs 67.880661 # Average number of references to valid blocks.
659system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit.
660system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490868 # Average occupied blocks per requestor
661system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy
--- 41 unchanged lines hidden (view full) ---
703system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency
704system.cpu0.icache.overall_avg_miss_latency::total 15458.854971 # average overall miss latency
705system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
706system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
707system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
708system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
709system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
710system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
711system.cpu0.icache.fast_writes 0 # number of fast writes performed
712system.cpu0.icache.cache_copies 0 # number of cache copies performed
713system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks
714system.cpu0.icache.writebacks::total 686545 # number of writebacks
715system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses
716system.cpu0.icache.ReadReq_mshr_misses::total 687179 # number of ReadReq MSHR misses
717system.cpu0.icache.demand_mshr_misses::cpu0.inst 687179 # number of demand (read+write) MSHR misses
718system.cpu0.icache.demand_mshr_misses::total 687179 # number of demand (read+write) MSHR misses
719system.cpu0.icache.overall_mshr_misses::cpu0.inst 687179 # number of overall MSHR misses
720system.cpu0.icache.overall_mshr_misses::total 687179 # number of overall MSHR misses
--- 10 unchanged lines hidden (view full) ---
731system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses
732system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses
733system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average ReadReq mshr miss latency
734system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14458.854971 # average ReadReq mshr miss latency
735system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency
736system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency
737system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency
738system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency
739system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
740system.cpu1.dtb.fetch_hits 0 # ITB hits
741system.cpu1.dtb.fetch_misses 0 # ITB misses
742system.cpu1.dtb.fetch_acv 0 # ITB acv
743system.cpu1.dtb.fetch_accesses 0 # ITB accesses
744system.cpu1.dtb.read_hits 2511191 # DTB read hits
745system.cpu1.dtb.read_misses 2993 # DTB read misses
746system.cpu1.dtb.read_acv 0 # DTB read access violations
747system.cpu1.dtb.read_accesses 239364 # DTB read accesses
--- 236 unchanged lines hidden (view full) ---
984system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency
985system.cpu1.dcache.overall_avg_miss_latency::total 18125.218826 # average overall miss latency
986system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
987system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
988system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
989system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
990system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
991system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
992system.cpu1.dcache.fast_writes 0 # number of fast writes performed
993system.cpu1.dcache.cache_copies 0 # number of cache copies performed
994system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks
995system.cpu1.dcache.writebacks::total 119726 # number of writebacks
996system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses
997system.cpu1.dcache.ReadReq_mshr_misses::total 123491 # number of ReadReq MSHR misses
998system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65586 # number of WriteReq MSHR misses
999system.cpu1.dcache.WriteReq_mshr_misses::total 65586 # number of WriteReq MSHR misses
1000system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9255 # number of LoadLockedReq MSHR misses
1001system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9255 # number of LoadLockedReq MSHR misses
--- 18 unchanged lines hidden (view full) ---
1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90856500 # number of StoreCondReq MSHR miss cycles
1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90856500 # number of StoreCondReq MSHR miss cycles
1022system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237985000 # number of demand (read+write) MSHR miss cycles
1023system.cpu1.dcache.demand_mshr_miss_latency::total 3237985000 # number of demand (read+write) MSHR miss cycles
1024system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 # number of overall MSHR miss cycles
1025system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles
1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles
1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles
1028system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles
1029system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles
1030system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles
1031system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles
1032system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses
1033system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses
1034system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses
1035system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses
1036system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses
1037system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses
1038system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses
1039system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses
--- 10 unchanged lines hidden (view full) ---
1050system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency
1051system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency
1052system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency
1053system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency
1054system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency
1055system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency
1056system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency
1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency
1058system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency
1059system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency
1060system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency
1061system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency
1062system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1063system.cpu1.icache.tags.replacements 331529 # number of replacements
1064system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use
1065system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks.
1066system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks.
1067system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks.
1068system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit.
1069system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor
1070system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy
--- 43 unchanged lines hidden (view full) ---
1114system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency
1115system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency
1116system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1117system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1118system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1119system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1120system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1121system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1122system.cpu1.icache.fast_writes 0 # number of fast writes performed
1123system.cpu1.icache.cache_copies 0 # number of cache copies performed
1124system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks
1125system.cpu1.icache.writebacks::total 331529 # number of writebacks
1126system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses
1127system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses
1128system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses
1129system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses
1130system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses
1131system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses
--- 10 unchanged lines hidden (view full) ---
1142system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses
1143system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses
1144system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency
1145system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency
1146system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency
1147system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
1148system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency
1149system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
1150system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1151system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1152system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1153system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1154system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1155system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1156system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1157system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1158system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
--- 68 unchanged lines hidden (view full) ---
1227system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1228system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1229system.iocache.tags.tag_accesses 375543 # Number of tag accesses
1230system.iocache.tags.data_accesses 375543 # Number of data accesses
1231system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
1232system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
1233system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1234system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1235system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
1236system.iocache.demand_misses::total 175 # number of demand (read+write) misses
1237system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
1238system.iocache.overall_misses::total 175 # number of overall misses
1239system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles
1240system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles
1241system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles
1242system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles
1243system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles
1244system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles
1245system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles
1246system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles
1247system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
1248system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
1249system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1250system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1251system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
1252system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
1253system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
1254system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
1255system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1256system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1257system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1258system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1259system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1260system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1261system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1262system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1263system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency
1264system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency
1265system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency
1266system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency
1267system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
1268system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency
1269system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
1270system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency
1271system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1272system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1273system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1274system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1275system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1276system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1277system.iocache.fast_writes 0 # number of fast writes performed
1278system.iocache.cache_copies 0 # number of cache copies performed
1279system.iocache.writebacks::writebacks 41520 # number of writebacks
1280system.iocache.writebacks::total 41520 # number of writebacks
1281system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
1282system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
1283system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1284system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1285system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
1286system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
1287system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
1288system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
1289system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles
1290system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles
1291system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles
1292system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles
1293system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles
1294system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles
1295system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles
1296system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles
1297system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1298system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1299system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1300system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1301system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1302system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1303system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1304system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1305system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency
1306system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency
1307system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency
1308system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency
1309system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
1310system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
1311system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
1312system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
1313system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1314system.l2c.tags.replacements 342136 # number of replacements
1315system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use
1316system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks.
1317system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks.
1318system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks.
1319system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit.
1320system.l2c.tags.occ_blocks::writebacks 54851.977847 # Average occupied blocks per requestor
1321system.l2c.tags.occ_blocks::cpu0.inst 4799.733629 # Average occupied blocks per requestor
--- 174 unchanged lines hidden (view full) ---
1496system.l2c.overall_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency
1497system.l2c.overall_avg_miss_latency::total 125267.568349 # average overall miss latency
1498system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1499system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1500system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1501system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1502system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1503system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1504system.l2c.fast_writes 0 # number of fast writes performed
1505system.l2c.cache_copies 0 # number of cache copies performed
1506system.l2c.writebacks::writebacks 79408 # number of writebacks
1507system.l2c.writebacks::total 79408 # number of writebacks
1508system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
1509system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1510system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
1511system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
1512system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
1513system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
--- 56 unchanged lines hidden (view full) ---
1570system.l2c.overall_mshr_miss_latency::cpu0.inst 1514765500 # number of overall MSHR miss cycles
1571system.l2c.overall_mshr_miss_latency::cpu0.data 44421592000 # number of overall MSHR miss cycles
1572system.l2c.overall_mshr_miss_latency::cpu1.inst 112494001 # number of overall MSHR miss cycles
1573system.l2c.overall_mshr_miss_latency::cpu1.data 997859001 # number of overall MSHR miss cycles
1574system.l2c.overall_mshr_miss_latency::total 47046710502 # number of overall MSHR miss cycles
1575system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478327000 # number of ReadReq MSHR uncacheable cycles
1576system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23575500 # number of ReadReq MSHR uncacheable cycles
1577system.l2c.ReadReq_mshr_uncacheable_latency::total 1501902500 # number of ReadReq MSHR uncacheable cycles
1578system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2327774501 # number of WriteReq MSHR uncacheable cycles
1579system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 750967500 # number of WriteReq MSHR uncacheable cycles
1580system.l2c.WriteReq_mshr_uncacheable_latency::total 3078742001 # number of WriteReq MSHR uncacheable cycles
1581system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3806101501 # number of overall MSHR uncacheable cycles
1582system.l2c.overall_mshr_uncacheable_latency::cpu1.data 774543000 # number of overall MSHR uncacheable cycles
1583system.l2c.overall_mshr_uncacheable_latency::total 4580644501 # number of overall MSHR uncacheable cycles
1584system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1585system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1586system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941997 # mshr miss rate for UpgradeReq accesses
1587system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767797 # mshr miss rate for UpgradeReq accesses
1588system.l2c.UpgradeReq_mshr_miss_rate::total 0.867452 # mshr miss rate for UpgradeReq accesses
1589system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.957601 # mshr miss rate for SCUpgradeReq accesses
1590system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974843 # mshr miss rate for SCUpgradeReq accesses
1591system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966163 # mshr miss rate for SCUpgradeReq accesses
--- 39 unchanged lines hidden (view full) ---
1631system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency
1632system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency
1633system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency
1634system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency
1635system.l2c.overall_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency
1636system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency
1637system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency
1638system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency
1639system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438 # average WriteReq mshr uncacheable latency
1640system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412 # average WriteReq mshr uncacheable latency
1641system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288 # average WriteReq mshr uncacheable latency
1642system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191 # average overall mshr uncacheable latency
1643system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162 # average overall mshr uncacheable latency
1644system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680 # average overall mshr uncacheable latency
1645system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1646system.membus.trans_dist::ReadReq 7201 # Transaction distribution
1647system.membus.trans_dist::ReadResp 292681 # Transaction distribution
1648system.membus.trans_dist::WriteReq 14131 # Transaction distribution
1649system.membus.trans_dist::WriteResp 14131 # Transaction distribution
1650system.membus.trans_dist::WritebackDirty 120928 # Transaction distribution
1651system.membus.trans_dist::CleanEvict 262098 # Transaction distribution
1652system.membus.trans_dist::UpgradeReq 16893 # Transaction distribution
1653system.membus.trans_dist::SCUpgradeReq 11783 # Transaction distribution
--- 127 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.982593 # Number of seconds simulated
4sim_ticks 1982592736000 # Number of ticks simulated
5final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 753764 # Simulator instruction rate (inst/s)
8host_op_rate 753764 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 24497172234 # Simulator tick rate (ticks/s)
10host_mem_usage 320072 # Number of bytes of host memory used
11host_seconds 80.93 # Real time elapsed on the host
12sim_insts 61003209 # Number of instructions simulated
13sim_ops 61003209 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory
--- 555 unchanged lines hidden (view full) ---
575system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency
576system.cpu0.dcache.overall_avg_miss_latency::total 50436.098305 # average overall miss latency
577system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
578system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
579system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
580system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
581system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
582system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
583system.cpu0.dcache.fast_writes 0 # number of fast writes performed
584system.cpu0.dcache.cache_copies 0 # number of cache copies performed
585system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks
586system.cpu0.dcache.writebacks::total 672790 # number of writebacks
587system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses
588system.cpu0.dcache.ReadReq_mshr_misses::total 934179 # number of ReadReq MSHR misses
589system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249076 # number of WriteReq MSHR misses
590system.cpu0.dcache.WriteReq_mshr_misses::total 249076 # number of WriteReq MSHR misses
591system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses
592system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses
--- 18 unchanged lines hidden (view full) ---
611system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89046500 # number of StoreCondReq MSHR miss cycles
612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89046500 # number of StoreCondReq MSHR miss cycles
613system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58495510500 # number of demand (read+write) MSHR miss cycles
614system.cpu0.dcache.demand_mshr_miss_latency::total 58495510500 # number of demand (read+write) MSHR miss cycles
615system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 # number of overall MSHR miss cycles
616system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles
617system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles
618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles
619system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451870500 # number of WriteReq MSHR uncacheable cycles
620system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451870500 # number of WriteReq MSHR uncacheable cycles
621system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4018772500 # number of overall MSHR uncacheable cycles
622system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4018772500 # number of overall MSHR uncacheable cycles
623system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses
624system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses
625system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses
626system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051354 # mshr miss rate for WriteReq accesses
627system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089501 # mshr miss rate for LoadLockedReq accesses
628system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089501 # mshr miss rate for LoadLockedReq accesses
629system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses
630system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses
--- 10 unchanged lines hidden (view full) ---
641system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15516.030667 # average StoreCondReq mshr miss latency
642system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15516.030667 # average StoreCondReq mshr miss latency
643system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency
644system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency
645system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency
646system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency
647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency
648system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency
649system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227382.963925 # average WriteReq mshr uncacheable latency
650system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227382.963925 # average WriteReq mshr uncacheable latency
651system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224939.689914 # average overall mshr uncacheable latency
652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224939.689914 # average overall mshr uncacheable latency
653system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
654system.cpu0.icache.tags.replacements 686545 # number of replacements
655system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use
656system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks.
657system.cpu0.icache.tags.sampled_refs 687057 # Sample count of references to valid blocks.
658system.cpu0.icache.tags.avg_refs 67.880661 # Average number of references to valid blocks.
659system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit.
660system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490868 # Average occupied blocks per requestor
661system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy
--- 41 unchanged lines hidden (view full) ---
703system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency
704system.cpu0.icache.overall_avg_miss_latency::total 15458.854971 # average overall miss latency
705system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
706system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
707system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
708system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
709system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
710system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
711system.cpu0.icache.fast_writes 0 # number of fast writes performed
712system.cpu0.icache.cache_copies 0 # number of cache copies performed
713system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks
714system.cpu0.icache.writebacks::total 686545 # number of writebacks
715system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses
716system.cpu0.icache.ReadReq_mshr_misses::total 687179 # number of ReadReq MSHR misses
717system.cpu0.icache.demand_mshr_misses::cpu0.inst 687179 # number of demand (read+write) MSHR misses
718system.cpu0.icache.demand_mshr_misses::total 687179 # number of demand (read+write) MSHR misses
719system.cpu0.icache.overall_mshr_misses::cpu0.inst 687179 # number of overall MSHR misses
720system.cpu0.icache.overall_mshr_misses::total 687179 # number of overall MSHR misses
--- 10 unchanged lines hidden (view full) ---
731system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses
732system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses
733system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average ReadReq mshr miss latency
734system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14458.854971 # average ReadReq mshr miss latency
735system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency
736system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency
737system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency
738system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency
739system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
740system.cpu1.dtb.fetch_hits 0 # ITB hits
741system.cpu1.dtb.fetch_misses 0 # ITB misses
742system.cpu1.dtb.fetch_acv 0 # ITB acv
743system.cpu1.dtb.fetch_accesses 0 # ITB accesses
744system.cpu1.dtb.read_hits 2511191 # DTB read hits
745system.cpu1.dtb.read_misses 2993 # DTB read misses
746system.cpu1.dtb.read_acv 0 # DTB read access violations
747system.cpu1.dtb.read_accesses 239364 # DTB read accesses
--- 236 unchanged lines hidden (view full) ---
984system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency
985system.cpu1.dcache.overall_avg_miss_latency::total 18125.218826 # average overall miss latency
986system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
987system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
988system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
989system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
990system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
991system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
992system.cpu1.dcache.fast_writes 0 # number of fast writes performed
993system.cpu1.dcache.cache_copies 0 # number of cache copies performed
994system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks
995system.cpu1.dcache.writebacks::total 119726 # number of writebacks
996system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses
997system.cpu1.dcache.ReadReq_mshr_misses::total 123491 # number of ReadReq MSHR misses
998system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65586 # number of WriteReq MSHR misses
999system.cpu1.dcache.WriteReq_mshr_misses::total 65586 # number of WriteReq MSHR misses
1000system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9255 # number of LoadLockedReq MSHR misses
1001system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9255 # number of LoadLockedReq MSHR misses
--- 18 unchanged lines hidden (view full) ---
1020system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90856500 # number of StoreCondReq MSHR miss cycles
1021system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90856500 # number of StoreCondReq MSHR miss cycles
1022system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237985000 # number of demand (read+write) MSHR miss cycles
1023system.cpu1.dcache.demand_mshr_miss_latency::total 3237985000 # number of demand (read+write) MSHR miss cycles
1024system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 # number of overall MSHR miss cycles
1025system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles
1026system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles
1027system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles
1028system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482500 # number of WriteReq MSHR uncacheable cycles
1029system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482500 # number of WriteReq MSHR uncacheable cycles
1030system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533500 # number of overall MSHR uncacheable cycles
1031system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533500 # number of overall MSHR uncacheable cycles
1032system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses
1033system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses
1034system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses
1035system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses
1036system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses
1037system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses
1038system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses
1039system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses
--- 10 unchanged lines hidden (view full) ---
1050system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency
1051system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency
1052system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency
1053system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency
1054system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency
1055system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency
1056system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency
1057system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency
1058system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.198327 # average WriteReq mshr uncacheable latency
1059system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.198327 # average WriteReq mshr uncacheable latency
1060system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.780150 # average overall mshr uncacheable latency
1061system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.780150 # average overall mshr uncacheable latency
1062system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1063system.cpu1.icache.tags.replacements 331529 # number of replacements
1064system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use
1065system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks.
1066system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks.
1067system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks.
1068system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit.
1069system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor
1070system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy
--- 43 unchanged lines hidden (view full) ---
1114system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency
1115system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency
1116system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1117system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1118system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1119system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1120system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1121system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1122system.cpu1.icache.fast_writes 0 # number of fast writes performed
1123system.cpu1.icache.cache_copies 0 # number of cache copies performed
1124system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks
1125system.cpu1.icache.writebacks::total 331529 # number of writebacks
1126system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses
1127system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses
1128system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses
1129system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses
1130system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses
1131system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses
--- 10 unchanged lines hidden (view full) ---
1142system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses
1143system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses
1144system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency
1145system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency
1146system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency
1147system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
1148system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency
1149system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency
1150system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1151system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1152system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1153system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1154system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1155system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1156system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1157system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1158system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
--- 68 unchanged lines hidden (view full) ---
1227system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1228system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1229system.iocache.tags.tag_accesses 375543 # Number of tag accesses
1230system.iocache.tags.data_accesses 375543 # Number of data accesses
1231system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
1232system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
1233system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1234system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1235system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
1236system.iocache.demand_misses::total 175 # number of demand (read+write) misses
1237system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
1238system.iocache.overall_misses::total 175 # number of overall misses
1239system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles
1240system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles
1241system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles
1242system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles
1243system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles
1244system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles
1245system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles
1246system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles
1247system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
1248system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
1249system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1250system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1251system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
1252system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
1253system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
1254system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
1255system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1256system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1257system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1258system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1259system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1260system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1261system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1262system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1263system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency
1264system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency
1265system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency
1266system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency
1267system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
1268system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency
1269system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency
1270system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency
1271system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1272system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1273system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1274system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1275system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1276system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1277system.iocache.fast_writes 0 # number of fast writes performed
1278system.iocache.cache_copies 0 # number of cache copies performed
1279system.iocache.writebacks::writebacks 41520 # number of writebacks
1280system.iocache.writebacks::total 41520 # number of writebacks
1281system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
1282system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
1283system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1284system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1285system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses
1286system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses
1287system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses
1288system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses
1289system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles
1290system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles
1291system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles
1292system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles
1293system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles
1294system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles
1295system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles
1296system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles
1297system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1298system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1299system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1300system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1301system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1302system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1303system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1304system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1305system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency
1306system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency
1307system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency
1308system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency
1309system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
1310system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
1311system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency
1312system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency
1313system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1314system.l2c.tags.replacements 342136 # number of replacements
1315system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use
1316system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks.
1317system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks.
1318system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks.
1319system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit.
1320system.l2c.tags.occ_blocks::writebacks 54851.977847 # Average occupied blocks per requestor
1321system.l2c.tags.occ_blocks::cpu0.inst 4799.733629 # Average occupied blocks per requestor
--- 174 unchanged lines hidden (view full) ---
1496system.l2c.overall_avg_miss_latency::cpu1.data 131467.985393 # average overall miss latency
1497system.l2c.overall_avg_miss_latency::total 125267.568349 # average overall miss latency
1498system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1499system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
1500system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
1501system.l2c.blocked::no_targets 0 # number of cycles access was blocked
1502system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1503system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1504system.l2c.fast_writes 0 # number of fast writes performed
1505system.l2c.cache_copies 0 # number of cache copies performed
1506system.l2c.writebacks::writebacks 79408 # number of writebacks
1507system.l2c.writebacks::total 79408 # number of writebacks
1508system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits
1509system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1510system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits
1511system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
1512system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits
1513system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
--- 56 unchanged lines hidden (view full) ---
1570system.l2c.overall_mshr_miss_latency::cpu0.inst 1514765500 # number of overall MSHR miss cycles
1571system.l2c.overall_mshr_miss_latency::cpu0.data 44421592000 # number of overall MSHR miss cycles
1572system.l2c.overall_mshr_miss_latency::cpu1.inst 112494001 # number of overall MSHR miss cycles
1573system.l2c.overall_mshr_miss_latency::cpu1.data 997859001 # number of overall MSHR miss cycles
1574system.l2c.overall_mshr_miss_latency::total 47046710502 # number of overall MSHR miss cycles
1575system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1478327000 # number of ReadReq MSHR uncacheable cycles
1576system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23575500 # number of ReadReq MSHR uncacheable cycles
1577system.l2c.ReadReq_mshr_uncacheable_latency::total 1501902500 # number of ReadReq MSHR uncacheable cycles
1578system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2327774501 # number of WriteReq MSHR uncacheable cycles
1579system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 750967500 # number of WriteReq MSHR uncacheable cycles
1580system.l2c.WriteReq_mshr_uncacheable_latency::total 3078742001 # number of WriteReq MSHR uncacheable cycles
1581system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3806101501 # number of overall MSHR uncacheable cycles
1582system.l2c.overall_mshr_uncacheable_latency::cpu1.data 774543000 # number of overall MSHR uncacheable cycles
1583system.l2c.overall_mshr_uncacheable_latency::total 4580644501 # number of overall MSHR uncacheable cycles
1584system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1585system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1586system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941997 # mshr miss rate for UpgradeReq accesses
1587system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767797 # mshr miss rate for UpgradeReq accesses
1588system.l2c.UpgradeReq_mshr_miss_rate::total 0.867452 # mshr miss rate for UpgradeReq accesses
1589system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.957601 # mshr miss rate for SCUpgradeReq accesses
1590system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974843 # mshr miss rate for SCUpgradeReq accesses
1591system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966163 # mshr miss rate for SCUpgradeReq accesses
--- 39 unchanged lines hidden (view full) ---
1631system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency
1632system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency
1633system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency
1634system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency
1635system.l2c.overall_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency
1636system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency
1637system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency
1638system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency
1639system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215874.478438 # average WriteReq mshr uncacheable latency
1640system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.315412 # average WriteReq mshr uncacheable latency
1641system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217871.488288 # average WriteReq mshr uncacheable latency
1642system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213036.018191 # average overall mshr uncacheable latency
1643system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.840162 # average overall mshr uncacheable latency
1644system.l2c.overall_avg_mshr_uncacheable_latency::total 214731.131680 # average overall mshr uncacheable latency
1645system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1646system.membus.trans_dist::ReadReq 7201 # Transaction distribution
1647system.membus.trans_dist::ReadResp 292681 # Transaction distribution
1648system.membus.trans_dist::WriteReq 14131 # Transaction distribution
1649system.membus.trans_dist::WriteResp 14131 # Transaction distribution
1650system.membus.trans_dist::WritebackDirty 120928 # Transaction distribution
1651system.membus.trans_dist::CleanEvict 262098 # Transaction distribution
1652system.membus.trans_dist::UpgradeReq 16893 # Transaction distribution
1653system.membus.trans_dist::SCUpgradeReq 11783 # Transaction distribution
--- 127 unchanged lines hidden ---