1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.962608 # Number of seconds simulated
4sim_ticks 1962608482500 # Number of ticks simulated
5final_tick 1962608482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1019388 # Simulator instruction rate (inst/s)
8host_op_rate 1019388 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 32859851956 # Simulator tick rate (ticks/s)
10host_mem_usage 375280 # Number of bytes of host memory used
11host_seconds 59.73 # Real time elapsed on the host
12sim_insts 60884587 # Number of instructions simulated
13sim_ops 60884587 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 831936 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24730240 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 435904 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 26030656 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 831936 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7705152 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7705152 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 12999 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 386410 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 6811 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 406729 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 120393 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 120393 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 423893 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 12600700 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 16109 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 222104 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 13263295 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 423893 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 16109 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 440002 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 3925975 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 3925975 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 3925975 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 423893 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 12600700 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 16109 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 222104 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 17189270 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 406729 # Number of read requests accepted
54system.physmem.writeReqs 120393 # Number of write requests accepted
55system.physmem.readBursts 406729 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 120393 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 26023296 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue
59system.physmem.bytesWritten 7703744 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 26030656 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 7705152 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 48492 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 25025 # Per bank write bursts
66system.physmem.perBankRdBursts::1 25421 # Per bank write bursts
67system.physmem.perBankRdBursts::2 25447 # Per bank write bursts
68system.physmem.perBankRdBursts::3 24899 # Per bank write bursts
69system.physmem.perBankRdBursts::4 25181 # Per bank write bursts
70system.physmem.perBankRdBursts::5 25235 # Per bank write bursts
71system.physmem.perBankRdBursts::6 25799 # Per bank write bursts
72system.physmem.perBankRdBursts::7 25539 # Per bank write bursts
73system.physmem.perBankRdBursts::8 25681 # Per bank write bursts
74system.physmem.perBankRdBursts::9 25348 # Per bank write bursts
75system.physmem.perBankRdBursts::10 25259 # Per bank write bursts
76system.physmem.perBankRdBursts::11 25592 # Per bank write bursts
77system.physmem.perBankRdBursts::12 25653 # Per bank write bursts
78system.physmem.perBankRdBursts::13 25554 # Per bank write bursts
79system.physmem.perBankRdBursts::14 25887 # Per bank write bursts
80system.physmem.perBankRdBursts::15 25094 # Per bank write bursts
81system.physmem.perBankWrBursts::0 7701 # Per bank write bursts
82system.physmem.perBankWrBursts::1 7641 # Per bank write bursts
83system.physmem.perBankWrBursts::2 7454 # Per bank write bursts
84system.physmem.perBankWrBursts::3 6926 # Per bank write bursts
85system.physmem.perBankWrBursts::4 7165 # Per bank write bursts
86system.physmem.perBankWrBursts::5 7117 # Per bank write bursts
87system.physmem.perBankWrBursts::6 7626 # Per bank write bursts
88system.physmem.perBankWrBursts::7 7252 # Per bank write bursts
89system.physmem.perBankWrBursts::8 7527 # Per bank write bursts
90system.physmem.perBankWrBursts::9 7238 # Per bank write bursts
91system.physmem.perBankWrBursts::10 7225 # Per bank write bursts
92system.physmem.perBankWrBursts::11 7418 # Per bank write bursts
93system.physmem.perBankWrBursts::12 7843 # Per bank write bursts
94system.physmem.perBankWrBursts::13 8207 # Per bank write bursts
95system.physmem.perBankWrBursts::14 8447 # Per bank write bursts
96system.physmem.perBankWrBursts::15 7584 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
99system.physmem.totGap 1962561950500 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 406729 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 120393 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 406538 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see

--- 29 unchanged lines hidden (view full) ---

153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 2287 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 6208 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 6416 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 6086 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 6462 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 7189 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 7401 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 9728 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 8835 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 7633 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 8346 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 6911 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 6709 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 7011 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 5875 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 5577 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 5574 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 178 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 114 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 206 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 171 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 189 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 144 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 158 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 124 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 127 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 109 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 95 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 67016 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 503.268473 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 299.027850 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 415.161234 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 16754 25.00% 25.00% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 12205 18.21% 43.21% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 5432 8.11% 51.32% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 3034 4.53% 55.84% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 2418 3.61% 59.45% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 1895 2.83% 62.28% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 1494 2.23% 64.51% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 1474 2.20% 66.71% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 22310 33.29% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 67016 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 5361 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 75.845178 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2883.640505 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-8191 5358 99.94% 99.94% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 5361 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 5361 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 22.453087 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 18.909523 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 23.339442 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16-23 4763 88.85% 88.85% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::24-31 210 3.92% 92.76% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::32-39 83 1.55% 94.31% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::40-47 15 0.28% 94.59% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::48-55 3 0.06% 94.65% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::56-63 2 0.04% 94.68% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::64-71 8 0.15% 94.83% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::72-79 9 0.17% 95.00% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::80-87 7 0.13% 95.13% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::88-95 35 0.65% 95.78% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::96-103 171 3.19% 98.97% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::104-111 7 0.13% 99.10% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::112-119 4 0.07% 99.18% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::120-127 1 0.02% 99.20% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::128-135 3 0.06% 99.25% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::136-143 3 0.06% 99.31% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::144-151 1 0.02% 99.33% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::152-159 3 0.06% 99.38% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::168-175 3 0.06% 99.44% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::176-183 4 0.07% 99.52% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::184-191 2 0.04% 99.55% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::192-199 4 0.07% 99.63% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::200-207 1 0.02% 99.65% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::216-223 6 0.11% 99.76% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::224-231 10 0.19% 99.94% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::232-239 1 0.02% 99.96% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::total 5361 # Writes before turning the bus around for reads
265system.physmem.totQLat 2204423500 # Total ticks spent queuing
266system.physmem.totMemAccLat 9828436000 # Total ticks spent from burst creation until serviced by the DRAM
267system.physmem.totBusLat 2033070000 # Total ticks spent in databus transfers
268system.physmem.avgQLat 5421.42 # Average queueing delay per DRAM burst
269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
270system.physmem.avgMemAccLat 24171.42 # Average memory access latency per DRAM burst
271system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s
272system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s
273system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s
274system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s
275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
276system.physmem.busUtil 0.13 # Data bus utilization in percentage
277system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
278system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
279system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
280system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing
281system.physmem.readRowHits 363741 # Number of row buffer hits during reads
282system.physmem.writeRowHits 96228 # Number of row buffer hits during writes
283system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads
284system.physmem.writeRowHitRate 79.93 # Row buffer hit rate for writes
285system.physmem.avgGap 3723164.56 # Average gap between requests
286system.physmem.pageHitRate 87.28 # Row buffer hit rate, read and write combined
287system.physmem_0.actEnergy 249797520 # Energy for activate commands per rank (pJ)
288system.physmem_0.preEnergy 136298250 # Energy for precharge commands per rank (pJ)
289system.physmem_0.readEnergy 1579858800 # Energy for read commands per rank (pJ)
290system.physmem_0.writeEnergy 381555360 # Energy for write commands per rank (pJ)
291system.physmem_0.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ)
292system.physmem_0.actBackEnergy 65826808245 # Energy for active background per rank (pJ)
293system.physmem_0.preBackEnergy 1119818638500 # Energy for precharge background per rank (pJ)
294system.physmem_0.totalEnergy 1316180590275 # Total energy per rank (pJ)
295system.physmem_0.averagePower 670.630269 # Core power per rank (mW)
296system.physmem_0.memoryStateTime::IDLE 1862676833500 # Time in different power states
297system.physmem_0.memoryStateTime::REF 65535600000 # Time in different power states
298system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
299system.physmem_0.memoryStateTime::ACT 34390001500 # Time in different power states
300system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
301system.physmem_1.actEnergy 256843440 # Energy for activate commands per rank (pJ)
302system.physmem_1.preEnergy 140142750 # Energy for precharge commands per rank (pJ)
303system.physmem_1.readEnergy 1591730400 # Energy for read commands per rank (pJ)
304system.physmem_1.writeEnergy 398448720 # Energy for write commands per rank (pJ)
305system.physmem_1.refreshEnergy 128187633600 # Energy for refresh commands per rank (pJ)
306system.physmem_1.actBackEnergy 66351904785 # Energy for active background per rank (pJ)
307system.physmem_1.preBackEnergy 1119358027500 # Energy for precharge background per rank (pJ)
308system.physmem_1.totalEnergy 1316284731195 # Total energy per rank (pJ)
309system.physmem_1.averagePower 670.683332 # Core power per rank (mW)
310system.physmem_1.memoryStateTime::IDLE 1861912025250 # Time in different power states
311system.physmem_1.memoryStateTime::REF 65535600000 # Time in different power states
312system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
313system.physmem_1.memoryStateTime::ACT 35154809750 # Time in different power states
314system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
315system.cpu_clk_domain.clock 500 # Clock period in ticks
316system.cpu0.dtb.fetch_hits 0 # ITB hits
317system.cpu0.dtb.fetch_misses 0 # ITB misses
318system.cpu0.dtb.fetch_acv 0 # ITB acv
319system.cpu0.dtb.fetch_accesses 0 # ITB accesses
320system.cpu0.dtb.read_hits 7500026 # DTB read hits
321system.cpu0.dtb.read_misses 7443 # DTB read misses
322system.cpu0.dtb.read_acv 210 # DTB read access violations
323system.cpu0.dtb.read_accesses 490673 # DTB read accesses
324system.cpu0.dtb.write_hits 5074087 # DTB write hits
325system.cpu0.dtb.write_misses 813 # DTB write misses
326system.cpu0.dtb.write_acv 134 # DTB write access violations
327system.cpu0.dtb.write_accesses 187452 # DTB write accesses
328system.cpu0.dtb.data_hits 12574113 # DTB hits
329system.cpu0.dtb.data_misses 8256 # DTB misses
330system.cpu0.dtb.data_acv 344 # DTB access violations
331system.cpu0.dtb.data_accesses 678125 # DTB accesses
332system.cpu0.itb.fetch_hits 3504450 # ITB hits
333system.cpu0.itb.fetch_misses 3871 # ITB misses
334system.cpu0.itb.fetch_acv 184 # ITB acv
335system.cpu0.itb.fetch_accesses 3508321 # ITB accesses
336system.cpu0.itb.read_hits 0 # DTB read hits
337system.cpu0.itb.read_misses 0 # DTB read misses
338system.cpu0.itb.read_acv 0 # DTB read access violations
339system.cpu0.itb.read_accesses 0 # DTB read accesses
340system.cpu0.itb.write_hits 0 # DTB write hits
341system.cpu0.itb.write_misses 0 # DTB write misses
342system.cpu0.itb.write_acv 0 # DTB write access violations
343system.cpu0.itb.write_accesses 0 # DTB write accesses
344system.cpu0.itb.data_hits 0 # DTB hits
345system.cpu0.itb.data_misses 0 # DTB misses
346system.cpu0.itb.data_acv 0 # DTB access violations
347system.cpu0.itb.data_accesses 0 # DTB accesses
348system.cpu0.numCycles 3923838721 # number of cpu cycles simulated
349system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
350system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
351system.cpu0.committedInsts 47783493 # Number of instructions committed
352system.cpu0.committedOps 47783493 # Number of ops (including micro ops) committed
353system.cpu0.num_int_alu_accesses 44315744 # Number of integer alu accesses
354system.cpu0.num_fp_alu_accesses 211234 # Number of float alu accesses
355system.cpu0.num_func_calls 1203861 # number of times a function call or return occured
356system.cpu0.num_conditional_control_insts 5612503 # number of instructions that are conditional controls
357system.cpu0.num_int_insts 44315744 # number of integer instructions
358system.cpu0.num_fp_insts 211234 # number of float instructions
359system.cpu0.num_int_register_reads 60912860 # number of times the integer registers were read
360system.cpu0.num_int_register_writes 33024751 # number of times the integer registers were written
361system.cpu0.num_fp_register_reads 102598 # number of times the floating registers were read
362system.cpu0.num_fp_register_writes 104462 # number of times the floating registers were written
363system.cpu0.num_mem_refs 12614351 # number of memory refs
364system.cpu0.num_load_insts 7527207 # Number of load instructions
365system.cpu0.num_store_insts 5087144 # Number of store instructions
366system.cpu0.num_idle_cycles 3699336863.028799 # Number of idle cycles
367system.cpu0.num_busy_cycles 224501857.971201 # Number of busy cycles
368system.cpu0.not_idle_fraction 0.057215 # Percentage of non-idle cycles
369system.cpu0.idle_fraction 0.942785 # Percentage of idle cycles
370system.cpu0.Branches 7204257 # Number of branches fetched
371system.cpu0.op_class::No_OpClass 2730537 5.71% 5.71% # Class of executed instruction
372system.cpu0.op_class::IntAlu 31447784 65.80% 71.51% # Class of executed instruction
373system.cpu0.op_class::IntMult 52772 0.11% 71.63% # Class of executed instruction
374system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction
375system.cpu0.op_class::FloatAdd 25731 0.05% 71.68% # Class of executed instruction
376system.cpu0.op_class::FloatCmp 0 0.00% 71.68% # Class of executed instruction
377system.cpu0.op_class::FloatCvt 0 0.00% 71.68% # Class of executed instruction
378system.cpu0.op_class::FloatMult 0 0.00% 71.68% # Class of executed instruction
379system.cpu0.op_class::FloatDiv 1656 0.00% 71.68% # Class of executed instruction
380system.cpu0.op_class::FloatSqrt 0 0.00% 71.68% # Class of executed instruction
381system.cpu0.op_class::SimdAdd 0 0.00% 71.68% # Class of executed instruction
382system.cpu0.op_class::SimdAddAcc 0 0.00% 71.68% # Class of executed instruction
383system.cpu0.op_class::SimdAlu 0 0.00% 71.68% # Class of executed instruction
384system.cpu0.op_class::SimdCmp 0 0.00% 71.68% # Class of executed instruction
385system.cpu0.op_class::SimdCvt 0 0.00% 71.68% # Class of executed instruction
386system.cpu0.op_class::SimdMisc 0 0.00% 71.68% # Class of executed instruction
387system.cpu0.op_class::SimdMult 0 0.00% 71.68% # Class of executed instruction
388system.cpu0.op_class::SimdMultAcc 0 0.00% 71.68% # Class of executed instruction
389system.cpu0.op_class::SimdShift 0 0.00% 71.68% # Class of executed instruction
390system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.68% # Class of executed instruction
391system.cpu0.op_class::SimdSqrt 0 0.00% 71.68% # Class of executed instruction
392system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.68% # Class of executed instruction
393system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.68% # Class of executed instruction
394system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.68% # Class of executed instruction
395system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.68% # Class of executed instruction
396system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.68% # Class of executed instruction
397system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.68% # Class of executed instruction
398system.cpu0.op_class::SimdFloatMult 0 0.00% 71.68% # Class of executed instruction
399system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.68% # Class of executed instruction
400system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.68% # Class of executed instruction
401system.cpu0.op_class::MemRead 7703007 16.12% 87.80% # Class of executed instruction
402system.cpu0.op_class::MemWrite 5093240 10.66% 98.46% # Class of executed instruction
403system.cpu0.op_class::IprAccess 737366 1.54% 100.00% # Class of executed instruction
404system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
405system.cpu0.op_class::total 47792093 # Class of executed instruction
406system.cpu0.kern.inst.arm 0 # number of arm instructions executed
407system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed
408system.cpu0.kern.inst.hwrei 165261 # number of hwrei instructions executed
409system.cpu0.kern.ipl_count::0 56971 40.19% 40.19% # number of times we switched to this ipl
410system.cpu0.kern.ipl_count::21 131 0.09% 40.29% # number of times we switched to this ipl
411system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl
412system.cpu0.kern.ipl_count::30 419 0.30% 41.97% # number of times we switched to this ipl
413system.cpu0.kern.ipl_count::31 82246 58.03% 100.00% # number of times we switched to this ipl
414system.cpu0.kern.ipl_count::total 141740 # number of times we switched to this ipl
415system.cpu0.kern.ipl_good::0 56429 49.08% 49.08% # number of times we switched to this ipl from a different ipl
416system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
417system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
418system.cpu0.kern.ipl_good::30 419 0.36% 51.28% # number of times we switched to this ipl from a different ipl
419system.cpu0.kern.ipl_good::31 56010 48.72% 100.00% # number of times we switched to this ipl from a different ipl
420system.cpu0.kern.ipl_good::total 114962 # number of times we switched to this ipl from a different ipl
421system.cpu0.kern.ipl_ticks::0 1900835958000 96.89% 96.89% # number of cycles we spent at this ipl
422system.cpu0.kern.ipl_ticks::21 91198500 0.00% 96.89% # number of cycles we spent at this ipl
423system.cpu0.kern.ipl_ticks::22 757506500 0.04% 96.93% # number of cycles we spent at this ipl
424system.cpu0.kern.ipl_ticks::30 303704500 0.02% 96.95% # number of cycles we spent at this ipl
425system.cpu0.kern.ipl_ticks::31 59930963000 3.05% 100.00% # number of cycles we spent at this ipl
426system.cpu0.kern.ipl_ticks::total 1961919330500 # number of cycles we spent at this ipl
427system.cpu0.kern.ipl_used::0 0.990486 # fraction of swpipl calls that actually changed the ipl
428system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
429system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
430system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
431system.cpu0.kern.ipl_used::31 0.681006 # fraction of swpipl calls that actually changed the ipl
432system.cpu0.kern.ipl_used::total 0.811077 # fraction of swpipl calls that actually changed the ipl
433system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
434system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
435system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
436system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
437system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
438system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
439system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
440system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed

--- 15 unchanged lines hidden (view full) ---

456system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
457system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
458system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
459system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
460system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
461system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
462system.cpu0.kern.syscall::total 222 # number of syscalls executed
463system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
464system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed
465system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed
466system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
467system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
468system.cpu0.kern.callpal::swpctx 3072 2.05% 2.38% # number of callpals executed
469system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
470system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed
471system.cpu0.kern.callpal::swpipl 134879 89.87% 92.29% # number of callpals executed
472system.cpu0.kern.callpal::rdps 6699 4.46% 96.76% # number of callpals executed
473system.cpu0.kern.callpal::wrkgp 1 0.00% 96.76% # number of callpals executed
474system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed
475system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
476system.cpu0.kern.callpal::whami 2 0.00% 96.77% # number of callpals executed
477system.cpu0.kern.callpal::rti 4337 2.89% 99.66% # number of callpals executed
478system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
479system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
480system.cpu0.kern.callpal::total 150081 # number of callpals executed
481system.cpu0.kern.mode_switch::kernel 6891 # number of protection mode switches
482system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches
483system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
484system.cpu0.kern.mode_good::kernel 1282
485system.cpu0.kern.mode_good::user 1282
486system.cpu0.kern.mode_good::idle 0
487system.cpu0.kern.mode_switch_good::kernel 0.186040 # fraction of useful protection mode switches
488system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
489system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
490system.cpu0.kern.mode_switch_good::total 0.313716 # fraction of useful protection mode switches
491system.cpu0.kern.mode_ticks::kernel 1958152340000 99.82% 99.82% # number of ticks spent at the given mode
492system.cpu0.kern.mode_ticks::user 3531530500 0.18% 100.00% # number of ticks spent at the given mode
493system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
494system.cpu0.kern.swap_context 3073 # number of times the context was actually changed
495system.cpu0.dcache.tags.replacements 1181794 # number of replacements
496system.cpu0.dcache.tags.tagsinuse 505.240594 # Cycle average of tags in use
497system.cpu0.dcache.tags.total_refs 11382177 # Total number of references to valid blocks.
498system.cpu0.dcache.tags.sampled_refs 1182212 # Sample count of references to valid blocks.
499system.cpu0.dcache.tags.avg_refs 9.627865 # Average number of references to valid blocks.
500system.cpu0.dcache.tags.warmup_cycle 112405500 # Cycle when the warmup percentage was hit.
501system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.240594 # Average occupied blocks per requestor
502system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986798 # Average percentage of cache occupancy
503system.cpu0.dcache.tags.occ_percent::total 0.986798 # Average percentage of cache occupancy
504system.cpu0.dcache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
505system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id
506system.cpu0.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id
507system.cpu0.dcache.tags.occ_task_id_percent::1024 0.816406 # Percentage of cache occupancy per task id
508system.cpu0.dcache.tags.tag_accesses 51530574 # Number of tag accesses
509system.cpu0.dcache.tags.data_accesses 51530574 # Number of data accesses
510system.cpu0.dcache.ReadReq_hits::cpu0.data 6418852 # number of ReadReq hits
511system.cpu0.dcache.ReadReq_hits::total 6418852 # number of ReadReq hits
512system.cpu0.dcache.WriteReq_hits::cpu0.data 4665452 # number of WriteReq hits
513system.cpu0.dcache.WriteReq_hits::total 4665452 # number of WriteReq hits
514system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140662 # number of LoadLockedReq hits
515system.cpu0.dcache.LoadLockedReq_hits::total 140662 # number of LoadLockedReq hits
516system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148383 # number of StoreCondReq hits
517system.cpu0.dcache.StoreCondReq_hits::total 148383 # number of StoreCondReq hits
518system.cpu0.dcache.demand_hits::cpu0.data 11084304 # number of demand (read+write) hits
519system.cpu0.dcache.demand_hits::total 11084304 # number of demand (read+write) hits
520system.cpu0.dcache.overall_hits::cpu0.data 11084304 # number of overall hits
521system.cpu0.dcache.overall_hits::total 11084304 # number of overall hits
522system.cpu0.dcache.ReadReq_misses::cpu0.data 939259 # number of ReadReq misses
523system.cpu0.dcache.ReadReq_misses::total 939259 # number of ReadReq misses
524system.cpu0.dcache.WriteReq_misses::cpu0.data 251797 # number of WriteReq misses
525system.cpu0.dcache.WriteReq_misses::total 251797 # number of WriteReq misses
526system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13671 # number of LoadLockedReq misses
527system.cpu0.dcache.LoadLockedReq_misses::total 13671 # number of LoadLockedReq misses
528system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5399 # number of StoreCondReq misses
529system.cpu0.dcache.StoreCondReq_misses::total 5399 # number of StoreCondReq misses
530system.cpu0.dcache.demand_misses::cpu0.data 1191056 # number of demand (read+write) misses
531system.cpu0.dcache.demand_misses::total 1191056 # number of demand (read+write) misses
532system.cpu0.dcache.overall_misses::cpu0.data 1191056 # number of overall misses
533system.cpu0.dcache.overall_misses::total 1191056 # number of overall misses
534system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 28901225000 # number of ReadReq miss cycles
535system.cpu0.dcache.ReadReq_miss_latency::total 28901225000 # number of ReadReq miss cycles
536system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10875412500 # number of WriteReq miss cycles
537system.cpu0.dcache.WriteReq_miss_latency::total 10875412500 # number of WriteReq miss cycles
538system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles
539system.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles
540system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47710000 # number of StoreCondReq miss cycles
541system.cpu0.dcache.StoreCondReq_miss_latency::total 47710000 # number of StoreCondReq miss cycles
542system.cpu0.dcache.demand_miss_latency::cpu0.data 39776637500 # number of demand (read+write) miss cycles
543system.cpu0.dcache.demand_miss_latency::total 39776637500 # number of demand (read+write) miss cycles
544system.cpu0.dcache.overall_miss_latency::cpu0.data 39776637500 # number of overall miss cycles
545system.cpu0.dcache.overall_miss_latency::total 39776637500 # number of overall miss cycles
546system.cpu0.dcache.ReadReq_accesses::cpu0.data 7358111 # number of ReadReq accesses(hits+misses)
547system.cpu0.dcache.ReadReq_accesses::total 7358111 # number of ReadReq accesses(hits+misses)
548system.cpu0.dcache.WriteReq_accesses::cpu0.data 4917249 # number of WriteReq accesses(hits+misses)
549system.cpu0.dcache.WriteReq_accesses::total 4917249 # number of WriteReq accesses(hits+misses)
550system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154333 # number of LoadLockedReq accesses(hits+misses)
551system.cpu0.dcache.LoadLockedReq_accesses::total 154333 # number of LoadLockedReq accesses(hits+misses)
552system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153782 # number of StoreCondReq accesses(hits+misses)
553system.cpu0.dcache.StoreCondReq_accesses::total 153782 # number of StoreCondReq accesses(hits+misses)
554system.cpu0.dcache.demand_accesses::cpu0.data 12275360 # number of demand (read+write) accesses
555system.cpu0.dcache.demand_accesses::total 12275360 # number of demand (read+write) accesses
556system.cpu0.dcache.overall_accesses::cpu0.data 12275360 # number of overall (read+write) accesses
557system.cpu0.dcache.overall_accesses::total 12275360 # number of overall (read+write) accesses
558system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127649 # miss rate for ReadReq accesses
559system.cpu0.dcache.ReadReq_miss_rate::total 0.127649 # miss rate for ReadReq accesses
560system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051207 # miss rate for WriteReq accesses
561system.cpu0.dcache.WriteReq_miss_rate::total 0.051207 # miss rate for WriteReq accesses
562system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088581 # miss rate for LoadLockedReq accesses
563system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088581 # miss rate for LoadLockedReq accesses
564system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035108 # miss rate for StoreCondReq accesses
565system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035108 # miss rate for StoreCondReq accesses
566system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097028 # miss rate for demand accesses
567system.cpu0.dcache.demand_miss_rate::total 0.097028 # miss rate for demand accesses
568system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097028 # miss rate for overall accesses
569system.cpu0.dcache.overall_miss_rate::total 0.097028 # miss rate for overall accesses
570system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30770.240157 # average ReadReq miss latency
571system.cpu0.dcache.ReadReq_avg_miss_latency::total 30770.240157 # average ReadReq miss latency
572system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43191.191714 # average WriteReq miss latency
573system.cpu0.dcache.WriteReq_avg_miss_latency::total 43191.191714 # average WriteReq miss latency
574system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10999.049082 # average LoadLockedReq miss latency
575system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10999.049082 # average LoadLockedReq miss latency
576system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8836.821634 # average StoreCondReq miss latency
577system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8836.821634 # average StoreCondReq miss latency
578system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency
579system.cpu0.dcache.demand_avg_miss_latency::total 33396.110258 # average overall miss latency
580system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33396.110258 # average overall miss latency
581system.cpu0.dcache.overall_avg_miss_latency::total 33396.110258 # average overall miss latency
582system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
583system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
584system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
585system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
586system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
587system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
588system.cpu0.dcache.fast_writes 0 # number of fast writes performed
589system.cpu0.dcache.cache_copies 0 # number of cache copies performed
590system.cpu0.dcache.writebacks::writebacks 679941 # number of writebacks
591system.cpu0.dcache.writebacks::total 679941 # number of writebacks
592system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939259 # number of ReadReq MSHR misses
593system.cpu0.dcache.ReadReq_mshr_misses::total 939259 # number of ReadReq MSHR misses
594system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251797 # number of WriteReq MSHR misses
595system.cpu0.dcache.WriteReq_mshr_misses::total 251797 # number of WriteReq MSHR misses
596system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13671 # number of LoadLockedReq MSHR misses
597system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13671 # number of LoadLockedReq MSHR misses
598system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5399 # number of StoreCondReq MSHR misses
599system.cpu0.dcache.StoreCondReq_mshr_misses::total 5399 # number of StoreCondReq MSHR misses
600system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191056 # number of demand (read+write) MSHR misses
601system.cpu0.dcache.demand_mshr_misses::total 1191056 # number of demand (read+write) MSHR misses
602system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191056 # number of overall MSHR misses
603system.cpu0.dcache.overall_mshr_misses::total 1191056 # number of overall MSHR misses
604system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
605system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable
606system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10829 # number of WriteReq MSHR uncacheable
607system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10829 # number of WriteReq MSHR uncacheable
608system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17939 # number of overall MSHR uncacheable misses
609system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17939 # number of overall MSHR uncacheable misses
610system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27961966000 # number of ReadReq MSHR miss cycles
611system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27961966000 # number of ReadReq MSHR miss cycles
612system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10623615500 # number of WriteReq MSHR miss cycles
613system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10623615500 # number of WriteReq MSHR miss cycles
614system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136697000 # number of LoadLockedReq MSHR miss cycles
615system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136697000 # number of LoadLockedReq MSHR miss cycles
616system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42311000 # number of StoreCondReq MSHR miss cycles
617system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42311000 # number of StoreCondReq MSHR miss cycles
618system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38585581500 # number of demand (read+write) MSHR miss cycles
619system.cpu0.dcache.demand_mshr_miss_latency::total 38585581500 # number of demand (read+write) MSHR miss cycles
620system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38585581500 # number of overall MSHR miss cycles
621system.cpu0.dcache.overall_mshr_miss_latency::total 38585581500 # number of overall MSHR miss cycles
622system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1492228000 # number of ReadReq MSHR uncacheable cycles
623system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1492228000 # number of ReadReq MSHR uncacheable cycles
624system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2319869500 # number of WriteReq MSHR uncacheable cycles
625system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2319869500 # number of WriteReq MSHR uncacheable cycles
626system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3812097500 # number of overall MSHR uncacheable cycles
627system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3812097500 # number of overall MSHR uncacheable cycles
628system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127649 # mshr miss rate for ReadReq accesses
629system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127649 # mshr miss rate for ReadReq accesses
630system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051207 # mshr miss rate for WriteReq accesses
631system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051207 # mshr miss rate for WriteReq accesses
632system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088581 # mshr miss rate for LoadLockedReq accesses
633system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088581 # mshr miss rate for LoadLockedReq accesses
634system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035108 # mshr miss rate for StoreCondReq accesses
635system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035108 # mshr miss rate for StoreCondReq accesses
636system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for demand accesses
637system.cpu0.dcache.demand_mshr_miss_rate::total 0.097028 # mshr miss rate for demand accesses
638system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097028 # mshr miss rate for overall accesses
639system.cpu0.dcache.overall_mshr_miss_rate::total 0.097028 # mshr miss rate for overall accesses
640system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29770.240157 # average ReadReq mshr miss latency
641system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29770.240157 # average ReadReq mshr miss latency
642system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42191.191714 # average WriteReq mshr miss latency
643system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42191.191714 # average WriteReq mshr miss latency
644system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9999.049082 # average LoadLockedReq mshr miss latency
645system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9999.049082 # average LoadLockedReq mshr miss latency
646system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7836.821634 # average StoreCondReq mshr miss latency
647system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7836.821634 # average StoreCondReq mshr miss latency
648system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency
649system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency
650system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32396.110258 # average overall mshr miss latency
651system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32396.110258 # average overall mshr miss latency
652system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209877.355837 # average ReadReq mshr uncacheable latency
653system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209877.355837 # average ReadReq mshr uncacheable latency
654system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 214227.490996 # average WriteReq mshr uncacheable latency
655system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 214227.490996 # average WriteReq mshr uncacheable latency
656system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 212503.344668 # average overall mshr uncacheable latency
657system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 212503.344668 # average overall mshr uncacheable latency
658system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
659system.cpu0.icache.tags.replacements 700401 # number of replacements
660system.cpu0.icache.tags.tagsinuse 508.179347 # Cycle average of tags in use
661system.cpu0.icache.tags.total_refs 47091062 # Total number of references to valid blocks.
662system.cpu0.icache.tags.sampled_refs 700913 # Sample count of references to valid blocks.
663system.cpu0.icache.tags.avg_refs 67.185317 # Average number of references to valid blocks.
664system.cpu0.icache.tags.warmup_cycle 42246954500 # Cycle when the warmup percentage was hit.
665system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.179347 # Average occupied blocks per requestor
666system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992538 # Average percentage of cache occupancy
667system.cpu0.icache.tags.occ_percent::total 0.992538 # Average percentage of cache occupancy
668system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
669system.cpu0.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id
670system.cpu0.icache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id
671system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
672system.cpu0.icache.tags.tag_accesses 48493124 # Number of tag accesses
673system.cpu0.icache.tags.data_accesses 48493124 # Number of data accesses
674system.cpu0.icache.ReadReq_hits::cpu0.inst 47091062 # number of ReadReq hits
675system.cpu0.icache.ReadReq_hits::total 47091062 # number of ReadReq hits
676system.cpu0.icache.demand_hits::cpu0.inst 47091062 # number of demand (read+write) hits
677system.cpu0.icache.demand_hits::total 47091062 # number of demand (read+write) hits
678system.cpu0.icache.overall_hits::cpu0.inst 47091062 # number of overall hits
679system.cpu0.icache.overall_hits::total 47091062 # number of overall hits
680system.cpu0.icache.ReadReq_misses::cpu0.inst 701031 # number of ReadReq misses
681system.cpu0.icache.ReadReq_misses::total 701031 # number of ReadReq misses
682system.cpu0.icache.demand_misses::cpu0.inst 701031 # number of demand (read+write) misses
683system.cpu0.icache.demand_misses::total 701031 # number of demand (read+write) misses
684system.cpu0.icache.overall_misses::cpu0.inst 701031 # number of overall misses
685system.cpu0.icache.overall_misses::total 701031 # number of overall misses
686system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017639000 # number of ReadReq miss cycles
687system.cpu0.icache.ReadReq_miss_latency::total 10017639000 # number of ReadReq miss cycles
688system.cpu0.icache.demand_miss_latency::cpu0.inst 10017639000 # number of demand (read+write) miss cycles
689system.cpu0.icache.demand_miss_latency::total 10017639000 # number of demand (read+write) miss cycles
690system.cpu0.icache.overall_miss_latency::cpu0.inst 10017639000 # number of overall miss cycles
691system.cpu0.icache.overall_miss_latency::total 10017639000 # number of overall miss cycles
692system.cpu0.icache.ReadReq_accesses::cpu0.inst 47792093 # number of ReadReq accesses(hits+misses)
693system.cpu0.icache.ReadReq_accesses::total 47792093 # number of ReadReq accesses(hits+misses)
694system.cpu0.icache.demand_accesses::cpu0.inst 47792093 # number of demand (read+write) accesses
695system.cpu0.icache.demand_accesses::total 47792093 # number of demand (read+write) accesses
696system.cpu0.icache.overall_accesses::cpu0.inst 47792093 # number of overall (read+write) accesses
697system.cpu0.icache.overall_accesses::total 47792093 # number of overall (read+write) accesses
698system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014668 # miss rate for ReadReq accesses
699system.cpu0.icache.ReadReq_miss_rate::total 0.014668 # miss rate for ReadReq accesses
700system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014668 # miss rate for demand accesses
701system.cpu0.icache.demand_miss_rate::total 0.014668 # miss rate for demand accesses
702system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014668 # miss rate for overall accesses
703system.cpu0.icache.overall_miss_rate::total 0.014668 # miss rate for overall accesses
704system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14289.865926 # average ReadReq miss latency
705system.cpu0.icache.ReadReq_avg_miss_latency::total 14289.865926 # average ReadReq miss latency
706system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency
707system.cpu0.icache.demand_avg_miss_latency::total 14289.865926 # average overall miss latency
708system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14289.865926 # average overall miss latency
709system.cpu0.icache.overall_avg_miss_latency::total 14289.865926 # average overall miss latency
710system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
711system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
712system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
713system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
714system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
715system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
716system.cpu0.icache.fast_writes 0 # number of fast writes performed
717system.cpu0.icache.cache_copies 0 # number of cache copies performed
718system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 701031 # number of ReadReq MSHR misses
719system.cpu0.icache.ReadReq_mshr_misses::total 701031 # number of ReadReq MSHR misses
720system.cpu0.icache.demand_mshr_misses::cpu0.inst 701031 # number of demand (read+write) MSHR misses
721system.cpu0.icache.demand_mshr_misses::total 701031 # number of demand (read+write) MSHR misses
722system.cpu0.icache.overall_mshr_misses::cpu0.inst 701031 # number of overall MSHR misses
723system.cpu0.icache.overall_mshr_misses::total 701031 # number of overall MSHR misses
724system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9316608000 # number of ReadReq MSHR miss cycles
725system.cpu0.icache.ReadReq_mshr_miss_latency::total 9316608000 # number of ReadReq MSHR miss cycles
726system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9316608000 # number of demand (read+write) MSHR miss cycles
727system.cpu0.icache.demand_mshr_miss_latency::total 9316608000 # number of demand (read+write) MSHR miss cycles
728system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9316608000 # number of overall MSHR miss cycles
729system.cpu0.icache.overall_mshr_miss_latency::total 9316608000 # number of overall MSHR miss cycles
730system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for ReadReq accesses
731system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014668 # mshr miss rate for ReadReq accesses
732system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for demand accesses
733system.cpu0.icache.demand_mshr_miss_rate::total 0.014668 # mshr miss rate for demand accesses
734system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014668 # mshr miss rate for overall accesses
735system.cpu0.icache.overall_mshr_miss_rate::total 0.014668 # mshr miss rate for overall accesses
736system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average ReadReq mshr miss latency
737system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13289.865926 # average ReadReq mshr miss latency
738system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency
739system.cpu0.icache.demand_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency
740system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13289.865926 # average overall mshr miss latency
741system.cpu0.icache.overall_avg_mshr_miss_latency::total 13289.865926 # average overall mshr miss latency
742system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
743system.cpu1.dtb.fetch_hits 0 # ITB hits
744system.cpu1.dtb.fetch_misses 0 # ITB misses
745system.cpu1.dtb.fetch_acv 0 # ITB acv
746system.cpu1.dtb.fetch_accesses 0 # ITB accesses
747system.cpu1.dtb.read_hits 2409623 # DTB read hits
748system.cpu1.dtb.read_misses 2992 # DTB read misses
749system.cpu1.dtb.read_acv 0 # DTB read access violations
750system.cpu1.dtb.read_accesses 239363 # DTB read accesses
751system.cpu1.dtb.write_hits 1749165 # DTB write hits
752system.cpu1.dtb.write_misses 341 # DTB write misses
753system.cpu1.dtb.write_acv 29 # DTB write access violations
754system.cpu1.dtb.write_accesses 105247 # DTB write accesses
755system.cpu1.dtb.data_hits 4158788 # DTB hits
756system.cpu1.dtb.data_misses 3333 # DTB misses
757system.cpu1.dtb.data_acv 29 # DTB access violations
758system.cpu1.dtb.data_accesses 344610 # DTB accesses
759system.cpu1.itb.fetch_hits 1960477 # ITB hits
760system.cpu1.itb.fetch_misses 1216 # ITB misses
761system.cpu1.itb.fetch_acv 0 # ITB acv
762system.cpu1.itb.fetch_accesses 1961693 # ITB accesses
763system.cpu1.itb.read_hits 0 # DTB read hits
764system.cpu1.itb.read_misses 0 # DTB read misses
765system.cpu1.itb.read_acv 0 # DTB read access violations
766system.cpu1.itb.read_accesses 0 # DTB read accesses
767system.cpu1.itb.write_hits 0 # DTB write hits
768system.cpu1.itb.write_misses 0 # DTB write misses
769system.cpu1.itb.write_acv 0 # DTB write access violations
770system.cpu1.itb.write_accesses 0 # DTB write accesses
771system.cpu1.itb.data_hits 0 # DTB hits
772system.cpu1.itb.data_misses 0 # DTB misses
773system.cpu1.itb.data_acv 0 # DTB access violations
774system.cpu1.itb.data_accesses 0 # DTB accesses
775system.cpu1.numCycles 3925216965 # number of cpu cycles simulated
776system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
777system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
778system.cpu1.committedInsts 13101094 # Number of instructions committed
779system.cpu1.committedOps 13101094 # Number of ops (including micro ops) committed
780system.cpu1.num_int_alu_accesses 12083765 # Number of integer alu accesses
781system.cpu1.num_fp_alu_accesses 172106 # Number of float alu accesses
782system.cpu1.num_func_calls 409417 # number of times a function call or return occured
783system.cpu1.num_conditional_control_insts 1299945 # number of instructions that are conditional controls
784system.cpu1.num_int_insts 12083765 # number of integer instructions
785system.cpu1.num_fp_insts 172106 # number of float instructions
786system.cpu1.num_int_register_reads 16637487 # number of times the integer registers were read
787system.cpu1.num_int_register_writes 8868500 # number of times the integer registers were written
788system.cpu1.num_fp_register_reads 90075 # number of times the floating registers were read
789system.cpu1.num_fp_register_writes 91936 # number of times the floating registers were written
790system.cpu1.num_mem_refs 4182249 # number of memory refs
791system.cpu1.num_load_insts 2423870 # Number of load instructions
792system.cpu1.num_store_insts 1758379 # Number of store instructions
793system.cpu1.num_idle_cycles 3876316507.998025 # Number of idle cycles
794system.cpu1.num_busy_cycles 48900457.001975 # Number of busy cycles
795system.cpu1.not_idle_fraction 0.012458 # Percentage of non-idle cycles
796system.cpu1.idle_fraction 0.987542 # Percentage of idle cycles
797system.cpu1.Branches 1864071 # Number of branches fetched
798system.cpu1.op_class::No_OpClass 700818 5.35% 5.35% # Class of executed instruction
799system.cpu1.op_class::IntAlu 7749061 59.13% 64.48% # Class of executed instruction
800system.cpu1.op_class::IntMult 21359 0.16% 64.64% # Class of executed instruction
801system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction
802system.cpu1.op_class::FloatAdd 14141 0.11% 64.75% # Class of executed instruction
803system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction
804system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction
805system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction
806system.cpu1.op_class::FloatDiv 1986 0.02% 64.77% # Class of executed instruction
807system.cpu1.op_class::FloatSqrt 0 0.00% 64.77% # Class of executed instruction
808system.cpu1.op_class::SimdAdd 0 0.00% 64.77% # Class of executed instruction
809system.cpu1.op_class::SimdAddAcc 0 0.00% 64.77% # Class of executed instruction
810system.cpu1.op_class::SimdAlu 0 0.00% 64.77% # Class of executed instruction
811system.cpu1.op_class::SimdCmp 0 0.00% 64.77% # Class of executed instruction
812system.cpu1.op_class::SimdCvt 0 0.00% 64.77% # Class of executed instruction
813system.cpu1.op_class::SimdMisc 0 0.00% 64.77% # Class of executed instruction
814system.cpu1.op_class::SimdMult 0 0.00% 64.77% # Class of executed instruction
815system.cpu1.op_class::SimdMultAcc 0 0.00% 64.77% # Class of executed instruction
816system.cpu1.op_class::SimdShift 0 0.00% 64.77% # Class of executed instruction
817system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.77% # Class of executed instruction
818system.cpu1.op_class::SimdSqrt 0 0.00% 64.77% # Class of executed instruction
819system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.77% # Class of executed instruction
820system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.77% # Class of executed instruction
821system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.77% # Class of executed instruction
822system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.77% # Class of executed instruction
823system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.77% # Class of executed instruction
824system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.77% # Class of executed instruction
825system.cpu1.op_class::SimdFloatMult 0 0.00% 64.77% # Class of executed instruction
826system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.77% # Class of executed instruction
827system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.77% # Class of executed instruction
828system.cpu1.op_class::MemRead 2495218 19.04% 83.81% # Class of executed instruction
829system.cpu1.op_class::MemWrite 1759360 13.43% 97.23% # Class of executed instruction
830system.cpu1.op_class::IprAccess 362513 2.77% 100.00% # Class of executed instruction
831system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
832system.cpu1.op_class::total 13104456 # Class of executed instruction
833system.cpu1.kern.inst.arm 0 # number of arm instructions executed
834system.cpu1.kern.inst.quiesce 2738 # number of quiesce instructions executed
835system.cpu1.kern.inst.hwrei 78185 # number of hwrei instructions executed
836system.cpu1.kern.ipl_count::0 26382 38.32% 38.32% # number of times we switched to this ipl
837system.cpu1.kern.ipl_count::22 1969 2.86% 41.18% # number of times we switched to this ipl
838system.cpu1.kern.ipl_count::30 500 0.73% 41.90% # number of times we switched to this ipl
839system.cpu1.kern.ipl_count::31 40003 58.10% 100.00% # number of times we switched to this ipl
840system.cpu1.kern.ipl_count::total 68854 # number of times we switched to this ipl
841system.cpu1.kern.ipl_good::0 25547 48.14% 48.14% # number of times we switched to this ipl from a different ipl
842system.cpu1.kern.ipl_good::22 1969 3.71% 51.85% # number of times we switched to this ipl from a different ipl
843system.cpu1.kern.ipl_good::30 500 0.94% 52.80% # number of times we switched to this ipl from a different ipl
844system.cpu1.kern.ipl_good::31 25048 47.20% 100.00% # number of times we switched to this ipl from a different ipl
845system.cpu1.kern.ipl_good::total 53064 # number of times we switched to this ipl from a different ipl
846system.cpu1.kern.ipl_ticks::0 1909718189500 97.31% 97.31% # number of cycles we spent at this ipl
847system.cpu1.kern.ipl_ticks::22 702775500 0.04% 97.34% # number of cycles we spent at this ipl
848system.cpu1.kern.ipl_ticks::30 343141500 0.02% 97.36% # number of cycles we spent at this ipl
849system.cpu1.kern.ipl_ticks::31 51843654000 2.64% 100.00% # number of cycles we spent at this ipl
850system.cpu1.kern.ipl_ticks::total 1962607760500 # number of cycles we spent at this ipl
851system.cpu1.kern.ipl_used::0 0.968350 # fraction of swpipl calls that actually changed the ipl
852system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
853system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
854system.cpu1.kern.ipl_used::31 0.626153 # fraction of swpipl calls that actually changed the ipl
855system.cpu1.kern.ipl_used::total 0.770674 # fraction of swpipl calls that actually changed the ipl
856system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
857system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
858system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
859system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
860system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
861system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
862system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
863system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
864system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
865system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
866system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
867system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
868system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
869system.cpu1.kern.syscall::total 104 # number of syscalls executed
870system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
871system.cpu1.kern.callpal::wripir 419 0.59% 0.59% # number of callpals executed
872system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed
873system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed
874system.cpu1.kern.callpal::swpctx 1985 2.79% 3.38% # number of callpals executed
875system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed
876system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed
877system.cpu1.kern.callpal::swpipl 62619 88.03% 91.42% # number of callpals executed
878system.cpu1.kern.callpal::rdps 2146 3.02% 94.44% # number of callpals executed
879system.cpu1.kern.callpal::wrkgp 1 0.00% 94.44% # number of callpals executed
880system.cpu1.kern.callpal::wrusp 4 0.01% 94.45% # number of callpals executed
881system.cpu1.kern.callpal::whami 3 0.00% 94.45% # number of callpals executed
882system.cpu1.kern.callpal::rti 3766 5.29% 99.75% # number of callpals executed
883system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed
884system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed
885system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
886system.cpu1.kern.callpal::total 71137 # number of callpals executed
887system.cpu1.kern.mode_switch::kernel 2053 # number of protection mode switches
888system.cpu1.kern.mode_switch::user 465 # number of protection mode switches
889system.cpu1.kern.mode_switch::idle 2874 # number of protection mode switches
890system.cpu1.kern.mode_good::kernel 889
891system.cpu1.kern.mode_good::user 465
892system.cpu1.kern.mode_good::idle 424
893system.cpu1.kern.mode_switch_good::kernel 0.433025 # fraction of useful protection mode switches
894system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
895system.cpu1.kern.mode_switch_good::idle 0.147530 # fraction of useful protection mode switches
896system.cpu1.kern.mode_switch_good::total 0.329748 # fraction of useful protection mode switches
897system.cpu1.kern.mode_ticks::kernel 17552018500 0.89% 0.89% # number of ticks spent at the given mode
898system.cpu1.kern.mode_ticks::user 1707542500 0.09% 0.98% # number of ticks spent at the given mode
899system.cpu1.kern.mode_ticks::idle 1943348197500 99.02% 100.00% # number of ticks spent at the given mode
900system.cpu1.kern.swap_context 1986 # number of times the context was actually changed
901system.cpu1.dcache.tags.replacements 165381 # number of replacements
902system.cpu1.dcache.tags.tagsinuse 485.645767 # Cycle average of tags in use
903system.cpu1.dcache.tags.total_refs 3991235 # Total number of references to valid blocks.
904system.cpu1.dcache.tags.sampled_refs 165893 # Sample count of references to valid blocks.
905system.cpu1.dcache.tags.avg_refs 24.059092 # Average number of references to valid blocks.
906system.cpu1.dcache.tags.warmup_cycle 1050804836500 # Cycle when the warmup percentage was hit.
907system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.645767 # Average occupied blocks per requestor
908system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948527 # Average percentage of cache occupancy
909system.cpu1.dcache.tags.occ_percent::total 0.948527 # Average percentage of cache occupancy
910system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
911system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id
912system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
913system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id
914system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
915system.cpu1.dcache.tags.tag_accesses 16867850 # Number of tag accesses
916system.cpu1.dcache.tags.data_accesses 16867850 # Number of data accesses
917system.cpu1.dcache.ReadReq_hits::cpu1.data 2245744 # number of ReadReq hits
918system.cpu1.dcache.ReadReq_hits::total 2245744 # number of ReadReq hits
919system.cpu1.dcache.WriteReq_hits::cpu1.data 1632527 # number of WriteReq hits
920system.cpu1.dcache.WriteReq_hits::total 1632527 # number of WriteReq hits
921system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48591 # number of LoadLockedReq hits
922system.cpu1.dcache.LoadLockedReq_hits::total 48591 # number of LoadLockedReq hits
923system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50409 # number of StoreCondReq hits
924system.cpu1.dcache.StoreCondReq_hits::total 50409 # number of StoreCondReq hits
925system.cpu1.dcache.demand_hits::cpu1.data 3878271 # number of demand (read+write) hits
926system.cpu1.dcache.demand_hits::total 3878271 # number of demand (read+write) hits
927system.cpu1.dcache.overall_hits::cpu1.data 3878271 # number of overall hits
928system.cpu1.dcache.overall_hits::total 3878271 # number of overall hits
929system.cpu1.dcache.ReadReq_misses::cpu1.data 117597 # number of ReadReq misses
930system.cpu1.dcache.ReadReq_misses::total 117597 # number of ReadReq misses
931system.cpu1.dcache.WriteReq_misses::cpu1.data 62279 # number of WriteReq misses
932system.cpu1.dcache.WriteReq_misses::total 62279 # number of WriteReq misses
933system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8857 # number of LoadLockedReq misses
934system.cpu1.dcache.LoadLockedReq_misses::total 8857 # number of LoadLockedReq misses
935system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5813 # number of StoreCondReq misses
936system.cpu1.dcache.StoreCondReq_misses::total 5813 # number of StoreCondReq misses
937system.cpu1.dcache.demand_misses::cpu1.data 179876 # number of demand (read+write) misses
938system.cpu1.dcache.demand_misses::total 179876 # number of demand (read+write) misses
939system.cpu1.dcache.overall_misses::cpu1.data 179876 # number of overall misses
940system.cpu1.dcache.overall_misses::total 179876 # number of overall misses
941system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1425631000 # number of ReadReq miss cycles
942system.cpu1.dcache.ReadReq_miss_latency::total 1425631000 # number of ReadReq miss cycles
943system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1255840500 # number of WriteReq miss cycles
944system.cpu1.dcache.WriteReq_miss_latency::total 1255840500 # number of WriteReq miss cycles
945system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80743500 # number of LoadLockedReq miss cycles
946system.cpu1.dcache.LoadLockedReq_miss_latency::total 80743500 # number of LoadLockedReq miss cycles
947system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49386500 # number of StoreCondReq miss cycles
948system.cpu1.dcache.StoreCondReq_miss_latency::total 49386500 # number of StoreCondReq miss cycles
949system.cpu1.dcache.demand_miss_latency::cpu1.data 2681471500 # number of demand (read+write) miss cycles
950system.cpu1.dcache.demand_miss_latency::total 2681471500 # number of demand (read+write) miss cycles
951system.cpu1.dcache.overall_miss_latency::cpu1.data 2681471500 # number of overall miss cycles
952system.cpu1.dcache.overall_miss_latency::total 2681471500 # number of overall miss cycles
953system.cpu1.dcache.ReadReq_accesses::cpu1.data 2363341 # number of ReadReq accesses(hits+misses)
954system.cpu1.dcache.ReadReq_accesses::total 2363341 # number of ReadReq accesses(hits+misses)
955system.cpu1.dcache.WriteReq_accesses::cpu1.data 1694806 # number of WriteReq accesses(hits+misses)
956system.cpu1.dcache.WriteReq_accesses::total 1694806 # number of WriteReq accesses(hits+misses)
957system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57448 # number of LoadLockedReq accesses(hits+misses)
958system.cpu1.dcache.LoadLockedReq_accesses::total 57448 # number of LoadLockedReq accesses(hits+misses)
959system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56222 # number of StoreCondReq accesses(hits+misses)
960system.cpu1.dcache.StoreCondReq_accesses::total 56222 # number of StoreCondReq accesses(hits+misses)
961system.cpu1.dcache.demand_accesses::cpu1.data 4058147 # number of demand (read+write) accesses
962system.cpu1.dcache.demand_accesses::total 4058147 # number of demand (read+write) accesses
963system.cpu1.dcache.overall_accesses::cpu1.data 4058147 # number of overall (read+write) accesses
964system.cpu1.dcache.overall_accesses::total 4058147 # number of overall (read+write) accesses
965system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049759 # miss rate for ReadReq accesses
966system.cpu1.dcache.ReadReq_miss_rate::total 0.049759 # miss rate for ReadReq accesses
967system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036747 # miss rate for WriteReq accesses
968system.cpu1.dcache.WriteReq_miss_rate::total 0.036747 # miss rate for WriteReq accesses
969system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154174 # miss rate for LoadLockedReq accesses
970system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154174 # miss rate for LoadLockedReq accesses
971system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103394 # miss rate for StoreCondReq accesses
972system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103394 # miss rate for StoreCondReq accesses
973system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044325 # miss rate for demand accesses
974system.cpu1.dcache.demand_miss_rate::total 0.044325 # miss rate for demand accesses
975system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044325 # miss rate for overall accesses
976system.cpu1.dcache.overall_miss_rate::total 0.044325 # miss rate for overall accesses
977system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12123.021846 # average ReadReq miss latency
978system.cpu1.dcache.ReadReq_avg_miss_latency::total 12123.021846 # average ReadReq miss latency
979system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20164.750558 # average WriteReq miss latency
980system.cpu1.dcache.WriteReq_avg_miss_latency::total 20164.750558 # average WriteReq miss latency
981system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9116.348651 # average LoadLockedReq miss latency
982system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9116.348651 # average LoadLockedReq miss latency
983system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8495.871323 # average StoreCondReq miss latency
984system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8495.871323 # average StoreCondReq miss latency
985system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency
986system.cpu1.dcache.demand_avg_miss_latency::total 14907.333385 # average overall miss latency
987system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14907.333385 # average overall miss latency
988system.cpu1.dcache.overall_avg_miss_latency::total 14907.333385 # average overall miss latency
989system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
990system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
991system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
992system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
993system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
994system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
995system.cpu1.dcache.fast_writes 0 # number of fast writes performed
996system.cpu1.dcache.cache_copies 0 # number of cache copies performed
997system.cpu1.dcache.writebacks::writebacks 113645 # number of writebacks
998system.cpu1.dcache.writebacks::total 113645 # number of writebacks
999system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117597 # number of ReadReq MSHR misses
1000system.cpu1.dcache.ReadReq_mshr_misses::total 117597 # number of ReadReq MSHR misses
1001system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62279 # number of WriteReq MSHR misses
1002system.cpu1.dcache.WriteReq_mshr_misses::total 62279 # number of WriteReq MSHR misses
1003system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8857 # number of LoadLockedReq MSHR misses
1004system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8857 # number of LoadLockedReq MSHR misses
1005system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5813 # number of StoreCondReq MSHR misses
1006system.cpu1.dcache.StoreCondReq_mshr_misses::total 5813 # number of StoreCondReq MSHR misses
1007system.cpu1.dcache.demand_mshr_misses::cpu1.data 179876 # number of demand (read+write) MSHR misses
1008system.cpu1.dcache.demand_mshr_misses::total 179876 # number of demand (read+write) MSHR misses
1009system.cpu1.dcache.overall_mshr_misses::cpu1.data 179876 # number of overall MSHR misses
1010system.cpu1.dcache.overall_mshr_misses::total 179876 # number of overall MSHR misses
1011system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable
1012system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable
1013system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3214 # number of WriteReq MSHR uncacheable
1014system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3214 # number of WriteReq MSHR uncacheable
1015system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3303 # number of overall MSHR uncacheable misses
1016system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3303 # number of overall MSHR uncacheable misses
1017system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1308034000 # number of ReadReq MSHR miss cycles
1018system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1308034000 # number of ReadReq MSHR miss cycles
1019system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1193561500 # number of WriteReq MSHR miss cycles
1020system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1193561500 # number of WriteReq MSHR miss cycles
1021system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 71886500 # number of LoadLockedReq MSHR miss cycles
1022system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 71886500 # number of LoadLockedReq MSHR miss cycles
1023system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43573500 # number of StoreCondReq MSHR miss cycles
1024system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43573500 # number of StoreCondReq MSHR miss cycles
1025system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2501595500 # number of demand (read+write) MSHR miss cycles
1026system.cpu1.dcache.demand_mshr_miss_latency::total 2501595500 # number of demand (read+write) MSHR miss cycles
1027system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2501595500 # number of overall MSHR miss cycles
1028system.cpu1.dcache.overall_mshr_miss_latency::total 2501595500 # number of overall MSHR miss cycles
1029system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19086500 # number of ReadReq MSHR uncacheable cycles
1030system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19086500 # number of ReadReq MSHR uncacheable cycles
1031system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 723672500 # number of WriteReq MSHR uncacheable cycles
1032system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 723672500 # number of WriteReq MSHR uncacheable cycles
1033system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742759000 # number of overall MSHR uncacheable cycles
1034system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742759000 # number of overall MSHR uncacheable cycles
1035system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049759 # mshr miss rate for ReadReq accesses
1036system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049759 # mshr miss rate for ReadReq accesses
1037system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036747 # mshr miss rate for WriteReq accesses
1038system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036747 # mshr miss rate for WriteReq accesses
1039system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154174 # mshr miss rate for LoadLockedReq accesses
1040system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154174 # mshr miss rate for LoadLockedReq accesses
1041system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103394 # mshr miss rate for StoreCondReq accesses
1042system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103394 # mshr miss rate for StoreCondReq accesses
1043system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for demand accesses
1044system.cpu1.dcache.demand_mshr_miss_rate::total 0.044325 # mshr miss rate for demand accesses
1045system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044325 # mshr miss rate for overall accesses
1046system.cpu1.dcache.overall_mshr_miss_rate::total 0.044325 # mshr miss rate for overall accesses
1047system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11123.021846 # average ReadReq mshr miss latency
1048system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11123.021846 # average ReadReq mshr miss latency
1049system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19164.750558 # average WriteReq mshr miss latency
1050system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19164.750558 # average WriteReq mshr miss latency
1051system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8116.348651 # average LoadLockedReq mshr miss latency
1052system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8116.348651 # average LoadLockedReq mshr miss latency
1053system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7495.871323 # average StoreCondReq mshr miss latency
1054system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7495.871323 # average StoreCondReq mshr miss latency
1055system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency
1056system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency
1057system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13907.333385 # average overall mshr miss latency
1058system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13907.333385 # average overall mshr miss latency
1059system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214455.056180 # average ReadReq mshr uncacheable latency
1060system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 214455.056180 # average ReadReq mshr uncacheable latency
1061system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 225162.570006 # average WriteReq mshr uncacheable latency
1062system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225162.570006 # average WriteReq mshr uncacheable latency
1063system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 224874.053890 # average overall mshr uncacheable latency
1064system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 224874.053890 # average overall mshr uncacheable latency
1065system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1066system.cpu1.icache.tags.replacements 313887 # number of replacements
1067system.cpu1.icache.tags.tagsinuse 445.952187 # Cycle average of tags in use
1068system.cpu1.icache.tags.total_refs 12790016 # Total number of references to valid blocks.
1069system.cpu1.icache.tags.sampled_refs 314399 # Sample count of references to valid blocks.
1070system.cpu1.icache.tags.avg_refs 40.680842 # Average number of references to valid blocks.
1071system.cpu1.icache.tags.warmup_cycle 1961762459500 # Cycle when the warmup percentage was hit.
1072system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.952187 # Average occupied blocks per requestor
1073system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871000 # Average percentage of cache occupancy
1074system.cpu1.icache.tags.occ_percent::total 0.871000 # Average percentage of cache occupancy
1075system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1076system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
1077system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
1078system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
1079system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
1080system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1081system.cpu1.icache.tags.tag_accesses 13418898 # Number of tag accesses
1082system.cpu1.icache.tags.data_accesses 13418898 # Number of data accesses
1083system.cpu1.icache.ReadReq_hits::cpu1.inst 12790016 # number of ReadReq hits
1084system.cpu1.icache.ReadReq_hits::total 12790016 # number of ReadReq hits
1085system.cpu1.icache.demand_hits::cpu1.inst 12790016 # number of demand (read+write) hits
1086system.cpu1.icache.demand_hits::total 12790016 # number of demand (read+write) hits
1087system.cpu1.icache.overall_hits::cpu1.inst 12790016 # number of overall hits
1088system.cpu1.icache.overall_hits::total 12790016 # number of overall hits
1089system.cpu1.icache.ReadReq_misses::cpu1.inst 314441 # number of ReadReq misses
1090system.cpu1.icache.ReadReq_misses::total 314441 # number of ReadReq misses
1091system.cpu1.icache.demand_misses::cpu1.inst 314441 # number of demand (read+write) misses
1092system.cpu1.icache.demand_misses::total 314441 # number of demand (read+write) misses
1093system.cpu1.icache.overall_misses::cpu1.inst 314441 # number of overall misses
1094system.cpu1.icache.overall_misses::total 314441 # number of overall misses
1095system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4125234500 # number of ReadReq miss cycles
1096system.cpu1.icache.ReadReq_miss_latency::total 4125234500 # number of ReadReq miss cycles
1097system.cpu1.icache.demand_miss_latency::cpu1.inst 4125234500 # number of demand (read+write) miss cycles
1098system.cpu1.icache.demand_miss_latency::total 4125234500 # number of demand (read+write) miss cycles
1099system.cpu1.icache.overall_miss_latency::cpu1.inst 4125234500 # number of overall miss cycles
1100system.cpu1.icache.overall_miss_latency::total 4125234500 # number of overall miss cycles
1101system.cpu1.icache.ReadReq_accesses::cpu1.inst 13104457 # number of ReadReq accesses(hits+misses)
1102system.cpu1.icache.ReadReq_accesses::total 13104457 # number of ReadReq accesses(hits+misses)
1103system.cpu1.icache.demand_accesses::cpu1.inst 13104457 # number of demand (read+write) accesses
1104system.cpu1.icache.demand_accesses::total 13104457 # number of demand (read+write) accesses
1105system.cpu1.icache.overall_accesses::cpu1.inst 13104457 # number of overall (read+write) accesses
1106system.cpu1.icache.overall_accesses::total 13104457 # number of overall (read+write) accesses
1107system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023995 # miss rate for ReadReq accesses
1108system.cpu1.icache.ReadReq_miss_rate::total 0.023995 # miss rate for ReadReq accesses
1109system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023995 # miss rate for demand accesses
1110system.cpu1.icache.demand_miss_rate::total 0.023995 # miss rate for demand accesses
1111system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023995 # miss rate for overall accesses
1112system.cpu1.icache.overall_miss_rate::total 0.023995 # miss rate for overall accesses
1113system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13119.264027 # average ReadReq miss latency
1114system.cpu1.icache.ReadReq_avg_miss_latency::total 13119.264027 # average ReadReq miss latency
1115system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency
1116system.cpu1.icache.demand_avg_miss_latency::total 13119.264027 # average overall miss latency
1117system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13119.264027 # average overall miss latency
1118system.cpu1.icache.overall_avg_miss_latency::total 13119.264027 # average overall miss latency
1119system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1120system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1121system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1122system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1123system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1124system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1125system.cpu1.icache.fast_writes 0 # number of fast writes performed
1126system.cpu1.icache.cache_copies 0 # number of cache copies performed
1127system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 314441 # number of ReadReq MSHR misses
1128system.cpu1.icache.ReadReq_mshr_misses::total 314441 # number of ReadReq MSHR misses
1129system.cpu1.icache.demand_mshr_misses::cpu1.inst 314441 # number of demand (read+write) MSHR misses
1130system.cpu1.icache.demand_mshr_misses::total 314441 # number of demand (read+write) MSHR misses
1131system.cpu1.icache.overall_mshr_misses::cpu1.inst 314441 # number of overall MSHR misses
1132system.cpu1.icache.overall_mshr_misses::total 314441 # number of overall MSHR misses
1133system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3810793500 # number of ReadReq MSHR miss cycles
1134system.cpu1.icache.ReadReq_mshr_miss_latency::total 3810793500 # number of ReadReq MSHR miss cycles
1135system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3810793500 # number of demand (read+write) MSHR miss cycles
1136system.cpu1.icache.demand_mshr_miss_latency::total 3810793500 # number of demand (read+write) MSHR miss cycles
1137system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3810793500 # number of overall MSHR miss cycles
1138system.cpu1.icache.overall_mshr_miss_latency::total 3810793500 # number of overall MSHR miss cycles
1139system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for ReadReq accesses
1140system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023995 # mshr miss rate for ReadReq accesses
1141system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for demand accesses
1142system.cpu1.icache.demand_mshr_miss_rate::total 0.023995 # mshr miss rate for demand accesses
1143system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023995 # mshr miss rate for overall accesses
1144system.cpu1.icache.overall_mshr_miss_rate::total 0.023995 # mshr miss rate for overall accesses
1145system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average ReadReq mshr miss latency
1146system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12119.264027 # average ReadReq mshr miss latency
1147system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency
1148system.cpu1.icache.demand_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency
1149system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12119.264027 # average overall mshr miss latency
1150system.cpu1.icache.overall_avg_mshr_miss_latency::total 12119.264027 # average overall mshr miss latency
1151system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1152system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1153system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1154system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1155system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1156system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1157system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1158system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1159system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1160system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1161system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1162system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1163system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1164system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
1165system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
1166system.iobus.trans_dist::WriteReq 55595 # Transaction distribution
1167system.iobus.trans_dist::WriteResp 55595 # Transaction distribution
1168system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13874 # Packet count per connected master and slave (bytes)
1169system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1170system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1171system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1172system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1173system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1174system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
1175system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1176system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1177system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1178system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1179system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1180system.iobus.pkt_count_system.bridge.master::total 42484 # Packet count per connected master and slave (bytes)
1181system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
1182system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
1183system.iobus.pkt_count::total 125936 # Packet count per connected master and slave (bytes)
1184system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55496 # Cumulative packet size per connected master and slave (bytes)
1185system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
1186system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1187system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1188system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1189system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1190system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
1191system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1192system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1193system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1194system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1195system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1196system.iobus.pkt_size_system.bridge.master::total 81762 # Cumulative packet size per connected master and slave (bytes)
1197system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
1198system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
1199system.iobus.pkt_size::total 2743378 # Cumulative packet size per connected master and slave (bytes)
1200system.iobus.reqLayer0.occupancy 13229000 # Layer occupancy (ticks)
1201system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1202system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1203system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1204system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1205system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1206system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1207system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1208system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1209system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1210system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1211system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1212system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
1213system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1214system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1215system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1216system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1217system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1218system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1219system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1220system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1221system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1222system.iobus.reqLayer29.occupancy 216079499 # Layer occupancy (ticks)
1223system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1224system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1225system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1226system.iobus.respLayer0.occupancy 28441000 # Layer occupancy (ticks)
1227system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1228system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks)
1229system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1230system.iocache.tags.replacements 41694 # number of replacements
1231system.iocache.tags.tagsinuse 0.567878 # Cycle average of tags in use
1232system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1233system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
1234system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1235system.iocache.tags.warmup_cycle 1756483227000 # Cycle when the warmup percentage was hit.
1236system.iocache.tags.occ_blocks::tsunami.ide 0.567878 # Average occupied blocks per requestor
1237system.iocache.tags.occ_percent::tsunami.ide 0.035492 # Average percentage of cache occupancy
1238system.iocache.tags.occ_percent::total 0.035492 # Average percentage of cache occupancy
1239system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1240system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1241system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1242system.iocache.tags.tag_accesses 375534 # Number of tag accesses
1243system.iocache.tags.data_accesses 375534 # Number of data accesses
1244system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
1245system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
1246system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
1247system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
1248system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
1249system.iocache.demand_misses::total 174 # number of demand (read+write) misses
1250system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
1251system.iocache.overall_misses::total 174 # number of overall misses
1252system.iocache.ReadReq_miss_latency::tsunami.ide 21744883 # number of ReadReq miss cycles
1253system.iocache.ReadReq_miss_latency::total 21744883 # number of ReadReq miss cycles
1254system.iocache.WriteLineReq_miss_latency::tsunami.ide 4908047616 # number of WriteLineReq miss cycles
1255system.iocache.WriteLineReq_miss_latency::total 4908047616 # number of WriteLineReq miss cycles
1256system.iocache.demand_miss_latency::tsunami.ide 21744883 # number of demand (read+write) miss cycles
1257system.iocache.demand_miss_latency::total 21744883 # number of demand (read+write) miss cycles
1258system.iocache.overall_miss_latency::tsunami.ide 21744883 # number of overall miss cycles
1259system.iocache.overall_miss_latency::total 21744883 # number of overall miss cycles
1260system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
1261system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
1262system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
1263system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
1264system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
1265system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
1266system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
1267system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
1268system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1269system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1270system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
1271system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
1272system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1273system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1274system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1275system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1276system.iocache.ReadReq_avg_miss_latency::tsunami.ide 124970.591954 # average ReadReq miss latency
1277system.iocache.ReadReq_avg_miss_latency::total 124970.591954 # average ReadReq miss latency
1278system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118118.204082 # average WriteLineReq miss latency
1279system.iocache.WriteLineReq_avg_miss_latency::total 118118.204082 # average WriteLineReq miss latency
1280system.iocache.demand_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency
1281system.iocache.demand_avg_miss_latency::total 124970.591954 # average overall miss latency
1282system.iocache.overall_avg_miss_latency::tsunami.ide 124970.591954 # average overall miss latency
1283system.iocache.overall_avg_miss_latency::total 124970.591954 # average overall miss latency
1284system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1285system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1286system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1287system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1288system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1289system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1290system.iocache.fast_writes 0 # number of fast writes performed
1291system.iocache.cache_copies 0 # number of cache copies performed
1292system.iocache.writebacks::writebacks 41520 # number of writebacks
1293system.iocache.writebacks::total 41520 # number of writebacks
1294system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
1295system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
1296system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
1297system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
1298system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses
1299system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
1300system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses
1301system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses
1302system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13044883 # number of ReadReq MSHR miss cycles
1303system.iocache.ReadReq_mshr_miss_latency::total 13044883 # number of ReadReq MSHR miss cycles
1304system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2830447616 # number of WriteLineReq MSHR miss cycles
1305system.iocache.WriteLineReq_mshr_miss_latency::total 2830447616 # number of WriteLineReq MSHR miss cycles
1306system.iocache.demand_mshr_miss_latency::tsunami.ide 13044883 # number of demand (read+write) MSHR miss cycles
1307system.iocache.demand_mshr_miss_latency::total 13044883 # number of demand (read+write) MSHR miss cycles
1308system.iocache.overall_mshr_miss_latency::tsunami.ide 13044883 # number of overall MSHR miss cycles
1309system.iocache.overall_mshr_miss_latency::total 13044883 # number of overall MSHR miss cycles
1310system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1311system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1312system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
1313system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
1314system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1315system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1316system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1317system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1318system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average ReadReq mshr miss latency
1319system.iocache.ReadReq_avg_mshr_miss_latency::total 74970.591954 # average ReadReq mshr miss latency
1320system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68118.204082 # average WriteLineReq mshr miss latency
1321system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68118.204082 # average WriteLineReq mshr miss latency
1322system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency
1323system.iocache.demand_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency
1324system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 74970.591954 # average overall mshr miss latency
1325system.iocache.overall_avg_mshr_miss_latency::total 74970.591954 # average overall mshr miss latency
1326system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1327system.l2c.tags.replacements 341250 # number of replacements
1328system.l2c.tags.tagsinuse 65213.641245 # Cycle average of tags in use
1329system.l2c.tags.total_refs 3683713 # Total number of references to valid blocks.
1330system.l2c.tags.sampled_refs 406253 # Sample count of references to valid blocks.
1331system.l2c.tags.avg_refs 9.067534 # Average number of references to valid blocks.
1332system.l2c.tags.warmup_cycle 9107201000 # Cycle when the warmup percentage was hit.
1333system.l2c.tags.occ_blocks::writebacks 55129.108381 # Average occupied blocks per requestor
1334system.l2c.tags.occ_blocks::cpu0.inst 4852.505635 # Average occupied blocks per requestor
1335system.l2c.tags.occ_blocks::cpu0.data 5029.950253 # Average occupied blocks per requestor
1336system.l2c.tags.occ_blocks::cpu1.inst 158.753057 # Average occupied blocks per requestor
1337system.l2c.tags.occ_blocks::cpu1.data 43.323918 # Average occupied blocks per requestor
1338system.l2c.tags.occ_percent::writebacks 0.841203 # Average percentage of cache occupancy
1339system.l2c.tags.occ_percent::cpu0.inst 0.074043 # Average percentage of cache occupancy
1340system.l2c.tags.occ_percent::cpu0.data 0.076751 # Average percentage of cache occupancy
1341system.l2c.tags.occ_percent::cpu1.inst 0.002422 # Average percentage of cache occupancy
1342system.l2c.tags.occ_percent::cpu1.data 0.000661 # Average percentage of cache occupancy
1343system.l2c.tags.occ_percent::total 0.995081 # Average percentage of cache occupancy
1344system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id
1345system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id
1346system.l2c.tags.age_task_id_blocks_1024::1 1120 # Occupied blocks per task id
1347system.l2c.tags.age_task_id_blocks_1024::2 4999 # Occupied blocks per task id
1348system.l2c.tags.age_task_id_blocks_1024::3 6097 # Occupied blocks per task id
1349system.l2c.tags.age_task_id_blocks_1024::4 52602 # Occupied blocks per task id
1350system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id
1351system.l2c.tags.tag_accesses 35905885 # Number of tag accesses
1352system.l2c.tags.data_accesses 35905885 # Number of data accesses
1353system.l2c.Writeback_hits::writebacks 793586 # number of Writeback hits
1354system.l2c.Writeback_hits::total 793586 # number of Writeback hits
1355system.l2c.UpgradeReq_hits::cpu0.data 173 # number of UpgradeReq hits
1356system.l2c.UpgradeReq_hits::cpu1.data 535 # number of UpgradeReq hits
1357system.l2c.UpgradeReq_hits::total 708 # number of UpgradeReq hits
1358system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits
1359system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
1360system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits
1361system.l2c.ReadExReq_hits::cpu0.data 126818 # number of ReadExReq hits
1362system.l2c.ReadExReq_hits::cpu1.data 46992 # number of ReadExReq hits
1363system.l2c.ReadExReq_hits::total 173810 # number of ReadExReq hits
1364system.l2c.ReadCleanReq_hits::cpu0.inst 688011 # number of ReadCleanReq hits
1365system.l2c.ReadCleanReq_hits::cpu1.inst 313935 # number of ReadCleanReq hits
1366system.l2c.ReadCleanReq_hits::total 1001946 # number of ReadCleanReq hits
1367system.l2c.ReadSharedReq_hits::cpu0.data 665063 # number of ReadSharedReq hits
1368system.l2c.ReadSharedReq_hits::cpu1.data 108615 # number of ReadSharedReq hits
1369system.l2c.ReadSharedReq_hits::total 773678 # number of ReadSharedReq hits
1370system.l2c.demand_hits::cpu0.inst 688011 # number of demand (read+write) hits
1371system.l2c.demand_hits::cpu0.data 791881 # number of demand (read+write) hits
1372system.l2c.demand_hits::cpu1.inst 313935 # number of demand (read+write) hits
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1585system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17974000 # number of ReadReq MSHR uncacheable cycles
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1596system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764109 # mshr miss rate for UpgradeReq accesses
1597system.l2c.UpgradeReq_mshr_miss_rate::total 0.868304 # mshr miss rate for UpgradeReq accesses
1598system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.953514 # mshr miss rate for SCUpgradeReq accesses
1599system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973828 # mshr miss rate for SCUpgradeReq accesses
1600system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.963626 # mshr miss rate for SCUpgradeReq accesses
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1605system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for ReadCleanReq accesses
1606system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013288 # mshr miss rate for ReadCleanReq accesses
1607system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.289979 # mshr miss rate for ReadSharedReq accesses
1608system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002168 # mshr miss rate for ReadSharedReq accesses
1609system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260015 # mshr miss rate for ReadSharedReq accesses
1610system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for demand accesses
1611system.l2c.demand_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for demand accesses
1612system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for demand accesses
1613system.l2c.demand_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for demand accesses
1614system.l2c.demand_mshr_miss_rate::total 0.172885 # mshr miss rate for demand accesses
1615system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018543 # mshr miss rate for overall accesses
1616system.l2c.overall_mshr_miss_rate::cpu0.data 0.328369 # mshr miss rate for overall accesses
1617system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001571 # mshr miss rate for overall accesses
1618system.l2c.overall_mshr_miss_rate::cpu1.data 0.042012 # mshr miss rate for overall accesses
1619system.l2c.overall_mshr_miss_rate::total 0.172885 # mshr miss rate for overall accesses
1620system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20637.989779 # average UpgradeReq mshr miss latency
1621system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20700.230814 # average UpgradeReq mshr miss latency
1622system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20661.096829 # average UpgradeReq mshr miss latency
1623system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20657.029478 # average SCUpgradeReq mshr miss latency
1624system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20520.156775 # average SCUpgradeReq mshr miss latency
1625system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20588.169014 # average SCUpgradeReq mshr miss latency
1626system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66275.263541 # average ReadExReq mshr miss latency
1627system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71685.564663 # average ReadExReq mshr miss latency
1628system.l2c.ReadExReq_avg_mshr_miss_latency::total 66567.108818 # average ReadExReq mshr miss latency
1629system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average ReadCleanReq mshr miss latency
1630system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average ReadCleanReq mshr miss latency
1631system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 69912.287853 # average ReadCleanReq mshr miss latency
1632system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 62378.890574 # average ReadSharedReq mshr miss latency
1633system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70368.644068 # average ReadSharedReq mshr miss latency
1634system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 62385.826583 # average ReadSharedReq mshr miss latency
1635system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency
1636system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency
1637system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency
1638system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency
1639system.l2c.demand_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency
1640system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69875.682745 # average overall mshr miss latency
1641system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63541.703688 # average overall mshr miss latency
1642system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70875.506073 # average overall mshr miss latency
1643system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71640.020516 # average overall mshr miss latency
1644system.l2c.overall_avg_mshr_miss_latency::total 63888.278357 # average overall mshr miss latency
1645system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197377.355837 # average ReadReq mshr uncacheable latency
1646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201955.056180 # average ReadReq mshr uncacheable latency
1647system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 197433.949160 # average ReadReq mshr uncacheable latency
1648system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 202727.398652 # average WriteReq mshr uncacheable latency
1649system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 213662.103298 # average WriteReq mshr uncacheable latency
1650system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 205230.007833 # average WriteReq mshr uncacheable latency
1651system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 200606.945761 # average overall mshr uncacheable latency
1652system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 213346.654556 # average overall mshr uncacheable latency
1653system.l2c.overall_avg_mshr_uncacheable_latency::total 202587.891912 # average overall mshr uncacheable latency
1654system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1655system.membus.trans_dist::ReadReq 7199 # Transaction distribution
1656system.membus.trans_dist::ReadResp 292720 # Transaction distribution
1657system.membus.trans_dist::WriteReq 14043 # Transaction distribution
1658system.membus.trans_dist::WriteResp 14043 # Transaction distribution
1659system.membus.trans_dist::Writeback 120393 # Transaction distribution
1660system.membus.trans_dist::CleanEvict 261901 # Transaction distribution
1661system.membus.trans_dist::UpgradeReq 15996 # Transaction distribution
1662system.membus.trans_dist::SCUpgradeReq 11145 # Transaction distribution
1663system.membus.trans_dist::UpgradeResp 6943 # Transaction distribution
1664system.membus.trans_dist::ReadExReq 122456 # Transaction distribution
1665system.membus.trans_dist::ReadExResp 121630 # Transaction distribution
1666system.membus.trans_dist::ReadSharedReq 285521 # Transaction distribution
1667system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
1668system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
1669system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42484 # Packet count per connected master and slave (bytes)
1670system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1189359 # Packet count per connected master and slave (bytes)
1671system.membus.pkt_count_system.l2c.mem_side::total 1231843 # Packet count per connected master and slave (bytes)
1672system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124826 # Packet count per connected master and slave (bytes)
1673system.membus.pkt_count_system.iocache.mem_side::total 124826 # Packet count per connected master and slave (bytes)
1674system.membus.pkt_count::total 1356669 # Packet count per connected master and slave (bytes)
1675system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81762 # Cumulative packet size per connected master and slave (bytes)
1676system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31077568 # Cumulative packet size per connected master and slave (bytes)
1677system.membus.pkt_size_system.l2c.mem_side::total 31159330 # Cumulative packet size per connected master and slave (bytes)
1678system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
1679system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
1680system.membus.pkt_size::total 33817570 # Cumulative packet size per connected master and slave (bytes)
1681system.membus.snoops 21449 # Total snoops (count)
1682system.membus.snoop_fanout::samples 880387 # Request fanout histogram
1683system.membus.snoop_fanout::mean 1 # Request fanout histogram
1684system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1685system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1686system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1687system.membus.snoop_fanout::1 880387 100.00% 100.00% # Request fanout histogram
1688system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1689system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1690system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1691system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1692system.membus.snoop_fanout::total 880387 # Request fanout histogram
1693system.membus.reqLayer0.occupancy 40402000 # Layer occupancy (ticks)
1694system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1695system.membus.reqLayer1.occupancy 1321574195 # Layer occupancy (ticks)
1696system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1697system.membus.respLayer1.occupancy 2188968059 # Layer occupancy (ticks)
1698system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
1699system.membus.respLayer2.occupancy 72063409 # Layer occupancy (ticks)
1700system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1701system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution
1702system.toL2Bus.trans_dist::ReadResp 2102214 # Transaction distribution
1703system.toL2Bus.trans_dist::WriteReq 14043 # Transaction distribution
1704system.toL2Bus.trans_dist::WriteResp 14043 # Transaction distribution
1705system.toL2Bus.trans_dist::Writeback 913999 # Transaction distribution
1706system.toL2Bus.trans_dist::CleanEvict 1505100 # Transaction distribution
1707system.toL2Bus.trans_dist::UpgradeReq 16204 # Transaction distribution
1708system.toL2Bus.trans_dist::SCUpgradeReq 11212 # Transaction distribution
1709system.toL2Bus.trans_dist::UpgradeResp 27416 # Transaction distribution
1710system.toL2Bus.trans_dist::ReadExReq 297872 # Transaction distribution
1711system.toL2Bus.trans_dist::ReadExResp 297872 # Transaction distribution
1712system.toL2Bus.trans_dist::ReadCleanReq 1015472 # Transaction distribution
1713system.toL2Bus.trans_dist::ReadSharedReq 1079558 # Transaction distribution
1714system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution
1715system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1960114 # Packet count per connected master and slave (bytes)
1716system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3569990 # Packet count per connected master and slave (bytes)
1717system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 818944 # Packet count per connected master and slave (bytes)
1718system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 514014 # Packet count per connected master and slave (bytes)
1719system.toL2Bus.pkt_count::total 6863062 # Packet count per connected master and slave (bytes)
1720system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44864640 # Cumulative packet size per connected master and slave (bytes)
1721system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119041472 # Cumulative packet size per connected master and slave (bytes)
1722system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20124160 # Cumulative packet size per connected master and slave (bytes)
1723system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17694178 # Cumulative packet size per connected master and slave (bytes)
1724system.toL2Bus.pkt_size::total 201724450 # Cumulative packet size per connected master and slave (bytes)
1725system.toL2Bus.snoops 480853 # Total snoops (count)
1726system.toL2Bus.snoop_fanout::samples 5227539 # Request fanout histogram
1727system.toL2Bus.snoop_fanout::mean 3.081241 # Request fanout histogram
1728system.toL2Bus.snoop_fanout::stdev 0.273205 # Request fanout histogram
1729system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1730system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1731system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1732system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1733system.toL2Bus.snoop_fanout::3 4802849 91.88% 91.88% # Request fanout histogram
1734system.toL2Bus.snoop_fanout::4 424690 8.12% 100.00% # Request fanout histogram
1735system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1736system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1737system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1738system.toL2Bus.snoop_fanout::total 5227539 # Request fanout histogram
1739system.toL2Bus.reqLayer0.occupancy 3202032998 # Layer occupancy (ticks)
1740system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1741system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks)
1742system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1743system.toL2Bus.respLayer0.occupancy 1051547997 # Layer occupancy (ticks)
1744system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1745system.toL2Bus.respLayer1.occupancy 1814279465 # Layer occupancy (ticks)
1746system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1747system.toL2Bus.respLayer2.occupancy 471668486 # Layer occupancy (ticks)
1748system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1749system.toL2Bus.respLayer3.occupancy 279553995 # Layer occupancy (ticks)
1750system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1751system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1752system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1753system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1754system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1755system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1756system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1757system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR

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