1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.961814 # Number of seconds simulated
4sim_ticks 1961813569500 # Number of ticks simulated
5final_tick 1961813569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1769979 # Simulator instruction rate (inst/s)
8host_op_rate 1769979 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 57024152249 # Simulator tick rate (ticks/s)
10host_mem_usage 311592 # Number of bytes of host memory used
11host_seconds 34.40 # Real time elapsed on the host
12sim_insts 60892925 # Number of instructions simulated
13sim_ops 60892925 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 833088 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24884096 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 31936 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 337152 # Number of bytes read from this memory
21system.physmem.bytes_read::total 28737152 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 833088 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7735232 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7735232 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 13017 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 388814 # Number of read requests responded to by this memory
29system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 499 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 5268 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 449018 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 120863 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 120863 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 424652 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 12684231 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::tsunami.ide 1351240 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.inst 16279 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.data 171857 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 14648258 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 424652 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 16279 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 440931 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 3942899 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 3942899 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 3942899 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 424652 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 12684231 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::tsunami.ide 1351240 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.inst 16279 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu1.data 171857 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 449018 # Number of read requests accepted
54system.physmem.writeReqs 120863 # Number of write requests accepted
55system.physmem.readBursts 449018 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 120863 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 28729600 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue
59system.physmem.bytesWritten 7733952 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 28737152 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 7735232 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 6983 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 28166 # Per bank write bursts
66system.physmem.perBankRdBursts::1 28350 # Per bank write bursts
67system.physmem.perBankRdBursts::2 28054 # Per bank write bursts
68system.physmem.perBankRdBursts::3 27500 # Per bank write bursts
69system.physmem.perBankRdBursts::4 27615 # Per bank write bursts
70system.physmem.perBankRdBursts::5 27605 # Per bank write bursts
71system.physmem.perBankRdBursts::6 28127 # Per bank write bursts
72system.physmem.perBankRdBursts::7 27851 # Per bank write bursts
73system.physmem.perBankRdBursts::8 28176 # Per bank write bursts
74system.physmem.perBankRdBursts::9 27723 # Per bank write bursts
75system.physmem.perBankRdBursts::10 27750 # Per bank write bursts
76system.physmem.perBankRdBursts::11 28018 # Per bank write bursts
77system.physmem.perBankRdBursts::12 28330 # Per bank write bursts
78system.physmem.perBankRdBursts::13 28694 # Per bank write bursts
79system.physmem.perBankRdBursts::14 28891 # Per bank write bursts
80system.physmem.perBankRdBursts::15 28050 # Per bank write bursts
81system.physmem.perBankWrBursts::0 7929 # Per bank write bursts
82system.physmem.perBankWrBursts::1 7797 # Per bank write bursts
83system.physmem.perBankWrBursts::2 7545 # Per bank write bursts
84system.physmem.perBankWrBursts::3 7029 # Per bank write bursts
85system.physmem.perBankWrBursts::4 7135 # Per bank write bursts
86system.physmem.perBankWrBursts::5 7129 # Per bank write bursts
87system.physmem.perBankWrBursts::6 7643 # Per bank write bursts
88system.physmem.perBankWrBursts::7 7252 # Per bank write bursts
89system.physmem.perBankWrBursts::8 7395 # Per bank write bursts
90system.physmem.perBankWrBursts::9 7084 # Per bank write bursts
91system.physmem.perBankWrBursts::10 7104 # Per bank write bursts
92system.physmem.perBankWrBursts::11 7401 # Per bank write bursts
93system.physmem.perBankWrBursts::12 7833 # Per bank write bursts
94system.physmem.perBankWrBursts::13 8315 # Per bank write bursts
95system.physmem.perBankWrBursts::14 8551 # Per bank write bursts
96system.physmem.perBankWrBursts::15 7701 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
99system.physmem.totGap 1961806557500 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 449018 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 120863 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 407987 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 1708 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 1544 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 1052 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 1160 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 4326 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 3779 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 3770 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 3964 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 2524 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::10 2113 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::11 2058 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::12 1914 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::13 1871 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::14 1569 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::15 1543 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::16 1513 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::17 1527 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::18 1719 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::19 1248 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 1574 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 1864 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 2356 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 4659 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 4719 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 4730 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 4812 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 4815 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 4859 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 6368 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 5252 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 5405 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 6934 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 5634 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 5860 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 5888 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 5671 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 1116 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 1056 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 1045 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 1090 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 1047 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 1031 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 1187 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 1508 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 1614 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 1739 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 1832 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 1868 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 1782 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 1877 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 1859 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 1827 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 1847 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 1717 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 1501 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 1291 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 437 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 293 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 48187 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 641.951066 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 418.430190 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 422.843508 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 8213 17.04% 17.04% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 7073 14.68% 31.72% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 2891 6.00% 37.72% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 1720 3.57% 41.29% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 1328 2.76% 44.05% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 906 1.88% 45.93% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 669 1.39% 47.32% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 536 1.11% 48.43% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 24851 51.57% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 48187 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 6896 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 65.095418 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2542.617511 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-8191 6893 99.96% 99.96% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 6896 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 6896 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 17.523637 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 17.253710 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 3.981541 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16 4466 64.76% 64.76% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::17 342 4.96% 69.72% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::18 377 5.47% 75.19% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::19 1323 19.19% 94.37% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::20 32 0.46% 94.84% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::21 16 0.23% 95.07% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::22 12 0.17% 95.24% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::23 22 0.32% 95.56% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::24 43 0.62% 96.19% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::25 30 0.44% 96.62% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::26 27 0.39% 97.01% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::27 32 0.46% 97.48% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::28 29 0.42% 97.90% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::29 31 0.45% 98.35% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::30 6 0.09% 98.43% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::31 8 0.12% 98.55% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::32 10 0.15% 98.69% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::33 3 0.04% 98.74% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::34 4 0.06% 98.80% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::35 4 0.06% 98.85% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::37 3 0.04% 98.90% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::38 3 0.04% 98.94% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::39 5 0.07% 99.01% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::40 3 0.04% 99.06% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::41 2 0.03% 99.09% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::42 2 0.03% 99.12% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::43 3 0.04% 99.16% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::45 3 0.04% 99.20% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::46 6 0.09% 99.29% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::47 12 0.17% 99.46% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::48 5 0.07% 99.54% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::49 7 0.10% 99.64% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::50 4 0.06% 99.70% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::51 3 0.04% 99.74% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::52 5 0.07% 99.81% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::53 6 0.09% 99.90% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::55 1 0.01% 99.91% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::56 2 0.03% 99.94% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::57 1 0.01% 99.96% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::total 6896 # Writes before turning the bus around for reads
277system.physmem.totQLat 7845433250 # Total ticks spent queuing
278system.physmem.totMemAccLat 16453873250 # Total ticks spent from burst creation until serviced by the DRAM
279system.physmem.totBusLat 2244500000 # Total ticks spent in databus transfers
280system.physmem.totBankLat 6363940000 # Total ticks spent accessing banks
281system.physmem.avgQLat 17477.02 # Average queueing delay per DRAM burst
282system.physmem.avgBankLat 14176.74 # Average bank access latency per DRAM burst
283system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
284system.physmem.avgMemAccLat 36653.76 # Average memory access latency per DRAM burst
285system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s
286system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s
287system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s
288system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s
289system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
290system.physmem.busUtil 0.15 # Data bus utilization in percentage
291system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
292system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
293system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
294system.physmem.avgWrQLen 26.52 # Average write queue length when enqueuing
295system.physmem.readRowHits 403422 # Number of row buffer hits during reads
296system.physmem.writeRowHits 97436 # Number of row buffer hits during writes
297system.physmem.readRowHitRate 89.87 # Row buffer hit rate for reads
298system.physmem.writeRowHitRate 80.62 # Row buffer hit rate for writes
299system.physmem.avgGap 3442484.58 # Average gap between requests
300system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined
301system.physmem.prechargeAllPercent 0.55 # Percentage of time for which DRAM has all the banks in precharge state
302system.membus.throughput 18651494 # Throughput (bytes/s)
303system.membus.trans_dist::ReadReq 292756 # Transaction distribution
304system.membus.trans_dist::ReadResp 292756 # Transaction distribution
305system.membus.trans_dist::WriteReq 14067 # Transaction distribution
306system.membus.trans_dist::WriteResp 14067 # Transaction distribution
307system.membus.trans_dist::Writeback 120863 # Transaction distribution
308system.membus.trans_dist::UpgradeReq 16150 # Transaction distribution
309system.membus.trans_dist::SCUpgradeReq 11271 # Transaction distribution
310system.membus.trans_dist::UpgradeResp 6986 # Transaction distribution
311system.membus.trans_dist::ReadExReq 164854 # Transaction distribution
312system.membus.trans_dist::ReadExResp 164030 # Transaction distribution
313system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes)
314system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930030 # Packet count per connected master and slave (bytes)
315system.membus.pkt_count_system.l2c.mem_side::total 972562 # Packet count per connected master and slave (bytes)
316system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes)
317system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes)
318system.membus.pkt_count::total 1097228 # Packet count per connected master and slave (bytes)
319system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes)
320system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31164224 # Cumulative packet size per connected master and slave (bytes)
321system.membus.tot_pkt_size_system.l2c.mem_side::total 31246178 # Cumulative packet size per connected master and slave (bytes)
322system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes)
323system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes)
324system.membus.tot_pkt_size::total 36554338 # Cumulative packet size per connected master and slave (bytes)
325system.membus.data_through_bus 36554338 # Total data (bytes)
326system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes)
327system.membus.reqLayer0.occupancy 43154000 # Layer occupancy (ticks)
328system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
329system.membus.reqLayer1.occupancy 1578633000 # Layer occupancy (ticks)
330system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
331system.membus.respLayer1.occupancy 3834132000 # Layer occupancy (ticks)
332system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
333system.membus.respLayer2.occupancy 376702000 # Layer occupancy (ticks)
334system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
335system.cpu_clk_domain.clock 500 # Clock period in ticks
336system.l2c.tags.replacements 342098 # number of replacements
337system.l2c.tags.tagsinuse 65220.106735 # Cycle average of tags in use
338system.l2c.tags.total_refs 2445213 # Total number of references to valid blocks.
339system.l2c.tags.sampled_refs 407285 # Sample count of references to valid blocks.
340system.l2c.tags.avg_refs 6.003690 # Average number of references to valid blocks.
341system.l2c.tags.warmup_cycle 8658635750 # Cycle when the warmup percentage was hit.
342system.l2c.tags.occ_blocks::writebacks 55273.758884 # Average occupied blocks per requestor
343system.l2c.tags.occ_blocks::cpu0.inst 4807.212496 # Average occupied blocks per requestor
344system.l2c.tags.occ_blocks::cpu0.data 4935.163888 # Average occupied blocks per requestor
345system.l2c.tags.occ_blocks::cpu1.inst 160.761256 # Average occupied blocks per requestor
346system.l2c.tags.occ_blocks::cpu1.data 43.210211 # Average occupied blocks per requestor
347system.l2c.tags.occ_percent::writebacks 0.843411 # Average percentage of cache occupancy
348system.l2c.tags.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy
349system.l2c.tags.occ_percent::cpu0.data 0.075305 # Average percentage of cache occupancy
350system.l2c.tags.occ_percent::cpu1.inst 0.002453 # Average percentage of cache occupancy
351system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy
352system.l2c.tags.occ_percent::total 0.995180 # Average percentage of cache occupancy
353system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id
354system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
355system.l2c.tags.age_task_id_blocks_1024::1 784 # Occupied blocks per task id
356system.l2c.tags.age_task_id_blocks_1024::2 5254 # Occupied blocks per task id
357system.l2c.tags.age_task_id_blocks_1024::3 7171 # Occupied blocks per task id
358system.l2c.tags.age_task_id_blocks_1024::4 51861 # Occupied blocks per task id
359system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id
360system.l2c.tags.tag_accesses 25954090 # Number of tag accesses
361system.l2c.tags.data_accesses 25954090 # Number of data accesses
362system.l2c.ReadReq_hits::cpu0.inst 690864 # number of ReadReq hits
363system.l2c.ReadReq_hits::cpu0.data 668298 # number of ReadReq hits
364system.l2c.ReadReq_hits::cpu1.inst 311515 # number of ReadReq hits
365system.l2c.ReadReq_hits::cpu1.data 104210 # number of ReadReq hits
366system.l2c.ReadReq_hits::total 1774887 # number of ReadReq hits
367system.l2c.Writeback_hits::writebacks 792911 # number of Writeback hits
368system.l2c.Writeback_hits::total 792911 # number of Writeback hits
369system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits
370system.l2c.UpgradeReq_hits::cpu1.data 529 # number of UpgradeReq hits
371system.l2c.UpgradeReq_hits::total 713 # number of UpgradeReq hits
372system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits
373system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits
374system.l2c.SCUpgradeReq_hits::total 64 # number of SCUpgradeReq hits
375system.l2c.ReadExReq_hits::cpu0.data 130516 # number of ReadExReq hits
376system.l2c.ReadExReq_hits::cpu1.data 42247 # number of ReadExReq hits
377system.l2c.ReadExReq_hits::total 172763 # number of ReadExReq hits
378system.l2c.demand_hits::cpu0.inst 690864 # number of demand (read+write) hits
379system.l2c.demand_hits::cpu0.data 798814 # number of demand (read+write) hits
380system.l2c.demand_hits::cpu1.inst 311515 # number of demand (read+write) hits
381system.l2c.demand_hits::cpu1.data 146457 # number of demand (read+write) hits
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383system.l2c.overall_hits::cpu0.inst 690864 # number of overall hits
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385system.l2c.overall_hits::cpu1.inst 311515 # number of overall hits
386system.l2c.overall_hits::cpu1.data 146457 # number of overall hits
387system.l2c.overall_hits::total 1947650 # number of overall hits
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393system.l2c.UpgradeReq_misses::cpu0.data 2952 # number of UpgradeReq misses
394system.l2c.UpgradeReq_misses::cpu1.data 1737 # number of UpgradeReq misses
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418system.l2c.UpgradeReq_miss_latency::cpu1.data 9942571 # number of UpgradeReq miss cycles
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440system.l2c.ReadReq_accesses::total 2060281 # number of ReadReq accesses(hits+misses)
441system.l2c.Writeback_accesses::writebacks 792911 # number of Writeback accesses(hits+misses)
442system.l2c.Writeback_accesses::total 792911 # number of Writeback accesses(hits+misses)
443system.l2c.UpgradeReq_accesses::cpu0.data 3136 # number of UpgradeReq accesses(hits+misses)
444system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses)
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447system.l2c.SCUpgradeReq_accesses::cpu1.data 933 # number of SCUpgradeReq accesses(hits+misses)
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461system.l2c.overall_accesses::total 2356022 # number of overall (read+write) accesses
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463system.l2c.ReadReq_miss_rate::cpu0.data 0.288990 # miss rate for ReadReq accesses
464system.l2c.ReadReq_miss_rate::cpu1.inst 0.001625 # miss rate for ReadReq accesses
465system.l2c.ReadReq_miss_rate::cpu1.data 0.002269 # miss rate for ReadReq accesses
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467system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941327 # miss rate for UpgradeReq accesses
468system.l2c.UpgradeReq_miss_rate::cpu1.data 0.766549 # miss rate for UpgradeReq accesses
469system.l2c.UpgradeReq_miss_rate::total 0.868012 # miss rate for UpgradeReq accesses
470system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.956897 # miss rate for SCUpgradeReq accesses
471system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974277 # miss rate for SCUpgradeReq accesses
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492system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5723.990213 # average UpgradeReq miss latency
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495system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 178.210121 # average SCUpgradeReq miss latency
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511system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
512system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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515system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
516system.l2c.fast_writes 0 # number of fast writes performed
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562system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9090909 # number of SCUpgradeReq MSHR miss cycles
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571system.l2c.demand_mshr_miss_latency::total 22032067517 # number of demand (read+write) MSHR miss cycles
572system.l2c.overall_mshr_miss_latency::cpu0.inst 793128009 # number of overall MSHR miss cycles
573system.l2c.overall_mshr_miss_latency::cpu0.data 20892906747 # number of overall MSHR miss cycles
574system.l2c.overall_mshr_miss_latency::cpu1.inst 30990750 # number of overall MSHR miss cycles
575system.l2c.overall_mshr_miss_latency::cpu1.data 315042011 # number of overall MSHR miss cycles
576system.l2c.overall_mshr_miss_latency::total 22032067517 # number of overall MSHR miss cycles
577system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373162000 # number of ReadReq MSHR uncacheable cycles
578system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17619500 # number of ReadReq MSHR uncacheable cycles
579system.l2c.ReadReq_mshr_uncacheable_latency::total 1390781500 # number of ReadReq MSHR uncacheable cycles
580system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2149958500 # number of WriteReq MSHR uncacheable cycles
581system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674822000 # number of WriteReq MSHR uncacheable cycles
582system.l2c.WriteReq_mshr_uncacheable_latency::total 2824780500 # number of WriteReq MSHR uncacheable cycles
583system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3523120500 # number of overall MSHR uncacheable cycles
584system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692441500 # number of overall MSHR uncacheable cycles
585system.l2c.overall_mshr_uncacheable_latency::total 4215562000 # number of overall MSHR uncacheable cycles
586system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for ReadReq accesses
587system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.288990 # mshr miss rate for ReadReq accesses
588system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for ReadReq accesses
589system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002269 # mshr miss rate for ReadReq accesses
590system.l2c.ReadReq_mshr_miss_rate::total 0.138517 # mshr miss rate for ReadReq accesses
591system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941327 # mshr miss rate for UpgradeReq accesses
592system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766549 # mshr miss rate for UpgradeReq accesses
593system.l2c.UpgradeReq_mshr_miss_rate::total 0.868012 # mshr miss rate for UpgradeReq accesses
594system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.956897 # mshr miss rate for SCUpgradeReq accesses
595system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974277 # mshr miss rate for SCUpgradeReq accesses
596system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.965610 # mshr miss rate for SCUpgradeReq accesses
597system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.474683 # mshr miss rate for ReadExReq accesses
598system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.106621 # mshr miss rate for ReadExReq accesses
599system.l2c.ReadExReq_mshr_miss_rate::total 0.415830 # mshr miss rate for ReadExReq accesses
600system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for demand accesses
601system.l2c.demand_mshr_miss_rate::cpu0.data 0.327813 # mshr miss rate for demand accesses
602system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for demand accesses
603system.l2c.demand_mshr_miss_rate::cpu1.data 0.034791 # mshr miss rate for demand accesses
604system.l2c.demand_mshr_miss_rate::total 0.173326 # mshr miss rate for demand accesses
605system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018493 # mshr miss rate for overall accesses
606system.l2c.overall_mshr_miss_rate::cpu0.data 0.327813 # mshr miss rate for overall accesses
607system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001599 # mshr miss rate for overall accesses
608system.l2c.overall_mshr_miss_rate::cpu1.data 0.034791 # mshr miss rate for overall accesses
609system.l2c.overall_mshr_miss_rate::total 0.173326 # mshr miss rate for overall accesses
610system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average ReadReq mshr miss latency
611system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52653.001351 # average ReadReq mshr miss latency
612system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average ReadReq mshr miss latency
613system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 60892.405063 # average ReadReq mshr miss latency
614system.l2c.ReadReq_avg_mshr_miss_latency::total 53053.913569 # average ReadReq mshr miss latency
615system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.674797 # average UpgradeReq mshr miss latency
616system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
617system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.161868 # average UpgradeReq mshr miss latency
618system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
619system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
620system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
621system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55884.310050 # average ReadExReq mshr miss latency
622system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59621.283419 # average ReadExReq mshr miss latency
623system.l2c.ReadExReq_avg_mshr_miss_latency::total 56037.522980 # average ReadExReq mshr miss latency
624system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency
625system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency
626system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency
627system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency
628system.l2c.demand_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency
629system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60930.168933 # average overall mshr miss latency
630system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53631.237703 # average overall mshr miss latency
631system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62105.711423 # average overall mshr miss latency
632system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59678.350256 # average overall mshr miss latency
633system.l2c.overall_avg_mshr_miss_latency::total 53952.428163 # average overall mshr miss latency
634system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
635system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
636system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
637system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
638system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
639system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
640system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
641system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
642system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
643system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
644system.iocache.tags.replacements 41694 # number of replacements
645system.iocache.tags.tagsinuse 0.569649 # Cycle average of tags in use
646system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
647system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
648system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
649system.iocache.tags.warmup_cycle 1755503918000 # Cycle when the warmup percentage was hit.
650system.iocache.tags.occ_blocks::tsunami.ide 0.569649 # Average occupied blocks per requestor
651system.iocache.tags.occ_percent::tsunami.ide 0.035603 # Average percentage of cache occupancy
652system.iocache.tags.occ_percent::total 0.035603 # Average percentage of cache occupancy
653system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
654system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
655system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
656system.iocache.tags.tag_accesses 375534 # Number of tag accesses
657system.iocache.tags.data_accesses 375534 # Number of data accesses
658system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
659system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
660system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
661system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
662system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
663system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
664system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
665system.iocache.overall_misses::total 41726 # number of overall misses
666system.iocache.ReadReq_miss_latency::tsunami.ide 21248883 # number of ReadReq miss cycles
667system.iocache.ReadReq_miss_latency::total 21248883 # number of ReadReq miss cycles
668system.iocache.WriteReq_miss_latency::tsunami.ide 13129991411 # number of WriteReq miss cycles
669system.iocache.WriteReq_miss_latency::total 13129991411 # number of WriteReq miss cycles
670system.iocache.demand_miss_latency::tsunami.ide 13151240294 # number of demand (read+write) miss cycles
671system.iocache.demand_miss_latency::total 13151240294 # number of demand (read+write) miss cycles
672system.iocache.overall_miss_latency::tsunami.ide 13151240294 # number of overall miss cycles
673system.iocache.overall_miss_latency::total 13151240294 # number of overall miss cycles
674system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
675system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
676system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
677system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
678system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
679system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
680system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
681system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
682system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
683system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
684system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
685system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
686system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
687system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
688system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
689system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
690system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241 # average ReadReq miss latency
691system.iocache.ReadReq_avg_miss_latency::total 122120.017241 # average ReadReq miss latency
692system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684 # average WriteReq miss latency
693system.iocache.WriteReq_avg_miss_latency::total 315989.396684 # average WriteReq miss latency
694system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency
695system.iocache.demand_avg_miss_latency::total 315180.949384 # average overall miss latency
696system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency
697system.iocache.overall_avg_miss_latency::total 315180.949384 # average overall miss latency
698system.iocache.blocked_cycles::no_mshrs 388544 # number of cycles access was blocked
699system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
700system.iocache.blocked::no_mshrs 28481 # number of cycles access was blocked
701system.iocache.blocked::no_targets 0 # number of cycles access was blocked
702system.iocache.avg_blocked_cycles::no_mshrs 13.642218 # average number of cycles each access was blocked
703system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
704system.iocache.fast_writes 0 # number of fast writes performed
705system.iocache.cache_copies 0 # number of cache copies performed
706system.iocache.writebacks::writebacks 41520 # number of writebacks
707system.iocache.writebacks::total 41520 # number of writebacks
708system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
709system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
710system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
711system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
712system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
713system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
714system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
715system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
716system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199883 # number of ReadReq MSHR miss cycles
717system.iocache.ReadReq_mshr_miss_latency::total 12199883 # number of ReadReq MSHR miss cycles
718system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10966952411 # number of WriteReq MSHR miss cycles
719system.iocache.WriteReq_mshr_miss_latency::total 10966952411 # number of WriteReq MSHR miss cycles
720system.iocache.demand_mshr_miss_latency::tsunami.ide 10979152294 # number of demand (read+write) MSHR miss cycles
721system.iocache.demand_mshr_miss_latency::total 10979152294 # number of demand (read+write) MSHR miss cycles
722system.iocache.overall_mshr_miss_latency::tsunami.ide 10979152294 # number of overall MSHR miss cycles
723system.iocache.overall_mshr_miss_latency::total 10979152294 # number of overall MSHR miss cycles
724system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
725system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
726system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
727system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
728system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
729system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
730system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
731system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
732system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115 # average ReadReq mshr miss latency
733system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115 # average ReadReq mshr miss latency
734system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036 # average WriteReq mshr miss latency
735system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036 # average WriteReq mshr miss latency
736system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency
737system.iocache.demand_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency
738system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency
739system.iocache.overall_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency
740system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
741system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
742system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
743system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
744system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
745system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
746system.disk0.dma_write_txs 395 # Number of DMA write transactions.
747system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
748system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
749system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
750system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
751system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
752system.disk2.dma_write_txs 1 # Number of DMA write transactions.
753system.cpu0.dtb.fetch_hits 0 # ITB hits
754system.cpu0.dtb.fetch_misses 0 # ITB misses
755system.cpu0.dtb.fetch_acv 0 # ITB acv
756system.cpu0.dtb.fetch_accesses 0 # ITB accesses
757system.cpu0.dtb.read_hits 7562587 # DTB read hits
758system.cpu0.dtb.read_misses 7765 # DTB read misses
759system.cpu0.dtb.read_acv 210 # DTB read access violations
760system.cpu0.dtb.read_accesses 524069 # DTB read accesses
761system.cpu0.dtb.write_hits 5147352 # DTB write hits
762system.cpu0.dtb.write_misses 910 # DTB write misses
763system.cpu0.dtb.write_acv 133 # DTB write access violations
764system.cpu0.dtb.write_accesses 202595 # DTB write accesses
765system.cpu0.dtb.data_hits 12709939 # DTB hits
766system.cpu0.dtb.data_misses 8675 # DTB misses
767system.cpu0.dtb.data_acv 343 # DTB access violations
768system.cpu0.dtb.data_accesses 726664 # DTB accesses
769system.cpu0.itb.fetch_hits 3660806 # ITB hits
770system.cpu0.itb.fetch_misses 3984 # ITB misses
771system.cpu0.itb.fetch_acv 184 # ITB acv
772system.cpu0.itb.fetch_accesses 3664790 # ITB accesses
773system.cpu0.itb.read_hits 0 # DTB read hits
774system.cpu0.itb.read_misses 0 # DTB read misses
775system.cpu0.itb.read_acv 0 # DTB read access violations
776system.cpu0.itb.read_accesses 0 # DTB read accesses
777system.cpu0.itb.write_hits 0 # DTB write hits
778system.cpu0.itb.write_misses 0 # DTB write misses
779system.cpu0.itb.write_acv 0 # DTB write access violations
780system.cpu0.itb.write_accesses 0 # DTB write accesses
781system.cpu0.itb.data_hits 0 # DTB hits
782system.cpu0.itb.data_misses 0 # DTB misses
783system.cpu0.itb.data_acv 0 # DTB access violations
784system.cpu0.itb.data_accesses 0 # DTB accesses
785system.cpu0.numCycles 3923627139 # number of cpu cycles simulated
786system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
787system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
788system.cpu0.committedInsts 48127942 # Number of instructions committed
789system.cpu0.committedOps 48127942 # Number of ops (including micro ops) committed
790system.cpu0.num_int_alu_accesses 44644072 # Number of integer alu accesses
791system.cpu0.num_fp_alu_accesses 213646 # Number of float alu accesses
792system.cpu0.num_func_calls 1209779 # number of times a function call or return occured
793system.cpu0.num_conditional_control_insts 5646914 # number of instructions that are conditional controls
794system.cpu0.num_int_insts 44644072 # number of integer instructions
795system.cpu0.num_fp_insts 213646 # number of float instructions
796system.cpu0.num_int_register_reads 61387929 # number of times the integer registers were read
797system.cpu0.num_int_register_writes 33243119 # number of times the integer registers were written
798system.cpu0.num_fp_register_reads 104403 # number of times the floating registers were read
799system.cpu0.num_fp_register_writes 106204 # number of times the floating registers were written
800system.cpu0.num_mem_refs 12751056 # number of memory refs
801system.cpu0.num_load_insts 7590434 # Number of load instructions
802system.cpu0.num_store_insts 5160622 # Number of store instructions
803system.cpu0.num_idle_cycles 3699531471.998114 # Number of idle cycles
804system.cpu0.num_busy_cycles 224095667.001886 # Number of busy cycles
805system.cpu0.not_idle_fraction 0.057114 # Percentage of non-idle cycles
806system.cpu0.idle_fraction 0.942886 # Percentage of idle cycles
807system.cpu0.Branches 7246727 # Number of branches fetched
808system.cpu0.kern.inst.arm 0 # number of arm instructions executed
809system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed
810system.cpu0.kern.inst.hwrei 166332 # number of hwrei instructions executed
811system.cpu0.kern.ipl_count::0 57240 40.25% 40.25% # number of times we switched to this ipl
812system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl
813system.cpu0.kern.ipl_count::22 1974 1.39% 41.73% # number of times we switched to this ipl
814system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl
815system.cpu0.kern.ipl_count::31 82451 57.97% 100.00% # number of times we switched to this ipl
816system.cpu0.kern.ipl_count::total 142220 # number of times we switched to this ipl
817system.cpu0.kern.ipl_good::0 56707 49.09% 49.09% # number of times we switched to this ipl from a different ipl
818system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
819system.cpu0.kern.ipl_good::22 1974 1.71% 50.91% # number of times we switched to this ipl from a different ipl
820system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl
821system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl
822system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl
823system.cpu0.kern.ipl_ticks::0 1902164041000 96.96% 96.96% # number of cycles we spent at this ipl
824system.cpu0.kern.ipl_ticks::21 95225000 0.00% 96.96% # number of cycles we spent at this ipl
825system.cpu0.kern.ipl_ticks::22 767277500 0.04% 97.00% # number of cycles we spent at this ipl
826system.cpu0.kern.ipl_ticks::30 314374500 0.02% 97.02% # number of cycles we spent at this ipl
827system.cpu0.kern.ipl_ticks::31 58471894000 2.98% 100.00% # number of cycles we spent at this ipl
828system.cpu0.kern.ipl_ticks::total 1961812812000 # number of cycles we spent at this ipl
829system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl
830system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
831system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
832system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
833system.cpu0.kern.ipl_used::31 0.682624 # fraction of swpipl calls that actually changed the ipl
834system.cpu0.kern.ipl_used::total 0.812256 # fraction of swpipl calls that actually changed the ipl
835system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
836system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
837system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
838system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
839system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
840system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
841system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
842system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed

--- 15 unchanged lines hidden (view full) ---

858system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
859system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
860system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
861system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
862system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
863system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
864system.cpu0.kern.syscall::total 234 # number of syscalls executed
865system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
866system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed
867system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
868system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
869system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
870system.cpu0.kern.callpal::swpctx 3107 2.06% 2.40% # number of callpals executed
871system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed
872system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed
873system.cpu0.kern.callpal::swpipl 135267 89.81% 92.25% # number of callpals executed
874system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed
875system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed
876system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed
877system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed
878system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed
879system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed
880system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed
881system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
882system.cpu0.kern.callpal::total 150615 # number of callpals executed
883system.cpu0.kern.mode_switch::kernel 7022 # number of protection mode switches
884system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches
885system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
886system.cpu0.kern.mode_good::kernel 1371
887system.cpu0.kern.mode_good::user 1372
888system.cpu0.kern.mode_good::idle 0
889system.cpu0.kern.mode_switch_good::kernel 0.195244 # fraction of useful protection mode switches
890system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
891system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
892system.cpu0.kern.mode_switch_good::total 0.326781 # fraction of useful protection mode switches
893system.cpu0.kern.mode_ticks::kernel 1958041026500 99.81% 99.81% # number of ticks spent at the given mode
894system.cpu0.kern.mode_ticks::user 3771781000 0.19% 100.00% # number of ticks spent at the given mode
895system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
896system.cpu0.kern.swap_context 3108 # number of times the context was actually changed
897system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
898system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
899system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
900system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
901system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
902system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
903system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
904system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

920system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
921system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
922system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
923system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
924system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
925system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
926system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
927system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
928system.toL2Bus.throughput 103965077 # Throughput (bytes/s)
929system.toL2Bus.trans_dist::ReadReq 2102306 # Transaction distribution
930system.toL2Bus.trans_dist::ReadResp 2102291 # Transaction distribution
931system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution
932system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution
933system.toL2Bus.trans_dist::Writeback 792911 # Transaction distribution
934system.toL2Bus.trans_dist::UpgradeReq 16363 # Transaction distribution
935system.toL2Bus.trans_dist::SCUpgradeReq 11335 # Transaction distribution
936system.toL2Bus.trans_dist::UpgradeResp 27698 # Transaction distribution
937system.toL2Bus.trans_dist::ReadExReq 339143 # Transaction distribution
938system.toL2Bus.trans_dist::ReadExResp 297593 # Transaction distribution
939system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407788 # Packet count per connected master and slave (bytes)
940system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134857 # Packet count per connected master and slave (bytes)
941system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624045 # Packet count per connected master and slave (bytes)
942system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452421 # Packet count per connected master and slave (bytes)
943system.toL2Bus.pkt_count::total 5619111 # Packet count per connected master and slave (bytes)
944system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45048576 # Cumulative packet size per connected master and slave (bytes)
945system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120057312 # Cumulative packet size per connected master and slave (bytes)
946system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19969408 # Cumulative packet size per connected master and slave (bytes)
947system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16548674 # Cumulative packet size per connected master and slave (bytes)
948system.toL2Bus.tot_pkt_size::total 201623970 # Cumulative packet size per connected master and slave (bytes)
949system.toL2Bus.data_through_bus 201613666 # Total data (bytes)
950system.toL2Bus.snoop_data_through_bus 2346432 # Total snoop data (bytes)
951system.toL2Bus.reqLayer0.occupancy 4795947858 # Layer occupancy (ticks)
952system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
953system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
954system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
955system.toL2Bus.respLayer0.occupancy 3170057255 # Layer occupancy (ticks)
956system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
957system.toL2Bus.respLayer1.occupancy 5536383084 # Layer occupancy (ticks)
958system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
959system.toL2Bus.respLayer2.occupancy 1404201241 # Layer occupancy (ticks)
960system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
961system.toL2Bus.respLayer3.occupancy 776393157 # Layer occupancy (ticks)
962system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
963system.iobus.throughput 1398487 # Throughput (bytes/s)
964system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
965system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
966system.iobus.trans_dist::WriteReq 55619 # Transaction distribution
967system.iobus.trans_dist::WriteResp 55619 # Transaction distribution
968system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes)
969system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
970system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
971system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
972system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
973system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
974system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
975system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
976system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
977system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
978system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
979system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
980system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes)
981system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
982system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
983system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes)
984system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes)
985system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
986system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
987system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
988system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
989system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
990system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
991system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
992system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
993system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
994system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
995system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
996system.iobus.tot_pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes)
997system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
998system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
999system.iobus.tot_pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes)
1000system.iobus.data_through_bus 2743570 # Total data (bytes)
1001system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks)
1002system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1003system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1004system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1005system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1006system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1007system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1008system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1009system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1010system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1011system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1012system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1013system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
1014system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1015system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1016system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1017system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1018system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1019system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1020system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1021system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1022system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1023system.iobus.reqLayer29.occupancy 380082294 # Layer occupancy (ticks)
1024system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1025system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1026system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1027system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks)
1028system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1029system.iobus.respLayer1.occupancy 43185000 # Layer occupancy (ticks)
1030system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1031system.cpu0.icache.tags.replacements 703274 # number of replacements
1032system.cpu0.icache.tags.tagsinuse 508.380970 # Cycle average of tags in use
1033system.cpu0.icache.tags.total_refs 47433057 # Total number of references to valid blocks.
1034system.cpu0.icache.tags.sampled_refs 703786 # Sample count of references to valid blocks.
1035system.cpu0.icache.tags.avg_refs 67.396989 # Average number of references to valid blocks.
1036system.cpu0.icache.tags.warmup_cycle 40278267250 # Cycle when the warmup percentage was hit.
1037system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.380970 # Average occupied blocks per requestor
1038system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992932 # Average percentage of cache occupancy
1039system.cpu0.icache.tags.occ_percent::total 0.992932 # Average percentage of cache occupancy
1040system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1041system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
1042system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
1043system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id
1044system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
1045system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1046system.cpu0.icache.tags.tag_accesses 48840865 # Number of tag accesses
1047system.cpu0.icache.tags.data_accesses 48840865 # Number of data accesses
1048system.cpu0.icache.ReadReq_hits::cpu0.inst 47433057 # number of ReadReq hits
1049system.cpu0.icache.ReadReq_hits::total 47433057 # number of ReadReq hits
1050system.cpu0.icache.demand_hits::cpu0.inst 47433057 # number of demand (read+write) hits
1051system.cpu0.icache.demand_hits::total 47433057 # number of demand (read+write) hits
1052system.cpu0.icache.overall_hits::cpu0.inst 47433057 # number of overall hits
1053system.cpu0.icache.overall_hits::total 47433057 # number of overall hits
1054system.cpu0.icache.ReadReq_misses::cpu0.inst 703904 # number of ReadReq misses
1055system.cpu0.icache.ReadReq_misses::total 703904 # number of ReadReq misses
1056system.cpu0.icache.demand_misses::cpu0.inst 703904 # number of demand (read+write) misses
1057system.cpu0.icache.demand_misses::total 703904 # number of demand (read+write) misses
1058system.cpu0.icache.overall_misses::cpu0.inst 703904 # number of overall misses
1059system.cpu0.icache.overall_misses::total 703904 # number of overall misses
1060system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10025783755 # number of ReadReq miss cycles
1061system.cpu0.icache.ReadReq_miss_latency::total 10025783755 # number of ReadReq miss cycles
1062system.cpu0.icache.demand_miss_latency::cpu0.inst 10025783755 # number of demand (read+write) miss cycles
1063system.cpu0.icache.demand_miss_latency::total 10025783755 # number of demand (read+write) miss cycles
1064system.cpu0.icache.overall_miss_latency::cpu0.inst 10025783755 # number of overall miss cycles
1065system.cpu0.icache.overall_miss_latency::total 10025783755 # number of overall miss cycles
1066system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136961 # number of ReadReq accesses(hits+misses)
1067system.cpu0.icache.ReadReq_accesses::total 48136961 # number of ReadReq accesses(hits+misses)
1068system.cpu0.icache.demand_accesses::cpu0.inst 48136961 # number of demand (read+write) accesses
1069system.cpu0.icache.demand_accesses::total 48136961 # number of demand (read+write) accesses
1070system.cpu0.icache.overall_accesses::cpu0.inst 48136961 # number of overall (read+write) accesses
1071system.cpu0.icache.overall_accesses::total 48136961 # number of overall (read+write) accesses
1072system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014623 # miss rate for ReadReq accesses
1073system.cpu0.icache.ReadReq_miss_rate::total 0.014623 # miss rate for ReadReq accesses
1074system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014623 # miss rate for demand accesses
1075system.cpu0.icache.demand_miss_rate::total 0.014623 # miss rate for demand accesses
1076system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014623 # miss rate for overall accesses
1077system.cpu0.icache.overall_miss_rate::total 0.014623 # miss rate for overall accesses
1078system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14243.112349 # average ReadReq miss latency
1079system.cpu0.icache.ReadReq_avg_miss_latency::total 14243.112349 # average ReadReq miss latency
1080system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency
1081system.cpu0.icache.demand_avg_miss_latency::total 14243.112349 # average overall miss latency
1082system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency
1083system.cpu0.icache.overall_avg_miss_latency::total 14243.112349 # average overall miss latency
1084system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1085system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1086system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1087system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1088system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1089system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1090system.cpu0.icache.fast_writes 0 # number of fast writes performed
1091system.cpu0.icache.cache_copies 0 # number of cache copies performed
1092system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703904 # number of ReadReq MSHR misses
1093system.cpu0.icache.ReadReq_mshr_misses::total 703904 # number of ReadReq MSHR misses
1094system.cpu0.icache.demand_mshr_misses::cpu0.inst 703904 # number of demand (read+write) MSHR misses
1095system.cpu0.icache.demand_mshr_misses::total 703904 # number of demand (read+write) MSHR misses
1096system.cpu0.icache.overall_mshr_misses::cpu0.inst 703904 # number of overall MSHR misses
1097system.cpu0.icache.overall_mshr_misses::total 703904 # number of overall MSHR misses
1098system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8612997245 # number of ReadReq MSHR miss cycles
1099system.cpu0.icache.ReadReq_mshr_miss_latency::total 8612997245 # number of ReadReq MSHR miss cycles
1100system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8612997245 # number of demand (read+write) MSHR miss cycles
1101system.cpu0.icache.demand_mshr_miss_latency::total 8612997245 # number of demand (read+write) MSHR miss cycles
1102system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8612997245 # number of overall MSHR miss cycles
1103system.cpu0.icache.overall_mshr_miss_latency::total 8612997245 # number of overall MSHR miss cycles
1104system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for ReadReq accesses
1105system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014623 # mshr miss rate for ReadReq accesses
1106system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for demand accesses
1107system.cpu0.icache.demand_mshr_miss_rate::total 0.014623 # mshr miss rate for demand accesses
1108system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for overall accesses
1109system.cpu0.icache.overall_mshr_miss_rate::total 0.014623 # mshr miss rate for overall accesses
1110system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average ReadReq mshr miss latency
1111system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12236.039638 # average ReadReq mshr miss latency
1112system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency
1113system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency
1114system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency
1115system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency
1116system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1117system.cpu0.dcache.tags.replacements 1191290 # number of replacements
1118system.cpu0.dcache.tags.tagsinuse 505.228160 # Cycle average of tags in use
1119system.cpu0.dcache.tags.total_refs 11513399 # Total number of references to valid blocks.
1120system.cpu0.dcache.tags.sampled_refs 1191802 # Sample count of references to valid blocks.
1121system.cpu0.dcache.tags.avg_refs 9.660496 # Average number of references to valid blocks.
1122system.cpu0.dcache.tags.warmup_cycle 108508250 # Cycle when the warmup percentage was hit.
1123system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.228160 # Average occupied blocks per requestor
1124system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986774 # Average percentage of cache occupancy
1125system.cpu0.dcache.tags.occ_percent::total 0.986774 # Average percentage of cache occupancy
1126system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1127system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
1128system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
1129system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
1130system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1131system.cpu0.dcache.tags.tag_accesses 52084916 # Number of tag accesses
1132system.cpu0.dcache.tags.data_accesses 52084916 # Number of data accesses
1133system.cpu0.dcache.ReadReq_hits::cpu0.data 6477391 # number of ReadReq hits
1134system.cpu0.dcache.ReadReq_hits::total 6477391 # number of ReadReq hits
1135system.cpu0.dcache.WriteReq_hits::cpu0.data 4731575 # number of WriteReq hits
1136system.cpu0.dcache.WriteReq_hits::total 4731575 # number of WriteReq hits
1137system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141550 # number of LoadLockedReq hits
1138system.cpu0.dcache.LoadLockedReq_hits::total 141550 # number of LoadLockedReq hits
1139system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149263 # number of StoreCondReq hits
1140system.cpu0.dcache.StoreCondReq_hits::total 149263 # number of StoreCondReq hits
1141system.cpu0.dcache.demand_hits::cpu0.data 11208966 # number of demand (read+write) hits
1142system.cpu0.dcache.demand_hits::total 11208966 # number of demand (read+write) hits
1143system.cpu0.dcache.overall_hits::cpu0.data 11208966 # number of overall hits
1144system.cpu0.dcache.overall_hits::total 11208966 # number of overall hits
1145system.cpu0.dcache.ReadReq_misses::cpu0.data 942691 # number of ReadReq misses
1146system.cpu0.dcache.ReadReq_misses::total 942691 # number of ReadReq misses
1147system.cpu0.dcache.WriteReq_misses::cpu0.data 258024 # number of WriteReq misses
1148system.cpu0.dcache.WriteReq_misses::total 258024 # number of WriteReq misses
1149system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13717 # number of LoadLockedReq misses
1150system.cpu0.dcache.LoadLockedReq_misses::total 13717 # number of LoadLockedReq misses
1151system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses
1152system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses
1153system.cpu0.dcache.demand_misses::cpu0.data 1200715 # number of demand (read+write) misses
1154system.cpu0.dcache.demand_misses::total 1200715 # number of demand (read+write) misses
1155system.cpu0.dcache.overall_misses::cpu0.data 1200715 # number of overall misses
1156system.cpu0.dcache.overall_misses::total 1200715 # number of overall misses
1157system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27259981257 # number of ReadReq miss cycles
1158system.cpu0.dcache.ReadReq_miss_latency::total 27259981257 # number of ReadReq miss cycles
1159system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10282729939 # number of WriteReq miss cycles
1160system.cpu0.dcache.WriteReq_miss_latency::total 10282729939 # number of WriteReq miss cycles
1161system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150891500 # number of LoadLockedReq miss cycles
1162system.cpu0.dcache.LoadLockedReq_miss_latency::total 150891500 # number of LoadLockedReq miss cycles
1163system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 41989388 # number of StoreCondReq miss cycles
1164system.cpu0.dcache.StoreCondReq_miss_latency::total 41989388 # number of StoreCondReq miss cycles
1165system.cpu0.dcache.demand_miss_latency::cpu0.data 37542711196 # number of demand (read+write) miss cycles
1166system.cpu0.dcache.demand_miss_latency::total 37542711196 # number of demand (read+write) miss cycles
1167system.cpu0.dcache.overall_miss_latency::cpu0.data 37542711196 # number of overall miss cycles
1168system.cpu0.dcache.overall_miss_latency::total 37542711196 # number of overall miss cycles
1169system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420082 # number of ReadReq accesses(hits+misses)
1170system.cpu0.dcache.ReadReq_accesses::total 7420082 # number of ReadReq accesses(hits+misses)
1171system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989599 # number of WriteReq accesses(hits+misses)
1172system.cpu0.dcache.WriteReq_accesses::total 4989599 # number of WriteReq accesses(hits+misses)
1173system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155267 # number of LoadLockedReq accesses(hits+misses)
1174system.cpu0.dcache.LoadLockedReq_accesses::total 155267 # number of LoadLockedReq accesses(hits+misses)
1175system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154715 # number of StoreCondReq accesses(hits+misses)
1176system.cpu0.dcache.StoreCondReq_accesses::total 154715 # number of StoreCondReq accesses(hits+misses)
1177system.cpu0.dcache.demand_accesses::cpu0.data 12409681 # number of demand (read+write) accesses
1178system.cpu0.dcache.demand_accesses::total 12409681 # number of demand (read+write) accesses
1179system.cpu0.dcache.overall_accesses::cpu0.data 12409681 # number of overall (read+write) accesses
1180system.cpu0.dcache.overall_accesses::total 12409681 # number of overall (read+write) accesses
1181system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127046 # miss rate for ReadReq accesses
1182system.cpu0.dcache.ReadReq_miss_rate::total 0.127046 # miss rate for ReadReq accesses
1183system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051712 # miss rate for WriteReq accesses
1184system.cpu0.dcache.WriteReq_miss_rate::total 0.051712 # miss rate for WriteReq accesses
1185system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088345 # miss rate for LoadLockedReq accesses
1186system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088345 # miss rate for LoadLockedReq accesses
1187system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035239 # miss rate for StoreCondReq accesses
1188system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035239 # miss rate for StoreCondReq accesses
1189system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096756 # miss rate for demand accesses
1190system.cpu0.dcache.demand_miss_rate::total 0.096756 # miss rate for demand accesses
1191system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096756 # miss rate for overall accesses
1192system.cpu0.dcache.overall_miss_rate::total 0.096756 # miss rate for overall accesses
1193system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894 # average ReadReq miss latency
1194system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894 # average ReadReq miss latency
1195system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252 # average WriteReq miss latency
1196system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252 # average WriteReq miss latency
1197system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060 # average LoadLockedReq miss latency
1198system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060 # average LoadLockedReq miss latency
1199system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7701.648569 # average StoreCondReq miss latency
1200system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7701.648569 # average StoreCondReq miss latency
1201system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency
1202system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765 # average overall miss latency
1203system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency
1204system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765 # average overall miss latency
1205system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1206system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1207system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1208system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1209system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1210system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1211system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1212system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1213system.cpu0.dcache.writebacks::writebacks 686471 # number of writebacks
1214system.cpu0.dcache.writebacks::total 686471 # number of writebacks
1215system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942691 # number of ReadReq MSHR misses
1216system.cpu0.dcache.ReadReq_mshr_misses::total 942691 # number of ReadReq MSHR misses
1217system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258024 # number of WriteReq MSHR misses
1218system.cpu0.dcache.WriteReq_mshr_misses::total 258024 # number of WriteReq MSHR misses
1219system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13717 # number of LoadLockedReq MSHR misses
1220system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13717 # number of LoadLockedReq MSHR misses
1221system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses
1222system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses
1223system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200715 # number of demand (read+write) MSHR misses
1224system.cpu0.dcache.demand_mshr_misses::total 1200715 # number of demand (read+write) MSHR misses
1225system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200715 # number of overall MSHR misses
1226system.cpu0.dcache.overall_mshr_misses::total 1200715 # number of overall MSHR misses
1227system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25249299743 # number of ReadReq MSHR miss cycles
1228system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25249299743 # number of ReadReq MSHR miss cycles
1229system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9714288061 # number of WriteReq MSHR miss cycles
1230system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9714288061 # number of WriteReq MSHR miss cycles
1231system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 123443500 # number of LoadLockedReq MSHR miss cycles
1232system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 123443500 # number of LoadLockedReq MSHR miss cycles
1233system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31083612 # number of StoreCondReq MSHR miss cycles
1234system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31083612 # number of StoreCondReq MSHR miss cycles
1235system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34963587804 # number of demand (read+write) MSHR miss cycles
1236system.cpu0.dcache.demand_mshr_miss_latency::total 34963587804 # number of demand (read+write) MSHR miss cycles
1237system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34963587804 # number of overall MSHR miss cycles
1238system.cpu0.dcache.overall_mshr_miss_latency::total 34963587804 # number of overall MSHR miss cycles
1239system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles
1240system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles
1241system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2280051500 # number of WriteReq MSHR uncacheable cycles
1242system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2280051500 # number of WriteReq MSHR uncacheable cycles
1243system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3745653500 # number of overall MSHR uncacheable cycles
1244system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3745653500 # number of overall MSHR uncacheable cycles
1245system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127046 # mshr miss rate for ReadReq accesses
1246system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127046 # mshr miss rate for ReadReq accesses
1247system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051712 # mshr miss rate for WriteReq accesses
1248system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051712 # mshr miss rate for WriteReq accesses
1249system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088345 # mshr miss rate for LoadLockedReq accesses
1250system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088345 # mshr miss rate for LoadLockedReq accesses
1251system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035239 # mshr miss rate for StoreCondReq accesses
1252system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035239 # mshr miss rate for StoreCondReq accesses
1253system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for demand accesses
1254system.cpu0.dcache.demand_mshr_miss_rate::total 0.096756 # mshr miss rate for demand accesses
1255system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096756 # mshr miss rate for overall accesses
1256system.cpu0.dcache.overall_mshr_miss_rate::total 0.096756 # mshr miss rate for overall accesses
1257system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26784.280048 # average ReadReq mshr miss latency
1258system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26784.280048 # average ReadReq mshr miss latency
1259system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37648.777094 # average WriteReq mshr miss latency
1260system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37648.777094 # average WriteReq mshr miss latency
1261system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8999.307429 # average LoadLockedReq mshr miss latency
1262system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8999.307429 # average LoadLockedReq mshr miss latency
1263system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5701.322817 # average StoreCondReq mshr miss latency
1264system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5701.322817 # average StoreCondReq mshr miss latency
1265system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency
1266system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency
1267system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29118.973115 # average overall mshr miss latency
1268system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29118.973115 # average overall mshr miss latency
1269system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1270system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1271system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1272system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1273system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1274system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1275system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1276system.cpu1.dtb.fetch_hits 0 # ITB hits
1277system.cpu1.dtb.fetch_misses 0 # ITB misses
1278system.cpu1.dtb.fetch_acv 0 # ITB acv
1279system.cpu1.dtb.fetch_accesses 0 # ITB accesses
1280system.cpu1.dtb.read_hits 2348422 # DTB read hits
1281system.cpu1.dtb.read_misses 2620 # DTB read misses
1282system.cpu1.dtb.read_acv 0 # DTB read access violations
1283system.cpu1.dtb.read_accesses 205337 # DTB read accesses
1284system.cpu1.dtb.write_hits 1677006 # DTB write hits
1285system.cpu1.dtb.write_misses 235 # DTB write misses
1286system.cpu1.dtb.write_acv 24 # DTB write access violations
1287system.cpu1.dtb.write_accesses 89739 # DTB write accesses
1288system.cpu1.dtb.data_hits 4025428 # DTB hits
1289system.cpu1.dtb.data_misses 2855 # DTB misses
1290system.cpu1.dtb.data_acv 24 # DTB access violations
1291system.cpu1.dtb.data_accesses 295076 # DTB accesses
1292system.cpu1.itb.fetch_hits 1801062 # ITB hits
1293system.cpu1.itb.fetch_misses 1064 # ITB misses
1294system.cpu1.itb.fetch_acv 0 # ITB acv
1295system.cpu1.itb.fetch_accesses 1802126 # ITB accesses
1296system.cpu1.itb.read_hits 0 # DTB read hits
1297system.cpu1.itb.read_misses 0 # DTB read misses
1298system.cpu1.itb.read_acv 0 # DTB read access violations
1299system.cpu1.itb.read_accesses 0 # DTB read accesses
1300system.cpu1.itb.write_hits 0 # DTB write hits
1301system.cpu1.itb.write_misses 0 # DTB write misses
1302system.cpu1.itb.write_acv 0 # DTB write access violations
1303system.cpu1.itb.write_accesses 0 # DTB write accesses
1304system.cpu1.itb.data_hits 0 # DTB hits
1305system.cpu1.itb.data_misses 0 # DTB misses
1306system.cpu1.itb.data_acv 0 # DTB access violations
1307system.cpu1.itb.data_accesses 0 # DTB accesses
1308system.cpu1.numCycles 3921881188 # number of cpu cycles simulated
1309system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1310system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1311system.cpu1.committedInsts 12764983 # Number of instructions committed
1312system.cpu1.committedOps 12764983 # Number of ops (including micro ops) committed
1313system.cpu1.num_int_alu_accesses 11763372 # Number of integer alu accesses
1314system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses
1315system.cpu1.num_func_calls 404056 # number of times a function call or return occured
1316system.cpu1.num_conditional_control_insts 1265589 # number of instructions that are conditional controls
1317system.cpu1.num_int_insts 11763372 # number of integer instructions
1318system.cpu1.num_fp_insts 170364 # number of float instructions
1319system.cpu1.num_int_register_reads 16177579 # number of times the integer registers were read
1320system.cpu1.num_int_register_writes 8656447 # number of times the integer registers were written
1321system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read
1322system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written
1323system.cpu1.num_mem_refs 4047975 # number of memory refs
1324system.cpu1.num_load_insts 2361944 # Number of load instructions
1325system.cpu1.num_store_insts 1686031 # Number of store instructions
1326system.cpu1.num_idle_cycles 3873256564.808130 # Number of idle cycles
1327system.cpu1.num_busy_cycles 48624623.191870 # Number of busy cycles
1328system.cpu1.not_idle_fraction 0.012398 # Percentage of non-idle cycles
1329system.cpu1.idle_fraction 0.987602 # Percentage of idle cycles
1330system.cpu1.Branches 1821589 # Number of branches fetched
1331system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1332system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed
1333system.cpu1.kern.inst.hwrei 77081 # number of hwrei instructions executed
1334system.cpu1.kern.ipl_count::0 26132 38.19% 38.19% # number of times we switched to this ipl
1335system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl
1336system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl
1337system.cpu1.kern.ipl_count::31 39821 58.19% 100.00% # number of times we switched to this ipl
1338system.cpu1.kern.ipl_count::total 68428 # number of times we switched to this ipl
1339system.cpu1.kern.ipl_good::0 25288 48.13% 48.13% # number of times we switched to this ipl from a different ipl
1340system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl
1341system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl
1342system.cpu1.kern.ipl_good::31 24782 47.16% 100.00% # number of times we switched to this ipl from a different ipl
1343system.cpu1.kern.ipl_good::total 52545 # number of times we switched to this ipl from a different ipl
1344system.cpu1.kern.ipl_ticks::0 1909614205500 97.38% 97.38% # number of cycles we spent at this ipl
1345system.cpu1.kern.ipl_ticks::22 700881500 0.04% 97.42% # number of cycles we spent at this ipl
1346system.cpu1.kern.ipl_ticks::30 353850000 0.02% 97.44% # number of cycles we spent at this ipl
1347system.cpu1.kern.ipl_ticks::31 50271627000 2.56% 100.00% # number of cycles we spent at this ipl
1348system.cpu1.kern.ipl_ticks::total 1960940564000 # number of cycles we spent at this ipl
1349system.cpu1.kern.ipl_used::0 0.967702 # fraction of swpipl calls that actually changed the ipl
1350system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1351system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
1352system.cpu1.kern.ipl_used::31 0.622335 # fraction of swpipl calls that actually changed the ipl
1353system.cpu1.kern.ipl_used::total 0.767887 # fraction of swpipl calls that actually changed the ipl
1354system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
1355system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
1356system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
1357system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
1358system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
1359system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
1360system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
1361system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
1362system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
1363system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
1364system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
1365system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
1366system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
1367system.cpu1.kern.syscall::total 92 # number of syscalls executed
1368system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
1369system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed
1370system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
1371system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
1372system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed
1373system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed
1374system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed
1375system.cpu1.kern.callpal::swpipl 62267 88.12% 91.51% # number of callpals executed
1376system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed
1377system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed
1378system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed
1379system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed
1380system.cpu1.kern.callpal::rti 3685 5.22% 99.77% # number of callpals executed
1381system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
1382system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
1383system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
1384system.cpu1.kern.callpal::total 70661 # number of callpals executed
1385system.cpu1.kern.mode_switch::kernel 1917 # number of protection mode switches
1386system.cpu1.kern.mode_switch::user 368 # number of protection mode switches
1387system.cpu1.kern.mode_switch::idle 2889 # number of protection mode switches
1388system.cpu1.kern.mode_good::kernel 798
1389system.cpu1.kern.mode_good::user 368
1390system.cpu1.kern.mode_good::idle 430
1391system.cpu1.kern.mode_switch_good::kernel 0.416275 # fraction of useful protection mode switches
1392system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1393system.cpu1.kern.mode_switch_good::idle 0.148840 # fraction of useful protection mode switches
1394system.cpu1.kern.mode_switch_good::total 0.308465 # fraction of useful protection mode switches
1395system.cpu1.kern.mode_ticks::kernel 17543884000 0.90% 0.90% # number of ticks spent at the given mode
1396system.cpu1.kern.mode_ticks::user 1484004500 0.08% 0.97% # number of ticks spent at the given mode
1397system.cpu1.kern.mode_ticks::idle 1941017048000 99.03% 100.00% # number of ticks spent at the given mode
1398system.cpu1.kern.swap_context 1956 # number of times the context was actually changed
1399system.cpu1.icache.tags.replacements 311472 # number of replacements
1400system.cpu1.icache.tags.tagsinuse 449.263709 # Cycle average of tags in use
1401system.cpu1.icache.tags.total_refs 12455839 # Total number of references to valid blocks.
1402system.cpu1.icache.tags.sampled_refs 311983 # Sample count of references to valid blocks.
1403system.cpu1.icache.tags.avg_refs 39.924736 # Average number of references to valid blocks.
1404system.cpu1.icache.tags.warmup_cycle 1960006992500 # Cycle when the warmup percentage was hit.
1405system.cpu1.icache.tags.occ_blocks::cpu1.inst 449.263709 # Average occupied blocks per requestor
1406system.cpu1.icache.tags.occ_percent::cpu1.inst 0.877468 # Average percentage of cache occupancy
1407system.cpu1.icache.tags.occ_percent::total 0.877468 # Average percentage of cache occupancy
1408system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
1409system.cpu1.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id
1410system.cpu1.icache.tags.age_task_id_blocks_1024::3 437 # Occupied blocks per task id
1411system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
1412system.cpu1.icache.tags.tag_accesses 13079885 # Number of tag accesses
1413system.cpu1.icache.tags.data_accesses 13079885 # Number of data accesses
1414system.cpu1.icache.ReadReq_hits::cpu1.inst 12455839 # number of ReadReq hits
1415system.cpu1.icache.ReadReq_hits::total 12455839 # number of ReadReq hits
1416system.cpu1.icache.demand_hits::cpu1.inst 12455839 # number of demand (read+write) hits
1417system.cpu1.icache.demand_hits::total 12455839 # number of demand (read+write) hits
1418system.cpu1.icache.overall_hits::cpu1.inst 12455839 # number of overall hits
1419system.cpu1.icache.overall_hits::total 12455839 # number of overall hits
1420system.cpu1.icache.ReadReq_misses::cpu1.inst 312023 # number of ReadReq misses
1421system.cpu1.icache.ReadReq_misses::total 312023 # number of ReadReq misses
1422system.cpu1.icache.demand_misses::cpu1.inst 312023 # number of demand (read+write) misses
1423system.cpu1.icache.demand_misses::total 312023 # number of demand (read+write) misses
1424system.cpu1.icache.overall_misses::cpu1.inst 312023 # number of overall misses
1425system.cpu1.icache.overall_misses::total 312023 # number of overall misses
1426system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4106650741 # number of ReadReq miss cycles
1427system.cpu1.icache.ReadReq_miss_latency::total 4106650741 # number of ReadReq miss cycles
1428system.cpu1.icache.demand_miss_latency::cpu1.inst 4106650741 # number of demand (read+write) miss cycles
1429system.cpu1.icache.demand_miss_latency::total 4106650741 # number of demand (read+write) miss cycles
1430system.cpu1.icache.overall_miss_latency::cpu1.inst 4106650741 # number of overall miss cycles
1431system.cpu1.icache.overall_miss_latency::total 4106650741 # number of overall miss cycles
1432system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767862 # number of ReadReq accesses(hits+misses)
1433system.cpu1.icache.ReadReq_accesses::total 12767862 # number of ReadReq accesses(hits+misses)
1434system.cpu1.icache.demand_accesses::cpu1.inst 12767862 # number of demand (read+write) accesses
1435system.cpu1.icache.demand_accesses::total 12767862 # number of demand (read+write) accesses
1436system.cpu1.icache.overall_accesses::cpu1.inst 12767862 # number of overall (read+write) accesses
1437system.cpu1.icache.overall_accesses::total 12767862 # number of overall (read+write) accesses
1438system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024438 # miss rate for ReadReq accesses
1439system.cpu1.icache.ReadReq_miss_rate::total 0.024438 # miss rate for ReadReq accesses
1440system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024438 # miss rate for demand accesses
1441system.cpu1.icache.demand_miss_rate::total 0.024438 # miss rate for demand accesses
1442system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024438 # miss rate for overall accesses
1443system.cpu1.icache.overall_miss_rate::total 0.024438 # miss rate for overall accesses
1444system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889 # average ReadReq miss latency
1445system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889 # average ReadReq miss latency
1446system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency
1447system.cpu1.icache.demand_avg_miss_latency::total 13161.371889 # average overall miss latency
1448system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency
1449system.cpu1.icache.overall_avg_miss_latency::total 13161.371889 # average overall miss latency
1450system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1451system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1452system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1453system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1454system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1455system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1456system.cpu1.icache.fast_writes 0 # number of fast writes performed
1457system.cpu1.icache.cache_copies 0 # number of cache copies performed
1458system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312023 # number of ReadReq MSHR misses
1459system.cpu1.icache.ReadReq_mshr_misses::total 312023 # number of ReadReq MSHR misses
1460system.cpu1.icache.demand_mshr_misses::cpu1.inst 312023 # number of demand (read+write) MSHR misses
1461system.cpu1.icache.demand_mshr_misses::total 312023 # number of demand (read+write) MSHR misses
1462system.cpu1.icache.overall_mshr_misses::cpu1.inst 312023 # number of overall MSHR misses
1463system.cpu1.icache.overall_mshr_misses::total 312023 # number of overall MSHR misses
1464system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3482409259 # number of ReadReq MSHR miss cycles
1465system.cpu1.icache.ReadReq_mshr_miss_latency::total 3482409259 # number of ReadReq MSHR miss cycles
1466system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3482409259 # number of demand (read+write) MSHR miss cycles
1467system.cpu1.icache.demand_mshr_miss_latency::total 3482409259 # number of demand (read+write) MSHR miss cycles
1468system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3482409259 # number of overall MSHR miss cycles
1469system.cpu1.icache.overall_mshr_miss_latency::total 3482409259 # number of overall MSHR miss cycles
1470system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for ReadReq accesses
1471system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024438 # mshr miss rate for ReadReq accesses
1472system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for demand accesses
1473system.cpu1.icache.demand_mshr_miss_rate::total 0.024438 # mshr miss rate for demand accesses
1474system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for overall accesses
1475system.cpu1.icache.overall_mshr_miss_rate::total 0.024438 # mshr miss rate for overall accesses
1476system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average ReadReq mshr miss latency
1477system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11160.745391 # average ReadReq mshr miss latency
1478system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency
1479system.cpu1.icache.demand_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency
1480system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency
1481system.cpu1.icache.overall_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency
1482system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1483system.cpu1.dcache.tags.replacements 155135 # number of replacements
1484system.cpu1.dcache.tags.tagsinuse 486.308895 # Cycle average of tags in use
1485system.cpu1.dcache.tags.total_refs 3855441 # Total number of references to valid blocks.
1486system.cpu1.dcache.tags.sampled_refs 155464 # Sample count of references to valid blocks.
1487system.cpu1.dcache.tags.avg_refs 24.799574 # Average number of references to valid blocks.
1488system.cpu1.dcache.tags.warmup_cycle 1048852146500 # Cycle when the warmup percentage was hit.
1489system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308895 # Average occupied blocks per requestor
1490system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949822 # Average percentage of cache occupancy
1491system.cpu1.dcache.tags.occ_percent::total 0.949822 # Average percentage of cache occupancy
1492system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id
1493system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
1494system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id
1495system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id
1496system.cpu1.dcache.tags.tag_accesses 16322717 # Number of tag accesses
1497system.cpu1.dcache.tags.data_accesses 16322717 # Number of data accesses
1498system.cpu1.dcache.ReadReq_hits::cpu1.data 2189668 # number of ReadReq hits
1499system.cpu1.dcache.ReadReq_hits::total 2189668 # number of ReadReq hits
1500system.cpu1.dcache.WriteReq_hits::cpu1.data 1567568 # number of WriteReq hits
1501system.cpu1.dcache.WriteReq_hits::total 1567568 # number of WriteReq hits
1502system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46969 # number of LoadLockedReq hits
1503system.cpu1.dcache.LoadLockedReq_hits::total 46969 # number of LoadLockedReq hits
1504system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49480 # number of StoreCondReq hits
1505system.cpu1.dcache.StoreCondReq_hits::total 49480 # number of StoreCondReq hits
1506system.cpu1.dcache.demand_hits::cpu1.data 3757236 # number of demand (read+write) hits
1507system.cpu1.dcache.demand_hits::total 3757236 # number of demand (read+write) hits
1508system.cpu1.dcache.overall_hits::cpu1.data 3757236 # number of overall hits
1509system.cpu1.dcache.overall_hits::total 3757236 # number of overall hits
1510system.cpu1.dcache.ReadReq_misses::cpu1.data 113735 # number of ReadReq misses
1511system.cpu1.dcache.ReadReq_misses::total 113735 # number of ReadReq misses
1512system.cpu1.dcache.WriteReq_misses::cpu1.data 55930 # number of WriteReq misses
1513system.cpu1.dcache.WriteReq_misses::total 55930 # number of WriteReq misses
1514system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8863 # number of LoadLockedReq misses
1515system.cpu1.dcache.LoadLockedReq_misses::total 8863 # number of LoadLockedReq misses
1516system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5883 # number of StoreCondReq misses
1517system.cpu1.dcache.StoreCondReq_misses::total 5883 # number of StoreCondReq misses
1518system.cpu1.dcache.demand_misses::cpu1.data 169665 # number of demand (read+write) misses
1519system.cpu1.dcache.demand_misses::total 169665 # number of demand (read+write) misses
1520system.cpu1.dcache.overall_misses::cpu1.data 169665 # number of overall misses
1521system.cpu1.dcache.overall_misses::total 169665 # number of overall misses
1522system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1371834000 # number of ReadReq miss cycles
1523system.cpu1.dcache.ReadReq_miss_latency::total 1371834000 # number of ReadReq miss cycles
1524system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1009197248 # number of WriteReq miss cycles
1525system.cpu1.dcache.WriteReq_miss_latency::total 1009197248 # number of WriteReq miss cycles
1526system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80472000 # number of LoadLockedReq miss cycles
1527system.cpu1.dcache.LoadLockedReq_miss_latency::total 80472000 # number of LoadLockedReq miss cycles
1528system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43306909 # number of StoreCondReq miss cycles
1529system.cpu1.dcache.StoreCondReq_miss_latency::total 43306909 # number of StoreCondReq miss cycles
1530system.cpu1.dcache.demand_miss_latency::cpu1.data 2381031248 # number of demand (read+write) miss cycles
1531system.cpu1.dcache.demand_miss_latency::total 2381031248 # number of demand (read+write) miss cycles
1532system.cpu1.dcache.overall_miss_latency::cpu1.data 2381031248 # number of overall miss cycles
1533system.cpu1.dcache.overall_miss_latency::total 2381031248 # number of overall miss cycles
1534system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303403 # number of ReadReq accesses(hits+misses)
1535system.cpu1.dcache.ReadReq_accesses::total 2303403 # number of ReadReq accesses(hits+misses)
1536system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623498 # number of WriteReq accesses(hits+misses)
1537system.cpu1.dcache.WriteReq_accesses::total 1623498 # number of WriteReq accesses(hits+misses)
1538system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55832 # number of LoadLockedReq accesses(hits+misses)
1539system.cpu1.dcache.LoadLockedReq_accesses::total 55832 # number of LoadLockedReq accesses(hits+misses)
1540system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55363 # number of StoreCondReq accesses(hits+misses)
1541system.cpu1.dcache.StoreCondReq_accesses::total 55363 # number of StoreCondReq accesses(hits+misses)
1542system.cpu1.dcache.demand_accesses::cpu1.data 3926901 # number of demand (read+write) accesses
1543system.cpu1.dcache.demand_accesses::total 3926901 # number of demand (read+write) accesses
1544system.cpu1.dcache.overall_accesses::cpu1.data 3926901 # number of overall (read+write) accesses
1545system.cpu1.dcache.overall_accesses::total 3926901 # number of overall (read+write) accesses
1546system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049377 # miss rate for ReadReq accesses
1547system.cpu1.dcache.ReadReq_miss_rate::total 0.049377 # miss rate for ReadReq accesses
1548system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034450 # miss rate for WriteReq accesses
1549system.cpu1.dcache.WriteReq_miss_rate::total 0.034450 # miss rate for WriteReq accesses
1550system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158744 # miss rate for LoadLockedReq accesses
1551system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158744 # miss rate for LoadLockedReq accesses
1552system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106262 # miss rate for StoreCondReq accesses
1553system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106262 # miss rate for StoreCondReq accesses
1554system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043206 # miss rate for demand accesses
1555system.cpu1.dcache.demand_miss_rate::total 0.043206 # miss rate for demand accesses
1556system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043206 # miss rate for overall accesses
1557system.cpu1.dcache.overall_miss_rate::total 0.043206 # miss rate for overall accesses
1558system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.669671 # average ReadReq miss latency
1559system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.669671 # average ReadReq miss latency
1560system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18043.934347 # average WriteReq miss latency
1561system.cpu1.dcache.WriteReq_avg_miss_latency::total 18043.934347 # average WriteReq miss latency
1562system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9079.544172 # average LoadLockedReq miss latency
1563system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9079.544172 # average LoadLockedReq miss latency
1564system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.364780 # average StoreCondReq miss latency
1565system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.364780 # average StoreCondReq miss latency
1566system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency
1567system.cpu1.dcache.demand_avg_miss_latency::total 14033.720850 # average overall miss latency
1568system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency
1569system.cpu1.dcache.overall_avg_miss_latency::total 14033.720850 # average overall miss latency
1570system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1571system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1572system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1573system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1574system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1575system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1576system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1577system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1578system.cpu1.dcache.writebacks::writebacks 106440 # number of writebacks
1579system.cpu1.dcache.writebacks::total 106440 # number of writebacks
1580system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113735 # number of ReadReq MSHR misses
1581system.cpu1.dcache.ReadReq_mshr_misses::total 113735 # number of ReadReq MSHR misses
1582system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55930 # number of WriteReq MSHR misses
1583system.cpu1.dcache.WriteReq_mshr_misses::total 55930 # number of WriteReq MSHR misses
1584system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8863 # number of LoadLockedReq MSHR misses
1585system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8863 # number of LoadLockedReq MSHR misses
1586system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5883 # number of StoreCondReq MSHR misses
1587system.cpu1.dcache.StoreCondReq_mshr_misses::total 5883 # number of StoreCondReq MSHR misses
1588system.cpu1.dcache.demand_mshr_misses::cpu1.data 169665 # number of demand (read+write) MSHR misses
1589system.cpu1.dcache.demand_mshr_misses::total 169665 # number of demand (read+write) MSHR misses
1590system.cpu1.dcache.overall_mshr_misses::cpu1.data 169665 # number of overall MSHR misses
1591system.cpu1.dcache.overall_mshr_misses::total 169665 # number of overall MSHR misses
1592system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144290000 # number of ReadReq MSHR miss cycles
1593system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144290000 # number of ReadReq MSHR miss cycles
1594system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 895105752 # number of WriteReq MSHR miss cycles
1595system.cpu1.dcache.WriteReq_mshr_miss_latency::total 895105752 # number of WriteReq MSHR miss cycles
1596system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62746000 # number of LoadLockedReq MSHR miss cycles
1597system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62746000 # number of LoadLockedReq MSHR miss cycles
1598system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31539091 # number of StoreCondReq MSHR miss cycles
1599system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31539091 # number of StoreCondReq MSHR miss cycles
1600system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2039395752 # number of demand (read+write) MSHR miss cycles
1601system.cpu1.dcache.demand_mshr_miss_latency::total 2039395752 # number of demand (read+write) MSHR miss cycles
1602system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2039395752 # number of overall MSHR miss cycles
1603system.cpu1.dcache.overall_mshr_miss_latency::total 2039395752 # number of overall MSHR miss cycles
1604system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776500 # number of ReadReq MSHR uncacheable cycles
1605system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776500 # number of ReadReq MSHR uncacheable cycles
1606system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713537000 # number of WriteReq MSHR uncacheable cycles
1607system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713537000 # number of WriteReq MSHR uncacheable cycles
1608system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732313500 # number of overall MSHR uncacheable cycles
1609system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732313500 # number of overall MSHR uncacheable cycles
1610system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049377 # mshr miss rate for ReadReq accesses
1611system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049377 # mshr miss rate for ReadReq accesses
1612system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034450 # mshr miss rate for WriteReq accesses
1613system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034450 # mshr miss rate for WriteReq accesses
1614system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158744 # mshr miss rate for LoadLockedReq accesses
1615system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158744 # mshr miss rate for LoadLockedReq accesses
1616system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106262 # mshr miss rate for StoreCondReq accesses
1617system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106262 # mshr miss rate for StoreCondReq accesses
1618system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for demand accesses
1619system.cpu1.dcache.demand_mshr_miss_rate::total 0.043206 # mshr miss rate for demand accesses
1620system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for overall accesses
1621system.cpu1.dcache.overall_mshr_miss_rate::total 0.043206 # mshr miss rate for overall accesses
1622system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035 # average ReadReq mshr miss latency
1623system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035 # average ReadReq mshr miss latency
1624system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331 # average WriteReq mshr miss latency
1625system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331 # average WriteReq mshr miss latency
1626system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.544172 # average LoadLockedReq mshr miss latency
1627system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.544172 # average LoadLockedReq mshr miss latency
1628system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.055754 # average StoreCondReq mshr miss latency
1629system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.055754 # average StoreCondReq mshr miss latency
1630system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency
1631system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency
1632system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency
1633system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency
1634system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1635system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1636system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1637system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1638system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1639system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1640system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1641
1642---------- End Simulation Statistics ----------