1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.960910 # Number of seconds simulated
4sim_ticks 1960909874500 # Number of ticks simulated
5final_tick 1960909874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 787846 # Simulator instruction rate (inst/s)
8host_op_rate 787845 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 25353578812 # Simulator tick rate (ticks/s)
10host_mem_usage 353976 # Number of bytes of host memory used
11host_seconds 77.34 # Real time elapsed on the host
12sim_insts 60933947 # Number of instructions simulated
13sim_ops 60933947 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 833472 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 24887104 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.inst 31680 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.data 338304 # Number of bytes read from this memory
19system.physmem.bytes_read::total 28741248 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu0.inst 833472 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::cpu1.inst 31680 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 865152 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 7743680 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7743680 # Number of bytes written to this memory
25system.physmem.num_reads::cpu0.inst 13023 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu0.data 388861 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu1.inst 495 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.data 5286 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 449082 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 120995 # Number of write requests responded to by this memory
32system.physmem.num_writes::total 120995 # Number of write requests responded to by this memory
33system.physmem.bw_read::cpu0.inst 425044 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu0.data 12691610 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::tsunami.ide 1351764 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu1.inst 16156 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.data 172524 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::total 14657098 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::cpu0.inst 425044 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu1.inst 16156 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 441199 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 3949024 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 3949024 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 3949024 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu0.inst 425044 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu0.data 12691610 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::tsunami.ide 1351764 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu1.inst 16156 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.data 172524 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 18606122 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.readReqs 449082 # Number of read requests accepted
52system.physmem.writeReqs 120995 # Number of write requests accepted
53system.physmem.readBursts 449082 # Number of DRAM read bursts, including those serviced by the write queue
54system.physmem.writeBursts 120995 # Number of DRAM write bursts, including those merged in the write queue
55system.physmem.bytesReadDRAM 28737664 # Total number of bytes read from DRAM
56system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue
57system.physmem.bytesWritten 7742592 # Total number of bytes written to DRAM
58system.physmem.bytesReadSys 28741248 # Total read bytes from the system interface side
59system.physmem.bytesWrittenSys 7743680 # Total written bytes from the system interface side
60system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue
61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62system.physmem.neitherReadNorWriteReqs 7094 # Number of requests that are neither read nor write
63system.physmem.perBankRdBursts::0 28167 # Per bank write bursts
64system.physmem.perBankRdBursts::1 28459 # Per bank write bursts
65system.physmem.perBankRdBursts::2 28057 # Per bank write bursts
66system.physmem.perBankRdBursts::3 27664 # Per bank write bursts
67system.physmem.perBankRdBursts::4 27762 # Per bank write bursts
68system.physmem.perBankRdBursts::5 27793 # Per bank write bursts
69system.physmem.perBankRdBursts::6 28259 # Per bank write bursts
70system.physmem.perBankRdBursts::7 27872 # Per bank write bursts
71system.physmem.perBankRdBursts::8 28083 # Per bank write bursts
72system.physmem.perBankRdBursts::9 27730 # Per bank write bursts
73system.physmem.perBankRdBursts::10 27672 # Per bank write bursts
74system.physmem.perBankRdBursts::11 28135 # Per bank write bursts
75system.physmem.perBankRdBursts::12 28179 # Per bank write bursts
76system.physmem.perBankRdBursts::13 28505 # Per bank write bursts
77system.physmem.perBankRdBursts::14 28654 # Per bank write bursts
78system.physmem.perBankRdBursts::15 28035 # Per bank write bursts
79system.physmem.perBankWrBursts::0 7928 # Per bank write bursts
80system.physmem.perBankWrBursts::1 7868 # Per bank write bursts
81system.physmem.perBankWrBursts::2 7543 # Per bank write bursts
82system.physmem.perBankWrBursts::3 7157 # Per bank write bursts
83system.physmem.perBankWrBursts::4 7275 # Per bank write bursts
84system.physmem.perBankWrBursts::5 7314 # Per bank write bursts
85system.physmem.perBankWrBursts::6 7747 # Per bank write bursts
86system.physmem.perBankWrBursts::7 7251 # Per bank write bursts
87system.physmem.perBankWrBursts::8 7322 # Per bank write bursts
88system.physmem.perBankWrBursts::9 7110 # Per bank write bursts
89system.physmem.perBankWrBursts::10 7099 # Per bank write bursts
90system.physmem.perBankWrBursts::11 7523 # Per bank write bursts
91system.physmem.perBankWrBursts::12 7681 # Per bank write bursts
92system.physmem.perBankWrBursts::13 8141 # Per bank write bursts
93system.physmem.perBankWrBursts::14 8335 # Per bank write bursts
94system.physmem.perBankWrBursts::15 7684 # Per bank write bursts
95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
97system.physmem.totGap 1960902862500 # Total gap between requests
98system.physmem.readPktSize::0 0 # Read request sizes (log2)
99system.physmem.readPktSize::1 0 # Read request sizes (log2)
100system.physmem.readPktSize::2 0 # Read request sizes (log2)
101system.physmem.readPktSize::3 0 # Read request sizes (log2)
102system.physmem.readPktSize::4 0 # Read request sizes (log2)
103system.physmem.readPktSize::5 0 # Read request sizes (log2)
104system.physmem.readPktSize::6 449082 # Read request sizes (log2)
105system.physmem.writePktSize::0 0 # Write request sizes (log2)
106system.physmem.writePktSize::1 0 # Write request sizes (log2)
107system.physmem.writePktSize::2 0 # Write request sizes (log2)
108system.physmem.writePktSize::3 0 # Write request sizes (log2)
109system.physmem.writePktSize::4 0 # Write request sizes (log2)
110system.physmem.writePktSize::5 0 # Write request sizes (log2)
111system.physmem.writePktSize::6 120995 # Write request sizes (log2)
112system.physmem.rdQLenPdf::0 409890 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::1 10611 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::2 5423 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::3 2684 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::4 2293 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::5 2304 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::6 1349 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::7 1329 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::8 1317 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::9 1416 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::10 1284 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::11 1243 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::12 1099 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::13 987 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::14 972 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::15 967 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::16 966 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::17 958 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::18 963 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::19 962 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
144system.physmem.wrQLenPdf::0 4882 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::1 4921 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::2 4932 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::3 5600 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::4 6306 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::5 5669 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::6 5682 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::7 5778 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::8 5861 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::9 5196 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::10 5200 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::11 5185 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::12 5982 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::13 6055 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::14 6054 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::15 6099 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::16 6134 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::17 5025 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::19 4966 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::20 4953 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::22 232 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::23 193 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::25 28 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::26 22 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::27 20 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::31 26 # What write queue length does an incoming req see
176system.physmem.bytesPerActivate::samples 49380 # Bytes accessed per row activation
177system.physmem.bytesPerActivate::mean 738.726934 # Bytes accessed per row activation
178system.physmem.bytesPerActivate::gmean 222.746795 # Bytes accessed per row activation
179system.physmem.bytesPerActivate::stdev 1735.319745 # Bytes accessed per row activation
180system.physmem.bytesPerActivate::64-67 17723 35.89% 35.89% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::128-131 7354 14.89% 50.78% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::192-195 4892 9.91% 60.69% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::256-259 2955 5.98% 66.67% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::320-323 1860 3.77% 70.44% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::384-387 1462 2.96% 73.40% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::448-451 1143 2.31% 75.72% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::512-515 851 1.72% 77.44% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::576-579 746 1.51% 78.95% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::640-643 676 1.37% 80.32% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::704-707 661 1.34% 81.66% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::768-771 443 0.90% 82.56% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::832-835 337 0.68% 83.24% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::896-899 276 0.56% 83.80% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::960-963 300 0.61% 84.40% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1024-1027 399 0.81% 85.21% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1088-1091 192 0.39% 85.60% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1152-1155 178 0.36% 85.96% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1216-1219 196 0.40% 86.36% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1280-1283 170 0.34% 86.70% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1344-1347 202 0.41% 87.11% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1408-1411 873 1.77% 88.88% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1472-1475 184 0.37% 89.25% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1536-1539 168 0.34% 89.59% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1600-1603 96 0.19% 89.79% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1664-1667 82 0.17% 89.95% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::1728-1731 107 0.22% 90.17% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::1792-1795 72 0.15% 90.32% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1856-1859 81 0.16% 90.48% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::1920-1923 51 0.10% 90.58% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::1984-1987 64 0.13% 90.71% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2048-2051 84 0.17% 90.88% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2112-2115 51 0.10% 90.99% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2176-2179 54 0.11% 91.10% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::2240-2243 70 0.14% 91.24% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::2304-2307 45 0.09% 91.33% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::2368-2371 72 0.15% 91.47% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::2432-2435 49 0.10% 91.57% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::2496-2499 40 0.08% 91.65% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::2560-2563 72 0.15% 91.80% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::2624-2627 42 0.09% 91.89% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::2688-2691 45 0.09% 91.98% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::2752-2755 69 0.14% 92.12% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::2816-2819 44 0.09% 92.21% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::2880-2883 64 0.13% 92.33% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::2944-2947 43 0.09% 92.42% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3008-3011 42 0.09% 92.51% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3072-3075 76 0.15% 92.66% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3136-3139 39 0.08% 92.74% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3200-3203 46 0.09% 92.83% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::3264-3267 67 0.14% 92.97% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::3328-3331 46 0.09% 93.06% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::3392-3395 66 0.13% 93.20% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::3456-3459 46 0.09% 93.29% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::3520-3523 37 0.07% 93.36% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::3584-3587 72 0.15% 93.51% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::3648-3651 38 0.08% 93.59% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::3712-3715 42 0.09% 93.67% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::3776-3779 69 0.14% 93.81% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::3840-3843 43 0.09% 93.90% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::3904-3907 64 0.13% 94.03% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::3968-3971 42 0.09% 94.11% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4032-4035 41 0.08% 94.20% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4096-4099 74 0.15% 94.35% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4160-4163 37 0.07% 94.42% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4224-4227 43 0.09% 94.51% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::4288-4291 66 0.13% 94.64% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::4352-4355 46 0.09% 94.73% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::4416-4419 64 0.13% 94.86% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::4480-4483 43 0.09% 94.95% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::4544-4547 37 0.07% 95.03% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::4608-4611 404 0.82% 95.84% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::4672-4675 34 0.07% 95.91% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::4736-4739 44 0.09% 96.00% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::4800-4803 36 0.07% 96.08% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::4864-4867 44 0.09% 96.16% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::4928-4931 34 0.07% 96.23% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::4992-4995 44 0.09% 96.32% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5056-5059 33 0.07% 96.39% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::5120-5123 41 0.08% 96.47% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::5184-5187 51 0.10% 96.58% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::5248-5251 44 0.09% 96.66% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::5312-5315 32 0.06% 96.73% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::5376-5379 40 0.08% 96.81% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::5440-5443 37 0.07% 96.89% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::5504-5507 43 0.09% 96.97% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::5568-5571 35 0.07% 97.04% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::5632-5635 40 0.08% 97.12% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::5696-5699 33 0.07% 97.19% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::5760-5763 47 0.10% 97.29% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::5824-5827 34 0.07% 97.36% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::5888-5891 43 0.09% 97.44% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::5952-5955 35 0.07% 97.51% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::6016-6019 44 0.09% 97.60% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::6080-6083 34 0.07% 97.67% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::6144-6147 44 0.09% 97.76% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::6208-6211 38 0.08% 97.84% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::6272-6275 42 0.09% 97.92% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::6336-6339 35 0.07% 97.99% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::6400-6403 43 0.09% 98.08% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::6464-6467 32 0.06% 98.14% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::6528-6531 40 0.08% 98.23% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::6592-6595 37 0.07% 98.30% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::6656-6659 41 0.08% 98.38% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::6720-6723 32 0.06% 98.45% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::6784-6787 431 0.87% 99.32% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::6912-6915 1 0.00% 99.32% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::7040-7043 1 0.00% 99.33% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::7168-7171 10 0.02% 99.35% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::7232-7235 1 0.00% 99.35% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::7296-7299 1 0.00% 99.35% # Bytes accessed per row activation
292system.physmem.bytesPerActivate::7488-7491 1 0.00% 99.35% # Bytes accessed per row activation
293system.physmem.bytesPerActivate::7552-7555 1 0.00% 99.36% # Bytes accessed per row activation
294system.physmem.bytesPerActivate::7616-7619 3 0.01% 99.36% # Bytes accessed per row activation
295system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.36% # Bytes accessed per row activation
296system.physmem.bytesPerActivate::7872-7875 1 0.00% 99.37% # Bytes accessed per row activation
297system.physmem.bytesPerActivate::7936-7939 2 0.00% 99.37% # Bytes accessed per row activation
298system.physmem.bytesPerActivate::8000-8003 1 0.00% 99.37% # Bytes accessed per row activation
299system.physmem.bytesPerActivate::8128-8131 1 0.00% 99.37% # Bytes accessed per row activation
300system.physmem.bytesPerActivate::8192-8195 8 0.02% 99.39% # Bytes accessed per row activation
301system.physmem.bytesPerActivate::8384-8387 2 0.00% 99.39% # Bytes accessed per row activation
302system.physmem.bytesPerActivate::8448-8451 2 0.00% 99.40% # Bytes accessed per row activation
303system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.40% # Bytes accessed per row activation
304system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.40% # Bytes accessed per row activation
305system.physmem.bytesPerActivate::8832-8835 1 0.00% 99.41% # Bytes accessed per row activation
306system.physmem.bytesPerActivate::8896-8899 1 0.00% 99.41% # Bytes accessed per row activation
307system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.41% # Bytes accessed per row activation
308system.physmem.bytesPerActivate::9088-9091 3 0.01% 99.42% # Bytes accessed per row activation
309system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.42% # Bytes accessed per row activation
310system.physmem.bytesPerActivate::9216-9219 1 0.00% 99.42% # Bytes accessed per row activation
311system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.42% # Bytes accessed per row activation
312system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.42% # Bytes accessed per row activation
313system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.43% # Bytes accessed per row activation
314system.physmem.bytesPerActivate::9600-9603 1 0.00% 99.43% # Bytes accessed per row activation
315system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.43% # Bytes accessed per row activation
316system.physmem.bytesPerActivate::10368-10371 1 0.00% 99.43% # Bytes accessed per row activation
317system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.43% # Bytes accessed per row activation
318system.physmem.bytesPerActivate::10752-10755 1 0.00% 99.44% # Bytes accessed per row activation
319system.physmem.bytesPerActivate::10880-10883 3 0.01% 99.44% # Bytes accessed per row activation
320system.physmem.bytesPerActivate::10944-10947 1 0.00% 99.45% # Bytes accessed per row activation
321system.physmem.bytesPerActivate::11136-11139 2 0.00% 99.45% # Bytes accessed per row activation
322system.physmem.bytesPerActivate::11520-11523 2 0.00% 99.45% # Bytes accessed per row activation
323system.physmem.bytesPerActivate::11776-11779 1 0.00% 99.46% # Bytes accessed per row activation
324system.physmem.bytesPerActivate::11840-11843 2 0.00% 99.46% # Bytes accessed per row activation
325system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.46% # Bytes accessed per row activation
326system.physmem.bytesPerActivate::12032-12035 1 0.00% 99.46% # Bytes accessed per row activation
327system.physmem.bytesPerActivate::12288-12291 2 0.00% 99.47% # Bytes accessed per row activation
328system.physmem.bytesPerActivate::12352-12355 3 0.01% 99.47% # Bytes accessed per row activation
329system.physmem.bytesPerActivate::12416-12419 1 0.00% 99.48% # Bytes accessed per row activation
330system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.48% # Bytes accessed per row activation
331system.physmem.bytesPerActivate::12672-12675 3 0.01% 99.48% # Bytes accessed per row activation
332system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.49% # Bytes accessed per row activation
333system.physmem.bytesPerActivate::13056-13059 2 0.00% 99.49% # Bytes accessed per row activation
334system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.49% # Bytes accessed per row activation
335system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.49% # Bytes accessed per row activation
336system.physmem.bytesPerActivate::13312-13315 1 0.00% 99.50% # Bytes accessed per row activation
337system.physmem.bytesPerActivate::13376-13379 2 0.00% 99.50% # Bytes accessed per row activation
338system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.50% # Bytes accessed per row activation
339system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.50% # Bytes accessed per row activation
340system.physmem.bytesPerActivate::13696-13699 3 0.01% 99.51% # Bytes accessed per row activation
341system.physmem.bytesPerActivate::14016-14019 1 0.00% 99.51% # Bytes accessed per row activation
342system.physmem.bytesPerActivate::14208-14211 3 0.01% 99.52% # Bytes accessed per row activation
343system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.52% # Bytes accessed per row activation
344system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.52% # Bytes accessed per row activation
345system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.53% # Bytes accessed per row activation
346system.physmem.bytesPerActivate::14656-14659 2 0.00% 99.53% # Bytes accessed per row activation
347system.physmem.bytesPerActivate::14912-14915 2 0.00% 99.53% # Bytes accessed per row activation
348system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.54% # Bytes accessed per row activation
349system.physmem.bytesPerActivate::15104-15107 3 0.01% 99.54% # Bytes accessed per row activation
350system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.54% # Bytes accessed per row activation
351system.physmem.bytesPerActivate::15232-15235 2 0.00% 99.55% # Bytes accessed per row activation
352system.physmem.bytesPerActivate::15296-15299 1 0.00% 99.55% # Bytes accessed per row activation
353system.physmem.bytesPerActivate::15360-15363 36 0.07% 99.62% # Bytes accessed per row activation
354system.physmem.bytesPerActivate::15424-15427 1 0.00% 99.63% # Bytes accessed per row activation
355system.physmem.bytesPerActivate::15488-15491 2 0.00% 99.63% # Bytes accessed per row activation
356system.physmem.bytesPerActivate::15616-15619 1 0.00% 99.63% # Bytes accessed per row activation
357system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.63% # Bytes accessed per row activation
358system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.64% # Bytes accessed per row activation
359system.physmem.bytesPerActivate::16384-16387 180 0.36% 100.00% # Bytes accessed per row activation
360system.physmem.bytesPerActivate::total 49380 # Bytes accessed per row activation
361system.physmem.totQLat 6346588750 # Total ticks spent queuing
362system.physmem.totMemAccLat 14721193750 # Total ticks spent from burst creation until serviced by the DRAM
363system.physmem.totBusLat 2245130000 # Total ticks spent in databus transfers
364system.physmem.totBankLat 6129475000 # Total ticks spent accessing banks
365system.physmem.avgQLat 14134.12 # Average queueing delay per DRAM burst
366system.physmem.avgBankLat 13650.60 # Average bank access latency per DRAM burst
367system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
368system.physmem.avgMemAccLat 32784.72 # Average memory access latency per DRAM burst
369system.physmem.avgRdBW 14.66 # Average DRAM read bandwidth in MiByte/s
370system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s
371system.physmem.avgRdBWSys 14.66 # Average system read bandwidth in MiByte/s
372system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s
373system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
374system.physmem.busUtil 0.15 # Data bus utilization in percentage
375system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
376system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
377system.physmem.avgRdQLen 0.01 # Average read queue length when enqueuing
378system.physmem.avgWrQLen 10.65 # Average write queue length when enqueuing
379system.physmem.readRowHits 424775 # Number of row buffer hits during reads
380system.physmem.writeRowHits 95849 # Number of row buffer hits during writes
381system.physmem.readRowHitRate 94.60 # Row buffer hit rate for reads
382system.physmem.writeRowHitRate 79.22 # Row buffer hit rate for writes
383system.physmem.avgGap 3439715.80 # Average gap between requests
384system.physmem.pageHitRate 91.33 # Row buffer hit rate, read and write combined
385system.physmem.prechargeAllPercent 0.53 # Percentage of time for which DRAM has all the banks in precharge state
386system.membus.throughput 18666756 # Throughput (bytes/s)
387system.membus.trans_dist::ReadReq 292805 # Transaction distribution
388system.membus.trans_dist::ReadResp 292805 # Transaction distribution
389system.membus.trans_dist::WriteReq 14109 # Transaction distribution
390system.membus.trans_dist::WriteResp 14109 # Transaction distribution
391system.membus.trans_dist::Writeback 120995 # Transaction distribution
392system.membus.trans_dist::UpgradeReq 16488 # Transaction distribution
393system.membus.trans_dist::SCUpgradeReq 11559 # Transaction distribution
394system.membus.trans_dist::UpgradeResp 7097 # Transaction distribution
395system.membus.trans_dist::ReadExReq 164894 # Transaction distribution
396system.membus.trans_dist::ReadExResp 164048 # Transaction distribution
397system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42616 # Packet count per connected master and slave (bytes)
398system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931055 # Packet count per connected master and slave (bytes)
399system.membus.pkt_count_system.l2c.mem_side::total 973671 # Packet count per connected master and slave (bytes)
400system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124663 # Packet count per connected master and slave (bytes)
401system.membus.pkt_count_system.iocache.mem_side::total 124663 # Packet count per connected master and slave (bytes)
402system.membus.pkt_count::total 1098334 # Packet count per connected master and slave (bytes)
403system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 82290 # Cumulative packet size per connected master and slave (bytes)
404system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31176960 # Cumulative packet size per connected master and slave (bytes)
405system.membus.tot_pkt_size_system.l2c.mem_side::total 31259250 # Cumulative packet size per connected master and slave (bytes)
406system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5307968 # Cumulative packet size per connected master and slave (bytes)
407system.membus.tot_pkt_size_system.iocache.mem_side::total 5307968 # Cumulative packet size per connected master and slave (bytes)
408system.membus.tot_pkt_size::total 36567218 # Cumulative packet size per connected master and slave (bytes)
409system.membus.data_through_bus 36567218 # Total data (bytes)
410system.membus.snoop_data_through_bus 36608 # Total snoop data (bytes)
411system.membus.reqLayer0.occupancy 43251000 # Layer occupancy (ticks)
412system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
413system.membus.reqLayer1.occupancy 1579578000 # Layer occupancy (ticks)
414system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
415system.membus.respLayer1.occupancy 3830990646 # Layer occupancy (ticks)
416system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
417system.membus.respLayer2.occupancy 376315500 # Layer occupancy (ticks)
418system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
419system.l2c.tags.replacements 342160 # number of replacements
420system.l2c.tags.tagsinuse 65219.945305 # Cycle average of tags in use
421system.l2c.tags.total_refs 2443226 # Total number of references to valid blocks.
422system.l2c.tags.sampled_refs 407347 # Sample count of references to valid blocks.
423system.l2c.tags.avg_refs 5.997899 # Average number of references to valid blocks.
424system.l2c.tags.warmup_cycle 8615385750 # Cycle when the warmup percentage was hit.
425system.l2c.tags.occ_blocks::writebacks 55312.026017 # Average occupied blocks per requestor
426system.l2c.tags.occ_blocks::cpu0.inst 4807.093964 # Average occupied blocks per requestor
427system.l2c.tags.occ_blocks::cpu0.data 4897.564051 # Average occupied blocks per requestor
428system.l2c.tags.occ_blocks::cpu1.inst 159.017352 # Average occupied blocks per requestor
429system.l2c.tags.occ_blocks::cpu1.data 44.243921 # Average occupied blocks per requestor
430system.l2c.tags.occ_percent::writebacks 0.843995 # Average percentage of cache occupancy
431system.l2c.tags.occ_percent::cpu0.inst 0.073350 # Average percentage of cache occupancy
432system.l2c.tags.occ_percent::cpu0.data 0.074731 # Average percentage of cache occupancy
433system.l2c.tags.occ_percent::cpu1.inst 0.002426 # Average percentage of cache occupancy
434system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy
435system.l2c.tags.occ_percent::total 0.995177 # Average percentage of cache occupancy
436system.l2c.ReadReq_hits::cpu0.inst 684719 # number of ReadReq hits
437system.l2c.ReadReq_hits::cpu0.data 664525 # number of ReadReq hits
438system.l2c.ReadReq_hits::cpu1.inst 317383 # number of ReadReq hits
439system.l2c.ReadReq_hits::cpu1.data 107430 # number of ReadReq hits
440system.l2c.ReadReq_hits::total 1774057 # number of ReadReq hits
441system.l2c.Writeback_hits::writebacks 791641 # number of Writeback hits
442system.l2c.Writeback_hits::total 791641 # number of Writeback hits
443system.l2c.UpgradeReq_hits::cpu0.data 180 # number of UpgradeReq hits
444system.l2c.UpgradeReq_hits::cpu1.data 539 # number of UpgradeReq hits
445system.l2c.UpgradeReq_hits::total 719 # number of UpgradeReq hits
446system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits
447system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits
448system.l2c.SCUpgradeReq_hits::total 59 # number of SCUpgradeReq hits
449system.l2c.ReadExReq_hits::cpu0.data 129054 # number of ReadExReq hits
450system.l2c.ReadExReq_hits::cpu1.data 42974 # number of ReadExReq hits
451system.l2c.ReadExReq_hits::total 172028 # number of ReadExReq hits
452system.l2c.demand_hits::cpu0.inst 684719 # number of demand (read+write) hits
453system.l2c.demand_hits::cpu0.data 793579 # number of demand (read+write) hits
454system.l2c.demand_hits::cpu1.inst 317383 # number of demand (read+write) hits
455system.l2c.demand_hits::cpu1.data 150404 # number of demand (read+write) hits
456system.l2c.demand_hits::total 1946085 # number of demand (read+write) hits
457system.l2c.overall_hits::cpu0.inst 684719 # number of overall hits
458system.l2c.overall_hits::cpu0.data 793579 # number of overall hits
459system.l2c.overall_hits::cpu1.inst 317383 # number of overall hits
460system.l2c.overall_hits::cpu1.data 150404 # number of overall hits
461system.l2c.overall_hits::total 1946085 # number of overall hits
462system.l2c.ReadReq_misses::cpu0.inst 13026 # number of ReadReq misses
463system.l2c.ReadReq_misses::cpu0.data 271672 # number of ReadReq misses
464system.l2c.ReadReq_misses::cpu1.inst 503 # number of ReadReq misses
465system.l2c.ReadReq_misses::cpu1.data 242 # number of ReadReq misses
466system.l2c.ReadReq_misses::total 285443 # number of ReadReq misses
467system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses
468system.l2c.UpgradeReq_misses::cpu1.data 1793 # number of UpgradeReq misses
469system.l2c.UpgradeReq_misses::total 4742 # number of UpgradeReq misses
470system.l2c.SCUpgradeReq_misses::cpu0.data 919 # number of SCUpgradeReq misses
471system.l2c.SCUpgradeReq_misses::cpu1.data 927 # number of SCUpgradeReq misses
472system.l2c.SCUpgradeReq_misses::total 1846 # number of SCUpgradeReq misses
473system.l2c.ReadExReq_misses::cpu0.data 117950 # number of ReadExReq misses
474system.l2c.ReadExReq_misses::cpu1.data 5055 # number of ReadExReq misses
475system.l2c.ReadExReq_misses::total 123005 # number of ReadExReq misses
476system.l2c.demand_misses::cpu0.inst 13026 # number of demand (read+write) misses
477system.l2c.demand_misses::cpu0.data 389622 # number of demand (read+write) misses
478system.l2c.demand_misses::cpu1.inst 503 # number of demand (read+write) misses
479system.l2c.demand_misses::cpu1.data 5297 # number of demand (read+write) misses
480system.l2c.demand_misses::total 408448 # number of demand (read+write) misses
481system.l2c.overall_misses::cpu0.inst 13026 # number of overall misses
482system.l2c.overall_misses::cpu0.data 389622 # number of overall misses
483system.l2c.overall_misses::cpu1.inst 503 # number of overall misses
484system.l2c.overall_misses::cpu1.data 5297 # number of overall misses
485system.l2c.overall_misses::total 408448 # number of overall misses
486system.l2c.ReadReq_miss_latency::cpu0.inst 997409492 # number of ReadReq miss cycles
487system.l2c.ReadReq_miss_latency::cpu0.data 17552881248 # number of ReadReq miss cycles
488system.l2c.ReadReq_miss_latency::cpu1.inst 35450000 # number of ReadReq miss cycles
489system.l2c.ReadReq_miss_latency::cpu1.data 19470500 # number of ReadReq miss cycles
490system.l2c.ReadReq_miss_latency::total 18605211240 # number of ReadReq miss cycles
491system.l2c.UpgradeReq_miss_latency::cpu0.data 1291954 # number of UpgradeReq miss cycles
492system.l2c.UpgradeReq_miss_latency::cpu1.data 10252557 # number of UpgradeReq miss cycles
493system.l2c.UpgradeReq_miss_latency::total 11544511 # number of UpgradeReq miss cycles
494system.l2c.SCUpgradeReq_miss_latency::cpu0.data 835964 # number of SCUpgradeReq miss cycles
495system.l2c.SCUpgradeReq_miss_latency::cpu1.data 163493 # number of SCUpgradeReq miss cycles
496system.l2c.SCUpgradeReq_miss_latency::total 999457 # number of SCUpgradeReq miss cycles
497system.l2c.ReadExReq_miss_latency::cpu0.data 8264985252 # number of ReadExReq miss cycles
498system.l2c.ReadExReq_miss_latency::cpu1.data 387201489 # number of ReadExReq miss cycles
499system.l2c.ReadExReq_miss_latency::total 8652186741 # number of ReadExReq miss cycles
500system.l2c.demand_miss_latency::cpu0.inst 997409492 # number of demand (read+write) miss cycles
501system.l2c.demand_miss_latency::cpu0.data 25817866500 # number of demand (read+write) miss cycles
502system.l2c.demand_miss_latency::cpu1.inst 35450000 # number of demand (read+write) miss cycles
503system.l2c.demand_miss_latency::cpu1.data 406671989 # number of demand (read+write) miss cycles
504system.l2c.demand_miss_latency::total 27257397981 # number of demand (read+write) miss cycles
505system.l2c.overall_miss_latency::cpu0.inst 997409492 # number of overall miss cycles
506system.l2c.overall_miss_latency::cpu0.data 25817866500 # number of overall miss cycles
507system.l2c.overall_miss_latency::cpu1.inst 35450000 # number of overall miss cycles
508system.l2c.overall_miss_latency::cpu1.data 406671989 # number of overall miss cycles
509system.l2c.overall_miss_latency::total 27257397981 # number of overall miss cycles
510system.l2c.ReadReq_accesses::cpu0.inst 697745 # number of ReadReq accesses(hits+misses)
511system.l2c.ReadReq_accesses::cpu0.data 936197 # number of ReadReq accesses(hits+misses)
512system.l2c.ReadReq_accesses::cpu1.inst 317886 # number of ReadReq accesses(hits+misses)
513system.l2c.ReadReq_accesses::cpu1.data 107672 # number of ReadReq accesses(hits+misses)
514system.l2c.ReadReq_accesses::total 2059500 # number of ReadReq accesses(hits+misses)
515system.l2c.Writeback_accesses::writebacks 791641 # number of Writeback accesses(hits+misses)
516system.l2c.Writeback_accesses::total 791641 # number of Writeback accesses(hits+misses)
517system.l2c.UpgradeReq_accesses::cpu0.data 3129 # number of UpgradeReq accesses(hits+misses)
518system.l2c.UpgradeReq_accesses::cpu1.data 2332 # number of UpgradeReq accesses(hits+misses)
519system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses)
520system.l2c.SCUpgradeReq_accesses::cpu0.data 957 # number of SCUpgradeReq accesses(hits+misses)
521system.l2c.SCUpgradeReq_accesses::cpu1.data 948 # number of SCUpgradeReq accesses(hits+misses)
522system.l2c.SCUpgradeReq_accesses::total 1905 # number of SCUpgradeReq accesses(hits+misses)
523system.l2c.ReadExReq_accesses::cpu0.data 247004 # number of ReadExReq accesses(hits+misses)
524system.l2c.ReadExReq_accesses::cpu1.data 48029 # number of ReadExReq accesses(hits+misses)
525system.l2c.ReadExReq_accesses::total 295033 # number of ReadExReq accesses(hits+misses)
526system.l2c.demand_accesses::cpu0.inst 697745 # number of demand (read+write) accesses
527system.l2c.demand_accesses::cpu0.data 1183201 # number of demand (read+write) accesses
528system.l2c.demand_accesses::cpu1.inst 317886 # number of demand (read+write) accesses
529system.l2c.demand_accesses::cpu1.data 155701 # number of demand (read+write) accesses
530system.l2c.demand_accesses::total 2354533 # number of demand (read+write) accesses
531system.l2c.overall_accesses::cpu0.inst 697745 # number of overall (read+write) accesses
532system.l2c.overall_accesses::cpu0.data 1183201 # number of overall (read+write) accesses
533system.l2c.overall_accesses::cpu1.inst 317886 # number of overall (read+write) accesses
534system.l2c.overall_accesses::cpu1.data 155701 # number of overall (read+write) accesses
535system.l2c.overall_accesses::total 2354533 # number of overall (read+write) accesses
536system.l2c.ReadReq_miss_rate::cpu0.inst 0.018669 # miss rate for ReadReq accesses
537system.l2c.ReadReq_miss_rate::cpu0.data 0.290187 # miss rate for ReadReq accesses
538system.l2c.ReadReq_miss_rate::cpu1.inst 0.001582 # miss rate for ReadReq accesses
539system.l2c.ReadReq_miss_rate::cpu1.data 0.002248 # miss rate for ReadReq accesses
540system.l2c.ReadReq_miss_rate::total 0.138598 # miss rate for ReadReq accesses
541system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942474 # miss rate for UpgradeReq accesses
542system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768868 # miss rate for UpgradeReq accesses
543system.l2c.UpgradeReq_miss_rate::total 0.868339 # miss rate for UpgradeReq accesses
544system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.960293 # miss rate for SCUpgradeReq accesses
545system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.977848 # miss rate for SCUpgradeReq accesses
546system.l2c.SCUpgradeReq_miss_rate::total 0.969029 # miss rate for SCUpgradeReq accesses
547system.l2c.ReadExReq_miss_rate::cpu0.data 0.477523 # miss rate for ReadExReq accesses
548system.l2c.ReadExReq_miss_rate::cpu1.data 0.105249 # miss rate for ReadExReq accesses
549system.l2c.ReadExReq_miss_rate::total 0.416919 # miss rate for ReadExReq accesses
550system.l2c.demand_miss_rate::cpu0.inst 0.018669 # miss rate for demand accesses
551system.l2c.demand_miss_rate::cpu0.data 0.329295 # miss rate for demand accesses
552system.l2c.demand_miss_rate::cpu1.inst 0.001582 # miss rate for demand accesses
553system.l2c.demand_miss_rate::cpu1.data 0.034020 # miss rate for demand accesses
554system.l2c.demand_miss_rate::total 0.173473 # miss rate for demand accesses
555system.l2c.overall_miss_rate::cpu0.inst 0.018669 # miss rate for overall accesses
556system.l2c.overall_miss_rate::cpu0.data 0.329295 # miss rate for overall accesses
557system.l2c.overall_miss_rate::cpu1.inst 0.001582 # miss rate for overall accesses
558system.l2c.overall_miss_rate::cpu1.data 0.034020 # miss rate for overall accesses
559system.l2c.overall_miss_rate::total 0.173473 # miss rate for overall accesses
560system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76570.665745 # average ReadReq miss latency
561system.l2c.ReadReq_avg_miss_latency::cpu0.data 64610.564386 # average ReadReq miss latency
562system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70477.137177 # average ReadReq miss latency
563system.l2c.ReadReq_avg_miss_latency::cpu1.data 80456.611570 # average ReadReq miss latency
564system.l2c.ReadReq_avg_miss_latency::total 65180.127871 # average ReadReq miss latency
565system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 438.099017 # average UpgradeReq miss latency
566system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5718.102064 # average UpgradeReq miss latency
567system.l2c.UpgradeReq_avg_miss_latency::total 2434.523619 # average UpgradeReq miss latency
568system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 909.645267 # average SCUpgradeReq miss latency
569system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 176.367853 # average SCUpgradeReq miss latency
570system.l2c.SCUpgradeReq_avg_miss_latency::total 541.417660 # average SCUpgradeReq miss latency
571system.l2c.ReadExReq_avg_miss_latency::cpu0.data 70071.939398 # average ReadExReq miss latency
572system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76597.722849 # average ReadExReq miss latency
573system.l2c.ReadExReq_avg_miss_latency::total 70340.122280 # average ReadExReq miss latency
574system.l2c.demand_avg_miss_latency::cpu0.inst 76570.665745 # average overall miss latency
575system.l2c.demand_avg_miss_latency::cpu0.data 66263.882686 # average overall miss latency
576system.l2c.demand_avg_miss_latency::cpu1.inst 70477.137177 # average overall miss latency
577system.l2c.demand_avg_miss_latency::cpu1.data 76774.020955 # average overall miss latency
578system.l2c.demand_avg_miss_latency::total 66734.071365 # average overall miss latency
579system.l2c.overall_avg_miss_latency::cpu0.inst 76570.665745 # average overall miss latency
580system.l2c.overall_avg_miss_latency::cpu0.data 66263.882686 # average overall miss latency
581system.l2c.overall_avg_miss_latency::cpu1.inst 70477.137177 # average overall miss latency
582system.l2c.overall_avg_miss_latency::cpu1.data 76774.020955 # average overall miss latency
583system.l2c.overall_avg_miss_latency::total 66734.071365 # average overall miss latency
584system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
585system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
586system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
587system.l2c.blocked::no_targets 0 # number of cycles access was blocked
588system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
589system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
590system.l2c.fast_writes 0 # number of fast writes performed
591system.l2c.cache_copies 0 # number of cache copies performed
592system.l2c.writebacks::writebacks 79475 # number of writebacks
593system.l2c.writebacks::total 79475 # number of writebacks
594system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits
595system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
596system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
597system.l2c.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
598system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
599system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
600system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
601system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
602system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits
603system.l2c.ReadReq_mshr_misses::cpu0.inst 13023 # number of ReadReq MSHR misses
604system.l2c.ReadReq_mshr_misses::cpu0.data 271672 # number of ReadReq MSHR misses
605system.l2c.ReadReq_mshr_misses::cpu1.inst 495 # number of ReadReq MSHR misses
606system.l2c.ReadReq_mshr_misses::cpu1.data 242 # number of ReadReq MSHR misses
607system.l2c.ReadReq_mshr_misses::total 285432 # number of ReadReq MSHR misses
608system.l2c.UpgradeReq_mshr_misses::cpu0.data 2949 # number of UpgradeReq MSHR misses
609system.l2c.UpgradeReq_mshr_misses::cpu1.data 1793 # number of UpgradeReq MSHR misses
610system.l2c.UpgradeReq_mshr_misses::total 4742 # number of UpgradeReq MSHR misses
611system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 919 # number of SCUpgradeReq MSHR misses
612system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 927 # number of SCUpgradeReq MSHR misses
613system.l2c.SCUpgradeReq_mshr_misses::total 1846 # number of SCUpgradeReq MSHR misses
614system.l2c.ReadExReq_mshr_misses::cpu0.data 117950 # number of ReadExReq MSHR misses
615system.l2c.ReadExReq_mshr_misses::cpu1.data 5055 # number of ReadExReq MSHR misses
616system.l2c.ReadExReq_mshr_misses::total 123005 # number of ReadExReq MSHR misses
617system.l2c.demand_mshr_misses::cpu0.inst 13023 # number of demand (read+write) MSHR misses
618system.l2c.demand_mshr_misses::cpu0.data 389622 # number of demand (read+write) MSHR misses
619system.l2c.demand_mshr_misses::cpu1.inst 495 # number of demand (read+write) MSHR misses
620system.l2c.demand_mshr_misses::cpu1.data 5297 # number of demand (read+write) MSHR misses
621system.l2c.demand_mshr_misses::total 408437 # number of demand (read+write) MSHR misses
622system.l2c.overall_mshr_misses::cpu0.inst 13023 # number of overall MSHR misses
623system.l2c.overall_mshr_misses::cpu0.data 389622 # number of overall MSHR misses
624system.l2c.overall_mshr_misses::cpu1.inst 495 # number of overall MSHR misses
625system.l2c.overall_mshr_misses::cpu1.data 5297 # number of overall MSHR misses
626system.l2c.overall_mshr_misses::total 408437 # number of overall MSHR misses
627system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 831386758 # number of ReadReq MSHR miss cycles
628system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14156096752 # number of ReadReq MSHR miss cycles
629system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 28603000 # number of ReadReq MSHR miss cycles
630system.l2c.ReadReq_mshr_miss_latency::cpu1.data 16450000 # number of ReadReq MSHR miss cycles
631system.l2c.ReadReq_mshr_miss_latency::total 15032536510 # number of ReadReq MSHR miss cycles
632system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29642946 # number of UpgradeReq MSHR miss cycles
633system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17939793 # number of UpgradeReq MSHR miss cycles
634system.l2c.UpgradeReq_mshr_miss_latency::total 47582739 # number of UpgradeReq MSHR miss cycles
635system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 9190919 # number of SCUpgradeReq MSHR miss cycles
636system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9270927 # number of SCUpgradeReq MSHR miss cycles
637system.l2c.SCUpgradeReq_mshr_miss_latency::total 18461846 # number of SCUpgradeReq MSHR miss cycles
638system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6783022748 # number of ReadExReq MSHR miss cycles
639system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 323366011 # number of ReadExReq MSHR miss cycles
640system.l2c.ReadExReq_mshr_miss_latency::total 7106388759 # number of ReadExReq MSHR miss cycles
641system.l2c.demand_mshr_miss_latency::cpu0.inst 831386758 # number of demand (read+write) MSHR miss cycles
642system.l2c.demand_mshr_miss_latency::cpu0.data 20939119500 # number of demand (read+write) MSHR miss cycles
643system.l2c.demand_mshr_miss_latency::cpu1.inst 28603000 # number of demand (read+write) MSHR miss cycles
644system.l2c.demand_mshr_miss_latency::cpu1.data 339816011 # number of demand (read+write) MSHR miss cycles
645system.l2c.demand_mshr_miss_latency::total 22138925269 # number of demand (read+write) MSHR miss cycles
646system.l2c.overall_mshr_miss_latency::cpu0.inst 831386758 # number of overall MSHR miss cycles
647system.l2c.overall_mshr_miss_latency::cpu0.data 20939119500 # number of overall MSHR miss cycles
648system.l2c.overall_mshr_miss_latency::cpu1.inst 28603000 # number of overall MSHR miss cycles
649system.l2c.overall_mshr_miss_latency::cpu1.data 339816011 # number of overall MSHR miss cycles
650system.l2c.overall_mshr_miss_latency::total 22138925269 # number of overall MSHR miss cycles
651system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373164500 # number of ReadReq MSHR uncacheable cycles
652system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17619000 # number of ReadReq MSHR uncacheable cycles
653system.l2c.ReadReq_mshr_uncacheable_latency::total 1390783500 # number of ReadReq MSHR uncacheable cycles
654system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154378500 # number of WriteReq MSHR uncacheable cycles
655system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 679235000 # number of WriteReq MSHR uncacheable cycles
656system.l2c.WriteReq_mshr_uncacheable_latency::total 2833613500 # number of WriteReq MSHR uncacheable cycles
657system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527543000 # number of overall MSHR uncacheable cycles
658system.l2c.overall_mshr_uncacheable_latency::cpu1.data 696854000 # number of overall MSHR uncacheable cycles
659system.l2c.overall_mshr_uncacheable_latency::total 4224397000 # number of overall MSHR uncacheable cycles
660system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for ReadReq accesses
661system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290187 # mshr miss rate for ReadReq accesses
662system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for ReadReq accesses
663system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002248 # mshr miss rate for ReadReq accesses
664system.l2c.ReadReq_mshr_miss_rate::total 0.138593 # mshr miss rate for ReadReq accesses
665system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942474 # mshr miss rate for UpgradeReq accesses
666system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768868 # mshr miss rate for UpgradeReq accesses
667system.l2c.UpgradeReq_mshr_miss_rate::total 0.868339 # mshr miss rate for UpgradeReq accesses
668system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.960293 # mshr miss rate for SCUpgradeReq accesses
669system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.977848 # mshr miss rate for SCUpgradeReq accesses
670system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969029 # mshr miss rate for SCUpgradeReq accesses
671system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477523 # mshr miss rate for ReadExReq accesses
672system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.105249 # mshr miss rate for ReadExReq accesses
673system.l2c.ReadExReq_mshr_miss_rate::total 0.416919 # mshr miss rate for ReadExReq accesses
674system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for demand accesses
675system.l2c.demand_mshr_miss_rate::cpu0.data 0.329295 # mshr miss rate for demand accesses
676system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for demand accesses
677system.l2c.demand_mshr_miss_rate::cpu1.data 0.034020 # mshr miss rate for demand accesses
678system.l2c.demand_mshr_miss_rate::total 0.173468 # mshr miss rate for demand accesses
679system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018664 # mshr miss rate for overall accesses
680system.l2c.overall_mshr_miss_rate::cpu0.data 0.329295 # mshr miss rate for overall accesses
681system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001557 # mshr miss rate for overall accesses
682system.l2c.overall_mshr_miss_rate::cpu1.data 0.034020 # mshr miss rate for overall accesses
683system.l2c.overall_mshr_miss_rate::total 0.173468 # mshr miss rate for overall accesses
684system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average ReadReq mshr miss latency
685system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52107.308637 # average ReadReq mshr miss latency
686system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average ReadReq mshr miss latency
687system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67975.206612 # average ReadReq mshr miss latency
688system.l2c.ReadReq_avg_mshr_miss_latency::total 52665.911706 # average ReadReq mshr miss latency
689system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10051.863683 # average UpgradeReq mshr miss latency
690system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.461796 # average UpgradeReq mshr miss latency
691system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.318642 # average UpgradeReq mshr miss latency
692system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
693system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
694system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
695system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57507.611259 # average ReadExReq mshr miss latency
696system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63969.537290 # average ReadExReq mshr miss latency
697system.l2c.ReadExReq_avg_mshr_miss_latency::total 57773.169863 # average ReadExReq mshr miss latency
698system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average overall mshr miss latency
699system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53742.138534 # average overall mshr miss latency
700system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency
701system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency
702system.l2c.demand_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency
703system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63839.880058 # average overall mshr miss latency
704system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53742.138534 # average overall mshr miss latency
705system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57783.838384 # average overall mshr miss latency
706system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64152.541250 # average overall mshr miss latency
707system.l2c.overall_avg_mshr_miss_latency::total 54204.014986 # average overall mshr miss latency
708system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
709system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
710system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
711system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
712system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
713system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
714system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
715system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
716system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
717system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
718system.iocache.tags.replacements 41694 # number of replacements
719system.iocache.tags.tagsinuse 0.570482 # Cycle average of tags in use
720system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
721system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks.
722system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
723system.iocache.tags.warmup_cycle 1754531382000 # Cycle when the warmup percentage was hit.
724system.iocache.tags.occ_blocks::tsunami.ide 0.570482 # Average occupied blocks per requestor
725system.iocache.tags.occ_percent::tsunami.ide 0.035655 # Average percentage of cache occupancy
726system.iocache.tags.occ_percent::total 0.035655 # Average percentage of cache occupancy
727system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
728system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
729system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
730system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
731system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
732system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
733system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
734system.iocache.overall_misses::total 41726 # number of overall misses
735system.iocache.ReadReq_miss_latency::tsunami.ide 21249133 # number of ReadReq miss cycles
736system.iocache.ReadReq_miss_latency::total 21249133 # number of ReadReq miss cycles
737system.iocache.WriteReq_miss_latency::tsunami.ide 12966402814 # number of WriteReq miss cycles
738system.iocache.WriteReq_miss_latency::total 12966402814 # number of WriteReq miss cycles
739system.iocache.demand_miss_latency::tsunami.ide 12987651947 # number of demand (read+write) miss cycles
740system.iocache.demand_miss_latency::total 12987651947 # number of demand (read+write) miss cycles
741system.iocache.overall_miss_latency::tsunami.ide 12987651947 # number of overall miss cycles
742system.iocache.overall_miss_latency::total 12987651947 # number of overall miss cycles
743system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
744system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
745system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
746system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
747system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
748system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
749system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
750system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
751system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
752system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
753system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
754system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
755system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
756system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
757system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
758system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
759system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122121.454023 # average ReadReq miss latency
760system.iocache.ReadReq_avg_miss_latency::total 122121.454023 # average ReadReq miss latency
761system.iocache.WriteReq_avg_miss_latency::tsunami.ide 312052.435839 # average WriteReq miss latency
762system.iocache.WriteReq_avg_miss_latency::total 312052.435839 # average WriteReq miss latency
763system.iocache.demand_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency
764system.iocache.demand_avg_miss_latency::total 311260.411901 # average overall miss latency
765system.iocache.overall_avg_miss_latency::tsunami.ide 311260.411901 # average overall miss latency
766system.iocache.overall_avg_miss_latency::total 311260.411901 # average overall miss latency
767system.iocache.blocked_cycles::no_mshrs 401197 # number of cycles access was blocked
768system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
769system.iocache.blocked::no_mshrs 28980 # number of cycles access was blocked
770system.iocache.blocked::no_targets 0 # number of cycles access was blocked
771system.iocache.avg_blocked_cycles::no_mshrs 13.843927 # average number of cycles each access was blocked
772system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
773system.iocache.fast_writes 0 # number of fast writes performed
774system.iocache.cache_copies 0 # number of cache copies performed
775system.iocache.writebacks::writebacks 41520 # number of writebacks
776system.iocache.writebacks::total 41520 # number of writebacks
777system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
778system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
779system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
780system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
781system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
782system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
783system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
784system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
785system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12200133 # number of ReadReq MSHR miss cycles
786system.iocache.ReadReq_mshr_miss_latency::total 12200133 # number of ReadReq MSHR miss cycles
787system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10804136814 # number of WriteReq MSHR miss cycles
788system.iocache.WriteReq_mshr_miss_latency::total 10804136814 # number of WriteReq MSHR miss cycles
789system.iocache.demand_mshr_miss_latency::tsunami.ide 10816336947 # number of demand (read+write) MSHR miss cycles
790system.iocache.demand_mshr_miss_latency::total 10816336947 # number of demand (read+write) MSHR miss cycles
791system.iocache.overall_mshr_miss_latency::tsunami.ide 10816336947 # number of overall MSHR miss cycles
792system.iocache.overall_mshr_miss_latency::total 10816336947 # number of overall MSHR miss cycles
793system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
794system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
795system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
796system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
797system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
798system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
799system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
800system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
801system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70115.706897 # average ReadReq mshr miss latency
802system.iocache.ReadReq_avg_mshr_miss_latency::total 70115.706897 # average ReadReq mshr miss latency
803system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 260014.844388 # average WriteReq mshr miss latency
804system.iocache.WriteReq_avg_mshr_miss_latency::total 260014.844388 # average WriteReq mshr miss latency
805system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency
806system.iocache.demand_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency
807system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 259222.953243 # average overall mshr miss latency
808system.iocache.overall_avg_mshr_miss_latency::total 259222.953243 # average overall mshr miss latency
809system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
810system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
811system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
812system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
813system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
814system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
815system.disk0.dma_write_txs 395 # Number of DMA write transactions.
816system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
817system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
818system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
819system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
820system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
821system.disk2.dma_write_txs 1 # Number of DMA write transactions.
822system.cpu0.dtb.fetch_hits 0 # ITB hits
823system.cpu0.dtb.fetch_misses 0 # ITB misses
824system.cpu0.dtb.fetch_acv 0 # ITB acv
825system.cpu0.dtb.fetch_accesses 0 # ITB accesses
826system.cpu0.dtb.read_hits 7532654 # DTB read hits
827system.cpu0.dtb.read_misses 7812 # DTB read misses
828system.cpu0.dtb.read_acv 210 # DTB read access violations
829system.cpu0.dtb.read_accesses 524694 # DTB read accesses
830system.cpu0.dtb.write_hits 5120278 # DTB write hits
831system.cpu0.dtb.write_misses 919 # DTB write misses
832system.cpu0.dtb.write_acv 139 # DTB write access violations
833system.cpu0.dtb.write_accesses 202960 # DTB write accesses
834system.cpu0.dtb.data_hits 12652932 # DTB hits
835system.cpu0.dtb.data_misses 8731 # DTB misses
836system.cpu0.dtb.data_acv 349 # DTB access violations
837system.cpu0.dtb.data_accesses 727654 # DTB accesses
838system.cpu0.itb.fetch_hits 3655515 # ITB hits
839system.cpu0.itb.fetch_misses 4023 # ITB misses
840system.cpu0.itb.fetch_acv 184 # ITB acv
841system.cpu0.itb.fetch_accesses 3659538 # ITB accesses
842system.cpu0.itb.read_hits 0 # DTB read hits
843system.cpu0.itb.read_misses 0 # DTB read misses
844system.cpu0.itb.read_acv 0 # DTB read access violations
845system.cpu0.itb.read_accesses 0 # DTB read accesses
846system.cpu0.itb.write_hits 0 # DTB write hits
847system.cpu0.itb.write_misses 0 # DTB write misses
848system.cpu0.itb.write_acv 0 # DTB write access violations
849system.cpu0.itb.write_accesses 0 # DTB write accesses
850system.cpu0.itb.data_hits 0 # DTB hits
851system.cpu0.itb.data_misses 0 # DTB misses
852system.cpu0.itb.data_acv 0 # DTB access violations
853system.cpu0.itb.data_accesses 0 # DTB accesses
854system.cpu0.numCycles 3921819749 # number of cpu cycles simulated
855system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
856system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
857system.cpu0.committedInsts 47983654 # Number of instructions committed
858system.cpu0.committedOps 47983654 # Number of ops (including micro ops) committed
859system.cpu0.num_int_alu_accesses 44515044 # Number of integer alu accesses
860system.cpu0.num_fp_alu_accesses 211401 # Number of float alu accesses
861system.cpu0.num_func_calls 1203620 # number of times a function call or return occured
862system.cpu0.num_conditional_control_insts 5635723 # number of instructions that are conditional controls
863system.cpu0.num_int_insts 44515044 # number of integer instructions
864system.cpu0.num_fp_insts 211401 # number of float instructions
865system.cpu0.num_int_register_reads 61226145 # number of times the integer registers were read
866system.cpu0.num_int_register_writes 33154260 # number of times the integer registers were written
867system.cpu0.num_fp_register_reads 103282 # number of times the floating registers were read
868system.cpu0.num_fp_register_writes 105080 # number of times the floating registers were written
869system.cpu0.num_mem_refs 12694028 # number of memory refs
870system.cpu0.num_load_insts 7560495 # Number of load instructions
871system.cpu0.num_store_insts 5133533 # Number of store instructions
872system.cpu0.num_idle_cycles 3698209766.998114 # Number of idle cycles
873system.cpu0.num_busy_cycles 223609982.001886 # Number of busy cycles
874system.cpu0.not_idle_fraction 0.057017 # Percentage of non-idle cycles
875system.cpu0.idle_fraction 0.942983 # Percentage of idle cycles
876system.cpu0.kern.inst.arm 0 # number of arm instructions executed
877system.cpu0.kern.inst.quiesce 6813 # number of quiesce instructions executed
878system.cpu0.kern.inst.hwrei 165343 # number of hwrei instructions executed
879system.cpu0.kern.ipl_count::0 56789 40.24% 40.24% # number of times we switched to this ipl
880system.cpu0.kern.ipl_count::21 131 0.09% 40.33% # number of times we switched to this ipl
881system.cpu0.kern.ipl_count::22 1973 1.40% 41.73% # number of times we switched to this ipl
882system.cpu0.kern.ipl_count::30 435 0.31% 42.04% # number of times we switched to this ipl
883system.cpu0.kern.ipl_count::31 81806 57.96% 100.00% # number of times we switched to this ipl
884system.cpu0.kern.ipl_count::total 141134 # number of times we switched to this ipl
885system.cpu0.kern.ipl_good::0 56279 49.08% 49.08% # number of times we switched to this ipl from a different ipl
886system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
887system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl
888system.cpu0.kern.ipl_good::30 435 0.38% 51.30% # number of times we switched to this ipl from a different ipl
889system.cpu0.kern.ipl_good::31 55844 48.70% 100.00% # number of times we switched to this ipl from a different ipl
890system.cpu0.kern.ipl_good::total 114662 # number of times we switched to this ipl from a different ipl
891system.cpu0.kern.ipl_ticks::0 1901501471500 96.97% 96.97% # number of cycles we spent at this ipl
892system.cpu0.kern.ipl_ticks::21 95150500 0.00% 96.98% # number of cycles we spent at this ipl
893system.cpu0.kern.ipl_ticks::22 767153500 0.04% 97.01% # number of cycles we spent at this ipl
894system.cpu0.kern.ipl_ticks::30 322241000 0.02% 97.03% # number of cycles we spent at this ipl
895system.cpu0.kern.ipl_ticks::31 58223100500 2.97% 100.00% # number of cycles we spent at this ipl
896system.cpu0.kern.ipl_ticks::total 1960909117000 # number of cycles we spent at this ipl
897system.cpu0.kern.ipl_used::0 0.991019 # fraction of swpipl calls that actually changed the ipl
898system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
899system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
900system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
901system.cpu0.kern.ipl_used::31 0.682639 # fraction of swpipl calls that actually changed the ipl
902system.cpu0.kern.ipl_used::total 0.812434 # fraction of swpipl calls that actually changed the ipl
903system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
904system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
905system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
906system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
907system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
908system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
909system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
910system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed

--- 19 unchanged lines hidden (view full) ---

930system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
931system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
932system.cpu0.kern.syscall::total 234 # number of syscalls executed
933system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
934system.cpu0.kern.callpal::wripir 517 0.35% 0.35% # number of callpals executed
935system.cpu0.kern.callpal::wrmces 1 0.00% 0.35% # number of callpals executed
936system.cpu0.kern.callpal::wrfen 1 0.00% 0.35% # number of callpals executed
937system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.35% # number of callpals executed
938system.cpu0.kern.callpal::swpctx 3090 2.07% 2.42% # number of callpals executed
939system.cpu0.kern.callpal::tbi 52 0.03% 2.45% # number of callpals executed
940system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed
941system.cpu0.kern.callpal::swpipl 134176 89.74% 92.20% # number of callpals executed
942system.cpu0.kern.callpal::rdps 6700 4.48% 96.68% # number of callpals executed
943system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed
944system.cpu0.kern.callpal::wrusp 4 0.00% 96.68% # number of callpals executed
945system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed
946system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed
947system.cpu0.kern.callpal::rti 4418 2.95% 99.64% # number of callpals executed
948system.cpu0.kern.callpal::callsys 396 0.26% 99.91% # number of callpals executed
949system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
950system.cpu0.kern.callpal::total 149515 # number of callpals executed
951system.cpu0.kern.mode_switch::kernel 7023 # number of protection mode switches
952system.cpu0.kern.mode_switch::user 1378 # number of protection mode switches
953system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
954system.cpu0.kern.mode_good::kernel 1377
955system.cpu0.kern.mode_good::user 1378
956system.cpu0.kern.mode_good::idle 0
957system.cpu0.kern.mode_switch_good::kernel 0.196070 # fraction of useful protection mode switches
958system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
959system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
960system.cpu0.kern.mode_switch_good::total 0.327937 # fraction of useful protection mode switches
961system.cpu0.kern.mode_ticks::kernel 1957102433500 99.81% 99.81% # number of ticks spent at the given mode
962system.cpu0.kern.mode_ticks::user 3806679000 0.19% 100.00% # number of ticks spent at the given mode
963system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
964system.cpu0.kern.swap_context 3091 # number of times the context was actually changed
965system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
966system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
967system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
968system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
969system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
970system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
971system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
972system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

988system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
989system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
990system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
991system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
992system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
993system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
994system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
995system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
996system.toL2Bus.throughput 103937669 # Throughput (bytes/s)
997system.toL2Bus.trans_dist::ReadReq 2101927 # Transaction distribution
998system.toL2Bus.trans_dist::ReadResp 2101912 # Transaction distribution
999system.toL2Bus.trans_dist::WriteReq 14109 # Transaction distribution
1000system.toL2Bus.trans_dist::WriteResp 14109 # Transaction distribution
1001system.toL2Bus.trans_dist::Writeback 791641 # Transaction distribution
1002system.toL2Bus.trans_dist::UpgradeReq 16698 # Transaction distribution
1003system.toL2Bus.trans_dist::SCUpgradeReq 11618 # Transaction distribution
1004system.toL2Bus.trans_dist::UpgradeResp 28316 # Transaction distribution
1005system.toL2Bus.trans_dist::ReadExReq 338479 # Transaction distribution
1006system.toL2Bus.trans_dist::ReadExResp 296929 # Transaction distribution
1007system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1395511 # Packet count per connected master and slave (bytes)
1008system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3121357 # Packet count per connected master and slave (bytes)
1009system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 635773 # Packet count per connected master and slave (bytes)
1010system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 463473 # Packet count per connected master and slave (bytes)
1011system.toL2Bus.pkt_count::total 5616114 # Packet count per connected master and slave (bytes)
1012system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44655680 # Cumulative packet size per connected master and slave (bytes)
1013system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119473096 # Cumulative packet size per connected master and slave (bytes)
1014system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20344704 # Cumulative packet size per connected master and slave (bytes)
1015system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16974250 # Cumulative packet size per connected master and slave (bytes)
1016system.toL2Bus.tot_pkt_size::total 201447730 # Cumulative packet size per connected master and slave (bytes)
1017system.toL2Bus.data_through_bus 201437426 # Total data (bytes)
1018system.toL2Bus.snoop_data_through_bus 2374976 # Total snoop data (bytes)
1019system.toL2Bus.reqLayer0.occupancy 4790041400 # Layer occupancy (ticks)
1020system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1021system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
1022system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1023system.toL2Bus.respLayer0.occupancy 3142512505 # Layer occupancy (ticks)
1024system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1025system.toL2Bus.respLayer1.occupancy 5519878863 # Layer occupancy (ticks)
1026system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
1027system.toL2Bus.respLayer2.occupancy 1430590492 # Layer occupancy (ticks)
1028system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
1029system.toL2Bus.respLayer3.occupancy 794307231 # Layer occupancy (ticks)
1030system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1031system.iobus.throughput 1399302 # Throughput (bytes/s)
1032system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
1033system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
1034system.iobus.trans_dist::WriteReq 55661 # Transaction distribution
1035system.iobus.trans_dist::WriteResp 55661 # Transaction distribution
1036system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14006 # Packet count per connected master and slave (bytes)
1037system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
1038system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1039system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1040system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1041system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1042system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
1043system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1044system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1045system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1046system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1047system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1048system.iobus.pkt_count_system.bridge.master::total 42616 # Packet count per connected master and slave (bytes)
1049system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
1050system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
1051system.iobus.pkt_count::total 126068 # Packet count per connected master and slave (bytes)
1052system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 56024 # Cumulative packet size per connected master and slave (bytes)
1053system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
1054system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1055system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1056system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1057system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1058system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
1059system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1060system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1061system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1062system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1063system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1064system.iobus.tot_pkt_size_system.bridge.master::total 82290 # Cumulative packet size per connected master and slave (bytes)
1065system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
1066system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
1067system.iobus.tot_pkt_size::total 2743906 # Cumulative packet size per connected master and slave (bytes)
1068system.iobus.data_through_bus 2743906 # Total data (bytes)
1069system.iobus.reqLayer0.occupancy 13361000 # Layer occupancy (ticks)
1070system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1071system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks)
1072system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1073system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1074system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1075system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1076system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1077system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)

--- 5 unchanged lines hidden (view full) ---

1083system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1084system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1085system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1086system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1087system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1088system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1089system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1090system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1091system.iobus.reqLayer29.occupancy 377744447 # Layer occupancy (ticks)
1092system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1093system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1094system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1095system.iobus.respLayer0.occupancy 28507000 # Layer occupancy (ticks)
1096system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1097system.iobus.respLayer1.occupancy 42681500 # Layer occupancy (ticks)
1098system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1099system.cpu0.icache.tags.replacements 697136 # number of replacements
1100system.cpu0.icache.tags.tagsinuse 508.398756 # Cycle average of tags in use
1101system.cpu0.icache.tags.total_refs 47294969 # Total number of references to valid blocks.
1102system.cpu0.icache.tags.sampled_refs 697648 # Sample count of references to valid blocks.
1103system.cpu0.icache.tags.avg_refs 67.792023 # Average number of references to valid blocks.
1104system.cpu0.icache.tags.warmup_cycle 40091069250 # Cycle when the warmup percentage was hit.
1105system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.398756 # Average occupied blocks per requestor
1106system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992966 # Average percentage of cache occupancy
1107system.cpu0.icache.tags.occ_percent::total 0.992966 # Average percentage of cache occupancy
1108system.cpu0.icache.ReadReq_hits::cpu0.inst 47294969 # number of ReadReq hits
1109system.cpu0.icache.ReadReq_hits::total 47294969 # number of ReadReq hits
1110system.cpu0.icache.demand_hits::cpu0.inst 47294969 # number of demand (read+write) hits
1111system.cpu0.icache.demand_hits::total 47294969 # number of demand (read+write) hits
1112system.cpu0.icache.overall_hits::cpu0.inst 47294969 # number of overall hits
1113system.cpu0.icache.overall_hits::total 47294969 # number of overall hits
1114system.cpu0.icache.ReadReq_misses::cpu0.inst 697766 # number of ReadReq misses
1115system.cpu0.icache.ReadReq_misses::total 697766 # number of ReadReq misses
1116system.cpu0.icache.demand_misses::cpu0.inst 697766 # number of demand (read+write) misses
1117system.cpu0.icache.demand_misses::total 697766 # number of demand (read+write) misses
1118system.cpu0.icache.overall_misses::cpu0.inst 697766 # number of overall misses
1119system.cpu0.icache.overall_misses::total 697766 # number of overall misses
1120system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9984385005 # number of ReadReq miss cycles
1121system.cpu0.icache.ReadReq_miss_latency::total 9984385005 # number of ReadReq miss cycles
1122system.cpu0.icache.demand_miss_latency::cpu0.inst 9984385005 # number of demand (read+write) miss cycles
1123system.cpu0.icache.demand_miss_latency::total 9984385005 # number of demand (read+write) miss cycles
1124system.cpu0.icache.overall_miss_latency::cpu0.inst 9984385005 # number of overall miss cycles
1125system.cpu0.icache.overall_miss_latency::total 9984385005 # number of overall miss cycles
1126system.cpu0.icache.ReadReq_accesses::cpu0.inst 47992735 # number of ReadReq accesses(hits+misses)
1127system.cpu0.icache.ReadReq_accesses::total 47992735 # number of ReadReq accesses(hits+misses)
1128system.cpu0.icache.demand_accesses::cpu0.inst 47992735 # number of demand (read+write) accesses
1129system.cpu0.icache.demand_accesses::total 47992735 # number of demand (read+write) accesses
1130system.cpu0.icache.overall_accesses::cpu0.inst 47992735 # number of overall (read+write) accesses
1131system.cpu0.icache.overall_accesses::total 47992735 # number of overall (read+write) accesses
1132system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014539 # miss rate for ReadReq accesses
1133system.cpu0.icache.ReadReq_miss_rate::total 0.014539 # miss rate for ReadReq accesses
1134system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014539 # miss rate for demand accesses
1135system.cpu0.icache.demand_miss_rate::total 0.014539 # miss rate for demand accesses
1136system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014539 # miss rate for overall accesses
1137system.cpu0.icache.overall_miss_rate::total 0.014539 # miss rate for overall accesses
1138system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14309.073536 # average ReadReq miss latency
1139system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.073536 # average ReadReq miss latency
1140system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency
1141system.cpu0.icache.demand_avg_miss_latency::total 14309.073536 # average overall miss latency
1142system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14309.073536 # average overall miss latency
1143system.cpu0.icache.overall_avg_miss_latency::total 14309.073536 # average overall miss latency
1144system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1145system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1146system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1147system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1148system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1149system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1150system.cpu0.icache.fast_writes 0 # number of fast writes performed
1151system.cpu0.icache.cache_copies 0 # number of cache copies performed
1152system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 697766 # number of ReadReq MSHR misses
1153system.cpu0.icache.ReadReq_mshr_misses::total 697766 # number of ReadReq MSHR misses
1154system.cpu0.icache.demand_mshr_misses::cpu0.inst 697766 # number of demand (read+write) MSHR misses
1155system.cpu0.icache.demand_mshr_misses::total 697766 # number of demand (read+write) MSHR misses
1156system.cpu0.icache.overall_mshr_misses::cpu0.inst 697766 # number of overall MSHR misses
1157system.cpu0.icache.overall_mshr_misses::total 697766 # number of overall MSHR misses
1158system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8583721995 # number of ReadReq MSHR miss cycles
1159system.cpu0.icache.ReadReq_mshr_miss_latency::total 8583721995 # number of ReadReq MSHR miss cycles
1160system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8583721995 # number of demand (read+write) MSHR miss cycles
1161system.cpu0.icache.demand_mshr_miss_latency::total 8583721995 # number of demand (read+write) MSHR miss cycles
1162system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8583721995 # number of overall MSHR miss cycles
1163system.cpu0.icache.overall_mshr_miss_latency::total 8583721995 # number of overall MSHR miss cycles
1164system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for ReadReq accesses
1165system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses
1166system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for demand accesses
1167system.cpu0.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses
1168system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014539 # mshr miss rate for overall accesses
1169system.cpu0.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses
1170system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average ReadReq mshr miss latency
1171system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12301.720054 # average ReadReq mshr miss latency
1172system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency
1173system.cpu0.icache.demand_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency
1174system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12301.720054 # average overall mshr miss latency
1175system.cpu0.icache.overall_avg_mshr_miss_latency::total 12301.720054 # average overall mshr miss latency
1176system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1177system.cpu0.dcache.tags.replacements 1186229 # number of replacements
1178system.cpu0.dcache.tags.tagsinuse 505.271614 # Cycle average of tags in use
1179system.cpu0.dcache.tags.total_refs 11460994 # Total number of references to valid blocks.
1180system.cpu0.dcache.tags.sampled_refs 1186741 # Sample count of references to valid blocks.
1181system.cpu0.dcache.tags.avg_refs 9.657536 # Average number of references to valid blocks.
1182system.cpu0.dcache.tags.warmup_cycle 107902250 # Cycle when the warmup percentage was hit.
1183system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.271614 # Average occupied blocks per requestor
1184system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986859 # Average percentage of cache occupancy
1185system.cpu0.dcache.tags.occ_percent::total 0.986859 # Average percentage of cache occupancy
1186system.cpu0.dcache.ReadReq_hits::cpu0.data 6451735 # number of ReadReq hits
1187system.cpu0.dcache.ReadReq_hits::total 6451735 # number of ReadReq hits
1188system.cpu0.dcache.WriteReq_hits::cpu0.data 4706856 # number of WriteReq hits
1189system.cpu0.dcache.WriteReq_hits::total 4706856 # number of WriteReq hits
1190system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140512 # number of LoadLockedReq hits
1191system.cpu0.dcache.LoadLockedReq_hits::total 140512 # number of LoadLockedReq hits
1192system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148003 # number of StoreCondReq hits
1193system.cpu0.dcache.StoreCondReq_hits::total 148003 # number of StoreCondReq hits
1194system.cpu0.dcache.demand_hits::cpu0.data 11158591 # number of demand (read+write) hits
1195system.cpu0.dcache.demand_hits::total 11158591 # number of demand (read+write) hits
1196system.cpu0.dcache.overall_hits::cpu0.data 11158591 # number of overall hits
1197system.cpu0.dcache.overall_hits::total 11158591 # number of overall hits
1198system.cpu0.dcache.ReadReq_misses::cpu0.data 939483 # number of ReadReq misses
1199system.cpu0.dcache.ReadReq_misses::total 939483 # number of ReadReq misses
1200system.cpu0.dcache.WriteReq_misses::cpu0.data 256736 # number of WriteReq misses
1201system.cpu0.dcache.WriteReq_misses::total 256736 # number of WriteReq misses
1202system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13633 # number of LoadLockedReq misses
1203system.cpu0.dcache.LoadLockedReq_misses::total 13633 # number of LoadLockedReq misses
1204system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5600 # number of StoreCondReq misses
1205system.cpu0.dcache.StoreCondReq_misses::total 5600 # number of StoreCondReq misses
1206system.cpu0.dcache.demand_misses::cpu0.data 1196219 # number of demand (read+write) misses
1207system.cpu0.dcache.demand_misses::total 1196219 # number of demand (read+write) misses
1208system.cpu0.dcache.overall_misses::cpu0.data 1196219 # number of overall misses
1209system.cpu0.dcache.overall_misses::total 1196219 # number of overall misses
1210system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27076055500 # number of ReadReq miss cycles
1211system.cpu0.dcache.ReadReq_miss_latency::total 27076055500 # number of ReadReq miss cycles
1212system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10459807694 # number of WriteReq miss cycles
1213system.cpu0.dcache.WriteReq_miss_latency::total 10459807694 # number of WriteReq miss cycles
1214system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 148332750 # number of LoadLockedReq miss cycles
1215system.cpu0.dcache.LoadLockedReq_miss_latency::total 148332750 # number of LoadLockedReq miss cycles
1216system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 43345419 # number of StoreCondReq miss cycles
1217system.cpu0.dcache.StoreCondReq_miss_latency::total 43345419 # number of StoreCondReq miss cycles
1218system.cpu0.dcache.demand_miss_latency::cpu0.data 37535863194 # number of demand (read+write) miss cycles
1219system.cpu0.dcache.demand_miss_latency::total 37535863194 # number of demand (read+write) miss cycles
1220system.cpu0.dcache.overall_miss_latency::cpu0.data 37535863194 # number of overall miss cycles
1221system.cpu0.dcache.overall_miss_latency::total 37535863194 # number of overall miss cycles
1222system.cpu0.dcache.ReadReq_accesses::cpu0.data 7391218 # number of ReadReq accesses(hits+misses)
1223system.cpu0.dcache.ReadReq_accesses::total 7391218 # number of ReadReq accesses(hits+misses)
1224system.cpu0.dcache.WriteReq_accesses::cpu0.data 4963592 # number of WriteReq accesses(hits+misses)
1225system.cpu0.dcache.WriteReq_accesses::total 4963592 # number of WriteReq accesses(hits+misses)
1226system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154145 # number of LoadLockedReq accesses(hits+misses)
1227system.cpu0.dcache.LoadLockedReq_accesses::total 154145 # number of LoadLockedReq accesses(hits+misses)
1228system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153603 # number of StoreCondReq accesses(hits+misses)
1229system.cpu0.dcache.StoreCondReq_accesses::total 153603 # number of StoreCondReq accesses(hits+misses)
1230system.cpu0.dcache.demand_accesses::cpu0.data 12354810 # number of demand (read+write) accesses
1231system.cpu0.dcache.demand_accesses::total 12354810 # number of demand (read+write) accesses
1232system.cpu0.dcache.overall_accesses::cpu0.data 12354810 # number of overall (read+write) accesses
1233system.cpu0.dcache.overall_accesses::total 12354810 # number of overall (read+write) accesses
1234system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127108 # miss rate for ReadReq accesses
1235system.cpu0.dcache.ReadReq_miss_rate::total 0.127108 # miss rate for ReadReq accesses
1236system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051724 # miss rate for WriteReq accesses
1237system.cpu0.dcache.WriteReq_miss_rate::total 0.051724 # miss rate for WriteReq accesses
1238system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088443 # miss rate for LoadLockedReq accesses
1239system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088443 # miss rate for LoadLockedReq accesses
1240system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036458 # miss rate for StoreCondReq accesses
1241system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036458 # miss rate for StoreCondReq accesses
1242system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096822 # miss rate for demand accesses
1243system.cpu0.dcache.demand_miss_rate::total 0.096822 # miss rate for demand accesses
1244system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096822 # miss rate for overall accesses
1245system.cpu0.dcache.overall_miss_rate::total 0.096822 # miss rate for overall accesses
1246system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28820.165453 # average ReadReq miss latency
1247system.cpu0.dcache.ReadReq_avg_miss_latency::total 28820.165453 # average ReadReq miss latency
1248system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40741.492015 # average WriteReq miss latency
1249system.cpu0.dcache.WriteReq_avg_miss_latency::total 40741.492015 # average WriteReq miss latency
1250system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10880.418837 # average LoadLockedReq miss latency
1251system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10880.418837 # average LoadLockedReq miss latency
1252system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7740.253393 # average StoreCondReq miss latency
1253system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7740.253393 # average StoreCondReq miss latency
1254system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency
1255system.cpu0.dcache.demand_avg_miss_latency::total 31378.755223 # average overall miss latency
1256system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31378.755223 # average overall miss latency
1257system.cpu0.dcache.overall_avg_miss_latency::total 31378.755223 # average overall miss latency
1258system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1259system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1260system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1261system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1262system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1263system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1264system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1265system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1266system.cpu0.dcache.writebacks::writebacks 682519 # number of writebacks
1267system.cpu0.dcache.writebacks::total 682519 # number of writebacks
1268system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939483 # number of ReadReq MSHR misses
1269system.cpu0.dcache.ReadReq_mshr_misses::total 939483 # number of ReadReq MSHR misses
1270system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256736 # number of WriteReq MSHR misses
1271system.cpu0.dcache.WriteReq_mshr_misses::total 256736 # number of WriteReq MSHR misses
1272system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13633 # number of LoadLockedReq MSHR misses
1273system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13633 # number of LoadLockedReq MSHR misses
1274system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5600 # number of StoreCondReq MSHR misses
1275system.cpu0.dcache.StoreCondReq_mshr_misses::total 5600 # number of StoreCondReq MSHR misses
1276system.cpu0.dcache.demand_mshr_misses::cpu0.data 1196219 # number of demand (read+write) MSHR misses
1277system.cpu0.dcache.demand_mshr_misses::total 1196219 # number of demand (read+write) MSHR misses
1278system.cpu0.dcache.overall_mshr_misses::cpu0.data 1196219 # number of overall MSHR misses
1279system.cpu0.dcache.overall_mshr_misses::total 1196219 # number of overall MSHR misses
1280system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25065202500 # number of ReadReq MSHR miss cycles
1281system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25065202500 # number of ReadReq MSHR miss cycles
1282system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9891526306 # number of WriteReq MSHR miss cycles
1283system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9891526306 # number of WriteReq MSHR miss cycles
1284system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121052250 # number of LoadLockedReq MSHR miss cycles
1285system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121052250 # number of LoadLockedReq MSHR miss cycles
1286system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 32145581 # number of StoreCondReq MSHR miss cycles
1287system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32145581 # number of StoreCondReq MSHR miss cycles
1288system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
1289system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
1290system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34956728806 # number of demand (read+write) MSHR miss cycles
1291system.cpu0.dcache.demand_mshr_miss_latency::total 34956728806 # number of demand (read+write) MSHR miss cycles
1292system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34956728806 # number of overall MSHR miss cycles
1293system.cpu0.dcache.overall_mshr_miss_latency::total 34956728806 # number of overall MSHR miss cycles
1294system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465602000 # number of ReadReq MSHR uncacheable cycles
1295system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465602000 # number of ReadReq MSHR uncacheable cycles
1296system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2284723500 # number of WriteReq MSHR uncacheable cycles
1297system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2284723500 # number of WriteReq MSHR uncacheable cycles
1298system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3750325500 # number of overall MSHR uncacheable cycles
1299system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3750325500 # number of overall MSHR uncacheable cycles
1300system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127108 # mshr miss rate for ReadReq accesses
1301system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127108 # mshr miss rate for ReadReq accesses
1302system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051724 # mshr miss rate for WriteReq accesses
1303system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051724 # mshr miss rate for WriteReq accesses
1304system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088443 # mshr miss rate for LoadLockedReq accesses
1305system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088443 # mshr miss rate for LoadLockedReq accesses
1306system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036458 # mshr miss rate for StoreCondReq accesses
1307system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036458 # mshr miss rate for StoreCondReq accesses
1308system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for demand accesses
1309system.cpu0.dcache.demand_mshr_miss_rate::total 0.096822 # mshr miss rate for demand accesses
1310system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096822 # mshr miss rate for overall accesses
1311system.cpu0.dcache.overall_mshr_miss_rate::total 0.096822 # mshr miss rate for overall accesses
1312system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26679.782923 # average ReadReq mshr miss latency
1313system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26679.782923 # average ReadReq mshr miss latency
1314system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 38528.006614 # average WriteReq mshr miss latency
1315system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 38528.006614 # average WriteReq mshr miss latency
1316system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8879.355241 # average LoadLockedReq mshr miss latency
1317system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8879.355241 # average LoadLockedReq mshr miss latency
1318system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5740.282321 # average StoreCondReq mshr miss latency
1319system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5740.282321 # average StoreCondReq mshr miss latency
1320system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1321system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1322system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency
1323system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency
1324system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29222.683142 # average overall mshr miss latency
1325system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29222.683142 # average overall mshr miss latency
1326system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1327system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1328system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1329system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1330system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1331system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1332system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1333system.cpu1.dtb.fetch_hits 0 # ITB hits
1334system.cpu1.dtb.fetch_misses 0 # ITB misses
1335system.cpu1.dtb.fetch_acv 0 # ITB acv
1336system.cpu1.dtb.fetch_accesses 0 # ITB accesses
1337system.cpu1.dtb.read_hits 2383442 # DTB read hits
1338system.cpu1.dtb.read_misses 2620 # DTB read misses
1339system.cpu1.dtb.read_acv 0 # DTB read access violations
1340system.cpu1.dtb.read_accesses 205337 # DTB read accesses
1341system.cpu1.dtb.write_hits 1706844 # DTB write hits
1342system.cpu1.dtb.write_misses 235 # DTB write misses
1343system.cpu1.dtb.write_acv 24 # DTB write access violations
1344system.cpu1.dtb.write_accesses 89739 # DTB write accesses
1345system.cpu1.dtb.data_hits 4090286 # DTB hits
1346system.cpu1.dtb.data_misses 2855 # DTB misses
1347system.cpu1.dtb.data_acv 24 # DTB access violations
1348system.cpu1.dtb.data_accesses 295076 # DTB accesses
1349system.cpu1.itb.fetch_hits 1814139 # ITB hits
1350system.cpu1.itb.fetch_misses 1064 # ITB misses
1351system.cpu1.itb.fetch_acv 0 # ITB acv
1352system.cpu1.itb.fetch_accesses 1815203 # ITB accesses
1353system.cpu1.itb.read_hits 0 # DTB read hits
1354system.cpu1.itb.read_misses 0 # DTB read misses
1355system.cpu1.itb.read_acv 0 # DTB read access violations
1356system.cpu1.itb.read_accesses 0 # DTB read accesses
1357system.cpu1.itb.write_hits 0 # DTB write hits
1358system.cpu1.itb.write_misses 0 # DTB write misses
1359system.cpu1.itb.write_acv 0 # DTB write access violations
1360system.cpu1.itb.write_accesses 0 # DTB write accesses
1361system.cpu1.itb.data_hits 0 # DTB hits
1362system.cpu1.itb.data_misses 0 # DTB misses
1363system.cpu1.itb.data_acv 0 # DTB access violations
1364system.cpu1.itb.data_accesses 0 # DTB accesses
1365system.cpu1.numCycles 3919927793 # number of cpu cycles simulated
1366system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1367system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1368system.cpu1.committedInsts 12950293 # Number of instructions committed
1369system.cpu1.committedOps 12950293 # Number of ops (including micro ops) committed
1370system.cpu1.num_int_alu_accesses 11929999 # Number of integer alu accesses
1371system.cpu1.num_fp_alu_accesses 174217 # Number of float alu accesses
1372system.cpu1.num_func_calls 410658 # number of times a function call or return occured
1373system.cpu1.num_conditional_control_insts 1281658 # number of instructions that are conditional controls
1374system.cpu1.num_int_insts 11929999 # number of integer instructions
1375system.cpu1.num_fp_insts 174217 # number of float instructions
1376system.cpu1.num_int_register_reads 16394755 # number of times the integer registers were read
1377system.cpu1.num_int_register_writes 8774296 # number of times the integer registers were written
1378system.cpu1.num_fp_register_reads 90513 # number of times the floating registers were read
1379system.cpu1.num_fp_register_writes 92474 # number of times the floating registers were written
1380system.cpu1.num_mem_refs 4113222 # number of memory refs
1381system.cpu1.num_load_insts 2397194 # Number of load instructions
1382system.cpu1.num_store_insts 1716028 # Number of store instructions
1383system.cpu1.num_idle_cycles 3870487590.349789 # Number of idle cycles
1384system.cpu1.num_busy_cycles 49440202.650211 # Number of busy cycles
1385system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles
1386system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles
1387system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1388system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed
1389system.cpu1.kern.inst.hwrei 78268 # number of hwrei instructions executed
1390system.cpu1.kern.ipl_count::0 26619 38.27% 38.27% # number of times we switched to this ipl
1391system.cpu1.kern.ipl_count::22 1969 2.83% 41.10% # number of times we switched to this ipl
1392system.cpu1.kern.ipl_count::30 517 0.74% 41.84% # number of times we switched to this ipl
1393system.cpu1.kern.ipl_count::31 40454 58.16% 100.00% # number of times we switched to this ipl
1394system.cpu1.kern.ipl_count::total 69559 # number of times we switched to this ipl
1395system.cpu1.kern.ipl_good::0 25752 48.16% 48.16% # number of times we switched to this ipl from a different ipl
1396system.cpu1.kern.ipl_good::22 1969 3.68% 51.84% # number of times we switched to this ipl from a different ipl
1397system.cpu1.kern.ipl_good::30 517 0.97% 52.81% # number of times we switched to this ipl from a different ipl
1398system.cpu1.kern.ipl_good::31 25236 47.19% 100.00% # number of times we switched to this ipl from a different ipl
1399system.cpu1.kern.ipl_good::total 53474 # number of times we switched to this ipl from a different ipl
1400system.cpu1.kern.ipl_ticks::0 1908686801000 97.38% 97.38% # number of cycles we spent at this ipl
1401system.cpu1.kern.ipl_ticks::22 700508000 0.04% 97.42% # number of cycles we spent at this ipl
1402system.cpu1.kern.ipl_ticks::30 362068000 0.02% 97.44% # number of cycles we spent at this ipl
1403system.cpu1.kern.ipl_ticks::31 50214489500 2.56% 100.00% # number of cycles we spent at this ipl
1404system.cpu1.kern.ipl_ticks::total 1959963866500 # number of cycles we spent at this ipl
1405system.cpu1.kern.ipl_used::0 0.967429 # fraction of swpipl calls that actually changed the ipl
1406system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1407system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
1408system.cpu1.kern.ipl_used::31 0.623820 # fraction of swpipl calls that actually changed the ipl
1409system.cpu1.kern.ipl_used::total 0.768757 # fraction of swpipl calls that actually changed the ipl
1410system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
1411system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
1412system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
1413system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
1414system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
1415system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
1416system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
1417system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
1418system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
1419system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
1420system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
1421system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
1422system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
1423system.cpu1.kern.syscall::total 92 # number of syscalls executed
1424system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
1425system.cpu1.kern.callpal::wripir 435 0.61% 0.61% # number of callpals executed
1426system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
1427system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed
1428system.cpu1.kern.callpal::swpctx 2001 2.79% 3.40% # number of callpals executed
1429system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed
1430system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed
1431system.cpu1.kern.callpal::swpipl 63355 88.19% 91.60% # number of callpals executed
1432system.cpu1.kern.callpal::rdps 2145 2.99% 94.59% # number of callpals executed
1433system.cpu1.kern.callpal::wrkgp 1 0.00% 94.59% # number of callpals executed
1434system.cpu1.kern.callpal::wrusp 3 0.00% 94.59% # number of callpals executed
1435system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed
1436system.cpu1.kern.callpal::rti 3718 5.18% 99.77% # number of callpals executed
1437system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
1438system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
1439system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
1440system.cpu1.kern.callpal::total 71838 # number of callpals executed
1441system.cpu1.kern.mode_switch::kernel 1956 # number of protection mode switches
1442system.cpu1.kern.mode_switch::user 368 # number of protection mode switches
1443system.cpu1.kern.mode_switch::idle 2906 # number of protection mode switches
1444system.cpu1.kern.mode_good::kernel 809
1445system.cpu1.kern.mode_good::user 368
1446system.cpu1.kern.mode_good::idle 441
1447system.cpu1.kern.mode_switch_good::kernel 0.413599 # fraction of useful protection mode switches
1448system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1449system.cpu1.kern.mode_switch_good::idle 0.151755 # fraction of useful protection mode switches
1450system.cpu1.kern.mode_switch_good::total 0.309369 # fraction of useful protection mode switches
1451system.cpu1.kern.mode_ticks::kernel 17986814000 0.92% 0.92% # number of ticks spent at the given mode
1452system.cpu1.kern.mode_ticks::user 1484472500 0.08% 0.99% # number of ticks spent at the given mode
1453system.cpu1.kern.mode_ticks::idle 1939632240000 99.01% 100.00% # number of ticks spent at the given mode
1454system.cpu1.kern.swap_context 2002 # number of times the context was actually changed
1455system.cpu1.icache.tags.replacements 317336 # number of replacements
1456system.cpu1.icache.tags.tagsinuse 446.450379 # Cycle average of tags in use
1457system.cpu1.icache.tags.total_refs 12635285 # Total number of references to valid blocks.
1458system.cpu1.icache.tags.sampled_refs 317847 # Sample count of references to valid blocks.
1459system.cpu1.icache.tags.avg_refs 39.752727 # Average number of references to valid blocks.
1460system.cpu1.icache.tags.warmup_cycle 1958987590000 # Cycle when the warmup percentage was hit.
1461system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.450379 # Average occupied blocks per requestor
1462system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871973 # Average percentage of cache occupancy
1463system.cpu1.icache.tags.occ_percent::total 0.871973 # Average percentage of cache occupancy
1464system.cpu1.icache.ReadReq_hits::cpu1.inst 12635285 # number of ReadReq hits
1465system.cpu1.icache.ReadReq_hits::total 12635285 # number of ReadReq hits
1466system.cpu1.icache.demand_hits::cpu1.inst 12635285 # number of demand (read+write) hits
1467system.cpu1.icache.demand_hits::total 12635285 # number of demand (read+write) hits
1468system.cpu1.icache.overall_hits::cpu1.inst 12635285 # number of overall hits
1469system.cpu1.icache.overall_hits::total 12635285 # number of overall hits
1470system.cpu1.icache.ReadReq_misses::cpu1.inst 317887 # number of ReadReq misses
1471system.cpu1.icache.ReadReq_misses::total 317887 # number of ReadReq misses
1472system.cpu1.icache.demand_misses::cpu1.inst 317887 # number of demand (read+write) misses
1473system.cpu1.icache.demand_misses::total 317887 # number of demand (read+write) misses
1474system.cpu1.icache.overall_misses::cpu1.inst 317887 # number of overall misses
1475system.cpu1.icache.overall_misses::total 317887 # number of overall misses
1476system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4180819492 # number of ReadReq miss cycles
1477system.cpu1.icache.ReadReq_miss_latency::total 4180819492 # number of ReadReq miss cycles
1478system.cpu1.icache.demand_miss_latency::cpu1.inst 4180819492 # number of demand (read+write) miss cycles
1479system.cpu1.icache.demand_miss_latency::total 4180819492 # number of demand (read+write) miss cycles
1480system.cpu1.icache.overall_miss_latency::cpu1.inst 4180819492 # number of overall miss cycles
1481system.cpu1.icache.overall_miss_latency::total 4180819492 # number of overall miss cycles
1482system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953172 # number of ReadReq accesses(hits+misses)
1483system.cpu1.icache.ReadReq_accesses::total 12953172 # number of ReadReq accesses(hits+misses)
1484system.cpu1.icache.demand_accesses::cpu1.inst 12953172 # number of demand (read+write) accesses
1485system.cpu1.icache.demand_accesses::total 12953172 # number of demand (read+write) accesses
1486system.cpu1.icache.overall_accesses::cpu1.inst 12953172 # number of overall (read+write) accesses
1487system.cpu1.icache.overall_accesses::total 12953172 # number of overall (read+write) accesses
1488system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024541 # miss rate for ReadReq accesses
1489system.cpu1.icache.ReadReq_miss_rate::total 0.024541 # miss rate for ReadReq accesses
1490system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024541 # miss rate for demand accesses
1491system.cpu1.icache.demand_miss_rate::total 0.024541 # miss rate for demand accesses
1492system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024541 # miss rate for overall accesses
1493system.cpu1.icache.overall_miss_rate::total 0.024541 # miss rate for overall accesses
1494system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13151.904582 # average ReadReq miss latency
1495system.cpu1.icache.ReadReq_avg_miss_latency::total 13151.904582 # average ReadReq miss latency
1496system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency
1497system.cpu1.icache.demand_avg_miss_latency::total 13151.904582 # average overall miss latency
1498system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13151.904582 # average overall miss latency
1499system.cpu1.icache.overall_avg_miss_latency::total 13151.904582 # average overall miss latency
1500system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1501system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1502system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1503system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1504system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1505system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1506system.cpu1.icache.fast_writes 0 # number of fast writes performed
1507system.cpu1.icache.cache_copies 0 # number of cache copies performed
1508system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 317887 # number of ReadReq MSHR misses
1509system.cpu1.icache.ReadReq_mshr_misses::total 317887 # number of ReadReq MSHR misses
1510system.cpu1.icache.demand_mshr_misses::cpu1.inst 317887 # number of demand (read+write) MSHR misses
1511system.cpu1.icache.demand_mshr_misses::total 317887 # number of demand (read+write) MSHR misses
1512system.cpu1.icache.overall_mshr_misses::cpu1.inst 317887 # number of overall MSHR misses
1513system.cpu1.icache.overall_mshr_misses::total 317887 # number of overall MSHR misses
1514system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3544847508 # number of ReadReq MSHR miss cycles
1515system.cpu1.icache.ReadReq_mshr_miss_latency::total 3544847508 # number of ReadReq MSHR miss cycles
1516system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3544847508 # number of demand (read+write) MSHR miss cycles
1517system.cpu1.icache.demand_mshr_miss_latency::total 3544847508 # number of demand (read+write) MSHR miss cycles
1518system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3544847508 # number of overall MSHR miss cycles
1519system.cpu1.icache.overall_mshr_miss_latency::total 3544847508 # number of overall MSHR miss cycles
1520system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for ReadReq accesses
1521system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024541 # mshr miss rate for ReadReq accesses
1522system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for demand accesses
1523system.cpu1.icache.demand_mshr_miss_rate::total 0.024541 # mshr miss rate for demand accesses
1524system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024541 # mshr miss rate for overall accesses
1525system.cpu1.icache.overall_mshr_miss_rate::total 0.024541 # mshr miss rate for overall accesses
1526system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average ReadReq mshr miss latency
1527system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11151.281770 # average ReadReq mshr miss latency
1528system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency
1529system.cpu1.icache.demand_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency
1530system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11151.281770 # average overall mshr miss latency
1531system.cpu1.icache.overall_avg_mshr_miss_latency::total 11151.281770 # average overall mshr miss latency
1532system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1533system.cpu1.dcache.tags.replacements 158764 # number of replacements
1534system.cpu1.dcache.tags.tagsinuse 485.752776 # Cycle average of tags in use
1535system.cpu1.dcache.tags.total_refs 3916687 # Total number of references to valid blocks.
1536system.cpu1.dcache.tags.sampled_refs 159090 # Sample count of references to valid blocks.
1537system.cpu1.dcache.tags.avg_refs 24.619316 # Average number of references to valid blocks.
1538system.cpu1.dcache.tags.warmup_cycle 67802253000 # Cycle when the warmup percentage was hit.
1539system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.752776 # Average occupied blocks per requestor
1540system.cpu1.dcache.tags.occ_percent::cpu1.data 0.948736 # Average percentage of cache occupancy
1541system.cpu1.dcache.tags.occ_percent::total 0.948736 # Average percentage of cache occupancy
1542system.cpu1.dcache.ReadReq_hits::cpu1.data 2220669 # number of ReadReq hits
1543system.cpu1.dcache.ReadReq_hits::total 2220669 # number of ReadReq hits
1544system.cpu1.dcache.WriteReq_hits::cpu1.data 1595283 # number of WriteReq hits
1545system.cpu1.dcache.WriteReq_hits::total 1595283 # number of WriteReq hits
1546system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48031 # number of LoadLockedReq hits
1547system.cpu1.dcache.LoadLockedReq_hits::total 48031 # number of LoadLockedReq hits
1548system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50613 # number of StoreCondReq hits
1549system.cpu1.dcache.StoreCondReq_hits::total 50613 # number of StoreCondReq hits
1550system.cpu1.dcache.demand_hits::cpu1.data 3815952 # number of demand (read+write) hits
1551system.cpu1.dcache.demand_hits::total 3815952 # number of demand (read+write) hits
1552system.cpu1.dcache.overall_hits::cpu1.data 3815952 # number of overall hits
1553system.cpu1.dcache.overall_hits::total 3815952 # number of overall hits
1554system.cpu1.dcache.ReadReq_misses::cpu1.data 116704 # number of ReadReq misses
1555system.cpu1.dcache.ReadReq_misses::total 116704 # number of ReadReq misses
1556system.cpu1.dcache.WriteReq_misses::cpu1.data 56889 # number of WriteReq misses
1557system.cpu1.dcache.WriteReq_misses::total 56889 # number of WriteReq misses
1558system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9081 # number of LoadLockedReq misses
1559system.cpu1.dcache.LoadLockedReq_misses::total 9081 # number of LoadLockedReq misses
1560system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6019 # number of StoreCondReq misses
1561system.cpu1.dcache.StoreCondReq_misses::total 6019 # number of StoreCondReq misses
1562system.cpu1.dcache.demand_misses::cpu1.data 173593 # number of demand (read+write) misses
1563system.cpu1.dcache.demand_misses::total 173593 # number of demand (read+write) misses
1564system.cpu1.dcache.overall_misses::cpu1.data 173593 # number of overall misses
1565system.cpu1.dcache.overall_misses::total 173593 # number of overall misses
1566system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1411486000 # number of ReadReq miss cycles
1567system.cpu1.dcache.ReadReq_miss_latency::total 1411486000 # number of ReadReq miss cycles
1568system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1044020804 # number of WriteReq miss cycles
1569system.cpu1.dcache.WriteReq_miss_latency::total 1044020804 # number of WriteReq miss cycles
1570system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82357000 # number of LoadLockedReq miss cycles
1571system.cpu1.dcache.LoadLockedReq_miss_latency::total 82357000 # number of LoadLockedReq miss cycles
1572system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 44184927 # number of StoreCondReq miss cycles
1573system.cpu1.dcache.StoreCondReq_miss_latency::total 44184927 # number of StoreCondReq miss cycles
1574system.cpu1.dcache.demand_miss_latency::cpu1.data 2455506804 # number of demand (read+write) miss cycles
1575system.cpu1.dcache.demand_miss_latency::total 2455506804 # number of demand (read+write) miss cycles
1576system.cpu1.dcache.overall_miss_latency::cpu1.data 2455506804 # number of overall miss cycles
1577system.cpu1.dcache.overall_miss_latency::total 2455506804 # number of overall miss cycles
1578system.cpu1.dcache.ReadReq_accesses::cpu1.data 2337373 # number of ReadReq accesses(hits+misses)
1579system.cpu1.dcache.ReadReq_accesses::total 2337373 # number of ReadReq accesses(hits+misses)
1580system.cpu1.dcache.WriteReq_accesses::cpu1.data 1652172 # number of WriteReq accesses(hits+misses)
1581system.cpu1.dcache.WriteReq_accesses::total 1652172 # number of WriteReq accesses(hits+misses)
1582system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57112 # number of LoadLockedReq accesses(hits+misses)
1583system.cpu1.dcache.LoadLockedReq_accesses::total 57112 # number of LoadLockedReq accesses(hits+misses)
1584system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56632 # number of StoreCondReq accesses(hits+misses)
1585system.cpu1.dcache.StoreCondReq_accesses::total 56632 # number of StoreCondReq accesses(hits+misses)
1586system.cpu1.dcache.demand_accesses::cpu1.data 3989545 # number of demand (read+write) accesses
1587system.cpu1.dcache.demand_accesses::total 3989545 # number of demand (read+write) accesses
1588system.cpu1.dcache.overall_accesses::cpu1.data 3989545 # number of overall (read+write) accesses
1589system.cpu1.dcache.overall_accesses::total 3989545 # number of overall (read+write) accesses
1590system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049930 # miss rate for ReadReq accesses
1591system.cpu1.dcache.ReadReq_miss_rate::total 0.049930 # miss rate for ReadReq accesses
1592system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034433 # miss rate for WriteReq accesses
1593system.cpu1.dcache.WriteReq_miss_rate::total 0.034433 # miss rate for WriteReq accesses
1594system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.159003 # miss rate for LoadLockedReq accesses
1595system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.159003 # miss rate for LoadLockedReq accesses
1596system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106283 # miss rate for StoreCondReq accesses
1597system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106283 # miss rate for StoreCondReq accesses
1598system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043512 # miss rate for demand accesses
1599system.cpu1.dcache.demand_miss_rate::total 0.043512 # miss rate for demand accesses
1600system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043512 # miss rate for overall accesses
1601system.cpu1.dcache.overall_miss_rate::total 0.043512 # miss rate for overall accesses
1602system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12094.581163 # average ReadReq miss latency
1603system.cpu1.dcache.ReadReq_avg_miss_latency::total 12094.581163 # average ReadReq miss latency
1604system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18351.892352 # average WriteReq miss latency
1605system.cpu1.dcache.WriteReq_avg_miss_latency::total 18351.892352 # average WriteReq miss latency
1606system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9069.155379 # average LoadLockedReq miss latency
1607system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9069.155379 # average LoadLockedReq miss latency
1608system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7340.908290 # average StoreCondReq miss latency
1609system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7340.908290 # average StoreCondReq miss latency
1610system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency
1611system.cpu1.dcache.demand_avg_miss_latency::total 14145.194818 # average overall miss latency
1612system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14145.194818 # average overall miss latency
1613system.cpu1.dcache.overall_avg_miss_latency::total 14145.194818 # average overall miss latency
1614system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1615system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1616system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1617system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1618system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1619system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1620system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1621system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1622system.cpu1.dcache.writebacks::writebacks 109122 # number of writebacks
1623system.cpu1.dcache.writebacks::total 109122 # number of writebacks
1624system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116704 # number of ReadReq MSHR misses
1625system.cpu1.dcache.ReadReq_mshr_misses::total 116704 # number of ReadReq MSHR misses
1626system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 56889 # number of WriteReq MSHR misses
1627system.cpu1.dcache.WriteReq_mshr_misses::total 56889 # number of WriteReq MSHR misses
1628system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9081 # number of LoadLockedReq MSHR misses
1629system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9081 # number of LoadLockedReq MSHR misses
1630system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6019 # number of StoreCondReq MSHR misses
1631system.cpu1.dcache.StoreCondReq_mshr_misses::total 6019 # number of StoreCondReq MSHR misses
1632system.cpu1.dcache.demand_mshr_misses::cpu1.data 173593 # number of demand (read+write) MSHR misses
1633system.cpu1.dcache.demand_mshr_misses::total 173593 # number of demand (read+write) MSHR misses
1634system.cpu1.dcache.overall_mshr_misses::cpu1.data 173593 # number of overall MSHR misses
1635system.cpu1.dcache.overall_mshr_misses::total 173593 # number of overall MSHR misses
1636system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1178000000 # number of ReadReq MSHR miss cycles
1637system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1178000000 # number of ReadReq MSHR miss cycles
1638system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 927938196 # number of WriteReq MSHR miss cycles
1639system.cpu1.dcache.WriteReq_mshr_miss_latency::total 927938196 # number of WriteReq MSHR miss cycles
1640system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 64195000 # number of LoadLockedReq MSHR miss cycles
1641system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 64195000 # number of LoadLockedReq MSHR miss cycles
1642system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32145073 # number of StoreCondReq MSHR miss cycles
1643system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32145073 # number of StoreCondReq MSHR miss cycles
1644system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2105938196 # number of demand (read+write) MSHR miss cycles
1645system.cpu1.dcache.demand_mshr_miss_latency::total 2105938196 # number of demand (read+write) MSHR miss cycles
1646system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2105938196 # number of overall MSHR miss cycles
1647system.cpu1.dcache.overall_mshr_miss_latency::total 2105938196 # number of overall MSHR miss cycles
1648system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776000 # number of ReadReq MSHR uncacheable cycles
1649system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776000 # number of ReadReq MSHR uncacheable cycles
1650system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 718207000 # number of WriteReq MSHR uncacheable cycles
1651system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 718207000 # number of WriteReq MSHR uncacheable cycles
1652system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 736983000 # number of overall MSHR uncacheable cycles
1653system.cpu1.dcache.overall_mshr_uncacheable_latency::total 736983000 # number of overall MSHR uncacheable cycles
1654system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049930 # mshr miss rate for ReadReq accesses
1655system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049930 # mshr miss rate for ReadReq accesses
1656system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034433 # mshr miss rate for WriteReq accesses
1657system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034433 # mshr miss rate for WriteReq accesses
1658system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159003 # mshr miss rate for LoadLockedReq accesses
1659system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159003 # mshr miss rate for LoadLockedReq accesses
1660system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106283 # mshr miss rate for StoreCondReq accesses
1661system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106283 # mshr miss rate for StoreCondReq accesses
1662system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for demand accesses
1663system.cpu1.dcache.demand_mshr_miss_rate::total 0.043512 # mshr miss rate for demand accesses
1664system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043512 # mshr miss rate for overall accesses
1665system.cpu1.dcache.overall_mshr_miss_rate::total 0.043512 # mshr miss rate for overall accesses
1666system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10093.912805 # average ReadReq mshr miss latency
1667system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10093.912805 # average ReadReq mshr miss latency
1668system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16311.381743 # average WriteReq mshr miss latency
1669system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16311.381743 # average WriteReq mshr miss latency
1670system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7069.155379 # average LoadLockedReq mshr miss latency
1671system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7069.155379 # average LoadLockedReq mshr miss latency
1672system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5340.600266 # average StoreCondReq mshr miss latency
1673system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5340.600266 # average StoreCondReq mshr miss latency
1674system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency
1675system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency
1676system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12131.469564 # average overall mshr miss latency
1677system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12131.469564 # average overall mshr miss latency
1678system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1679system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1680system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1681system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1682system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1683system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1684system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1685
1686---------- End Simulation Statistics ----------