1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.954691 # Number of seconds simulated
4sim_ticks 1954691371500 # Number of ticks simulated
5final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 798728 # Simulator instruction rate (inst/s)
8host_op_rate 798728 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 26318676085 # Simulator tick rate (ticks/s)
10host_mem_usage 332420 # Number of bytes of host memory used
11host_seconds 74.27 # Real time elapsed on the host
12sim_insts 59321614 # Number of instructions simulated
13sim_ops 59321614 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory
19system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory
25system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory
32system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory
33system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::tsunami.ide 1356130 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.data 199364 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.readReqs 447836 # Total number of read requests seen
52system.physmem.writeReqs 119953 # Total number of write requests seen
53system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady
54system.physmem.bytesRead 28661504 # Total number of bytes read from memory
55system.physmem.bytesWritten 7676992 # Total number of bytes written to memory
56system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize()
57system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize()
58system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
59system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed
60system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis
74system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis
75system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis
76system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::1 7504 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis
90system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis
91system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis
92system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
93system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry
94system.physmem.totGap 1954684300500 # Total gap between requests
95system.physmem.readPktSize::0 0 # Categorize read packet sizes
96system.physmem.readPktSize::1 0 # Categorize read packet sizes
97system.physmem.readPktSize::2 0 # Categorize read packet sizes
98system.physmem.readPktSize::3 0 # Categorize read packet sizes
99system.physmem.readPktSize::4 0 # Categorize read packet sizes
100system.physmem.readPktSize::5 0 # Categorize read packet sizes
101system.physmem.readPktSize::6 447836 # Categorize read packet sizes
102system.physmem.writePktSize::0 0 # Categorize write packet sizes
103system.physmem.writePktSize::1 0 # Categorize write packet sizes
104system.physmem.writePktSize::2 0 # Categorize write packet sizes
105system.physmem.writePktSize::3 0 # Categorize write packet sizes
106system.physmem.writePktSize::4 0 # Categorize write packet sizes
107system.physmem.writePktSize::5 0 # Categorize write packet sizes
108system.physmem.writePktSize::6 119953 # Categorize write packet sizes
109system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
141system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::12 5215 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::13 5215 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::14 5215 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::15 5215 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::16 5215 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::17 5215 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::18 5215 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::19 5215 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::23 1507 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::25 940 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::26 888 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
173system.physmem.totQLat 4783798250 # Total cycles spent in queuing delays
174system.physmem.totMemAccLat 13397999500 # Sum of mem lat for all requests
175system.physmem.totBusLat 2238835000 # Total cycles spent in databus access
176system.physmem.totBankLat 6375366250 # Total cycles spent in bank access
177system.physmem.avgQLat 10683.68 # Average queueing delay per request
178system.physmem.avgBankLat 14238.13 # Average bank access latency per request
179system.physmem.avgBusLat 5000.00 # Average bus latency per request
180system.physmem.avgMemAccLat 29921.81 # Average memory access latency
181system.physmem.avgRdBW 14.66 # Average achieved read bandwidth in MB/s
182system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s
183system.physmem.avgConsumedRdBW 14.66 # Average consumed read bandwidth in MB/s
184system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s
185system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
186system.physmem.busUtil 0.15 # Data bus utilization in percentage
187system.physmem.avgRdQLen 0.01 # Average read queue length over time
188system.physmem.avgWrQLen 10.91 # Average write queue length over time
189system.physmem.readRowHits 419870 # Number of row buffer hits during reads
190system.physmem.writeRowHits 92076 # Number of row buffer hits during writes
191system.physmem.readRowHitRate 93.77 # Row buffer hit rate for reads
192system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes
193system.physmem.avgGap 3442624.46 # Average gap between requests
194system.l2c.replacements 340771 # number of replacements
195system.l2c.tagsinuse 65303.436480 # Cycle average of tags in use
196system.l2c.total_refs 2493415 # Total number of references to valid blocks.
197system.l2c.sampled_refs 405943 # Sample count of references to valid blocks.
198system.l2c.avg_refs 6.142279 # Average number of references to valid blocks.
199system.l2c.warmup_cycle 6937754751 # Cycle when the warmup percentage was hit.
200system.l2c.occ_blocks::writebacks 55559.705668 # Average occupied blocks per requestor
201system.l2c.occ_blocks::cpu0.inst 4839.489270 # Average occupied blocks per requestor
202system.l2c.occ_blocks::cpu0.data 4775.815267 # Average occupied blocks per requestor
203system.l2c.occ_blocks::cpu1.inst 117.980929 # Average occupied blocks per requestor
204system.l2c.occ_blocks::cpu1.data 10.445347 # Average occupied blocks per requestor
205system.l2c.occ_percent::writebacks 0.847774 # Average percentage of cache occupancy
206system.l2c.occ_percent::cpu0.inst 0.073845 # Average percentage of cache occupancy
207system.l2c.occ_percent::cpu0.data 0.072873 # Average percentage of cache occupancy
208system.l2c.occ_percent::cpu1.inst 0.001800 # Average percentage of cache occupancy
209system.l2c.occ_percent::cpu1.data 0.000159 # Average percentage of cache occupancy
210system.l2c.occ_percent::total 0.996451 # Average percentage of cache occupancy
211system.l2c.ReadReq_hits::cpu0.inst 902966 # number of ReadReq hits
212system.l2c.ReadReq_hits::cpu0.data 773506 # number of ReadReq hits
213system.l2c.ReadReq_hits::cpu1.inst 86370 # number of ReadReq hits
214system.l2c.ReadReq_hits::cpu1.data 33767 # number of ReadReq hits
215system.l2c.ReadReq_hits::total 1796609 # number of ReadReq hits
216system.l2c.Writeback_hits::writebacks 820435 # number of Writeback hits
217system.l2c.Writeback_hits::total 820435 # number of Writeback hits
218system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits
219system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits
220system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits
221system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits
222system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits
223system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits
224system.l2c.ReadExReq_hits::cpu0.data 171833 # number of ReadExReq hits
225system.l2c.ReadExReq_hits::cpu1.data 12858 # number of ReadExReq hits
226system.l2c.ReadExReq_hits::total 184691 # number of ReadExReq hits
227system.l2c.demand_hits::cpu0.inst 902966 # number of demand (read+write) hits
228system.l2c.demand_hits::cpu0.data 945339 # number of demand (read+write) hits
229system.l2c.demand_hits::cpu1.inst 86370 # number of demand (read+write) hits
230system.l2c.demand_hits::cpu1.data 46625 # number of demand (read+write) hits
231system.l2c.demand_hits::total 1981300 # number of demand (read+write) hits
232system.l2c.overall_hits::cpu0.inst 902966 # number of overall hits
233system.l2c.overall_hits::cpu0.data 945339 # number of overall hits
234system.l2c.overall_hits::cpu1.inst 86370 # number of overall hits
235system.l2c.overall_hits::cpu1.data 46625 # number of overall hits
236system.l2c.overall_hits::total 1981300 # number of overall hits
237system.l2c.ReadReq_misses::cpu0.inst 12959 # number of ReadReq misses
238system.l2c.ReadReq_misses::cpu0.data 271596 # number of ReadReq misses
239system.l2c.ReadReq_misses::cpu1.inst 545 # number of ReadReq misses
240system.l2c.ReadReq_misses::cpu1.data 189 # number of ReadReq misses
241system.l2c.ReadReq_misses::total 285289 # number of ReadReq misses
242system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses
243system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses
244system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses
245system.l2c.SCUpgradeReq_misses::cpu0.data 27 # number of SCUpgradeReq misses
246system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses
247system.l2c.SCUpgradeReq_misses::total 100 # number of SCUpgradeReq misses
248system.l2c.ReadExReq_misses::cpu0.data 115623 # number of ReadExReq misses
249system.l2c.ReadExReq_misses::cpu1.data 5918 # number of ReadExReq misses
250system.l2c.ReadExReq_misses::total 121541 # number of ReadExReq misses
251system.l2c.demand_misses::cpu0.inst 12959 # number of demand (read+write) misses
252system.l2c.demand_misses::cpu0.data 387219 # number of demand (read+write) misses
253system.l2c.demand_misses::cpu1.inst 545 # number of demand (read+write) misses
254system.l2c.demand_misses::cpu1.data 6107 # number of demand (read+write) misses
255system.l2c.demand_misses::total 406830 # number of demand (read+write) misses
256system.l2c.overall_misses::cpu0.inst 12959 # number of overall misses
257system.l2c.overall_misses::cpu0.data 387219 # number of overall misses
258system.l2c.overall_misses::cpu1.inst 545 # number of overall misses
259system.l2c.overall_misses::cpu1.data 6107 # number of overall misses
260system.l2c.overall_misses::total 406830 # number of overall misses
261system.l2c.ReadReq_miss_latency::cpu0.inst 800348000 # number of ReadReq miss cycles
262system.l2c.ReadReq_miss_latency::cpu0.data 11682390000 # number of ReadReq miss cycles
263system.l2c.ReadReq_miss_latency::cpu1.inst 34833000 # number of ReadReq miss cycles
264system.l2c.ReadReq_miss_latency::cpu1.data 14789000 # number of ReadReq miss cycles
265system.l2c.ReadReq_miss_latency::total 12532360000 # number of ReadReq miss cycles
266system.l2c.UpgradeReq_miss_latency::cpu0.data 1038000 # number of UpgradeReq miss cycles
267system.l2c.UpgradeReq_miss_latency::cpu1.data 229000 # number of UpgradeReq miss cycles
268system.l2c.UpgradeReq_miss_latency::total 1267000 # number of UpgradeReq miss cycles
269system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles
270system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles
271system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles
272system.l2c.ReadExReq_miss_latency::cpu0.data 5536684000 # number of ReadExReq miss cycles
273system.l2c.ReadExReq_miss_latency::cpu1.data 338210000 # number of ReadExReq miss cycles
274system.l2c.ReadExReq_miss_latency::total 5874894000 # number of ReadExReq miss cycles
275system.l2c.demand_miss_latency::cpu0.inst 800348000 # number of demand (read+write) miss cycles
276system.l2c.demand_miss_latency::cpu0.data 17219074000 # number of demand (read+write) miss cycles
277system.l2c.demand_miss_latency::cpu1.inst 34833000 # number of demand (read+write) miss cycles
278system.l2c.demand_miss_latency::cpu1.data 352999000 # number of demand (read+write) miss cycles
279system.l2c.demand_miss_latency::total 18407254000 # number of demand (read+write) miss cycles
280system.l2c.overall_miss_latency::cpu0.inst 800348000 # number of overall miss cycles
281system.l2c.overall_miss_latency::cpu0.data 17219074000 # number of overall miss cycles
282system.l2c.overall_miss_latency::cpu1.inst 34833000 # number of overall miss cycles
283system.l2c.overall_miss_latency::cpu1.data 352999000 # number of overall miss cycles
284system.l2c.overall_miss_latency::total 18407254000 # number of overall miss cycles
285system.l2c.ReadReq_accesses::cpu0.inst 915925 # number of ReadReq accesses(hits+misses)
286system.l2c.ReadReq_accesses::cpu0.data 1045102 # number of ReadReq accesses(hits+misses)
287system.l2c.ReadReq_accesses::cpu1.inst 86915 # number of ReadReq accesses(hits+misses)
288system.l2c.ReadReq_accesses::cpu1.data 33956 # number of ReadReq accesses(hits+misses)
289system.l2c.ReadReq_accesses::total 2081898 # number of ReadReq accesses(hits+misses)
290system.l2c.Writeback_accesses::writebacks 820435 # number of Writeback accesses(hits+misses)
291system.l2c.Writeback_accesses::total 820435 # number of Writeback accesses(hits+misses)
292system.l2c.UpgradeReq_accesses::cpu0.data 2605 # number of UpgradeReq accesses(hits+misses)
293system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses)
294system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses)
295system.l2c.SCUpgradeReq_accesses::cpu0.data 48 # number of SCUpgradeReq accesses(hits+misses)
296system.l2c.SCUpgradeReq_accesses::cpu1.data 92 # number of SCUpgradeReq accesses(hits+misses)
297system.l2c.SCUpgradeReq_accesses::total 140 # number of SCUpgradeReq accesses(hits+misses)
298system.l2c.ReadExReq_accesses::cpu0.data 287456 # number of ReadExReq accesses(hits+misses)
299system.l2c.ReadExReq_accesses::cpu1.data 18776 # number of ReadExReq accesses(hits+misses)
300system.l2c.ReadExReq_accesses::total 306232 # number of ReadExReq accesses(hits+misses)
301system.l2c.demand_accesses::cpu0.inst 915925 # number of demand (read+write) accesses
302system.l2c.demand_accesses::cpu0.data 1332558 # number of demand (read+write) accesses
303system.l2c.demand_accesses::cpu1.inst 86915 # number of demand (read+write) accesses
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341system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 474.120083 # average UpgradeReq miss latency
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344system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1575.342466 # average SCUpgradeReq miss latency
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364system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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368system.l2c.writebacks::total 78433 # number of writebacks
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424system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 18171000 # number of ReadReq MSHR uncacheable cycles
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438system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.896104 # mshr miss rate for UpgradeReq accesses
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441system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.793478 # mshr miss rate for SCUpgradeReq accesses
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454system.l2c.overall_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for overall accesses
455system.l2c.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses
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457system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30735.648128 # average ReadReq mshr miss latency
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462system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
463system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10056.895726 # average UpgradeReq mshr miss latency
464system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
465system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
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468system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44509.775431 # average ReadExReq mshr miss latency
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473system.l2c.demand_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency
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475system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency
476system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency
477system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency
478system.l2c.overall_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency
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481system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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484system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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487system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
488system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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491system.iocache.tagsinuse 0.572561 # Cycle average of tags in use
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494system.iocache.avg_refs 0 # Average number of references to valid blocks.
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526system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
527system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
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532system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency
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536system.iocache.demand_avg_miss_latency::total 256337.626516 # average overall miss latency
537system.iocache.overall_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency
538system.iocache.overall_avg_miss_latency::total 256337.626516 # average overall miss latency
539system.iocache.blocked_cycles::no_mshrs 286340 # number of cycles access was blocked
540system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
541system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked
542system.iocache.blocked::no_targets 0 # number of cycles access was blocked
543system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked
544system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
545system.iocache.fast_writes 0 # number of fast writes performed
546system.iocache.cache_copies 0 # number of cache copies performed
547system.iocache.writebacks::writebacks 41520 # number of writebacks
548system.iocache.writebacks::total 41520 # number of writebacks
549system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
550system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
551system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
552system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
553system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
554system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
555system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
556system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
557system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles
558system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles
559system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles
560system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles
561system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles
562system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles
563system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles
564system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles
565system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
566system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
567system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
568system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
569system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
570system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
571system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
572system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
573system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency
574system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency
575system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency
576system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency
577system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
578system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
579system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
580system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
581system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
582system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
583system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
584system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
585system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
586system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
587system.disk0.dma_write_txs 395 # Number of DMA write transactions.
588system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
589system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
590system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
591system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
592system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
593system.disk2.dma_write_txs 1 # Number of DMA write transactions.
594system.cpu0.dtb.fetch_hits 0 # ITB hits
595system.cpu0.dtb.fetch_misses 0 # ITB misses
596system.cpu0.dtb.fetch_acv 0 # ITB acv
597system.cpu0.dtb.fetch_accesses 0 # ITB accesses
598system.cpu0.dtb.read_hits 8631552 # DTB read hits
599system.cpu0.dtb.read_misses 7447 # DTB read misses
600system.cpu0.dtb.read_acv 210 # DTB read access violations
601system.cpu0.dtb.read_accesses 490676 # DTB read accesses
602system.cpu0.dtb.write_hits 6044616 # DTB write hits
603system.cpu0.dtb.write_misses 813 # DTB write misses
604system.cpu0.dtb.write_acv 134 # DTB write access violations
605system.cpu0.dtb.write_accesses 187452 # DTB write accesses
606system.cpu0.dtb.data_hits 14676168 # DTB hits
607system.cpu0.dtb.data_misses 8260 # DTB misses
608system.cpu0.dtb.data_acv 344 # DTB access violations
609system.cpu0.dtb.data_accesses 678128 # DTB accesses
610system.cpu0.itb.fetch_hits 3853435 # ITB hits
611system.cpu0.itb.fetch_misses 3871 # ITB misses
612system.cpu0.itb.fetch_acv 184 # ITB acv
613system.cpu0.itb.fetch_accesses 3857306 # ITB accesses
614system.cpu0.itb.read_hits 0 # DTB read hits
615system.cpu0.itb.read_misses 0 # DTB read misses
616system.cpu0.itb.read_acv 0 # DTB read access violations
617system.cpu0.itb.read_accesses 0 # DTB read accesses
618system.cpu0.itb.write_hits 0 # DTB write hits
619system.cpu0.itb.write_misses 0 # DTB write misses
620system.cpu0.itb.write_acv 0 # DTB write access violations
621system.cpu0.itb.write_accesses 0 # DTB write accesses
622system.cpu0.itb.data_hits 0 # DTB hits
623system.cpu0.itb.data_misses 0 # DTB misses
624system.cpu0.itb.data_acv 0 # DTB access violations
625system.cpu0.itb.data_accesses 0 # DTB accesses
626system.cpu0.numCycles 3908211536 # number of cpu cycles simulated
627system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
628system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
629system.cpu0.committedInsts 54061829 # Number of instructions committed
630system.cpu0.committedOps 54061829 # Number of ops (including micro ops) committed
631system.cpu0.num_int_alu_accesses 50032862 # Number of integer alu accesses
632system.cpu0.num_fp_alu_accesses 294101 # Number of float alu accesses
633system.cpu0.num_func_calls 1426501 # number of times a function call or return occured
634system.cpu0.num_conditional_control_insts 6236445 # number of instructions that are conditional controls
635system.cpu0.num_int_insts 50032862 # number of integer instructions
636system.cpu0.num_fp_insts 294101 # number of float instructions
637system.cpu0.num_int_register_reads 68513770 # number of times the integer registers were read
638system.cpu0.num_int_register_writes 37070851 # number of times the integer registers were written
639system.cpu0.num_fp_register_reads 143419 # number of times the floating registers were read
640system.cpu0.num_fp_register_writes 146520 # number of times the floating registers were written
641system.cpu0.num_mem_refs 14722187 # number of memory refs
642system.cpu0.num_load_insts 8662865 # Number of load instructions
643system.cpu0.num_store_insts 6059322 # Number of store instructions
644system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles
645system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles
646system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles
647system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles
648system.cpu0.kern.inst.arm 0 # number of arm instructions executed
649system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed
650system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed
651system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl
652system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl
653system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl
654system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
655system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl
656system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl
657system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl
658system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
659system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl
660system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
661system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl
662system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl
663system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl
664system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl
665system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl
666system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl
667system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl
668system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl
669system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl
670system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
671system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
672system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
673system.cpu0.kern.ipl_used::31 0.684859 # fraction of swpipl calls that actually changed the ipl
674system.cpu0.kern.ipl_used::total 0.808964 # fraction of swpipl calls that actually changed the ipl
675system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
676system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
677system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
678system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
679system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
680system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
681system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
682system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed

--- 15 unchanged lines hidden (view full) ---

698system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
699system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
700system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
701system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
702system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
703system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
704system.cpu0.kern.syscall::total 222 # number of syscalls executed
705system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
706system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed
707system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
708system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
709system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
710system.cpu0.kern.callpal::swpctx 3896 2.07% 2.12% # number of callpals executed
711system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed
712system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed
713system.cpu0.kern.callpal::swpipl 172217 91.50% 93.65% # number of callpals executed
714system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed
715system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed
716system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed
717system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
718system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed
719system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed
720system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
721system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
722system.cpu0.kern.callpal::total 188224 # number of callpals executed
723system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches
724system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
725system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
726system.cpu0.kern.mode_good::kernel 1283
727system.cpu0.kern.mode_good::user 1283
728system.cpu0.kern.mode_good::idle 0
729system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches
730system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
731system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
732system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches
733system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode
734system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode
735system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
736system.cpu0.kern.swap_context 3897 # number of times the context was actually changed
737system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
738system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
739system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
740system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
741system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
742system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
743system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
744system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

760system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
761system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
762system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
763system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
764system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
765system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
766system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
767system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
768system.cpu0.icache.replacements 915312 # number of replacements
769system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use
770system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks.
771system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks.
772system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks.
773system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit.
774system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor
775system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy
776system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy
777system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits
778system.cpu0.icache.ReadReq_hits::total 53154487 # number of ReadReq hits
779system.cpu0.icache.demand_hits::cpu0.inst 53154487 # number of demand (read+write) hits
780system.cpu0.icache.demand_hits::total 53154487 # number of demand (read+write) hits
781system.cpu0.icache.overall_hits::cpu0.inst 53154487 # number of overall hits
782system.cpu0.icache.overall_hits::total 53154487 # number of overall hits
783system.cpu0.icache.ReadReq_misses::cpu0.inst 915946 # number of ReadReq misses
784system.cpu0.icache.ReadReq_misses::total 915946 # number of ReadReq misses
785system.cpu0.icache.demand_misses::cpu0.inst 915946 # number of demand (read+write) misses
786system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses
787system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses
788system.cpu0.icache.overall_misses::total 915946 # number of overall misses
789system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles
790system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles
791system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles
792system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles
793system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles
794system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles
795system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses)
796system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses)
797system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses
798system.cpu0.icache.demand_accesses::total 54070433 # number of demand (read+write) accesses
799system.cpu0.icache.overall_accesses::cpu0.inst 54070433 # number of overall (read+write) accesses
800system.cpu0.icache.overall_accesses::total 54070433 # number of overall (read+write) accesses
801system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016940 # miss rate for ReadReq accesses
802system.cpu0.icache.ReadReq_miss_rate::total 0.016940 # miss rate for ReadReq accesses
803system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 # miss rate for demand accesses
804system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses
805system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses
806system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses
807system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency
808system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency
809system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency
810system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency
811system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency
812system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency
813system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
814system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
815system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
816system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
817system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
818system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
819system.cpu0.icache.fast_writes 0 # number of fast writes performed
820system.cpu0.icache.cache_copies 0 # number of cache copies performed
821system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915946 # number of ReadReq MSHR misses
822system.cpu0.icache.ReadReq_mshr_misses::total 915946 # number of ReadReq MSHR misses
823system.cpu0.icache.demand_mshr_misses::cpu0.inst 915946 # number of demand (read+write) MSHR misses
824system.cpu0.icache.demand_mshr_misses::total 915946 # number of demand (read+write) MSHR misses
825system.cpu0.icache.overall_mshr_misses::cpu0.inst 915946 # number of overall MSHR misses
826system.cpu0.icache.overall_mshr_misses::total 915946 # number of overall MSHR misses
827system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813261500 # number of ReadReq MSHR miss cycles
828system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813261500 # number of ReadReq MSHR miss cycles
829system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813261500 # number of demand (read+write) MSHR miss cycles
830system.cpu0.icache.demand_mshr_miss_latency::total 10813261500 # number of demand (read+write) MSHR miss cycles
831system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813261500 # number of overall MSHR miss cycles
832system.cpu0.icache.overall_mshr_miss_latency::total 10813261500 # number of overall MSHR miss cycles
833system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses
834system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses
835system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses
836system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses
837system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses
838system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses
839system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency
840system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency
841system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency
842system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency
843system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency
844system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency
845system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
846system.cpu0.dcache.replacements 1337909 # number of replacements
847system.cpu0.dcache.tagsinuse 506.537579 # Cycle average of tags in use
848system.cpu0.dcache.total_refs 13346950 # Total number of references to valid blocks.
849system.cpu0.dcache.sampled_refs 1338324 # Sample count of references to valid blocks.
850system.cpu0.dcache.avg_refs 9.972884 # Average number of references to valid blocks.
851system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit.
852system.cpu0.dcache.occ_blocks::cpu0.data 506.537579 # Average occupied blocks per requestor
853system.cpu0.dcache.occ_percent::cpu0.data 0.989331 # Average percentage of cache occupancy
854system.cpu0.dcache.occ_percent::total 0.989331 # Average percentage of cache occupancy
855system.cpu0.dcache.ReadReq_hits::cpu0.data 7419116 # number of ReadReq hits
856system.cpu0.dcache.ReadReq_hits::total 7419116 # number of ReadReq hits
857system.cpu0.dcache.WriteReq_hits::cpu0.data 5560491 # number of WriteReq hits
858system.cpu0.dcache.WriteReq_hits::total 5560491 # number of WriteReq hits
859system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits
860system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits
861system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits
862system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits
863system.cpu0.dcache.demand_hits::cpu0.data 12979607 # number of demand (read+write) hits
864system.cpu0.dcache.demand_hits::total 12979607 # number of demand (read+write) hits
865system.cpu0.dcache.overall_hits::cpu0.data 12979607 # number of overall hits
866system.cpu0.dcache.overall_hits::total 12979607 # number of overall hits
867system.cpu0.dcache.ReadReq_misses::cpu0.data 1035921 # number of ReadReq misses
868system.cpu0.dcache.ReadReq_misses::total 1035921 # number of ReadReq misses
869system.cpu0.dcache.WriteReq_misses::cpu0.data 291041 # number of WriteReq misses
870system.cpu0.dcache.WriteReq_misses::total 291041 # number of WriteReq misses
871system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses
872system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses
873system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses
874system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses
875system.cpu0.dcache.demand_misses::cpu0.data 1326962 # number of demand (read+write) misses
876system.cpu0.dcache.demand_misses::total 1326962 # number of demand (read+write) misses
877system.cpu0.dcache.overall_misses::cpu0.data 1326962 # number of overall misses
878system.cpu0.dcache.overall_misses::total 1326962 # number of overall misses
879system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391252000 # number of ReadReq miss cycles
880system.cpu0.dcache.ReadReq_miss_latency::total 22391252000 # number of ReadReq miss cycles
881system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8190685500 # number of WriteReq miss cycles
882system.cpu0.dcache.WriteReq_miss_latency::total 8190685500 # number of WriteReq miss cycles
883system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles
884system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles
885system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles
886system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles
887system.cpu0.dcache.demand_miss_latency::cpu0.data 30581937500 # number of demand (read+write) miss cycles
888system.cpu0.dcache.demand_miss_latency::total 30581937500 # number of demand (read+write) miss cycles
889system.cpu0.dcache.overall_miss_latency::cpu0.data 30581937500 # number of overall miss cycles
890system.cpu0.dcache.overall_miss_latency::total 30581937500 # number of overall miss cycles
891system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses)
892system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses)
893system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses)
894system.cpu0.dcache.WriteReq_accesses::total 5851532 # number of WriteReq accesses(hits+misses)
895system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193066 # number of LoadLockedReq accesses(hits+misses)
896system.cpu0.dcache.LoadLockedReq_accesses::total 193066 # number of LoadLockedReq accesses(hits+misses)
897system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192099 # number of StoreCondReq accesses(hits+misses)
898system.cpu0.dcache.StoreCondReq_accesses::total 192099 # number of StoreCondReq accesses(hits+misses)
899system.cpu0.dcache.demand_accesses::cpu0.data 14306569 # number of demand (read+write) accesses
900system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses
901system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses
902system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses
903system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122521 # miss rate for ReadReq accesses
904system.cpu0.dcache.ReadReq_miss_rate::total 0.122521 # miss rate for ReadReq accesses
905system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049738 # miss rate for WriteReq accesses
906system.cpu0.dcache.WriteReq_miss_rate::total 0.049738 # miss rate for WriteReq accesses
907system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses
908system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses
909system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses
910system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses
911system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses
912system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses
913system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses
914system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses
915system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency
916system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency
917system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.720441 # average WriteReq miss latency
918system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency
919system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency
920system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency
921system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency
922system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency
923system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
924system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency
925system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
926system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency
927system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
928system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
929system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
930system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
931system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
932system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
933system.cpu0.dcache.fast_writes 0 # number of fast writes performed
934system.cpu0.dcache.cache_copies 0 # number of cache copies performed
935system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks
936system.cpu0.dcache.writebacks::total 789805 # number of writebacks
937system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses
938system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses
939system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses
940system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses
941system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses
942system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses
943system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses
944system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses
945system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses
946system.cpu0.dcache.demand_mshr_misses::total 1326962 # number of demand (read+write) MSHR misses
947system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326962 # number of overall MSHR misses
948system.cpu0.dcache.overall_mshr_misses::total 1326962 # number of overall MSHR misses
949system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319410000 # number of ReadReq MSHR miss cycles
950system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319410000 # number of ReadReq MSHR miss cycles
951system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608603500 # number of WriteReq MSHR miss cycles
952system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608603500 # number of WriteReq MSHR miss cycles
953system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles
954system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles
955system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles
956system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles
957system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928013500 # number of demand (read+write) MSHR miss cycles
958system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles
959system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928013500 # number of overall MSHR miss cycles
960system.cpu0.dcache.overall_mshr_miss_latency::total 27928013500 # number of overall MSHR miss cycles
961system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465455500 # number of ReadReq MSHR uncacheable cycles
962system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465455500 # number of ReadReq MSHR uncacheable cycles
963system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092162000 # number of WriteReq MSHR uncacheable cycles
964system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles
965system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles
966system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles
967system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses
968system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses
969system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses
970system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses
971system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses
972system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses
973system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses
974system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses
975system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses
976system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses
977system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses
978system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses
979system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency
980system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency
981system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency
982system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency
983system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency
984system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency
985system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency
986system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency
987system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
988system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency
989system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
990system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency
991system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
992system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
993system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
994system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
995system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
996system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
997system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
998system.cpu1.dtb.fetch_hits 0 # ITB hits
999system.cpu1.dtb.fetch_misses 0 # ITB misses
1000system.cpu1.dtb.fetch_acv 0 # ITB acv
1001system.cpu1.dtb.fetch_accesses 0 # ITB accesses
1002system.cpu1.dtb.read_hits 1047086 # DTB read hits
1003system.cpu1.dtb.read_misses 2992 # DTB read misses
1004system.cpu1.dtb.read_acv 0 # DTB read access violations
1005system.cpu1.dtb.read_accesses 239363 # DTB read accesses
1006system.cpu1.dtb.write_hits 650181 # DTB write hits
1007system.cpu1.dtb.write_misses 341 # DTB write misses
1008system.cpu1.dtb.write_acv 29 # DTB write access violations
1009system.cpu1.dtb.write_accesses 105247 # DTB write accesses
1010system.cpu1.dtb.data_hits 1697267 # DTB hits
1011system.cpu1.dtb.data_misses 3333 # DTB misses
1012system.cpu1.dtb.data_acv 29 # DTB access violations
1013system.cpu1.dtb.data_accesses 344610 # DTB accesses
1014system.cpu1.itb.fetch_hits 1487534 # ITB hits
1015system.cpu1.itb.fetch_misses 1216 # ITB misses
1016system.cpu1.itb.fetch_acv 0 # ITB acv
1017system.cpu1.itb.fetch_accesses 1488750 # ITB accesses
1018system.cpu1.itb.read_hits 0 # DTB read hits
1019system.cpu1.itb.read_misses 0 # DTB read misses
1020system.cpu1.itb.read_acv 0 # DTB read access violations
1021system.cpu1.itb.read_accesses 0 # DTB read accesses
1022system.cpu1.itb.write_hits 0 # DTB write hits
1023system.cpu1.itb.write_misses 0 # DTB write misses
1024system.cpu1.itb.write_acv 0 # DTB write access violations
1025system.cpu1.itb.write_accesses 0 # DTB write accesses
1026system.cpu1.itb.data_hits 0 # DTB hits
1027system.cpu1.itb.data_misses 0 # DTB misses
1028system.cpu1.itb.data_acv 0 # DTB access violations
1029system.cpu1.itb.data_accesses 0 # DTB accesses
1030system.cpu1.numCycles 3909382743 # number of cpu cycles simulated
1031system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1032system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1033system.cpu1.committedInsts 5259785 # Number of instructions committed
1034system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed
1035system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses
1036system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
1037system.cpu1.num_func_calls 156703 # number of times a function call or return occured
1038system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls
1039system.cpu1.num_int_insts 4928462 # number of integer instructions
1040system.cpu1.num_fp_insts 34031 # number of float instructions
1041system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read
1042system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written
1043system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
1044system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
1045system.cpu1.num_mem_refs 1706720 # number of memory refs
1046system.cpu1.num_load_insts 1053093 # Number of load instructions
1047system.cpu1.num_store_insts 653627 # Number of store instructions
1048system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles
1049system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles
1050system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles
1051system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles
1052system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1053system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed
1054system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed
1055system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl
1056system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl
1057system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl
1058system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl
1059system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl
1060system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl
1061system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl
1062system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl
1063system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl
1064system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl
1065system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl
1066system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl
1067system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl
1068system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl
1069system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl
1070system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl
1071system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
1072system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
1073system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl
1074system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl
1075system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
1076system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
1077system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
1078system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
1079system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
1080system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
1081system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
1082system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
1083system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
1084system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
1085system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
1086system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
1087system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
1088system.cpu1.kern.syscall::total 104 # number of syscalls executed
1089system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
1090system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed
1091system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
1092system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
1093system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed
1094system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed
1095system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed
1096system.cpu1.kern.callpal::swpipl 23653 81.85% 83.08% # number of callpals executed
1097system.cpu1.kern.callpal::rdps 2170 7.51% 90.59% # number of callpals executed
1098system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed
1099system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed
1100system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed
1101system.cpu1.kern.callpal::rti 2530 8.75% 99.37% # number of callpals executed
1102system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed
1103system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed
1104system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
1105system.cpu1.kern.callpal::total 28898 # number of callpals executed
1106system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches
1107system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
1108system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches
1109system.cpu1.kern.mode_good::kernel 477
1110system.cpu1.kern.mode_good::user 464
1111system.cpu1.kern.mode_good::idle 13
1112system.cpu1.kern.mode_switch_good::kernel 0.594022 # fraction of useful protection mode switches
1113system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
1114system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches
1115system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches
1116system.cpu1.kern.mode_ticks::kernel 3558805000 0.18% 0.18% # number of ticks spent at the given mode
1117system.cpu1.kern.mode_ticks::user 1714794500 0.09% 0.27% # number of ticks spent at the given mode
1118system.cpu1.kern.mode_ticks::idle 1949417010500 99.73% 100.00% # number of ticks spent at the given mode
1119system.cpu1.kern.swap_context 338 # number of times the context was actually changed
1120system.cpu1.icache.replacements 86368 # number of replacements
1121system.cpu1.icache.tagsinuse 420.702382 # Cycle average of tags in use
1122system.cpu1.icache.total_refs 5176232 # Total number of references to valid blocks.
1123system.cpu1.icache.sampled_refs 86880 # Sample count of references to valid blocks.
1124system.cpu1.icache.avg_refs 59.579098 # Average number of references to valid blocks.
1125system.cpu1.icache.warmup_cycle 1938927920500 # Cycle when the warmup percentage was hit.
1126system.cpu1.icache.occ_blocks::cpu1.inst 420.702382 # Average occupied blocks per requestor
1127system.cpu1.icache.occ_percent::cpu1.inst 0.821684 # Average percentage of cache occupancy
1128system.cpu1.icache.occ_percent::total 0.821684 # Average percentage of cache occupancy
1129system.cpu1.icache.ReadReq_hits::cpu1.inst 5176232 # number of ReadReq hits
1130system.cpu1.icache.ReadReq_hits::total 5176232 # number of ReadReq hits
1131system.cpu1.icache.demand_hits::cpu1.inst 5176232 # number of demand (read+write) hits
1132system.cpu1.icache.demand_hits::total 5176232 # number of demand (read+write) hits
1133system.cpu1.icache.overall_hits::cpu1.inst 5176232 # number of overall hits
1134system.cpu1.icache.overall_hits::total 5176232 # number of overall hits
1135system.cpu1.icache.ReadReq_misses::cpu1.inst 86916 # number of ReadReq misses
1136system.cpu1.icache.ReadReq_misses::total 86916 # number of ReadReq misses
1137system.cpu1.icache.demand_misses::cpu1.inst 86916 # number of demand (read+write) misses
1138system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses
1139system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses
1140system.cpu1.icache.overall_misses::total 86916 # number of overall misses
1141system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles
1142system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles
1143system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles
1144system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles
1145system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles
1146system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles
1147system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses)
1148system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses)
1149system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses
1150system.cpu1.icache.demand_accesses::total 5263148 # number of demand (read+write) accesses
1151system.cpu1.icache.overall_accesses::cpu1.inst 5263148 # number of overall (read+write) accesses
1152system.cpu1.icache.overall_accesses::total 5263148 # number of overall (read+write) accesses
1153system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016514 # miss rate for ReadReq accesses
1154system.cpu1.icache.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses
1155system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 # miss rate for demand accesses
1156system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses
1157system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses
1158system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses
1159system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency
1160system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency
1161system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
1162system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency
1163system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
1164system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency
1165system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1166system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1167system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1168system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1169system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1170system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1171system.cpu1.icache.fast_writes 0 # number of fast writes performed
1172system.cpu1.icache.cache_copies 0 # number of cache copies performed
1173system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86916 # number of ReadReq MSHR misses
1174system.cpu1.icache.ReadReq_mshr_misses::total 86916 # number of ReadReq MSHR misses
1175system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 # number of demand (read+write) MSHR misses
1176system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses
1177system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses
1178system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses
1179system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002119500 # number of ReadReq MSHR miss cycles
1180system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles
1181system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles
1182system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles
1183system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002119500 # number of overall MSHR miss cycles
1184system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles
1185system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses
1186system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses
1187system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses
1188system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses
1189system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses
1190system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses
1191system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average ReadReq mshr miss latency
1192system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency
1193system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency
1194system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
1195system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency
1196system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
1197system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1198system.cpu1.dcache.replacements 52807 # number of replacements
1199system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use
1200system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks.
1201system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks.
1202system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks.
1203system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit.
1204system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor
1205system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy
1206system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy
1207system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits
1208system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits
1209system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits
1210system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits
1211system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits
1212system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits
1213system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits
1214system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits
1215system.cpu1.dcache.demand_hits::cpu1.data 1617458 # number of demand (read+write) hits
1216system.cpu1.dcache.demand_hits::total 1617458 # number of demand (read+write) hits
1217system.cpu1.dcache.overall_hits::cpu1.data 1617458 # number of overall hits
1218system.cpu1.dcache.overall_hits::total 1617458 # number of overall hits
1219system.cpu1.dcache.ReadReq_misses::cpu1.data 37008 # number of ReadReq misses
1220system.cpu1.dcache.ReadReq_misses::total 37008 # number of ReadReq misses
1221system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses
1222system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses
1223system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses
1224system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses
1225system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses
1226system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses
1227system.cpu1.dcache.demand_misses::cpu1.data 57409 # number of demand (read+write) misses
1228system.cpu1.dcache.demand_misses::total 57409 # number of demand (read+write) misses
1229system.cpu1.dcache.overall_misses::cpu1.data 57409 # number of overall misses
1230system.cpu1.dcache.overall_misses::total 57409 # number of overall misses
1231system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463706500 # number of ReadReq miss cycles
1232system.cpu1.dcache.ReadReq_miss_latency::total 463706500 # number of ReadReq miss cycles
1233system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 540901000 # number of WriteReq miss cycles
1234system.cpu1.dcache.WriteReq_miss_latency::total 540901000 # number of WriteReq miss cycles
1235system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 10601500 # number of LoadLockedReq miss cycles
1236system.cpu1.dcache.LoadLockedReq_miss_latency::total 10601500 # number of LoadLockedReq miss cycles
1237system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3694000 # number of StoreCondReq miss cycles
1238system.cpu1.dcache.StoreCondReq_miss_latency::total 3694000 # number of StoreCondReq miss cycles
1239system.cpu1.dcache.demand_miss_latency::cpu1.data 1004607500 # number of demand (read+write) miss cycles
1240system.cpu1.dcache.demand_miss_latency::total 1004607500 # number of demand (read+write) miss cycles
1241system.cpu1.dcache.overall_miss_latency::cpu1.data 1004607500 # number of overall miss cycles
1242system.cpu1.dcache.overall_miss_latency::total 1004607500 # number of overall miss cycles
1243system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses)
1244system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses)
1245system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses)
1246system.cpu1.dcache.WriteReq_accesses::total 636621 # number of WriteReq accesses(hits+misses)
1247system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 11762 # number of LoadLockedReq accesses(hits+misses)
1248system.cpu1.dcache.LoadLockedReq_accesses::total 11762 # number of LoadLockedReq accesses(hits+misses)
1249system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 11703 # number of StoreCondReq accesses(hits+misses)
1250system.cpu1.dcache.StoreCondReq_accesses::total 11703 # number of StoreCondReq accesses(hits+misses)
1251system.cpu1.dcache.demand_accesses::cpu1.data 1674867 # number of demand (read+write) accesses
1252system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses
1253system.cpu1.dcache.overall_accesses::cpu1.data 1674867 # number of overall (read+write) accesses
1254system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses
1255system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035645 # miss rate for ReadReq accesses
1256system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses
1257system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses
1258system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses
1259system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses
1260system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081279 # miss rate for LoadLockedReq accesses
1261system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042724 # miss rate for StoreCondReq accesses
1262system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042724 # miss rate for StoreCondReq accesses
1263system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 # miss rate for demand accesses
1264system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses
1265system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses
1266system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses
1267system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency
1268system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency
1269system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency
1270system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency
1271system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency
1272system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency
1273system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency
1274system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency
1275system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
1276system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency
1277system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
1278system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency
1279system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1280system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1281system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1282system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1283system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1284system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1285system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1286system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1287system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks
1288system.cpu1.dcache.writebacks::total 30630 # number of writebacks
1289system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses
1290system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses
1291system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses
1292system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses
1293system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses
1294system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses
1295system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses
1296system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses
1297system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses
1298system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses
1299system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses
1300system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses
1301system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles
1302system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles
1303system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles
1304system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles
1305system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles
1306system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles
1307system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles
1308system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles
1309system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles
1310system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles
1311system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles
1312system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles
1313system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles
1314system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles
1315system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles
1316system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles
1317system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles
1318system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles
1319system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses
1320system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses
1321system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses
1322system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses
1323system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses
1324system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081279 # mshr miss rate for LoadLockedReq accesses
1325system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042724 # mshr miss rate for StoreCondReq accesses
1326system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042724 # mshr miss rate for StoreCondReq accesses
1327system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for demand accesses
1328system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses
1329system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses
1330system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses
1331system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency
1332system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency
1333system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency
1334system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency
1335system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency
1336system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency
1337system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency
1338system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency
1339system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
1340system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
1341system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
1342system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
1343system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1344system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1345system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1346system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1347system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1348system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1349system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1350
1351---------- End Simulation Statistics ----------