1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.962845 # Number of seconds simulated
4sim_ticks 1962844580000 # Number of ticks simulated
5final_tick 1962844580000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1184099 # Simulator instruction rate (inst/s)
8host_op_rate 1184098 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 38148129943 # Simulator tick rate (ticks/s)
10host_mem_usage 318172 # Number of bytes of host memory used
11host_seconds 51.45 # Real time elapsed on the host
12sim_insts 60925667 # Number of instructions simulated
13sim_ops 60925667 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 823168 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 24882816 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 41728 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 386368 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 26135040 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 823168 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 41728 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7758336 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7758336 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 12862 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 388794 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 652 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 6037 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 408360 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 121224 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 121224 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 419375 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 12676916 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 21259 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 196841 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 13314880 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 419375 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 21259 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 3952598 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 3952598 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 3952598 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 419375 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 12676916 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 21259 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 196841 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 17267478 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.readReqs 408360 # Number of read requests accepted
54system.physmem.writeReqs 162776 # Number of write requests accepted
55system.physmem.readBursts 408360 # Number of DRAM read bursts, including those serviced by the write queue
56system.physmem.writeBursts 162776 # Number of DRAM write bursts, including those merged in the write queue
57system.physmem.bytesReadDRAM 26127936 # Total number of bytes read from DRAM
58system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
59system.physmem.bytesWritten 10271680 # Total number of bytes written to DRAM
60system.physmem.bytesReadSys 26135040 # Total read bytes from the system interface side
61system.physmem.bytesWrittenSys 10417664 # Total written bytes from the system interface side
62system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
63system.physmem.mergedWrBursts 2254 # Number of DRAM write bursts merged with an existing one
64system.physmem.neitherReadNorWriteReqs 7048 # Number of requests that are neither read nor write
65system.physmem.perBankRdBursts::0 25705 # Per bank write bursts
66system.physmem.perBankRdBursts::1 25985 # Per bank write bursts
67system.physmem.perBankRdBursts::2 25732 # Per bank write bursts
68system.physmem.perBankRdBursts::3 25537 # Per bank write bursts
69system.physmem.perBankRdBursts::4 24847 # Per bank write bursts
70system.physmem.perBankRdBursts::5 24747 # Per bank write bursts
71system.physmem.perBankRdBursts::6 25534 # Per bank write bursts
72system.physmem.perBankRdBursts::7 25495 # Per bank write bursts
73system.physmem.perBankRdBursts::8 25150 # Per bank write bursts
74system.physmem.perBankRdBursts::9 25518 # Per bank write bursts
75system.physmem.perBankRdBursts::10 25462 # Per bank write bursts
76system.physmem.perBankRdBursts::11 25292 # Per bank write bursts
77system.physmem.perBankRdBursts::12 25577 # Per bank write bursts
78system.physmem.perBankRdBursts::13 25454 # Per bank write bursts
79system.physmem.perBankRdBursts::14 26241 # Per bank write bursts
80system.physmem.perBankRdBursts::15 25973 # Per bank write bursts
81system.physmem.perBankWrBursts::0 10613 # Per bank write bursts
82system.physmem.perBankWrBursts::1 10753 # Per bank write bursts
83system.physmem.perBankWrBursts::2 9796 # Per bank write bursts
84system.physmem.perBankWrBursts::3 9387 # Per bank write bursts
85system.physmem.perBankWrBursts::4 8893 # Per bank write bursts
86system.physmem.perBankWrBursts::5 9110 # Per bank write bursts
87system.physmem.perBankWrBursts::6 9958 # Per bank write bursts
88system.physmem.perBankWrBursts::7 9669 # Per bank write bursts
89system.physmem.perBankWrBursts::8 9689 # Per bank write bursts
90system.physmem.perBankWrBursts::9 9901 # Per bank write bursts
91system.physmem.perBankWrBursts::10 9876 # Per bank write bursts
92system.physmem.perBankWrBursts::11 10215 # Per bank write bursts
93system.physmem.perBankWrBursts::12 10815 # Per bank write bursts
94system.physmem.perBankWrBursts::13 10652 # Per bank write bursts
95system.physmem.perBankWrBursts::14 10531 # Per bank write bursts
96system.physmem.perBankWrBursts::15 10637 # Per bank write bursts
97system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
98system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
99system.physmem.totGap 1962839541500 # Total gap between requests
100system.physmem.readPktSize::0 0 # Read request sizes (log2)
101system.physmem.readPktSize::1 0 # Read request sizes (log2)
102system.physmem.readPktSize::2 0 # Read request sizes (log2)
103system.physmem.readPktSize::3 0 # Read request sizes (log2)
104system.physmem.readPktSize::4 0 # Read request sizes (log2)
105system.physmem.readPktSize::5 0 # Read request sizes (log2)
106system.physmem.readPktSize::6 408360 # Read request sizes (log2)
107system.physmem.writePktSize::0 0 # Write request sizes (log2)
108system.physmem.writePktSize::1 0 # Write request sizes (log2)
109system.physmem.writePktSize::2 0 # Write request sizes (log2)
110system.physmem.writePktSize::3 0 # Write request sizes (log2)
111system.physmem.writePktSize::4 0 # Write request sizes (log2)
112system.physmem.writePktSize::5 0 # Write request sizes (log2)
113system.physmem.writePktSize::6 162776 # Write request sizes (log2)
114system.physmem.rdQLenPdf::0 408168 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::1 68 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see

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153system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::15 2297 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::16 4384 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::17 8312 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::18 9464 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::19 10119 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::20 10932 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::21 11465 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::22 12365 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::23 11871 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::24 11907 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::25 10784 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::26 10008 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::27 8529 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::28 8090 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::29 6890 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::30 6447 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::31 6307 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::33 345 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::34 313 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::37 266 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::38 222 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::41 212 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::42 223 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::43 206 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::44 191 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::45 177 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::46 154 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
210system.physmem.bytesPerActivate::samples 69162 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::mean 526.295017 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::gmean 318.923666 # Bytes accessed per row activation
213system.physmem.bytesPerActivate::stdev 416.254848 # Bytes accessed per row activation
214system.physmem.bytesPerActivate::0-127 16035 23.18% 23.18% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::128-255 12178 17.61% 40.79% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::256-383 5186 7.50% 48.29% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::384-511 3086 4.46% 52.75% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::512-639 3308 4.78% 57.54% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::640-767 1800 2.60% 60.14% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::768-895 1507 2.18% 62.32% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::896-1023 1316 1.90% 64.22% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1024-1151 24746 35.78% 100.00% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::total 69162 # Bytes accessed per row activation
224system.physmem.rdPerTurnAround::samples 5880 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::mean 69.428401 # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::stdev 2107.963348 # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::0-4095 5875 99.91% 99.91% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes
232system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes
233system.physmem.rdPerTurnAround::total 5880 # Reads before turning the bus around for writes
234system.physmem.wrPerTurnAround::samples 5880 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::mean 27.295068 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::gmean 20.802481 # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::stdev 33.368634 # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::16-23 4837 82.26% 82.26% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::24-31 186 3.16% 85.43% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::32-39 281 4.78% 90.20% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::40-47 57 0.97% 91.17% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::48-55 98 1.67% 92.84% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::56-63 42 0.71% 93.55% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::64-71 21 0.36% 93.91% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::72-79 12 0.20% 94.12% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::80-87 21 0.36% 94.47% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::88-95 6 0.10% 94.57% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::96-103 10 0.17% 94.74% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::104-111 8 0.14% 94.88% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::112-119 13 0.22% 95.10% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::120-127 5 0.09% 95.19% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::128-135 22 0.37% 95.56% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::136-143 44 0.75% 96.31% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::144-151 23 0.39% 96.70% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::152-159 6 0.10% 96.80% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::160-167 80 1.36% 98.16% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::168-175 40 0.68% 98.84% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::176-183 14 0.24% 99.08% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::184-191 24 0.41% 99.49% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::192-199 14 0.24% 99.73% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::200-207 2 0.03% 99.76% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::208-215 5 0.09% 99.85% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::216-223 1 0.02% 99.86% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::232-239 1 0.02% 99.91% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::240-247 4 0.07% 99.98% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::total 5880 # Writes before turning the bus around for reads
269system.physmem.totQLat 2202002500 # Total ticks spent queuing
270system.physmem.totMemAccLat 9856671250 # Total ticks spent from burst creation until serviced by the DRAM
271system.physmem.totBusLat 2041245000 # Total ticks spent in databus transfers
272system.physmem.avgQLat 5393.77 # Average queueing delay per DRAM burst
273system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
274system.physmem.avgMemAccLat 24143.77 # Average memory access latency per DRAM burst
275system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s
276system.physmem.avgWrBW 5.23 # Average achieved write bandwidth in MiByte/s
277system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s
278system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s
279system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
280system.physmem.busUtil 0.14 # Data bus utilization in percentage
281system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads
282system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes
283system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
284system.physmem.avgWrQLen 26.11 # Average write queue length when enqueuing
285system.physmem.readRowHits 365785 # Number of row buffer hits during reads
286system.physmem.writeRowHits 133797 # Number of row buffer hits during writes
287system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads
288system.physmem.writeRowHitRate 83.35 # Row buffer hit rate for writes
289system.physmem.avgGap 3436728.80 # Average gap between requests
290system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined
291system.physmem.memoryStateTime::IDLE 1840639787000 # Time in different power states
292system.physmem.memoryStateTime::REF 65543660000 # Time in different power states
293system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
294system.physmem.memoryStateTime::ACT 56660375500 # Time in different power states
295system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
296system.physmem.actEnergy::0 257115600 # Energy for activate commands per rank (pJ)
297system.physmem.actEnergy::1 265749120 # Energy for activate commands per rank (pJ)
298system.physmem.preEnergy::0 140291250 # Energy for precharge commands per rank (pJ)
299system.physmem.preEnergy::1 145002000 # Energy for precharge commands per rank (pJ)
300system.physmem.readEnergy::0 1587939600 # Energy for read commands per rank (pJ)
301system.physmem.readEnergy::1 1596402600 # Energy for read commands per rank (pJ)
302system.physmem.writeEnergy::0 506599920 # Energy for write commands per rank (pJ)
303system.physmem.writeEnergy::1 533407680 # Energy for write commands per rank (pJ)
304system.physmem.refreshEnergy::0 128203398960 # Energy for refresh commands per rank (pJ)
305system.physmem.refreshEnergy::1 128203398960 # Energy for refresh commands per rank (pJ)
306system.physmem.actBackEnergy::0 65563204050 # Energy for active background per rank (pJ)
307system.physmem.actBackEnergy::1 65997539775 # Energy for active background per rank (pJ)
308system.physmem.preBackEnergy::0 1120194702750 # Energy for precharge background per rank (pJ)
309system.physmem.preBackEnergy::1 1119813706500 # Energy for precharge background per rank (pJ)
310system.physmem.totalEnergy::0 1316453252130 # Total energy per rank (pJ)
311system.physmem.totalEnergy::1 1316555206635 # Total energy per rank (pJ)
312system.physmem.averagePower::0 670.686708 # Core power per rank (mW)
313system.physmem.averagePower::1 670.738650 # Core power per rank (mW)
314system.cpu_clk_domain.clock 500 # Clock period in ticks
315system.cpu0.dtb.fetch_hits 0 # ITB hits
316system.cpu0.dtb.fetch_misses 0 # ITB misses
317system.cpu0.dtb.fetch_acv 0 # ITB acv
318system.cpu0.dtb.fetch_accesses 0 # ITB accesses
319system.cpu0.dtb.read_hits 7534386 # DTB read hits
320system.cpu0.dtb.read_misses 7765 # DTB read misses
321system.cpu0.dtb.read_acv 210 # DTB read access violations
322system.cpu0.dtb.read_accesses 524069 # DTB read accesses
323system.cpu0.dtb.write_hits 5126601 # DTB write hits
324system.cpu0.dtb.write_misses 910 # DTB write misses
325system.cpu0.dtb.write_acv 133 # DTB write access violations
326system.cpu0.dtb.write_accesses 202595 # DTB write accesses
327system.cpu0.dtb.data_hits 12660987 # DTB hits
328system.cpu0.dtb.data_misses 8675 # DTB misses
329system.cpu0.dtb.data_acv 343 # DTB access violations
330system.cpu0.dtb.data_accesses 726664 # DTB accesses
331system.cpu0.itb.fetch_hits 3654300 # ITB hits
332system.cpu0.itb.fetch_misses 3984 # ITB misses
333system.cpu0.itb.fetch_acv 184 # ITB acv
334system.cpu0.itb.fetch_accesses 3658284 # ITB accesses
335system.cpu0.itb.read_hits 0 # DTB read hits
336system.cpu0.itb.read_misses 0 # DTB read misses
337system.cpu0.itb.read_acv 0 # DTB read access violations
338system.cpu0.itb.read_accesses 0 # DTB read accesses
339system.cpu0.itb.write_hits 0 # DTB write hits
340system.cpu0.itb.write_misses 0 # DTB write misses
341system.cpu0.itb.write_acv 0 # DTB write access violations
342system.cpu0.itb.write_accesses 0 # DTB write accesses
343system.cpu0.itb.data_hits 0 # DTB hits
344system.cpu0.itb.data_misses 0 # DTB misses
345system.cpu0.itb.data_acv 0 # DTB access violations
346system.cpu0.itb.data_accesses 0 # DTB accesses
347system.cpu0.numCycles 3925689160 # number of cpu cycles simulated
348system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
349system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
350system.cpu0.committedInsts 47974635 # Number of instructions committed
351system.cpu0.committedOps 47974635 # Number of ops (including micro ops) committed
352system.cpu0.num_int_alu_accesses 44501266 # Number of integer alu accesses
353system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses
354system.cpu0.num_func_calls 1202793 # number of times a function call or return occured
355system.cpu0.num_conditional_control_insts 5632199 # number of instructions that are conditional controls
356system.cpu0.num_int_insts 44501266 # number of integer instructions
357system.cpu0.num_fp_insts 212945 # number of float instructions
358system.cpu0.num_int_register_reads 61193579 # number of times the integer registers were read
359system.cpu0.num_int_register_writes 33138119 # number of times the integer registers were written
360system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read
361system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written
362system.cpu0.num_mem_refs 12702031 # number of memory refs
363system.cpu0.num_load_insts 7562183 # Number of load instructions
364system.cpu0.num_store_insts 5139848 # Number of store instructions
365system.cpu0.num_idle_cycles 3702096779.998114 # Number of idle cycles
366system.cpu0.num_busy_cycles 223592380.001886 # Number of busy cycles
367system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles
368system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles
369system.cpu0.Branches 7223323 # Number of branches fetched
370system.cpu0.op_class::No_OpClass 2734296 5.70% 5.70% # Class of executed instruction
371system.cpu0.op_class::IntAlu 31541688 65.73% 71.43% # Class of executed instruction
372system.cpu0.op_class::IntMult 52334 0.11% 71.54% # Class of executed instruction
373system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction
374system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction
375system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction
376system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction
377system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction
378system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction
379system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction
380system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction
381system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction
382system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction
383system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction
384system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction
385system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction
386system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction
387system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction
388system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction
389system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction
390system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction
391system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction
392system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction
393system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction
394system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction
395system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction
396system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction
397system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction
398system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction
399system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction
400system.cpu0.op_class::MemRead 7738218 16.13% 87.73% # Class of executed instruction
401system.cpu0.op_class::MemWrite 5145965 10.72% 98.45% # Class of executed instruction
402system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction
403system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
404system.cpu0.op_class::total 47983653 # Class of executed instruction
405system.cpu0.kern.inst.arm 0 # number of arm instructions executed
406system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
407system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed
408system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl
409system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl
410system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl
411system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl
412system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl
413system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl
414system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl
415system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
416system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl
417system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl
418system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl
419system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl
420system.cpu0.kern.ipl_ticks::0 1903342573000 96.97% 96.97% # number of cycles we spent at this ipl
421system.cpu0.kern.ipl_ticks::21 94358500 0.00% 96.97% # number of cycles we spent at this ipl
422system.cpu0.kern.ipl_ticks::22 767882500 0.04% 97.01% # number of cycles we spent at this ipl
423system.cpu0.kern.ipl_ticks::30 314406500 0.02% 97.03% # number of cycles we spent at this ipl
424system.cpu0.kern.ipl_ticks::31 58324587500 2.97% 100.00% # number of cycles we spent at this ipl
425system.cpu0.kern.ipl_ticks::total 1962843808000 # number of cycles we spent at this ipl
426system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl
427system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
428system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
429system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
430system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl
431system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl
432system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
433system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
434system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
435system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
436system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
437system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
438system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
439system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed

--- 15 unchanged lines hidden (view full) ---

455system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
456system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
457system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
458system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
459system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
460system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
461system.cpu0.kern.syscall::total 234 # number of syscalls executed
462system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
463system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed
464system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
465system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
466system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
467system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed
468system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed
469system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed
470system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed
471system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed
472system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed
473system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed
474system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed
475system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed
476system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed
477system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed
478system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
479system.cpu0.kern.callpal::total 149871 # number of callpals executed
480system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches
481system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches
482system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
483system.cpu0.kern.mode_good::kernel 1369
484system.cpu0.kern.mode_good::user 1370
485system.cpu0.kern.mode_good::idle 0
486system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches
487system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
488system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
489system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches
490system.cpu0.kern.mode_ticks::kernel 1959059969000 99.81% 99.81% # number of ticks spent at the given mode
491system.cpu0.kern.mode_ticks::user 3783834500 0.19% 100.00% # number of ticks spent at the given mode
492system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
493system.cpu0.kern.swap_context 3098 # number of times the context was actually changed
494system.cpu0.dcache.tags.replacements 1190018 # number of replacements
495system.cpu0.dcache.tags.tagsinuse 505.199068 # Cycle average of tags in use
496system.cpu0.dcache.tags.total_refs 11465472 # Total number of references to valid blocks.
497system.cpu0.dcache.tags.sampled_refs 1190530 # Sample count of references to valid blocks.
498system.cpu0.dcache.tags.avg_refs 9.630561 # Average number of references to valid blocks.
499system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit.
500system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.199068 # Average occupied blocks per requestor
501system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986717 # Average percentage of cache occupancy
502system.cpu0.dcache.tags.occ_percent::total 0.986717 # Average percentage of cache occupancy
503system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
504system.cpu0.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
505system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id
506system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
507system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
508system.cpu0.dcache.tags.tag_accesses 51888213 # Number of tag accesses
509system.cpu0.dcache.tags.data_accesses 51888213 # Number of data accesses
510system.cpu0.dcache.ReadReq_hits::cpu0.data 6450398 # number of ReadReq hits
511system.cpu0.dcache.ReadReq_hits::total 6450398 # number of ReadReq hits
512system.cpu0.dcache.WriteReq_hits::cpu0.data 4712072 # number of WriteReq hits
513system.cpu0.dcache.WriteReq_hits::total 4712072 # number of WriteReq hits
514system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140773 # number of LoadLockedReq hits
515system.cpu0.dcache.LoadLockedReq_hits::total 140773 # number of LoadLockedReq hits
516system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148356 # number of StoreCondReq hits
517system.cpu0.dcache.StoreCondReq_hits::total 148356 # number of StoreCondReq hits
518system.cpu0.dcache.demand_hits::cpu0.data 11162470 # number of demand (read+write) hits
519system.cpu0.dcache.demand_hits::total 11162470 # number of demand (read+write) hits
520system.cpu0.dcache.overall_hits::cpu0.data 11162470 # number of overall hits
521system.cpu0.dcache.overall_hits::total 11162470 # number of overall hits
522system.cpu0.dcache.ReadReq_misses::cpu0.data 942246 # number of ReadReq misses
523system.cpu0.dcache.ReadReq_misses::total 942246 # number of ReadReq misses
524system.cpu0.dcache.WriteReq_misses::cpu0.data 257610 # number of WriteReq misses
525system.cpu0.dcache.WriteReq_misses::total 257610 # number of WriteReq misses
526system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13707 # number of LoadLockedReq misses
527system.cpu0.dcache.LoadLockedReq_misses::total 13707 # number of LoadLockedReq misses
528system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5575 # number of StoreCondReq misses
529system.cpu0.dcache.StoreCondReq_misses::total 5575 # number of StoreCondReq misses
530system.cpu0.dcache.demand_misses::cpu0.data 1199856 # number of demand (read+write) misses
531system.cpu0.dcache.demand_misses::total 1199856 # number of demand (read+write) misses
532system.cpu0.dcache.overall_misses::cpu0.data 1199856 # number of overall misses
533system.cpu0.dcache.overall_misses::total 1199856 # number of overall misses
534system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27226306250 # number of ReadReq miss cycles
535system.cpu0.dcache.ReadReq_miss_latency::total 27226306250 # number of ReadReq miss cycles
536system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10348541688 # number of WriteReq miss cycles
537system.cpu0.dcache.WriteReq_miss_latency::total 10348541688 # number of WriteReq miss cycles
538system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149709000 # number of LoadLockedReq miss cycles
539system.cpu0.dcache.LoadLockedReq_miss_latency::total 149709000 # number of LoadLockedReq miss cycles
540system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42660894 # number of StoreCondReq miss cycles
541system.cpu0.dcache.StoreCondReq_miss_latency::total 42660894 # number of StoreCondReq miss cycles
542system.cpu0.dcache.demand_miss_latency::cpu0.data 37574847938 # number of demand (read+write) miss cycles
543system.cpu0.dcache.demand_miss_latency::total 37574847938 # number of demand (read+write) miss cycles
544system.cpu0.dcache.overall_miss_latency::cpu0.data 37574847938 # number of overall miss cycles
545system.cpu0.dcache.overall_miss_latency::total 37574847938 # number of overall miss cycles
546system.cpu0.dcache.ReadReq_accesses::cpu0.data 7392644 # number of ReadReq accesses(hits+misses)
547system.cpu0.dcache.ReadReq_accesses::total 7392644 # number of ReadReq accesses(hits+misses)
548system.cpu0.dcache.WriteReq_accesses::cpu0.data 4969682 # number of WriteReq accesses(hits+misses)
549system.cpu0.dcache.WriteReq_accesses::total 4969682 # number of WriteReq accesses(hits+misses)
550system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154480 # number of LoadLockedReq accesses(hits+misses)
551system.cpu0.dcache.LoadLockedReq_accesses::total 154480 # number of LoadLockedReq accesses(hits+misses)
552system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153931 # number of StoreCondReq accesses(hits+misses)
553system.cpu0.dcache.StoreCondReq_accesses::total 153931 # number of StoreCondReq accesses(hits+misses)
554system.cpu0.dcache.demand_accesses::cpu0.data 12362326 # number of demand (read+write) accesses
555system.cpu0.dcache.demand_accesses::total 12362326 # number of demand (read+write) accesses
556system.cpu0.dcache.overall_accesses::cpu0.data 12362326 # number of overall (read+write) accesses
557system.cpu0.dcache.overall_accesses::total 12362326 # number of overall (read+write) accesses
558system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127457 # miss rate for ReadReq accesses
559system.cpu0.dcache.ReadReq_miss_rate::total 0.127457 # miss rate for ReadReq accesses
560system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses
561system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses
562system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088730 # miss rate for LoadLockedReq accesses
563system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088730 # miss rate for LoadLockedReq accesses
564system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036218 # miss rate for StoreCondReq accesses
565system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036218 # miss rate for StoreCondReq accesses
566system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097057 # miss rate for demand accesses
567system.cpu0.dcache.demand_miss_rate::total 0.097057 # miss rate for demand accesses
568system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097057 # miss rate for overall accesses
569system.cpu0.dcache.overall_miss_rate::total 0.097057 # miss rate for overall accesses
570system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28895.114705 # average ReadReq miss latency
571system.cpu0.dcache.ReadReq_avg_miss_latency::total 28895.114705 # average ReadReq miss latency
572system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40171.350833 # average WriteReq miss latency
573system.cpu0.dcache.WriteReq_avg_miss_latency::total 40171.350833 # average WriteReq miss latency
574system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10922.083607 # average LoadLockedReq miss latency
575system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10922.083607 # average LoadLockedReq miss latency
576system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7652.178296 # average StoreCondReq miss latency
577system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7652.178296 # average StoreCondReq miss latency
578system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency
579system.cpu0.dcache.demand_avg_miss_latency::total 31316.131217 # average overall miss latency
580system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31316.131217 # average overall miss latency
581system.cpu0.dcache.overall_avg_miss_latency::total 31316.131217 # average overall miss latency
582system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
583system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
584system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
585system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
586system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
587system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
588system.cpu0.dcache.fast_writes 0 # number of fast writes performed
589system.cpu0.dcache.cache_copies 0 # number of cache copies performed
590system.cpu0.dcache.writebacks::writebacks 685854 # number of writebacks
591system.cpu0.dcache.writebacks::total 685854 # number of writebacks
592system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942246 # number of ReadReq MSHR misses
593system.cpu0.dcache.ReadReq_mshr_misses::total 942246 # number of ReadReq MSHR misses
594system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257610 # number of WriteReq MSHR misses
595system.cpu0.dcache.WriteReq_mshr_misses::total 257610 # number of WriteReq MSHR misses
596system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13707 # number of LoadLockedReq MSHR misses
597system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13707 # number of LoadLockedReq MSHR misses
598system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5575 # number of StoreCondReq MSHR misses
599system.cpu0.dcache.StoreCondReq_mshr_misses::total 5575 # number of StoreCondReq MSHR misses
600system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199856 # number of demand (read+write) MSHR misses
601system.cpu0.dcache.demand_mshr_misses::total 1199856 # number of demand (read+write) MSHR misses
602system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199856 # number of overall MSHR misses
603system.cpu0.dcache.overall_mshr_misses::total 1199856 # number of overall MSHR misses
604system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25216322750 # number of ReadReq MSHR miss cycles
605system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25216322750 # number of ReadReq MSHR miss cycles
606system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9780175312 # number of WriteReq MSHR miss cycles
607system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9780175312 # number of WriteReq MSHR miss cycles
608system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122281000 # number of LoadLockedReq MSHR miss cycles
609system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122281000 # number of LoadLockedReq MSHR miss cycles
610system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31509106 # number of StoreCondReq MSHR miss cycles
611system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31509106 # number of StoreCondReq MSHR miss cycles
612system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34996498062 # number of demand (read+write) MSHR miss cycles
613system.cpu0.dcache.demand_mshr_miss_latency::total 34996498062 # number of demand (read+write) MSHR miss cycles
614system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34996498062 # number of overall MSHR miss cycles
615system.cpu0.dcache.overall_mshr_miss_latency::total 34996498062 # number of overall MSHR miss cycles
616system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461499500 # number of ReadReq MSHR uncacheable cycles
617system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461499500 # number of ReadReq MSHR uncacheable cycles
618system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267126500 # number of WriteReq MSHR uncacheable cycles
619system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267126500 # number of WriteReq MSHR uncacheable cycles
620system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728626000 # number of overall MSHR uncacheable cycles
621system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728626000 # number of overall MSHR uncacheable cycles
622system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127457 # mshr miss rate for ReadReq accesses
623system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127457 # mshr miss rate for ReadReq accesses
624system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses
625system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses
626system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088730 # mshr miss rate for LoadLockedReq accesses
627system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088730 # mshr miss rate for LoadLockedReq accesses
628system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036218 # mshr miss rate for StoreCondReq accesses
629system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036218 # mshr miss rate for StoreCondReq accesses
630system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for demand accesses
631system.cpu0.dcache.demand_mshr_miss_rate::total 0.097057 # mshr miss rate for demand accesses
632system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097057 # mshr miss rate for overall accesses
633system.cpu0.dcache.overall_mshr_miss_rate::total 0.097057 # mshr miss rate for overall accesses
634system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26761.931332 # average ReadReq mshr miss latency
635system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26761.931332 # average ReadReq mshr miss latency
636system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37965.045270 # average WriteReq mshr miss latency
637system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37965.045270 # average WriteReq mshr miss latency
638system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8921.062231 # average LoadLockedReq mshr miss latency
639system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8921.062231 # average LoadLockedReq mshr miss latency
640system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5651.857578 # average StoreCondReq mshr miss latency
641system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5651.857578 # average StoreCondReq mshr miss latency
642system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency
643system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency
644system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29167.248455 # average overall mshr miss latency
645system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29167.248455 # average overall mshr miss latency
646system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
647system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
648system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
649system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
650system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
651system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
652system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
653system.cpu0.icache.tags.replacements 699671 # number of replacements
654system.cpu0.icache.tags.tagsinuse 508.391653 # Cycle average of tags in use
655system.cpu0.icache.tags.total_refs 47283349 # Total number of references to valid blocks.
656system.cpu0.icache.tags.sampled_refs 700182 # Sample count of references to valid blocks.
657system.cpu0.icache.tags.avg_refs 67.530084 # Average number of references to valid blocks.
658system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit.
659system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391653 # Average occupied blocks per requestor
660system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy
661system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy
662system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
663system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
664system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
665system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id
666system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
667system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
668system.cpu0.icache.tags.tag_accesses 48683959 # Number of tag accesses
669system.cpu0.icache.tags.data_accesses 48683959 # Number of data accesses
670system.cpu0.icache.ReadReq_hits::cpu0.inst 47283349 # number of ReadReq hits
671system.cpu0.icache.ReadReq_hits::total 47283349 # number of ReadReq hits
672system.cpu0.icache.demand_hits::cpu0.inst 47283349 # number of demand (read+write) hits
673system.cpu0.icache.demand_hits::total 47283349 # number of demand (read+write) hits
674system.cpu0.icache.overall_hits::cpu0.inst 47283349 # number of overall hits
675system.cpu0.icache.overall_hits::total 47283349 # number of overall hits
676system.cpu0.icache.ReadReq_misses::cpu0.inst 700305 # number of ReadReq misses
677system.cpu0.icache.ReadReq_misses::total 700305 # number of ReadReq misses
678system.cpu0.icache.demand_misses::cpu0.inst 700305 # number of demand (read+write) misses
679system.cpu0.icache.demand_misses::total 700305 # number of demand (read+write) misses
680system.cpu0.icache.overall_misses::cpu0.inst 700305 # number of overall misses
681system.cpu0.icache.overall_misses::total 700305 # number of overall misses
682system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9967517496 # number of ReadReq miss cycles
683system.cpu0.icache.ReadReq_miss_latency::total 9967517496 # number of ReadReq miss cycles
684system.cpu0.icache.demand_miss_latency::cpu0.inst 9967517496 # number of demand (read+write) miss cycles
685system.cpu0.icache.demand_miss_latency::total 9967517496 # number of demand (read+write) miss cycles
686system.cpu0.icache.overall_miss_latency::cpu0.inst 9967517496 # number of overall miss cycles
687system.cpu0.icache.overall_miss_latency::total 9967517496 # number of overall miss cycles
688system.cpu0.icache.ReadReq_accesses::cpu0.inst 47983654 # number of ReadReq accesses(hits+misses)
689system.cpu0.icache.ReadReq_accesses::total 47983654 # number of ReadReq accesses(hits+misses)
690system.cpu0.icache.demand_accesses::cpu0.inst 47983654 # number of demand (read+write) accesses
691system.cpu0.icache.demand_accesses::total 47983654 # number of demand (read+write) accesses
692system.cpu0.icache.overall_accesses::cpu0.inst 47983654 # number of overall (read+write) accesses
693system.cpu0.icache.overall_accesses::total 47983654 # number of overall (read+write) accesses
694system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses
695system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses
696system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses
697system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses
698system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses
699system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses
700system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14233.109140 # average ReadReq miss latency
701system.cpu0.icache.ReadReq_avg_miss_latency::total 14233.109140 # average ReadReq miss latency
702system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency
703system.cpu0.icache.demand_avg_miss_latency::total 14233.109140 # average overall miss latency
704system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14233.109140 # average overall miss latency
705system.cpu0.icache.overall_avg_miss_latency::total 14233.109140 # average overall miss latency
706system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
707system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
708system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
709system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
710system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
711system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
712system.cpu0.icache.fast_writes 0 # number of fast writes performed
713system.cpu0.icache.cache_copies 0 # number of cache copies performed
714system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700305 # number of ReadReq MSHR misses
715system.cpu0.icache.ReadReq_mshr_misses::total 700305 # number of ReadReq MSHR misses
716system.cpu0.icache.demand_mshr_misses::cpu0.inst 700305 # number of demand (read+write) MSHR misses
717system.cpu0.icache.demand_mshr_misses::total 700305 # number of demand (read+write) MSHR misses
718system.cpu0.icache.overall_mshr_misses::cpu0.inst 700305 # number of overall MSHR misses
719system.cpu0.icache.overall_mshr_misses::total 700305 # number of overall MSHR misses
720system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8561918504 # number of ReadReq MSHR miss cycles
721system.cpu0.icache.ReadReq_mshr_miss_latency::total 8561918504 # number of ReadReq MSHR miss cycles
722system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8561918504 # number of demand (read+write) MSHR miss cycles
723system.cpu0.icache.demand_mshr_miss_latency::total 8561918504 # number of demand (read+write) MSHR miss cycles
724system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8561918504 # number of overall MSHR miss cycles
725system.cpu0.icache.overall_mshr_miss_latency::total 8561918504 # number of overall MSHR miss cycles
726system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses
727system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses
728system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses
729system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses
730system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses
731system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses
732system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average ReadReq mshr miss latency
733system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12225.985112 # average ReadReq mshr miss latency
734system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency
735system.cpu0.icache.demand_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency
736system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12225.985112 # average overall mshr miss latency
737system.cpu0.icache.overall_avg_mshr_miss_latency::total 12225.985112 # average overall mshr miss latency
738system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
739system.cpu1.dtb.fetch_hits 0 # ITB hits
740system.cpu1.dtb.fetch_misses 0 # ITB misses
741system.cpu1.dtb.fetch_acv 0 # ITB acv
742system.cpu1.dtb.fetch_accesses 0 # ITB accesses
743system.cpu1.dtb.read_hits 2382379 # DTB read hits
744system.cpu1.dtb.read_misses 2620 # DTB read misses
745system.cpu1.dtb.read_acv 0 # DTB read access violations
746system.cpu1.dtb.read_accesses 205337 # DTB read accesses
747system.cpu1.dtb.write_hits 1702197 # DTB write hits
748system.cpu1.dtb.write_misses 235 # DTB write misses
749system.cpu1.dtb.write_acv 24 # DTB write access violations
750system.cpu1.dtb.write_accesses 89739 # DTB write accesses
751system.cpu1.dtb.data_hits 4084576 # DTB hits
752system.cpu1.dtb.data_misses 2855 # DTB misses
753system.cpu1.dtb.data_acv 24 # DTB access violations
754system.cpu1.dtb.data_accesses 295076 # DTB accesses
755system.cpu1.itb.fetch_hits 1808740 # ITB hits
756system.cpu1.itb.fetch_misses 1064 # ITB misses
757system.cpu1.itb.fetch_acv 0 # ITB acv
758system.cpu1.itb.fetch_accesses 1809804 # ITB accesses
759system.cpu1.itb.read_hits 0 # DTB read hits
760system.cpu1.itb.read_misses 0 # DTB read misses
761system.cpu1.itb.read_acv 0 # DTB read access violations
762system.cpu1.itb.read_accesses 0 # DTB read accesses
763system.cpu1.itb.write_hits 0 # DTB write hits
764system.cpu1.itb.write_misses 0 # DTB write misses
765system.cpu1.itb.write_acv 0 # DTB write access violations
766system.cpu1.itb.write_accesses 0 # DTB write accesses
767system.cpu1.itb.data_hits 0 # DTB hits
768system.cpu1.itb.data_misses 0 # DTB misses
769system.cpu1.itb.data_acv 0 # DTB access violations
770system.cpu1.itb.data_accesses 0 # DTB accesses
771system.cpu1.numCycles 3923834014 # number of cpu cycles simulated
772system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
773system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
774system.cpu1.committedInsts 12951032 # Number of instructions committed
775system.cpu1.committedOps 12951032 # Number of ops (including micro ops) committed
776system.cpu1.num_int_alu_accesses 11936898 # Number of integer alu accesses
777system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses
778system.cpu1.num_func_calls 411532 # number of times a function call or return occured
779system.cpu1.num_conditional_control_insts 1284277 # number of instructions that are conditional controls
780system.cpu1.num_int_insts 11936898 # number of integer instructions
781system.cpu1.num_fp_insts 171199 # number of float instructions
782system.cpu1.num_int_register_reads 16412569 # number of times the integer registers were read
783system.cpu1.num_int_register_writes 8783541 # number of times the integer registers were written
784system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read
785system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written
786system.cpu1.num_mem_refs 4107226 # number of memory refs
787system.cpu1.num_load_insts 2395961 # Number of load instructions
788system.cpu1.num_store_insts 1711265 # Number of store instructions
789system.cpu1.num_idle_cycles 3874307298.691787 # Number of idle cycles
790system.cpu1.num_busy_cycles 49526715.308213 # Number of busy cycles
791system.cpu1.not_idle_fraction 0.012622 # Percentage of non-idle cycles
792system.cpu1.idle_fraction 0.987378 # Percentage of idle cycles
793system.cpu1.Branches 1849703 # Number of branches fetched
794system.cpu1.op_class::No_OpClass 699491 5.40% 5.40% # Class of executed instruction
795system.cpu1.op_class::IntAlu 7680347 59.29% 64.69% # Class of executed instruction
796system.cpu1.op_class::IntMult 22457 0.17% 64.86% # Class of executed instruction
797system.cpu1.op_class::IntDiv 0 0.00% 64.86% # Class of executed instruction
798system.cpu1.op_class::FloatAdd 13113 0.10% 64.96% # Class of executed instruction
799system.cpu1.op_class::FloatCmp 0 0.00% 64.96% # Class of executed instruction
800system.cpu1.op_class::FloatCvt 0 0.00% 64.96% # Class of executed instruction
801system.cpu1.op_class::FloatMult 0 0.00% 64.96% # Class of executed instruction
802system.cpu1.op_class::FloatDiv 1759 0.01% 64.98% # Class of executed instruction
803system.cpu1.op_class::FloatSqrt 0 0.00% 64.98% # Class of executed instruction
804system.cpu1.op_class::SimdAdd 0 0.00% 64.98% # Class of executed instruction
805system.cpu1.op_class::SimdAddAcc 0 0.00% 64.98% # Class of executed instruction
806system.cpu1.op_class::SimdAlu 0 0.00% 64.98% # Class of executed instruction
807system.cpu1.op_class::SimdCmp 0 0.00% 64.98% # Class of executed instruction
808system.cpu1.op_class::SimdCvt 0 0.00% 64.98% # Class of executed instruction
809system.cpu1.op_class::SimdMisc 0 0.00% 64.98% # Class of executed instruction
810system.cpu1.op_class::SimdMult 0 0.00% 64.98% # Class of executed instruction
811system.cpu1.op_class::SimdMultAcc 0 0.00% 64.98% # Class of executed instruction
812system.cpu1.op_class::SimdShift 0 0.00% 64.98% # Class of executed instruction
813system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.98% # Class of executed instruction
814system.cpu1.op_class::SimdSqrt 0 0.00% 64.98% # Class of executed instruction
815system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.98% # Class of executed instruction
816system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.98% # Class of executed instruction
817system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.98% # Class of executed instruction
818system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.98% # Class of executed instruction
819system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.98% # Class of executed instruction
820system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.98% # Class of executed instruction
821system.cpu1.op_class::SimdFloatMult 0 0.00% 64.98% # Class of executed instruction
822system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.98% # Class of executed instruction
823system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.98% # Class of executed instruction
824system.cpu1.op_class::MemRead 2467292 19.05% 84.02% # Class of executed instruction
825system.cpu1.op_class::MemWrite 1712246 13.22% 97.24% # Class of executed instruction
826system.cpu1.op_class::IprAccess 357206 2.76% 100.00% # Class of executed instruction
827system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
828system.cpu1.op_class::total 12953911 # Class of executed instruction
829system.cpu1.kern.inst.arm 0 # number of arm instructions executed
830system.cpu1.kern.inst.quiesce 2765 # number of quiesce instructions executed
831system.cpu1.kern.inst.hwrei 77892 # number of hwrei instructions executed
832system.cpu1.kern.ipl_count::0 26462 38.26% 38.26% # number of times we switched to this ipl
833system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl
834system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl
835system.cpu1.kern.ipl_count::31 40213 58.15% 100.00% # number of times we switched to this ipl
836system.cpu1.kern.ipl_count::total 69157 # number of times we switched to this ipl
837system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl
838system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl
839system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl
840system.cpu1.kern.ipl_good::31 25106 47.19% 100.00% # number of times we switched to this ipl from a different ipl
841system.cpu1.kern.ipl_good::total 53206 # number of times we switched to this ipl from a different ipl
842system.cpu1.kern.ipl_ticks::0 1910435586500 97.38% 97.38% # number of cycles we spent at this ipl
843system.cpu1.kern.ipl_ticks::22 701157000 0.04% 97.41% # number of cycles we spent at this ipl
844system.cpu1.kern.ipl_ticks::30 358940000 0.02% 97.43% # number of cycles we spent at this ipl
845system.cpu1.kern.ipl_ticks::31 50421293500 2.57% 100.00% # number of cycles we spent at this ipl
846system.cpu1.kern.ipl_ticks::total 1961916977000 # number of cycles we spent at this ipl
847system.cpu1.kern.ipl_used::0 0.968105 # fraction of swpipl calls that actually changed the ipl
848system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
849system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
850system.cpu1.kern.ipl_used::31 0.624325 # fraction of swpipl calls that actually changed the ipl
851system.cpu1.kern.ipl_used::total 0.769351 # fraction of swpipl calls that actually changed the ipl
852system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
853system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
854system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
855system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
856system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
857system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
858system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
859system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
860system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
861system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
862system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
863system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
864system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
865system.cpu1.kern.syscall::total 92 # number of syscalls executed
866system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
867system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed
868system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed
869system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed
870system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed
871system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed
872system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed
873system.cpu1.kern.callpal::swpipl 62982 88.13% 91.49% # number of callpals executed
874system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed
875system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed
876system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed
877system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed
878system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed
879system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
880system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed
881system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
882system.cpu1.kern.callpal::total 71465 # number of callpals executed
883system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches
884system.cpu1.kern.mode_switch::user 367 # number of protection mode switches
885system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches
886system.cpu1.kern.mode_good::kernel 803
887system.cpu1.kern.mode_good::user 367
888system.cpu1.kern.mode_good::idle 436
889system.cpu1.kern.mode_switch_good::kernel 0.417577 # fraction of useful protection mode switches
890system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
891system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches
892system.cpu1.kern.mode_switch_good::total 0.309322 # fraction of useful protection mode switches
893system.cpu1.kern.mode_ticks::kernel 17997631500 0.92% 0.92% # number of ticks spent at the given mode
894system.cpu1.kern.mode_ticks::user 1494992000 0.08% 0.99% # number of ticks spent at the given mode
895system.cpu1.kern.mode_ticks::idle 1941547962000 99.01% 100.00% # number of ticks spent at the given mode
896system.cpu1.kern.swap_context 1968 # number of times the context was actually changed
897system.cpu1.dcache.tags.replacements 157269 # number of replacements
898system.cpu1.dcache.tags.tagsinuse 486.065602 # Cycle average of tags in use
899system.cpu1.dcache.tags.total_refs 3912422 # Total number of references to valid blocks.
900system.cpu1.dcache.tags.sampled_refs 157596 # Sample count of references to valid blocks.
901system.cpu1.dcache.tags.avg_refs 24.825643 # Average number of references to valid blocks.
902system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit.
903system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.065602 # Average occupied blocks per requestor
904system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949347 # Average percentage of cache occupancy
905system.cpu1.dcache.tags.occ_percent::total 0.949347 # Average percentage of cache occupancy
906system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id
907system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
908system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id
909system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id
910system.cpu1.dcache.tags.tag_accesses 16561703 # Number of tag accesses
911system.cpu1.dcache.tags.data_accesses 16561703 # Number of data accesses
912system.cpu1.dcache.ReadReq_hits::cpu1.data 2221454 # number of ReadReq hits
913system.cpu1.dcache.ReadReq_hits::total 2221454 # number of ReadReq hits
914system.cpu1.dcache.WriteReq_hits::cpu1.data 1590675 # number of WriteReq hits
915system.cpu1.dcache.WriteReq_hits::total 1590675 # number of WriteReq hits
916system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47775 # number of LoadLockedReq hits
917system.cpu1.dcache.LoadLockedReq_hits::total 47775 # number of LoadLockedReq hits
918system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50240 # number of StoreCondReq hits
919system.cpu1.dcache.StoreCondReq_hits::total 50240 # number of StoreCondReq hits
920system.cpu1.dcache.demand_hits::cpu1.data 3812129 # number of demand (read+write) hits
921system.cpu1.dcache.demand_hits::total 3812129 # number of demand (read+write) hits
922system.cpu1.dcache.overall_hits::cpu1.data 3812129 # number of overall hits
923system.cpu1.dcache.overall_hits::total 3812129 # number of overall hits
924system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses
925system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses
926system.cpu1.dcache.WriteReq_misses::cpu1.data 57126 # number of WriteReq misses
927system.cpu1.dcache.WriteReq_misses::total 57126 # number of WriteReq misses
928system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8902 # number of LoadLockedReq misses
929system.cpu1.dcache.LoadLockedReq_misses::total 8902 # number of LoadLockedReq misses
930system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5962 # number of StoreCondReq misses
931system.cpu1.dcache.StoreCondReq_misses::total 5962 # number of StoreCondReq misses
932system.cpu1.dcache.demand_misses::cpu1.data 172223 # number of demand (read+write) misses
933system.cpu1.dcache.demand_misses::total 172223 # number of demand (read+write) misses
934system.cpu1.dcache.overall_misses::cpu1.data 172223 # number of overall misses
935system.cpu1.dcache.overall_misses::total 172223 # number of overall misses
936system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1389994499 # number of ReadReq miss cycles
937system.cpu1.dcache.ReadReq_miss_latency::total 1389994499 # number of ReadReq miss cycles
938system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079772299 # number of WriteReq miss cycles
939system.cpu1.dcache.WriteReq_miss_latency::total 1079772299 # number of WriteReq miss cycles
940system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80592000 # number of LoadLockedReq miss cycles
941system.cpu1.dcache.LoadLockedReq_miss_latency::total 80592000 # number of LoadLockedReq miss cycles
942system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43791416 # number of StoreCondReq miss cycles
943system.cpu1.dcache.StoreCondReq_miss_latency::total 43791416 # number of StoreCondReq miss cycles
944system.cpu1.dcache.demand_miss_latency::cpu1.data 2469766798 # number of demand (read+write) miss cycles
945system.cpu1.dcache.demand_miss_latency::total 2469766798 # number of demand (read+write) miss cycles
946system.cpu1.dcache.overall_miss_latency::cpu1.data 2469766798 # number of overall miss cycles
947system.cpu1.dcache.overall_miss_latency::total 2469766798 # number of overall miss cycles
948system.cpu1.dcache.ReadReq_accesses::cpu1.data 2336551 # number of ReadReq accesses(hits+misses)
949system.cpu1.dcache.ReadReq_accesses::total 2336551 # number of ReadReq accesses(hits+misses)
950system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647801 # number of WriteReq accesses(hits+misses)
951system.cpu1.dcache.WriteReq_accesses::total 1647801 # number of WriteReq accesses(hits+misses)
952system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56677 # number of LoadLockedReq accesses(hits+misses)
953system.cpu1.dcache.LoadLockedReq_accesses::total 56677 # number of LoadLockedReq accesses(hits+misses)
954system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56202 # number of StoreCondReq accesses(hits+misses)
955system.cpu1.dcache.StoreCondReq_accesses::total 56202 # number of StoreCondReq accesses(hits+misses)
956system.cpu1.dcache.demand_accesses::cpu1.data 3984352 # number of demand (read+write) accesses
957system.cpu1.dcache.demand_accesses::total 3984352 # number of demand (read+write) accesses
958system.cpu1.dcache.overall_accesses::cpu1.data 3984352 # number of overall (read+write) accesses
959system.cpu1.dcache.overall_accesses::total 3984352 # number of overall (read+write) accesses
960system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049259 # miss rate for ReadReq accesses
961system.cpu1.dcache.ReadReq_miss_rate::total 0.049259 # miss rate for ReadReq accesses
962system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034668 # miss rate for WriteReq accesses
963system.cpu1.dcache.WriteReq_miss_rate::total 0.034668 # miss rate for WriteReq accesses
964system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157065 # miss rate for LoadLockedReq accesses
965system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157065 # miss rate for LoadLockedReq accesses
966system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106082 # miss rate for StoreCondReq accesses
967system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106082 # miss rate for StoreCondReq accesses
968system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043225 # miss rate for demand accesses
969system.cpu1.dcache.demand_miss_rate::total 0.043225 # miss rate for demand accesses
970system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043225 # miss rate for overall accesses
971system.cpu1.dcache.overall_miss_rate::total 0.043225 # miss rate for overall accesses
972system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12076.722234 # average ReadReq miss latency
973system.cpu1.dcache.ReadReq_avg_miss_latency::total 12076.722234 # average ReadReq miss latency
974system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18901.591202 # average WriteReq miss latency
975system.cpu1.dcache.WriteReq_avg_miss_latency::total 18901.591202 # average WriteReq miss latency
976system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9053.246461 # average LoadLockedReq miss latency
977system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9053.246461 # average LoadLockedReq miss latency
978system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7345.088225 # average StoreCondReq miss latency
979system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7345.088225 # average StoreCondReq miss latency
980system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency
981system.cpu1.dcache.demand_avg_miss_latency::total 14340.516644 # average overall miss latency
982system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14340.516644 # average overall miss latency
983system.cpu1.dcache.overall_avg_miss_latency::total 14340.516644 # average overall miss latency
984system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
985system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
986system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
987system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
988system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
989system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
990system.cpu1.dcache.fast_writes 0 # number of fast writes performed
991system.cpu1.dcache.cache_copies 0 # number of cache copies performed
992system.cpu1.dcache.writebacks::writebacks 107940 # number of writebacks
993system.cpu1.dcache.writebacks::total 107940 # number of writebacks
994system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses
995system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses
996system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57126 # number of WriteReq MSHR misses
997system.cpu1.dcache.WriteReq_mshr_misses::total 57126 # number of WriteReq MSHR misses
998system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8902 # number of LoadLockedReq MSHR misses
999system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8902 # number of LoadLockedReq MSHR misses
1000system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5962 # number of StoreCondReq MSHR misses
1001system.cpu1.dcache.StoreCondReq_mshr_misses::total 5962 # number of StoreCondReq MSHR misses
1002system.cpu1.dcache.demand_mshr_misses::cpu1.data 172223 # number of demand (read+write) MSHR misses
1003system.cpu1.dcache.demand_mshr_misses::total 172223 # number of demand (read+write) MSHR misses
1004system.cpu1.dcache.overall_mshr_misses::cpu1.data 172223 # number of overall MSHR misses
1005system.cpu1.dcache.overall_mshr_misses::total 172223 # number of overall MSHR misses
1006system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1159712501 # number of ReadReq MSHR miss cycles
1007system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1159712501 # number of ReadReq MSHR miss cycles
1008system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962952701 # number of WriteReq MSHR miss cycles
1009system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962952701 # number of WriteReq MSHR miss cycles
1010system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62788000 # number of LoadLockedReq MSHR miss cycles
1011system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62788000 # number of LoadLockedReq MSHR miss cycles
1012system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31865584 # number of StoreCondReq MSHR miss cycles
1013system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31865584 # number of StoreCondReq MSHR miss cycles
1014system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2122665202 # number of demand (read+write) MSHR miss cycles
1015system.cpu1.dcache.demand_mshr_miss_latency::total 2122665202 # number of demand (read+write) MSHR miss cycles
1016system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2122665202 # number of overall MSHR miss cycles
1017system.cpu1.dcache.overall_mshr_miss_latency::total 2122665202 # number of overall MSHR miss cycles
1018system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles
1019system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles
1020system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726758000 # number of WriteReq MSHR uncacheable cycles
1021system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726758000 # number of WriteReq MSHR uncacheable cycles
1022system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749204500 # number of overall MSHR uncacheable cycles
1023system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749204500 # number of overall MSHR uncacheable cycles
1024system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049259 # mshr miss rate for ReadReq accesses
1025system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049259 # mshr miss rate for ReadReq accesses
1026system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034668 # mshr miss rate for WriteReq accesses
1027system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034668 # mshr miss rate for WriteReq accesses
1028system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157065 # mshr miss rate for LoadLockedReq accesses
1029system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157065 # mshr miss rate for LoadLockedReq accesses
1030system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106082 # mshr miss rate for StoreCondReq accesses
1031system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106082 # mshr miss rate for StoreCondReq accesses
1032system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for demand accesses
1033system.cpu1.dcache.demand_mshr_miss_rate::total 0.043225 # mshr miss rate for demand accesses
1034system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043225 # mshr miss rate for overall accesses
1035system.cpu1.dcache.overall_mshr_miss_rate::total 0.043225 # mshr miss rate for overall accesses
1036system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10075.957679 # average ReadReq mshr miss latency
1037system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10075.957679 # average ReadReq mshr miss latency
1038system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16856.644978 # average WriteReq mshr miss latency
1039system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16856.644978 # average WriteReq mshr miss latency
1040system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7053.246461 # average LoadLockedReq mshr miss latency
1041system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7053.246461 # average LoadLockedReq mshr miss latency
1042system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5344.780946 # average StoreCondReq mshr miss latency
1043system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5344.780946 # average StoreCondReq mshr miss latency
1044system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency
1045system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency
1046system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12325.097124 # average overall mshr miss latency
1047system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12325.097124 # average overall mshr miss latency
1048system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1049system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1050system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1051system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1052system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1053system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1054system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1055system.cpu1.icache.tags.replacements 318302 # number of replacements
1056system.cpu1.icache.tags.tagsinuse 446.541764 # Cycle average of tags in use
1057system.cpu1.icache.tags.total_refs 12635057 # Total number of references to valid blocks.
1058system.cpu1.icache.tags.sampled_refs 318814 # Sample count of references to valid blocks.
1059system.cpu1.icache.tags.avg_refs 39.631437 # Average number of references to valid blocks.
1060system.cpu1.icache.tags.warmup_cycle 1956986830500 # Cycle when the warmup percentage was hit.
1061system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541764 # Average occupied blocks per requestor
1062system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy
1063system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy
1064system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1065system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id
1066system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id
1067system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
1068system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1069system.cpu1.icache.tags.tag_accesses 13272765 # Number of tag accesses
1070system.cpu1.icache.tags.data_accesses 13272765 # Number of data accesses
1071system.cpu1.icache.ReadReq_hits::cpu1.inst 12635057 # number of ReadReq hits
1072system.cpu1.icache.ReadReq_hits::total 12635057 # number of ReadReq hits
1073system.cpu1.icache.demand_hits::cpu1.inst 12635057 # number of demand (read+write) hits
1074system.cpu1.icache.demand_hits::total 12635057 # number of demand (read+write) hits
1075system.cpu1.icache.overall_hits::cpu1.inst 12635057 # number of overall hits
1076system.cpu1.icache.overall_hits::total 12635057 # number of overall hits
1077system.cpu1.icache.ReadReq_misses::cpu1.inst 318854 # number of ReadReq misses
1078system.cpu1.icache.ReadReq_misses::total 318854 # number of ReadReq misses
1079system.cpu1.icache.demand_misses::cpu1.inst 318854 # number of demand (read+write) misses
1080system.cpu1.icache.demand_misses::total 318854 # number of demand (read+write) misses
1081system.cpu1.icache.overall_misses::cpu1.inst 318854 # number of overall misses
1082system.cpu1.icache.overall_misses::total 318854 # number of overall misses
1083system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4204550742 # number of ReadReq miss cycles
1084system.cpu1.icache.ReadReq_miss_latency::total 4204550742 # number of ReadReq miss cycles
1085system.cpu1.icache.demand_miss_latency::cpu1.inst 4204550742 # number of demand (read+write) miss cycles
1086system.cpu1.icache.demand_miss_latency::total 4204550742 # number of demand (read+write) miss cycles
1087system.cpu1.icache.overall_miss_latency::cpu1.inst 4204550742 # number of overall miss cycles
1088system.cpu1.icache.overall_miss_latency::total 4204550742 # number of overall miss cycles
1089system.cpu1.icache.ReadReq_accesses::cpu1.inst 12953911 # number of ReadReq accesses(hits+misses)
1090system.cpu1.icache.ReadReq_accesses::total 12953911 # number of ReadReq accesses(hits+misses)
1091system.cpu1.icache.demand_accesses::cpu1.inst 12953911 # number of demand (read+write) accesses
1092system.cpu1.icache.demand_accesses::total 12953911 # number of demand (read+write) accesses
1093system.cpu1.icache.overall_accesses::cpu1.inst 12953911 # number of overall (read+write) accesses
1094system.cpu1.icache.overall_accesses::total 12953911 # number of overall (read+write) accesses
1095system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024614 # miss rate for ReadReq accesses
1096system.cpu1.icache.ReadReq_miss_rate::total 0.024614 # miss rate for ReadReq accesses
1097system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024614 # miss rate for demand accesses
1098system.cpu1.icache.demand_miss_rate::total 0.024614 # miss rate for demand accesses
1099system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024614 # miss rate for overall accesses
1100system.cpu1.icache.overall_miss_rate::total 0.024614 # miss rate for overall accesses
1101system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13186.445025 # average ReadReq miss latency
1102system.cpu1.icache.ReadReq_avg_miss_latency::total 13186.445025 # average ReadReq miss latency
1103system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency
1104system.cpu1.icache.demand_avg_miss_latency::total 13186.445025 # average overall miss latency
1105system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13186.445025 # average overall miss latency
1106system.cpu1.icache.overall_avg_miss_latency::total 13186.445025 # average overall miss latency
1107system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1108system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1109system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1110system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1111system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1112system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1113system.cpu1.icache.fast_writes 0 # number of fast writes performed
1114system.cpu1.icache.cache_copies 0 # number of cache copies performed
1115system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318854 # number of ReadReq MSHR misses
1116system.cpu1.icache.ReadReq_mshr_misses::total 318854 # number of ReadReq MSHR misses
1117system.cpu1.icache.demand_mshr_misses::cpu1.inst 318854 # number of demand (read+write) MSHR misses
1118system.cpu1.icache.demand_mshr_misses::total 318854 # number of demand (read+write) MSHR misses
1119system.cpu1.icache.overall_mshr_misses::cpu1.inst 318854 # number of overall MSHR misses
1120system.cpu1.icache.overall_mshr_misses::total 318854 # number of overall MSHR misses
1121system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3566590258 # number of ReadReq MSHR miss cycles
1122system.cpu1.icache.ReadReq_mshr_miss_latency::total 3566590258 # number of ReadReq MSHR miss cycles
1123system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3566590258 # number of demand (read+write) MSHR miss cycles
1124system.cpu1.icache.demand_mshr_miss_latency::total 3566590258 # number of demand (read+write) MSHR miss cycles
1125system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3566590258 # number of overall MSHR miss cycles
1126system.cpu1.icache.overall_mshr_miss_latency::total 3566590258 # number of overall MSHR miss cycles
1127system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for ReadReq accesses
1128system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024614 # mshr miss rate for ReadReq accesses
1129system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for demand accesses
1130system.cpu1.icache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses
1131system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024614 # mshr miss rate for overall accesses
1132system.cpu1.icache.overall_mshr_miss_rate::total 0.024614 # mshr miss rate for overall accesses
1133system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average ReadReq mshr miss latency
1134system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11185.653177 # average ReadReq mshr miss latency
1135system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency
1136system.cpu1.icache.demand_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency
1137system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11185.653177 # average overall mshr miss latency
1138system.cpu1.icache.overall_avg_mshr_miss_latency::total 11185.653177 # average overall mshr miss latency
1139system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1140system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1141system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
1142system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
1143system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
1144system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
1145system.disk0.dma_write_txs 395 # Number of DMA write transactions.
1146system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
1147system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
1148system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
1149system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
1150system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
1151system.disk2.dma_write_txs 1 # Number of DMA write transactions.
1152system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
1153system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
1154system.iobus.trans_dist::WriteReq 55631 # Transaction distribution
1155system.iobus.trans_dist::WriteResp 14079 # Transaction distribution
1156system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1157system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes)
1158system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
1159system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
1160system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
1161system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
1162system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
1163system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
1164system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
1165system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
1166system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
1167system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
1168system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1169system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes)
1170system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes)
1171system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes)
1172system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes)
1173system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes)
1174system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
1175system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
1176system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
1177system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
1178system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
1179system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes)
1180system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
1181system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
1182system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
1183system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
1184system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1185system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes)
1186system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes)
1187system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes)
1188system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes)
1189system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks)
1190system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1191system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
1192system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1193system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
1194system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1195system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
1196system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1197system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
1198system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1199system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
1200system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1201system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
1202system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1203system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
1204system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1205system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
1206system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1207system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
1208system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1209system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
1210system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1211system.iobus.reqLayer29.occupancy 406206788 # Layer occupancy (ticks)
1212system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
1213system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
1214system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
1215system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks)
1216system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1217system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks)
1218system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
1219system.iocache.tags.replacements 41696 # number of replacements
1220system.iocache.tags.tagsinuse 0.577792 # Cycle average of tags in use
1221system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1222system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks.
1223system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
1224system.iocache.tags.warmup_cycle 1755504938000 # Cycle when the warmup percentage was hit.
1225system.iocache.tags.occ_blocks::tsunami.ide 0.577792 # Average occupied blocks per requestor
1226system.iocache.tags.occ_percent::tsunami.ide 0.036112 # Average percentage of cache occupancy
1227system.iocache.tags.occ_percent::total 0.036112 # Average percentage of cache occupancy
1228system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
1229system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
1230system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
1231system.iocache.tags.tag_accesses 375552 # Number of tag accesses
1232system.iocache.tags.data_accesses 375552 # Number of data accesses
1233system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses
1234system.iocache.ReadReq_misses::total 176 # number of ReadReq misses
1235system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
1236system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
1237system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses
1238system.iocache.demand_misses::total 176 # number of demand (read+write) misses
1239system.iocache.overall_misses::tsunami.ide 176 # number of overall misses
1240system.iocache.overall_misses::total 176 # number of overall misses
1241system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles
1242system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles
1243system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634244905 # number of WriteInvalidateReq miss cycles
1244system.iocache.WriteInvalidateReq_miss_latency::total 13634244905 # number of WriteInvalidateReq miss cycles
1245system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles
1246system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles
1247system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles
1248system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles
1249system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses)
1250system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses)
1251system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
1252system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
1253system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses
1254system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses
1255system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses
1256system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses
1257system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
1258system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
1259system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
1260system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1261system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
1262system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
1263system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
1264system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
1265system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency
1266system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency
1267system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328124.877383 # average WriteInvalidateReq miss latency
1268system.iocache.WriteInvalidateReq_avg_miss_latency::total 328124.877383 # average WriteInvalidateReq miss latency
1269system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency
1270system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency
1271system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency
1272system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency
1273system.iocache.blocked_cycles::no_mshrs 206283 # number of cycles access was blocked
1274system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1275system.iocache.blocked::no_mshrs 23550 # number of cycles access was blocked
1276system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1277system.iocache.avg_blocked_cycles::no_mshrs 8.759363 # average number of cycles each access was blocked
1278system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1279system.iocache.fast_writes 0 # number of fast writes performed
1280system.iocache.cache_copies 0 # number of cache copies performed
1281system.iocache.writebacks::writebacks 41520 # number of writebacks
1282system.iocache.writebacks::total 41520 # number of writebacks
1283system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses
1284system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses
1285system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses
1286system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses
1287system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses
1288system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses
1289system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses
1290system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses
1291system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles
1292system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles
1293system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473540905 # number of WriteInvalidateReq MSHR miss cycles
1294system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473540905 # number of WriteInvalidateReq MSHR miss cycles
1295system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles
1296system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles
1297system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles
1298system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles
1299system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
1300system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
1301system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses
1302system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1303system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
1304system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
1305system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
1306system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
1307system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency
1308system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency
1309system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276124.877383 # average WriteInvalidateReq mshr miss latency
1310system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276124.877383 # average WriteInvalidateReq mshr miss latency
1311system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
1312system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
1313system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency
1314system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency
1315system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1316system.l2c.tags.replacements 342754 # number of replacements
1317system.l2c.tags.tagsinuse 65220.433043 # Cycle average of tags in use
1318system.l2c.tags.total_refs 2449371 # Total number of references to valid blocks.
1319system.l2c.tags.sampled_refs 407927 # Sample count of references to valid blocks.
1320system.l2c.tags.avg_refs 6.004435 # Average number of references to valid blocks.
1321system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit.
1322system.l2c.tags.occ_blocks::writebacks 55272.994922 # Average occupied blocks per requestor
1323system.l2c.tags.occ_blocks::cpu0.inst 4808.176589 # Average occupied blocks per requestor
1324system.l2c.tags.occ_blocks::cpu0.data 4932.064474 # Average occupied blocks per requestor
1325system.l2c.tags.occ_blocks::cpu1.inst 162.933205 # Average occupied blocks per requestor
1326system.l2c.tags.occ_blocks::cpu1.data 44.263854 # Average occupied blocks per requestor
1327system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy
1328system.l2c.tags.occ_percent::cpu0.inst 0.073367 # Average percentage of cache occupancy
1329system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy
1330system.l2c.tags.occ_percent::cpu1.inst 0.002486 # Average percentage of cache occupancy
1331system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy
1332system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy
1333system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id
1334system.l2c.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
1335system.l2c.tags.age_task_id_blocks_1024::1 764 # Occupied blocks per task id
1336system.l2c.tags.age_task_id_blocks_1024::2 5225 # Occupied blocks per task id
1337system.l2c.tags.age_task_id_blocks_1024::3 7223 # Occupied blocks per task id
1338system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id
1339system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id
1340system.l2c.tags.tag_accesses 25998619 # Number of tag accesses
1341system.l2c.tags.data_accesses 25998619 # Number of data accesses
1342system.l2c.ReadReq_hits::cpu0.inst 687419 # number of ReadReq hits
1343system.l2c.ReadReq_hits::cpu0.data 668122 # number of ReadReq hits
1344system.l2c.ReadReq_hits::cpu1.inst 318193 # number of ReadReq hits
1345system.l2c.ReadReq_hits::cpu1.data 105248 # number of ReadReq hits
1346system.l2c.ReadReq_hits::total 1778982 # number of ReadReq hits
1347system.l2c.Writeback_hits::writebacks 793794 # number of Writeback hits
1348system.l2c.Writeback_hits::total 793794 # number of Writeback hits
1349system.l2c.UpgradeReq_hits::cpu0.data 182 # number of UpgradeReq hits
1350system.l2c.UpgradeReq_hits::cpu1.data 544 # number of UpgradeReq hits
1351system.l2c.UpgradeReq_hits::total 726 # number of UpgradeReq hits
1352system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits
1353system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits
1354system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits
1355system.l2c.ReadExReq_hits::cpu0.data 129870 # number of ReadExReq hits
1356system.l2c.ReadExReq_hits::cpu1.data 42509 # number of ReadExReq hits
1357system.l2c.ReadExReq_hits::total 172379 # number of ReadExReq hits
1358system.l2c.demand_hits::cpu0.inst 687419 # number of demand (read+write) hits
1359system.l2c.demand_hits::cpu0.data 797992 # number of demand (read+write) hits
1360system.l2c.demand_hits::cpu1.inst 318193 # number of demand (read+write) hits
1361system.l2c.demand_hits::cpu1.data 147757 # number of demand (read+write) hits
1362system.l2c.demand_hits::total 1951361 # number of demand (read+write) hits
1363system.l2c.overall_hits::cpu0.inst 687419 # number of overall hits
1364system.l2c.overall_hits::cpu0.data 797992 # number of overall hits
1365system.l2c.overall_hits::cpu1.inst 318193 # number of overall hits
1366system.l2c.overall_hits::cpu1.data 147757 # number of overall hits
1367system.l2c.overall_hits::total 1951361 # number of overall hits
1368system.l2c.ReadReq_misses::cpu0.inst 12865 # number of ReadReq misses
1369system.l2c.ReadReq_misses::cpu0.data 271552 # number of ReadReq misses
1370system.l2c.ReadReq_misses::cpu1.inst 660 # number of ReadReq misses
1371system.l2c.ReadReq_misses::cpu1.data 293 # number of ReadReq misses
1372system.l2c.ReadReq_misses::total 285370 # number of ReadReq misses
1373system.l2c.UpgradeReq_misses::cpu0.data 2959 # number of UpgradeReq misses
1374system.l2c.UpgradeReq_misses::cpu1.data 1779 # number of UpgradeReq misses
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1604system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency
1605system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency
1606system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency
1607system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency
1608system.l2c.demand_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency
1609system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60793.986161 # average overall mshr miss latency
1610system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53743.165348 # average overall mshr miss latency
1611system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60230.828221 # average overall mshr miss latency
1612system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61134.555501 # average overall mshr miss latency
1613system.l2c.overall_avg_mshr_miss_latency::total 54084.877339 # average overall mshr miss latency
1614system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1615system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1616system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1617system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1618system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1619system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1620system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1621system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1622system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1623system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
1624system.membus.trans_dist::ReadReq 292732 # Transaction distribution
1625system.membus.trans_dist::ReadResp 292732 # Transaction distribution
1626system.membus.trans_dist::WriteReq 14079 # Transaction distribution
1627system.membus.trans_dist::WriteResp 14079 # Transaction distribution
1628system.membus.trans_dist::Writeback 121224 # Transaction distribution
1629system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
1630system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
1631system.membus.trans_dist::UpgradeReq 16421 # Transaction distribution
1632system.membus.trans_dist::SCUpgradeReq 11471 # Transaction distribution
1633system.membus.trans_dist::UpgradeResp 7051 # Transaction distribution
1634system.membus.trans_dist::ReadExReq 124094 # Transaction distribution
1635system.membus.trans_dist::ReadExResp 123249 # Transaction distribution
1636system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes)
1637system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932442 # Packet count per connected master and slave (bytes)
1638system.membus.pkt_count_system.l2c.mem_side::total 974994 # Packet count per connected master and slave (bytes)
1639system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes)
1640system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes)
1641system.membus.pkt_count::total 1099809 # Packet count per connected master and slave (bytes)
1642system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes)
1643system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235136 # Cumulative packet size per connected master and slave (bytes)
1644system.membus.pkt_size_system.l2c.mem_side::total 31317170 # Cumulative packet size per connected master and slave (bytes)
1645system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes)
1646system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
1647system.membus.pkt_size::total 36634738 # Cumulative packet size per connected master and slave (bytes)
1648system.membus.snoops 22113 # Total snoops (count)
1649system.membus.snoop_fanout::samples 600297 # Request fanout histogram
1650system.membus.snoop_fanout::mean 1 # Request fanout histogram
1651system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1652system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1653system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1654system.membus.snoop_fanout::1 600297 100.00% 100.00% # Request fanout histogram
1655system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1656system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1657system.membus.snoop_fanout::min_value 1 # Request fanout histogram
1658system.membus.snoop_fanout::max_value 1 # Request fanout histogram
1659system.membus.snoop_fanout::total 600297 # Request fanout histogram
1660system.membus.reqLayer0.occupancy 40801500 # Layer occupancy (ticks)
1661system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
1662system.membus.reqLayer1.occupancy 1914880000 # Layer occupancy (ticks)
1663system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
1664system.membus.respLayer1.occupancy 3840416202 # Layer occupancy (ticks)
1665system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
1666system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks)
1667system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
1668system.toL2Bus.trans_dist::ReadReq 2106484 # Transaction distribution
1669system.toL2Bus.trans_dist::ReadResp 2106469 # Transaction distribution
1670system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution
1671system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution
1672system.toL2Bus.trans_dist::Writeback 793794 # Transaction distribution
1673system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
1674system.toL2Bus.trans_dist::UpgradeReq 16644 # Transaction distribution
1675system.toL2Bus.trans_dist::SCUpgradeReq 11537 # Transaction distribution
1676system.toL2Bus.trans_dist::UpgradeResp 28181 # Transaction distribution
1677system.toL2Bus.trans_dist::ReadExReq 298092 # Transaction distribution
1678system.toL2Bus.trans_dist::ReadExResp 298092 # Transaction distribution
1679system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400589 # Packet count per connected master and slave (bytes)
1680system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132441 # Packet count per connected master and slave (bytes)
1681system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637707 # Packet count per connected master and slave (bytes)
1682system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458977 # Packet count per connected master and slave (bytes)
1683system.toL2Bus.pkt_count::total 5629714 # Packet count per connected master and slave (bytes)
1684system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44818176 # Cumulative packet size per connected master and slave (bytes)
1685system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119962112 # Cumulative packet size per connected master and slave (bytes)
1686system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20406592 # Cumulative packet size per connected master and slave (bytes)
1687system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779186 # Cumulative packet size per connected master and slave (bytes)
1688system.toL2Bus.pkt_size::total 201966066 # Cumulative packet size per connected master and slave (bytes)
1689system.toL2Bus.snoops 99450 # Total snoops (count)
1690system.toL2Bus.snoop_fanout::samples 3260906 # Request fanout histogram
1691system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram
1692system.toL2Bus.snoop_fanout::stdev 0.112395 # Request fanout histogram
1693system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1694system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1695system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1696system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1697system.toL2Bus.snoop_fanout::3 3219178 98.72% 98.72% # Request fanout histogram
1698system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram
1699system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1700system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1701system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1702system.toL2Bus.snoop_fanout::total 3260906 # Request fanout histogram
1703system.toL2Bus.reqLayer0.occupancy 4802513358 # Layer occupancy (ticks)
1704system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
1705system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
1706system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1707system.toL2Bus.respLayer0.occupancy 3153866996 # Layer occupancy (ticks)
1708system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
1709system.toL2Bus.respLayer1.occupancy 5532423832 # Layer occupancy (ticks)
1710system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
1711system.toL2Bus.respLayer2.occupancy 1434969242 # Layer occupancy (ticks)
1712system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
1713system.toL2Bus.respLayer3.occupancy 787756714 # Layer occupancy (ticks)
1714system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1715system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
1716system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
1717system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
1718system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
1719system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
1720system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
1721system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
1722system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
1723system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
1724system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
1725system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
1726system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
1727system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
1728system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
1729system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
1730system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
1731system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
1732system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
1733system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
1734system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
1735system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
1736system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
1737system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
1738system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
1739system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
1740system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
1741system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
1742system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
1743system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
1744system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
1745system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
1746
1747---------- End Simulation Statistics ----------