| config.ini (8983:8800b05e1cb3) | config.ini (9055:38f1926fb599) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 260 unchanged lines hidden (view full) --- 269image_file=/dist/m5/system/disks/linux-bigswap2.img 270read_only=true 271 272[system.intrctrl] 273type=IntrControl 274sys=system 275 276[system.iobus] | 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 260 unchanged lines hidden (view full) --- 269image_file=/dist/m5/system/disks/linux-bigswap2.img 270read_only=true 271 272[system.intrctrl] 273type=IntrControl 274sys=system 275 276[system.iobus] |
| 277type=Bus | 277type=NoncoherentBus |
| 278block_size=64 | 278block_size=64 |
| 279bus_id=0 | |
| 280clock=1000 281header_cycles=1 282use_default_range=true 283width=64 284default=system.tsunami.pciconfig.pio 285master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 286slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 287 --- 43 unchanged lines hidden (view full) --- 331tgts_per_mshr=16 332trace_addr=0 333two_queue=false 334write_buffers=8 335cpu_side=system.toL2Bus.master[0] 336mem_side=system.membus.slave[2] 337 338[system.membus] | 279clock=1000 280header_cycles=1 281use_default_range=true 282width=64 283default=system.tsunami.pciconfig.pio 284master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 285slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 286 --- 43 unchanged lines hidden (view full) --- 330tgts_per_mshr=16 331trace_addr=0 332two_queue=false 333write_buffers=8 334cpu_side=system.toL2Bus.master[0] 335mem_side=system.membus.slave[2] 336 337[system.membus] |
| 339type=Bus | 338type=CoherentBus |
| 340children=badaddr_responder 341block_size=64 | 339children=badaddr_responder 340block_size=64 |
| 342bus_id=1 | |
| 343clock=1000 344header_cycles=1 345use_default_range=false 346width=64 347default=system.membus.badaddr_responder.pio 348master=system.bridge.slave system.physmem.port[0] 349slave=system.system_port system.iocache.mem_side system.l2c.mem_side 350 --- 39 unchanged lines hidden (view full) --- 390[system.terminal] 391type=Terminal 392intr_control=system.intrctrl 393number=0 394output=true 395port=3456 396 397[system.toL2Bus] | 341clock=1000 342header_cycles=1 343use_default_range=false 344width=64 345default=system.membus.badaddr_responder.pio 346master=system.bridge.slave system.physmem.port[0] 347slave=system.system_port system.iocache.mem_side system.l2c.mem_side 348 --- 39 unchanged lines hidden (view full) --- 388[system.terminal] 389type=Terminal 390intr_control=system.intrctrl 391number=0 392output=true 393port=3456 394 395[system.toL2Bus] |
| 398type=Bus | 396type=CoherentBus |
| 399block_size=64 | 397block_size=64 |
| 400bus_id=0 | |
| 401clock=1000 402header_cycles=1 403use_default_range=false 404width=64 405master=system.l2c.cpu_side 406slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 407 408[system.tsunami] --- 500 unchanged lines hidden --- | 398clock=1000 399header_cycles=1 400use_default_range=false 401width=64 402master=system.l2c.cpu_side 403slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 404 405[system.tsunami] --- 500 unchanged lines hidden --- |