| config.ini (8835:7c68f84d7c4e) | config.ini (8983:8800b05e1cb3) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 5 unchanged lines hidden (view full) --- 14console=/dist/m5/system/binaries/console 15init_param=0 16kernel=/dist/m5/system/binaries/vmlinux 17load_addr_mask=1099511627775 18mem_mode=timing 19memories=system.physmem 20num_work_ids=16 21pal=/dist/m5/system/binaries/ts_osfpal | 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 5 unchanged lines hidden (view full) --- 14console=/dist/m5/system/binaries/console 15init_param=0 16kernel=/dist/m5/system/binaries/vmlinux 17load_addr_mask=1099511627775 18mem_mode=timing 19memories=system.physmem 20num_work_ids=16 21pal=/dist/m5/system/binaries/ts_osfpal |
| 22physmem=system.physmem | |
| 23readfile=tests/halt.sh 24symbolfile= 25system_rev=1024 26system_type=34 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 | 22readfile=tests/halt.sh 23symbolfile= 24system_rev=1024 25system_type=34 26work_begin_ckpt_count=0 27work_begin_cpu_id_exit=-1 28work_begin_exit_count=0 29work_cpus_ckpt_count=0 30work_end_ckpt_count=0 31work_end_exit_count=0 32work_item_id=-1 |
| 34system_port=system.membus.port[2] | 33system_port=system.membus.slave[0] |
| 35 36[system.bridge] 37type=Bridge 38delay=50000 39nack_delay=4000 40ranges=8796093022208:18446744073709551615 41req_size=16 42resp_size=16 43write_ack=false | 34 35[system.bridge] 36type=Bridge 37delay=50000 38nack_delay=4000 39ranges=8796093022208:18446744073709551615 40req_size=16 41resp_size=16 42write_ack=false |
| 44master=system.iobus.port[0] 45slave=system.membus.port[0] | 43master=system.iobus.slave[0] 44slave=system.membus.master[0] |
| 46 47[system.cpu0] 48type=TimingSimpleCPU 49children=dcache dtb icache interrupts itb tracer 50checker=Null 51clock=500 52cpu_id=0 53defer_registration=false --- 16 unchanged lines hidden (view full) --- 70system=system 71tracer=system.cpu0.tracer 72workload= 73dcache_port=system.cpu0.dcache.cpu_side 74icache_port=system.cpu0.icache.cpu_side 75 76[system.cpu0.dcache] 77type=BaseCache | 45 46[system.cpu0] 47type=TimingSimpleCPU 48children=dcache dtb icache interrupts itb tracer 49checker=Null 50clock=500 51cpu_id=0 52defer_registration=false --- 16 unchanged lines hidden (view full) --- 69system=system 70tracer=system.cpu0.tracer 71workload= 72dcache_port=system.cpu0.dcache.cpu_side 73icache_port=system.cpu0.icache.cpu_side 74 75[system.cpu0.dcache] 76type=BaseCache |
| 78addr_range=0:18446744073709551615 | 77addr_ranges=0:18446744073709551615 |
| 79assoc=4 80block_size=64 81forward_snoops=true 82hash_delay=1 83is_top_level=true 84latency=1000 85max_miss_count=0 86mshrs=4 --- 4 unchanged lines hidden (view full) --- 91size=32768 92subblock_size=0 93system=system 94tgts_per_mshr=8 95trace_addr=0 96two_queue=false 97write_buffers=8 98cpu_side=system.cpu0.dcache_port | 78assoc=4 79block_size=64 80forward_snoops=true 81hash_delay=1 82is_top_level=true 83latency=1000 84max_miss_count=0 85mshrs=4 --- 4 unchanged lines hidden (view full) --- 90size=32768 91subblock_size=0 92system=system 93tgts_per_mshr=8 94trace_addr=0 95two_queue=false 96write_buffers=8 97cpu_side=system.cpu0.dcache_port |
| 99mem_side=system.toL2Bus.port[2] | 98mem_side=system.toL2Bus.slave[1] |
| 100 101[system.cpu0.dtb] 102type=AlphaTLB 103size=64 104 105[system.cpu0.icache] 106type=BaseCache | 99 100[system.cpu0.dtb] 101type=AlphaTLB 102size=64 103 104[system.cpu0.icache] 105type=BaseCache |
| 107addr_range=0:18446744073709551615 | 106addr_ranges=0:18446744073709551615 |
| 108assoc=1 109block_size=64 110forward_snoops=true 111hash_delay=1 112is_top_level=true 113latency=1000 114max_miss_count=0 115mshrs=4 --- 4 unchanged lines hidden (view full) --- 120size=32768 121subblock_size=0 122system=system 123tgts_per_mshr=8 124trace_addr=0 125two_queue=false 126write_buffers=8 127cpu_side=system.cpu0.icache_port | 107assoc=1 108block_size=64 109forward_snoops=true 110hash_delay=1 111is_top_level=true 112latency=1000 113max_miss_count=0 114mshrs=4 --- 4 unchanged lines hidden (view full) --- 119size=32768 120subblock_size=0 121system=system 122tgts_per_mshr=8 123trace_addr=0 124two_queue=false 125write_buffers=8 126cpu_side=system.cpu0.icache_port |
| 128mem_side=system.toL2Bus.port[1] | 127mem_side=system.toL2Bus.slave[0] |
| 129 130[system.cpu0.interrupts] 131type=AlphaInterrupts 132 133[system.cpu0.itb] 134type=AlphaTLB 135size=48 136 --- 26 unchanged lines hidden (view full) --- 163system=system 164tracer=system.cpu1.tracer 165workload= 166dcache_port=system.cpu1.dcache.cpu_side 167icache_port=system.cpu1.icache.cpu_side 168 169[system.cpu1.dcache] 170type=BaseCache | 128 129[system.cpu0.interrupts] 130type=AlphaInterrupts 131 132[system.cpu0.itb] 133type=AlphaTLB 134size=48 135 --- 26 unchanged lines hidden (view full) --- 162system=system 163tracer=system.cpu1.tracer 164workload= 165dcache_port=system.cpu1.dcache.cpu_side 166icache_port=system.cpu1.icache.cpu_side 167 168[system.cpu1.dcache] 169type=BaseCache |
| 171addr_range=0:18446744073709551615 | 170addr_ranges=0:18446744073709551615 |
| 172assoc=4 173block_size=64 174forward_snoops=true 175hash_delay=1 176is_top_level=true 177latency=1000 178max_miss_count=0 179mshrs=4 --- 4 unchanged lines hidden (view full) --- 184size=32768 185subblock_size=0 186system=system 187tgts_per_mshr=8 188trace_addr=0 189two_queue=false 190write_buffers=8 191cpu_side=system.cpu1.dcache_port | 171assoc=4 172block_size=64 173forward_snoops=true 174hash_delay=1 175is_top_level=true 176latency=1000 177max_miss_count=0 178mshrs=4 --- 4 unchanged lines hidden (view full) --- 183size=32768 184subblock_size=0 185system=system 186tgts_per_mshr=8 187trace_addr=0 188two_queue=false 189write_buffers=8 190cpu_side=system.cpu1.dcache_port |
| 192mem_side=system.toL2Bus.port[4] | 191mem_side=system.toL2Bus.slave[3] |
| 193 194[system.cpu1.dtb] 195type=AlphaTLB 196size=64 197 198[system.cpu1.icache] 199type=BaseCache | 192 193[system.cpu1.dtb] 194type=AlphaTLB 195size=64 196 197[system.cpu1.icache] 198type=BaseCache |
| 200addr_range=0:18446744073709551615 | 199addr_ranges=0:18446744073709551615 |
| 201assoc=1 202block_size=64 203forward_snoops=true 204hash_delay=1 205is_top_level=true 206latency=1000 207max_miss_count=0 208mshrs=4 --- 4 unchanged lines hidden (view full) --- 213size=32768 214subblock_size=0 215system=system 216tgts_per_mshr=8 217trace_addr=0 218two_queue=false 219write_buffers=8 220cpu_side=system.cpu1.icache_port | 200assoc=1 201block_size=64 202forward_snoops=true 203hash_delay=1 204is_top_level=true 205latency=1000 206max_miss_count=0 207mshrs=4 --- 4 unchanged lines hidden (view full) --- 212size=32768 213subblock_size=0 214system=system 215tgts_per_mshr=8 216trace_addr=0 217two_queue=false 218write_buffers=8 219cpu_side=system.cpu1.icache_port |
| 221mem_side=system.toL2Bus.port[3] | 220mem_side=system.toL2Bus.slave[2] |
| 222 223[system.cpu1.interrupts] 224type=AlphaInterrupts 225 226[system.cpu1.itb] 227type=AlphaTLB 228size=48 229 --- 48 unchanged lines hidden (view full) --- 278type=Bus 279block_size=64 280bus_id=0 281clock=1000 282header_cycles=1 283use_default_range=true 284width=64 285default=system.tsunami.pciconfig.pio | 221 222[system.cpu1.interrupts] 223type=AlphaInterrupts 224 225[system.cpu1.itb] 226type=AlphaTLB 227size=48 228 --- 48 unchanged lines hidden (view full) --- 277type=Bus 278block_size=64 279bus_id=0 280clock=1000 281header_cycles=1 282use_default_range=true 283width=64 284default=system.tsunami.pciconfig.pio |
| 286port=system.bridge.master system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ide.dma system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.iocache.cpu_side | 285master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 286slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma |
| 287 288[system.iocache] 289type=BaseCache | 287 288[system.iocache] 289type=BaseCache |
| 290addr_range=0:8589934591 | 290addr_ranges=0:8589934591 |
| 291assoc=8 292block_size=64 293forward_snoops=false 294hash_delay=1 295is_top_level=true 296latency=50000 297max_miss_count=0 298mshrs=20 299prefetch_on_access=false 300prefetcher=Null 301prioritizeRequests=false 302repl=Null 303size=1024 304subblock_size=0 305system=system 306tgts_per_mshr=12 307trace_addr=0 308two_queue=false 309write_buffers=8 | 291assoc=8 292block_size=64 293forward_snoops=false 294hash_delay=1 295is_top_level=true 296latency=50000 297max_miss_count=0 298mshrs=20 299prefetch_on_access=false 300prefetcher=Null 301prioritizeRequests=false 302repl=Null 303size=1024 304subblock_size=0 305system=system 306tgts_per_mshr=12 307trace_addr=0 308two_queue=false 309write_buffers=8 |
| 310cpu_side=system.iobus.port[32] 311mem_side=system.membus.port[3] | 310cpu_side=system.iobus.master[29] 311mem_side=system.membus.slave[1] |
| 312 313[system.l2c] 314type=BaseCache | 312 313[system.l2c] 314type=BaseCache |
| 315addr_range=0:18446744073709551615 | 315addr_ranges=0:18446744073709551615 |
| 316assoc=8 317block_size=64 318forward_snoops=true 319hash_delay=1 320is_top_level=false 321latency=10000 322max_miss_count=0 323mshrs=92 324prefetch_on_access=false 325prefetcher=Null 326prioritizeRequests=false 327repl=Null 328size=4194304 329subblock_size=0 330system=system 331tgts_per_mshr=16 332trace_addr=0 333two_queue=false 334write_buffers=8 | 316assoc=8 317block_size=64 318forward_snoops=true 319hash_delay=1 320is_top_level=false 321latency=10000 322max_miss_count=0 323mshrs=92 324prefetch_on_access=false 325prefetcher=Null 326prioritizeRequests=false 327repl=Null 328size=4194304 329subblock_size=0 330system=system 331tgts_per_mshr=16 332trace_addr=0 333two_queue=false 334write_buffers=8 |
| 335cpu_side=system.toL2Bus.port[0] 336mem_side=system.membus.port[4] | 335cpu_side=system.toL2Bus.master[0] 336mem_side=system.membus.slave[2] |
| 337 338[system.membus] 339type=Bus 340children=badaddr_responder 341block_size=64 342bus_id=1 343clock=1000 344header_cycles=1 345use_default_range=false 346width=64 347default=system.membus.badaddr_responder.pio | 337 338[system.membus] 339type=Bus 340children=badaddr_responder 341block_size=64 342bus_id=1 343clock=1000 344header_cycles=1 345use_default_range=false 346width=64 347default=system.membus.badaddr_responder.pio |
| 348port=system.bridge.slave system.physmem.port[0] system.system_port system.iocache.mem_side system.l2c.mem_side | 348master=system.bridge.slave system.physmem.port[0] 349slave=system.system_port system.iocache.mem_side system.l2c.mem_side |
| 349 350[system.membus.badaddr_responder] 351type=IsaFake 352fake_mem=false 353pio_addr=0 354pio_latency=1000 355pio_size=8 356ret_bad_addr=true 357ret_data16=65535 358ret_data32=4294967295 359ret_data64=18446744073709551615 360ret_data8=255 361system=system 362update_data=false 363warn_access= 364pio=system.membus.default 365 366[system.physmem] | 350 351[system.membus.badaddr_responder] 352type=IsaFake 353fake_mem=false 354pio_addr=0 355pio_latency=1000 356pio_size=8 357ret_bad_addr=true 358ret_data16=65535 359ret_data32=4294967295 360ret_data64=18446744073709551615 361ret_data8=255 362system=system 363update_data=false 364warn_access= 365pio=system.membus.default 366 367[system.physmem] |
| 367type=PhysicalMemory | 368type=SimpleMemory 369conf_table_reported=false |
| 368file= | 370file= |
| 371in_addr_map=true |
|
| 369latency=30000 370latency_var=0 371null=false 372range=0:134217727 373zero=false | 372latency=30000 373latency_var=0 374null=false 375range=0:134217727 376zero=false |
| 374port=system.membus.port[1] | 377port=system.membus.master[1] |
| 375 376[system.simple_disk] 377type=SimpleDisk 378children=disk 379disk=system.simple_disk.disk 380system=system 381 382[system.simple_disk.disk] --- 11 unchanged lines hidden (view full) --- 394[system.toL2Bus] 395type=Bus 396block_size=64 397bus_id=0 398clock=1000 399header_cycles=1 400use_default_range=false 401width=64 | 378 379[system.simple_disk] 380type=SimpleDisk 381children=disk 382disk=system.simple_disk.disk 383system=system 384 385[system.simple_disk.disk] --- 11 unchanged lines hidden (view full) --- 397[system.toL2Bus] 398type=Bus 399block_size=64 400bus_id=0 401clock=1000 402header_cycles=1 403use_default_range=false 404width=64 |
| 402port=system.l2c.cpu_side system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side | 405master=system.l2c.cpu_side 406slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side |
| 403 404[system.tsunami] 405type=Tsunami 406children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 407intrctrl=system.intrctrl 408system=system 409 410[system.tsunami.backdoor] 411type=AlphaBackdoor 412cpu=system.cpu0 413disk=system.simple_disk 414pio_addr=8804682956800 415pio_latency=1000 416platform=system.tsunami 417system=system 418terminal=system.terminal | 407 408[system.tsunami] 409type=Tsunami 410children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 411intrctrl=system.intrctrl 412system=system 413 414[system.tsunami.backdoor] 415type=AlphaBackdoor 416cpu=system.cpu0 417disk=system.simple_disk 418pio_addr=8804682956800 419pio_latency=1000 420platform=system.tsunami 421system=system 422terminal=system.terminal |
| 419pio=system.iobus.port[25] | 423pio=system.iobus.master[24] |
| 420 421[system.tsunami.cchip] 422type=TsunamiCChip 423pio_addr=8803072344064 424pio_latency=1000 425system=system 426tsunami=system.tsunami | 424 425[system.tsunami.cchip] 426type=TsunamiCChip 427pio_addr=8803072344064 428pio_latency=1000 429system=system 430tsunami=system.tsunami |
| 427pio=system.iobus.port[1] | 431pio=system.iobus.master[0] |
| 428 429[system.tsunami.ethernet] 430type=NSGigE 431BAR0=1 432BAR0LegacyIO=false 433BAR0Size=256 434BAR1=0 435BAR1LegacyIO=false --- 52 unchanged lines hidden (view full) --- 488rx_delay=1000000 489rx_fifo_size=524288 490rx_filter=true 491rx_thread=false 492system=system 493tx_delay=1000000 494tx_fifo_size=524288 495tx_thread=false | 432 433[system.tsunami.ethernet] 434type=NSGigE 435BAR0=1 436BAR0LegacyIO=false 437BAR0Size=256 438BAR1=0 439BAR1LegacyIO=false --- 52 unchanged lines hidden (view full) --- 492rx_delay=1000000 493rx_fifo_size=524288 494rx_filter=true 495rx_thread=false 496system=system 497tx_delay=1000000 498tx_fifo_size=524288 499tx_thread=false |
| 496config=system.iobus.port[30] 497dma=system.iobus.port[31] 498pio=system.iobus.port[29] | 500config=system.iobus.master[28] 501dma=system.iobus.slave[2] 502pio=system.iobus.master[27] |
| 499 500[system.tsunami.fake_OROM] 501type=IsaFake 502fake_mem=false 503pio_addr=8796093677568 504pio_latency=1000 505pio_size=393216 506ret_bad_addr=false 507ret_data16=65535 508ret_data32=4294967295 509ret_data64=18446744073709551615 510ret_data8=255 511system=system 512update_data=false 513warn_access= | 503 504[system.tsunami.fake_OROM] 505type=IsaFake 506fake_mem=false 507pio_addr=8796093677568 508pio_latency=1000 509pio_size=393216 510ret_bad_addr=false 511ret_data16=65535 512ret_data32=4294967295 513ret_data64=18446744073709551615 514ret_data8=255 515system=system 516update_data=false 517warn_access= |
| 514pio=system.iobus.port[9] | 518pio=system.iobus.master[8] |
| 515 516[system.tsunami.fake_ata0] 517type=IsaFake 518fake_mem=false 519pio_addr=8804615848432 520pio_latency=1000 521pio_size=8 522ret_bad_addr=false 523ret_data16=65535 524ret_data32=4294967295 525ret_data64=18446744073709551615 526ret_data8=255 527system=system 528update_data=false 529warn_access= | 519 520[system.tsunami.fake_ata0] 521type=IsaFake 522fake_mem=false 523pio_addr=8804615848432 524pio_latency=1000 525pio_size=8 526ret_bad_addr=false 527ret_data16=65535 528ret_data32=4294967295 529ret_data64=18446744073709551615 530ret_data8=255 531system=system 532update_data=false 533warn_access= |
| 530pio=system.iobus.port[20] | 534pio=system.iobus.master[19] |
| 531 532[system.tsunami.fake_ata1] 533type=IsaFake 534fake_mem=false 535pio_addr=8804615848304 536pio_latency=1000 537pio_size=8 538ret_bad_addr=false 539ret_data16=65535 540ret_data32=4294967295 541ret_data64=18446744073709551615 542ret_data8=255 543system=system 544update_data=false 545warn_access= | 535 536[system.tsunami.fake_ata1] 537type=IsaFake 538fake_mem=false 539pio_addr=8804615848304 540pio_latency=1000 541pio_size=8 542ret_bad_addr=false 543ret_data16=65535 544ret_data32=4294967295 545ret_data64=18446744073709551615 546ret_data8=255 547system=system 548update_data=false 549warn_access= |
| 546pio=system.iobus.port[21] | 550pio=system.iobus.master[20] |
| 547 548[system.tsunami.fake_pnp_addr] 549type=IsaFake 550fake_mem=false 551pio_addr=8804615848569 552pio_latency=1000 553pio_size=8 554ret_bad_addr=false 555ret_data16=65535 556ret_data32=4294967295 557ret_data64=18446744073709551615 558ret_data8=255 559system=system 560update_data=false 561warn_access= | 551 552[system.tsunami.fake_pnp_addr] 553type=IsaFake 554fake_mem=false 555pio_addr=8804615848569 556pio_latency=1000 557pio_size=8 558ret_bad_addr=false 559ret_data16=65535 560ret_data32=4294967295 561ret_data64=18446744073709551615 562ret_data8=255 563system=system 564update_data=false 565warn_access= |
| 562pio=system.iobus.port[10] | 566pio=system.iobus.master[9] |
| 563 564[system.tsunami.fake_pnp_read0] 565type=IsaFake 566fake_mem=false 567pio_addr=8804615848451 568pio_latency=1000 569pio_size=8 570ret_bad_addr=false 571ret_data16=65535 572ret_data32=4294967295 573ret_data64=18446744073709551615 574ret_data8=255 575system=system 576update_data=false 577warn_access= | 567 568[system.tsunami.fake_pnp_read0] 569type=IsaFake 570fake_mem=false 571pio_addr=8804615848451 572pio_latency=1000 573pio_size=8 574ret_bad_addr=false 575ret_data16=65535 576ret_data32=4294967295 577ret_data64=18446744073709551615 578ret_data8=255 579system=system 580update_data=false 581warn_access= |
| 578pio=system.iobus.port[12] | 582pio=system.iobus.master[11] |
| 579 580[system.tsunami.fake_pnp_read1] 581type=IsaFake 582fake_mem=false 583pio_addr=8804615848515 584pio_latency=1000 585pio_size=8 586ret_bad_addr=false 587ret_data16=65535 588ret_data32=4294967295 589ret_data64=18446744073709551615 590ret_data8=255 591system=system 592update_data=false 593warn_access= | 583 584[system.tsunami.fake_pnp_read1] 585type=IsaFake 586fake_mem=false 587pio_addr=8804615848515 588pio_latency=1000 589pio_size=8 590ret_bad_addr=false 591ret_data16=65535 592ret_data32=4294967295 593ret_data64=18446744073709551615 594ret_data8=255 595system=system 596update_data=false 597warn_access= |
| 594pio=system.iobus.port[13] | 598pio=system.iobus.master[12] |
| 595 596[system.tsunami.fake_pnp_read2] 597type=IsaFake 598fake_mem=false 599pio_addr=8804615848579 600pio_latency=1000 601pio_size=8 602ret_bad_addr=false 603ret_data16=65535 604ret_data32=4294967295 605ret_data64=18446744073709551615 606ret_data8=255 607system=system 608update_data=false 609warn_access= | 599 600[system.tsunami.fake_pnp_read2] 601type=IsaFake 602fake_mem=false 603pio_addr=8804615848579 604pio_latency=1000 605pio_size=8 606ret_bad_addr=false 607ret_data16=65535 608ret_data32=4294967295 609ret_data64=18446744073709551615 610ret_data8=255 611system=system 612update_data=false 613warn_access= |
| 610pio=system.iobus.port[14] | 614pio=system.iobus.master[13] |
| 611 612[system.tsunami.fake_pnp_read3] 613type=IsaFake 614fake_mem=false 615pio_addr=8804615848643 616pio_latency=1000 617pio_size=8 618ret_bad_addr=false 619ret_data16=65535 620ret_data32=4294967295 621ret_data64=18446744073709551615 622ret_data8=255 623system=system 624update_data=false 625warn_access= | 615 616[system.tsunami.fake_pnp_read3] 617type=IsaFake 618fake_mem=false 619pio_addr=8804615848643 620pio_latency=1000 621pio_size=8 622ret_bad_addr=false 623ret_data16=65535 624ret_data32=4294967295 625ret_data64=18446744073709551615 626ret_data8=255 627system=system 628update_data=false 629warn_access= |
| 626pio=system.iobus.port[15] | 630pio=system.iobus.master[14] |
| 627 628[system.tsunami.fake_pnp_read4] 629type=IsaFake 630fake_mem=false 631pio_addr=8804615848707 632pio_latency=1000 633pio_size=8 634ret_bad_addr=false 635ret_data16=65535 636ret_data32=4294967295 637ret_data64=18446744073709551615 638ret_data8=255 639system=system 640update_data=false 641warn_access= | 631 632[system.tsunami.fake_pnp_read4] 633type=IsaFake 634fake_mem=false 635pio_addr=8804615848707 636pio_latency=1000 637pio_size=8 638ret_bad_addr=false 639ret_data16=65535 640ret_data32=4294967295 641ret_data64=18446744073709551615 642ret_data8=255 643system=system 644update_data=false 645warn_access= |
| 642pio=system.iobus.port[16] | 646pio=system.iobus.master[15] |
| 643 644[system.tsunami.fake_pnp_read5] 645type=IsaFake 646fake_mem=false 647pio_addr=8804615848771 648pio_latency=1000 649pio_size=8 650ret_bad_addr=false 651ret_data16=65535 652ret_data32=4294967295 653ret_data64=18446744073709551615 654ret_data8=255 655system=system 656update_data=false 657warn_access= | 647 648[system.tsunami.fake_pnp_read5] 649type=IsaFake 650fake_mem=false 651pio_addr=8804615848771 652pio_latency=1000 653pio_size=8 654ret_bad_addr=false 655ret_data16=65535 656ret_data32=4294967295 657ret_data64=18446744073709551615 658ret_data8=255 659system=system 660update_data=false 661warn_access= |
| 658pio=system.iobus.port[17] | 662pio=system.iobus.master[16] |
| 659 660[system.tsunami.fake_pnp_read6] 661type=IsaFake 662fake_mem=false 663pio_addr=8804615848835 664pio_latency=1000 665pio_size=8 666ret_bad_addr=false 667ret_data16=65535 668ret_data32=4294967295 669ret_data64=18446744073709551615 670ret_data8=255 671system=system 672update_data=false 673warn_access= | 663 664[system.tsunami.fake_pnp_read6] 665type=IsaFake 666fake_mem=false 667pio_addr=8804615848835 668pio_latency=1000 669pio_size=8 670ret_bad_addr=false 671ret_data16=65535 672ret_data32=4294967295 673ret_data64=18446744073709551615 674ret_data8=255 675system=system 676update_data=false 677warn_access= |
| 674pio=system.iobus.port[18] | 678pio=system.iobus.master[17] |
| 675 676[system.tsunami.fake_pnp_read7] 677type=IsaFake 678fake_mem=false 679pio_addr=8804615848899 680pio_latency=1000 681pio_size=8 682ret_bad_addr=false 683ret_data16=65535 684ret_data32=4294967295 685ret_data64=18446744073709551615 686ret_data8=255 687system=system 688update_data=false 689warn_access= | 679 680[system.tsunami.fake_pnp_read7] 681type=IsaFake 682fake_mem=false 683pio_addr=8804615848899 684pio_latency=1000 685pio_size=8 686ret_bad_addr=false 687ret_data16=65535 688ret_data32=4294967295 689ret_data64=18446744073709551615 690ret_data8=255 691system=system 692update_data=false 693warn_access= |
| 690pio=system.iobus.port[19] | 694pio=system.iobus.master[18] |
| 691 692[system.tsunami.fake_pnp_write] 693type=IsaFake 694fake_mem=false 695pio_addr=8804615850617 696pio_latency=1000 697pio_size=8 698ret_bad_addr=false 699ret_data16=65535 700ret_data32=4294967295 701ret_data64=18446744073709551615 702ret_data8=255 703system=system 704update_data=false 705warn_access= | 695 696[system.tsunami.fake_pnp_write] 697type=IsaFake 698fake_mem=false 699pio_addr=8804615850617 700pio_latency=1000 701pio_size=8 702ret_bad_addr=false 703ret_data16=65535 704ret_data32=4294967295 705ret_data64=18446744073709551615 706ret_data8=255 707system=system 708update_data=false 709warn_access= |
| 706pio=system.iobus.port[11] | 710pio=system.iobus.master[10] |
| 707 708[system.tsunami.fake_ppc] 709type=IsaFake 710fake_mem=false 711pio_addr=8804615848891 712pio_latency=1000 713pio_size=8 714ret_bad_addr=false 715ret_data16=65535 716ret_data32=4294967295 717ret_data64=18446744073709551615 718ret_data8=255 719system=system 720update_data=false 721warn_access= | 711 712[system.tsunami.fake_ppc] 713type=IsaFake 714fake_mem=false 715pio_addr=8804615848891 716pio_latency=1000 717pio_size=8 718ret_bad_addr=false 719ret_data16=65535 720ret_data32=4294967295 721ret_data64=18446744073709551615 722ret_data8=255 723system=system 724update_data=false 725warn_access= |
| 722pio=system.iobus.port[8] | 726pio=system.iobus.master[7] |
| 723 724[system.tsunami.fake_sm_chip] 725type=IsaFake 726fake_mem=false 727pio_addr=8804615848816 728pio_latency=1000 729pio_size=8 730ret_bad_addr=false 731ret_data16=65535 732ret_data32=4294967295 733ret_data64=18446744073709551615 734ret_data8=255 735system=system 736update_data=false 737warn_access= | 727 728[system.tsunami.fake_sm_chip] 729type=IsaFake 730fake_mem=false 731pio_addr=8804615848816 732pio_latency=1000 733pio_size=8 734ret_bad_addr=false 735ret_data16=65535 736ret_data32=4294967295 737ret_data64=18446744073709551615 738ret_data8=255 739system=system 740update_data=false 741warn_access= |
| 738pio=system.iobus.port[3] | 742pio=system.iobus.master[2] |
| 739 740[system.tsunami.fake_uart1] 741type=IsaFake 742fake_mem=false 743pio_addr=8804615848696 744pio_latency=1000 745pio_size=8 746ret_bad_addr=false 747ret_data16=65535 748ret_data32=4294967295 749ret_data64=18446744073709551615 750ret_data8=255 751system=system 752update_data=false 753warn_access= | 743 744[system.tsunami.fake_uart1] 745type=IsaFake 746fake_mem=false 747pio_addr=8804615848696 748pio_latency=1000 749pio_size=8 750ret_bad_addr=false 751ret_data16=65535 752ret_data32=4294967295 753ret_data64=18446744073709551615 754ret_data8=255 755system=system 756update_data=false 757warn_access= |
| 754pio=system.iobus.port[4] | 758pio=system.iobus.master[3] |
| 755 756[system.tsunami.fake_uart2] 757type=IsaFake 758fake_mem=false 759pio_addr=8804615848936 760pio_latency=1000 761pio_size=8 762ret_bad_addr=false 763ret_data16=65535 764ret_data32=4294967295 765ret_data64=18446744073709551615 766ret_data8=255 767system=system 768update_data=false 769warn_access= | 759 760[system.tsunami.fake_uart2] 761type=IsaFake 762fake_mem=false 763pio_addr=8804615848936 764pio_latency=1000 765pio_size=8 766ret_bad_addr=false 767ret_data16=65535 768ret_data32=4294967295 769ret_data64=18446744073709551615 770ret_data8=255 771system=system 772update_data=false 773warn_access= |
| 770pio=system.iobus.port[5] | 774pio=system.iobus.master[4] |
| 771 772[system.tsunami.fake_uart3] 773type=IsaFake 774fake_mem=false 775pio_addr=8804615848680 776pio_latency=1000 777pio_size=8 778ret_bad_addr=false 779ret_data16=65535 780ret_data32=4294967295 781ret_data64=18446744073709551615 782ret_data8=255 783system=system 784update_data=false 785warn_access= | 775 776[system.tsunami.fake_uart3] 777type=IsaFake 778fake_mem=false 779pio_addr=8804615848680 780pio_latency=1000 781pio_size=8 782ret_bad_addr=false 783ret_data16=65535 784ret_data32=4294967295 785ret_data64=18446744073709551615 786ret_data8=255 787system=system 788update_data=false 789warn_access= |
| 786pio=system.iobus.port[6] | 790pio=system.iobus.master[5] |
| 787 788[system.tsunami.fake_uart4] 789type=IsaFake 790fake_mem=false 791pio_addr=8804615848944 792pio_latency=1000 793pio_size=8 794ret_bad_addr=false 795ret_data16=65535 796ret_data32=4294967295 797ret_data64=18446744073709551615 798ret_data8=255 799system=system 800update_data=false 801warn_access= | 791 792[system.tsunami.fake_uart4] 793type=IsaFake 794fake_mem=false 795pio_addr=8804615848944 796pio_latency=1000 797pio_size=8 798ret_bad_addr=false 799ret_data16=65535 800ret_data32=4294967295 801ret_data64=18446744073709551615 802ret_data8=255 803system=system 804update_data=false 805warn_access= |
| 802pio=system.iobus.port[7] | 806pio=system.iobus.master[6] |
| 803 804[system.tsunami.fb] 805type=BadDevice 806devicename=FrameBuffer 807pio_addr=8804615848912 808pio_latency=1000 809system=system | 807 808[system.tsunami.fb] 809type=BadDevice 810devicename=FrameBuffer 811pio_addr=8804615848912 812pio_latency=1000 813system=system |
| 810pio=system.iobus.port[22] | 814pio=system.iobus.master[21] |
| 811 812[system.tsunami.ide] 813type=IdeController 814BAR0=1 815BAR0LegacyIO=false 816BAR0Size=8 817BAR1=1 818BAR1LegacyIO=false --- 37 unchanged lines hidden (view full) --- 856max_backoff_delay=10000000 857min_backoff_delay=4000 858pci_bus=0 859pci_dev=0 860pci_func=0 861pio_latency=1000 862platform=system.tsunami 863system=system | 815 816[system.tsunami.ide] 817type=IdeController 818BAR0=1 819BAR0LegacyIO=false 820BAR0Size=8 821BAR1=1 822BAR1LegacyIO=false --- 37 unchanged lines hidden (view full) --- 860max_backoff_delay=10000000 861min_backoff_delay=4000 862pci_bus=0 863pci_dev=0 864pci_func=0 865pio_latency=1000 866platform=system.tsunami 867system=system |
| 864config=system.iobus.port[27] 865dma=system.iobus.port[28] 866pio=system.iobus.port[26] | 868config=system.iobus.master[26] 869dma=system.iobus.slave[1] 870pio=system.iobus.master[25] |
| 867 868[system.tsunami.io] 869type=TsunamiIO 870frequency=976562500 871pio_addr=8804615847936 872pio_latency=1000 873system=system 874time=Thu Jan 1 00:00:00 2009 875tsunami=system.tsunami 876year_is_bcd=false | 871 872[system.tsunami.io] 873type=TsunamiIO 874frequency=976562500 875pio_addr=8804615847936 876pio_latency=1000 877system=system 878time=Thu Jan 1 00:00:00 2009 879tsunami=system.tsunami 880year_is_bcd=false |
| 877pio=system.iobus.port[23] | 881pio=system.iobus.master[22] |
| 878 879[system.tsunami.pchip] 880type=TsunamiPChip 881pio_addr=8802535473152 882pio_latency=1000 883system=system 884tsunami=system.tsunami | 882 883[system.tsunami.pchip] 884type=TsunamiPChip 885pio_addr=8802535473152 886pio_latency=1000 887system=system 888tsunami=system.tsunami |
| 885pio=system.iobus.port[2] | 889pio=system.iobus.master[1] |
| 886 887[system.tsunami.pciconfig] 888type=PciConfigAll 889bus=0 890pio_latency=1 891platform=system.tsunami 892size=16777216 893system=system 894pio=system.iobus.default 895 896[system.tsunami.uart] 897type=Uart8250 898pio_addr=8804615848952 899pio_latency=1000 900platform=system.tsunami 901system=system 902terminal=system.terminal | 890 891[system.tsunami.pciconfig] 892type=PciConfigAll 893bus=0 894pio_latency=1 895platform=system.tsunami 896size=16777216 897system=system 898pio=system.iobus.default 899 900[system.tsunami.uart] 901type=Uart8250 902pio_addr=8804615848952 903pio_latency=1000 904platform=system.tsunami 905system=system 906terminal=system.terminal |
| 903pio=system.iobus.port[24] | 907pio=system.iobus.master[23] |
| 904 | 908 |