| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing |
| 28mem_ranges=0:134217727 | 28mem_ranges=0:134217727:0:0:0:0 |
| 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal --- 18 unchanged lines hidden (view full) --- 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null | 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal --- 18 unchanged lines hidden (view full) --- 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null |
| 63ranges=8796093022208:18446744073709551615 | 63ranges=8796093022208:18446744073709551615:0:0:0:0 |
| 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 --- 38 unchanged lines hidden (view full) --- 110tracer=system.cpu0.tracer 111workload= 112dcache_port=system.cpu0.dcache.cpu_side 113icache_port=system.cpu0.icache.cpu_side 114 115[system.cpu0.dcache] 116type=Cache 117children=tags | 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 --- 38 unchanged lines hidden (view full) --- 110tracer=system.cpu0.tracer 111workload= 112dcache_port=system.cpu0.dcache.cpu_side 113icache_port=system.cpu0.icache.cpu_side 114 115[system.cpu0.dcache] 116type=Cache 117children=tags |
| 118addr_ranges=0:18446744073709551615 | 118addr_ranges=0:18446744073709551615:0:0:0:0 |
| 119assoc=4 120clk_domain=system.cpu_clk_domain 121clusivity=mostly_incl 122default_p_state=UNDEFINED 123demand_mshr_reserve=1 124eventq_index=0 125hit_latency=2 126is_read_only=false --- 34 unchanged lines hidden (view full) --- 161[system.cpu0.dtb] 162type=AlphaTLB 163eventq_index=0 164size=64 165 166[system.cpu0.icache] 167type=Cache 168children=tags | 119assoc=4 120clk_domain=system.cpu_clk_domain 121clusivity=mostly_incl 122default_p_state=UNDEFINED 123demand_mshr_reserve=1 124eventq_index=0 125hit_latency=2 126is_read_only=false --- 34 unchanged lines hidden (view full) --- 161[system.cpu0.dtb] 162type=AlphaTLB 163eventq_index=0 164size=64 165 166[system.cpu0.icache] 167type=Cache 168children=tags |
| 169addr_ranges=0:18446744073709551615 | 169addr_ranges=0:18446744073709551615:0:0:0:0 |
| 170assoc=1 171clk_domain=system.cpu_clk_domain 172clusivity=mostly_incl 173default_p_state=UNDEFINED 174demand_mshr_reserve=1 175eventq_index=0 176hit_latency=2 177is_read_only=true --- 85 unchanged lines hidden (view full) --- 263tracer=system.cpu1.tracer 264workload= 265dcache_port=system.cpu1.dcache.cpu_side 266icache_port=system.cpu1.icache.cpu_side 267 268[system.cpu1.dcache] 269type=Cache 270children=tags | 170assoc=1 171clk_domain=system.cpu_clk_domain 172clusivity=mostly_incl 173default_p_state=UNDEFINED 174demand_mshr_reserve=1 175eventq_index=0 176hit_latency=2 177is_read_only=true --- 85 unchanged lines hidden (view full) --- 263tracer=system.cpu1.tracer 264workload= 265dcache_port=system.cpu1.dcache.cpu_side 266icache_port=system.cpu1.icache.cpu_side 267 268[system.cpu1.dcache] 269type=Cache 270children=tags |
| 271addr_ranges=0:18446744073709551615 | 271addr_ranges=0:18446744073709551615:0:0:0:0 |
| 272assoc=4 273clk_domain=system.cpu_clk_domain 274clusivity=mostly_incl 275default_p_state=UNDEFINED 276demand_mshr_reserve=1 277eventq_index=0 278hit_latency=2 279is_read_only=false --- 34 unchanged lines hidden (view full) --- 314[system.cpu1.dtb] 315type=AlphaTLB 316eventq_index=0 317size=64 318 319[system.cpu1.icache] 320type=Cache 321children=tags | 272assoc=4 273clk_domain=system.cpu_clk_domain 274clusivity=mostly_incl 275default_p_state=UNDEFINED 276demand_mshr_reserve=1 277eventq_index=0 278hit_latency=2 279is_read_only=false --- 34 unchanged lines hidden (view full) --- 314[system.cpu1.dtb] 315type=AlphaTLB 316eventq_index=0 317size=64 318 319[system.cpu1.icache] 320type=Cache 321children=tags |
| 322addr_ranges=0:18446744073709551615 | 322addr_ranges=0:18446744073709551615:0:0:0:0 |
| 323assoc=1 324clk_domain=system.cpu_clk_domain 325clusivity=mostly_incl 326default_p_state=UNDEFINED 327demand_mshr_reserve=1 328eventq_index=0 329hit_latency=2 330is_read_only=true --- 131 unchanged lines hidden (view full) --- 462use_default_range=false 463width=16 464master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 465slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 466 467[system.iocache] 468type=Cache 469children=tags | 323assoc=1 324clk_domain=system.cpu_clk_domain 325clusivity=mostly_incl 326default_p_state=UNDEFINED 327demand_mshr_reserve=1 328eventq_index=0 329hit_latency=2 330is_read_only=true --- 131 unchanged lines hidden (view full) --- 462use_default_range=false 463width=16 464master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 465slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 466 467[system.iocache] 468type=Cache 469children=tags |
| 470addr_ranges=0:134217727 | 470addr_ranges=0:134217727:0:0:0:0 |
| 471assoc=8 472clk_domain=system.clk_domain 473clusivity=mostly_incl 474default_p_state=UNDEFINED 475demand_mshr_reserve=1 476eventq_index=0 477hit_latency=50 478is_read_only=false --- 29 unchanged lines hidden (view full) --- 508p_state_clk_gate_min=1000 509power_model=Null 510sequential_access=false 511size=1024 512 513[system.l2c] 514type=Cache 515children=tags | 471assoc=8 472clk_domain=system.clk_domain 473clusivity=mostly_incl 474default_p_state=UNDEFINED 475demand_mshr_reserve=1 476eventq_index=0 477hit_latency=50 478is_read_only=false --- 29 unchanged lines hidden (view full) --- 508p_state_clk_gate_min=1000 509power_model=Null 510sequential_access=false 511size=1024 512 513[system.l2c] 514type=Cache 515children=tags |
| 516addr_ranges=0:18446744073709551615 | 516addr_ranges=0:18446744073709551615:0:0:0:0 |
| 517assoc=8 518clk_domain=system.cpu_clk_domain 519clusivity=mostly_incl 520default_p_state=UNDEFINED 521demand_mshr_reserve=1 522eventq_index=0 523hit_latency=20 524is_read_only=false --- 81 unchanged lines hidden (view full) --- 606type=SnoopFilter 607eventq_index=0 608lookup_latency=1 609max_capacity=8388608 610system=system 611 612[system.physmem] 613type=DRAMCtrl | 517assoc=8 518clk_domain=system.cpu_clk_domain 519clusivity=mostly_incl 520default_p_state=UNDEFINED 521demand_mshr_reserve=1 522eventq_index=0 523hit_latency=20 524is_read_only=false --- 81 unchanged lines hidden (view full) --- 606type=SnoopFilter 607eventq_index=0 608lookup_latency=1 609max_capacity=8388608 610system=system 611 612[system.physmem] 613type=DRAMCtrl |
| 614IDD0=0.075000 | 614IDD0=0.055000 |
| 615IDD02=0.000000 | 615IDD02=0.000000 |
| 616IDD2N=0.050000 | 616IDD2N=0.032000 |
| 617IDD2N2=0.000000 618IDD2P0=0.000000 619IDD2P02=0.000000 | 617IDD2N2=0.000000 618IDD2P0=0.000000 619IDD2P02=0.000000 |
| 620IDD2P1=0.000000 | 620IDD2P1=0.032000 |
| 621IDD2P12=0.000000 | 621IDD2P12=0.000000 |
| 622IDD3N=0.057000 | 622IDD3N=0.038000 |
| 623IDD3N2=0.000000 624IDD3P0=0.000000 625IDD3P02=0.000000 | 623IDD3N2=0.000000 624IDD3P0=0.000000 625IDD3P02=0.000000 |
| 626IDD3P1=0.000000 | 626IDD3P1=0.038000 |
| 627IDD3P12=0.000000 | 627IDD3P12=0.000000 |
| 628IDD4R=0.187000 | 628IDD4R=0.157000 |
| 629IDD4R2=0.000000 | 629IDD4R2=0.000000 |
| 630IDD4W=0.165000 | 630IDD4W=0.125000 |
| 631IDD4W2=0.000000 | 631IDD4W2=0.000000 |
| 632IDD5=0.220000 | 632IDD5=0.235000 |
| 633IDD52=0.000000 | 633IDD52=0.000000 |
| 634IDD6=0.000000 | 634IDD6=0.020000 |
| 635IDD62=0.000000 636VDD=1.500000 637VDD2=0.000000 638activation_limit=4 639addr_mapping=RoRaBaCoCh 640bank_groups_per_rank=0 641banks_per_rank=8 642burst_length=8 643channels=1 644clk_domain=system.clk_domain 645conf_table_reported=true 646default_p_state=UNDEFINED 647device_bus_width=8 648device_rowbuffer_size=1024 649device_size=536870912 650devices_per_rank=8 651dll=true 652eventq_index=0 653in_addr_map=true | 635IDD62=0.000000 636VDD=1.500000 637VDD2=0.000000 638activation_limit=4 639addr_mapping=RoRaBaCoCh 640bank_groups_per_rank=0 641banks_per_rank=8 642burst_length=8 643channels=1 644clk_domain=system.clk_domain 645conf_table_reported=true 646default_p_state=UNDEFINED 647device_bus_width=8 648device_rowbuffer_size=1024 649device_size=536870912 650devices_per_rank=8 651dll=true 652eventq_index=0 653in_addr_map=true |
| 654kvm_map=true |
|
| 654max_accesses_per_row=16 655mem_sched_policy=frfcfs 656min_writes_per_switch=16 657null=false 658p_state_clk_gate_bins=20 659p_state_clk_gate_max=1000000000000 660p_state_clk_gate_min=1000 661page_policy=open_adaptive 662power_model=Null | 655max_accesses_per_row=16 656mem_sched_policy=frfcfs 657min_writes_per_switch=16 658null=false 659p_state_clk_gate_bins=20 660p_state_clk_gate_max=1000000000000 661p_state_clk_gate_min=1000 662page_policy=open_adaptive 663power_model=Null |
| 663range=0:134217727 | 664range=0:134217727:0:0:0:0 |
| 664ranks_per_channel=2 665read_buffer_size=32 666static_backend_latency=10000 667static_frontend_latency=10000 668tBURST=5000 669tCCD_L=0 670tCK=1250 671tCL=13750 --- 5 unchanged lines hidden (view full) --- 677tRP=13750 678tRRD=6000 679tRRD_L=0 680tRTP=7500 681tRTW=2500 682tWR=15000 683tWTR=7500 684tXAW=30000 | 665ranks_per_channel=2 666read_buffer_size=32 667static_backend_latency=10000 668static_frontend_latency=10000 669tBURST=5000 670tCCD_L=0 671tCK=1250 672tCL=13750 --- 5 unchanged lines hidden (view full) --- 678tRP=13750 679tRRD=6000 680tRRD_L=0 681tRTP=7500 682tRTW=2500 683tWR=15000 684tWTR=7500 685tXAW=30000 |
| 685tXP=0 | 686tXP=6000 |
| 686tXPDLL=0 | 687tXPDLL=0 |
| 687tXS=0 | 688tXS=270000 |
| 688tXSDLL=0 689write_buffer_size=64 690write_high_thresh_perc=85 691write_low_thresh_perc=50 692port=system.membus.master[1] 693 694[system.simple_disk] 695type=SimpleDisk --- 803 unchanged lines hidden --- | 689tXSDLL=0 690write_buffer_size=64 691write_high_thresh_perc=85 692write_low_thresh_perc=50 693port=system.membus.master[1] 694 695[system.simple_disk] 696type=SimpleDisk --- 803 unchanged lines hidden --- |