| config.ini (10636:9ac724889705) | config.ini (10736:4433fb00fa7d) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20init_param=0 21kernel=/scratch/nilay/GEM5/system/binaries/vmlinux 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 11 unchanged lines hidden (view full) --- 20init_param=0 21kernel=/scratch/nilay/GEM5/system/binaries/vmlinux 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:134217727 27memories=system.physmem |
| 28mmap_using_noreserve=false |
|
| 28num_work_ids=16 29pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal 30readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 31symbolfile= 32system_rev=1024 33system_type=34 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 --- 345 unchanged lines hidden (view full) --- 381type=IntrControl 382eventq_index=0 383sys=system 384 385[system.iobus] 386type=NoncoherentXBar 387clk_domain=system.clk_domain 388eventq_index=0 | 29num_work_ids=16 30pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal 31readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 32symbolfile= 33system_rev=1024 34system_type=34 35work_begin_ckpt_count=0 36work_begin_cpu_id_exit=-1 --- 345 unchanged lines hidden (view full) --- 382type=IntrControl 383eventq_index=0 384sys=system 385 386[system.iobus] 387type=NoncoherentXBar 388clk_domain=system.clk_domain 389eventq_index=0 |
| 389header_cycles=1 | 390forward_latency=1 391frontend_latency=2 392response_latency=2 |
| 390use_default_range=true | 393use_default_range=true |
| 391width=8 | 394width=16 |
| 392default=system.tsunami.pciconfig.pio 393master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 394slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 395 396[system.iocache] 397type=BaseCache 398children=tags 399addr_ranges=0:134217727 --- 65 unchanged lines hidden (view full) --- 465sequential_access=false 466size=4194304 467 468[system.membus] 469type=CoherentXBar 470children=badaddr_responder 471clk_domain=system.clk_domain 472eventq_index=0 | 395default=system.tsunami.pciconfig.pio 396master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 397slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 398 399[system.iocache] 400type=BaseCache 401children=tags 402addr_ranges=0:134217727 --- 65 unchanged lines hidden (view full) --- 468sequential_access=false 469size=4194304 470 471[system.membus] 472type=CoherentXBar 473children=badaddr_responder 474clk_domain=system.clk_domain 475eventq_index=0 |
| 473header_cycles=1 | 476forward_latency=4 477frontend_latency=3 478response_latency=2 |
| 474snoop_filter=Null | 479snoop_filter=Null |
| 480snoop_response_latency=4 |
|
| 475system=system 476use_default_range=false | 481system=system 482use_default_range=false |
| 477width=8 | 483width=16 |
| 478default=system.membus.badaddr_responder.pio 479master=system.bridge.slave system.physmem.port 480slave=system.system_port system.l2c.mem_side system.iocache.mem_side 481 482[system.membus.badaddr_responder] 483type=IsaFake 484clk_domain=system.clk_domain 485eventq_index=0 --- 33 unchanged lines hidden (view full) --- 519IDD4W2=0.000000 520IDD5=0.220000 521IDD52=0.000000 522IDD6=0.000000 523IDD62=0.000000 524VDD=1.500000 525VDD2=0.000000 526activation_limit=4 | 484default=system.membus.badaddr_responder.pio 485master=system.bridge.slave system.physmem.port 486slave=system.system_port system.l2c.mem_side system.iocache.mem_side 487 488[system.membus.badaddr_responder] 489type=IsaFake 490clk_domain=system.clk_domain 491eventq_index=0 --- 33 unchanged lines hidden (view full) --- 525IDD4W2=0.000000 526IDD5=0.220000 527IDD52=0.000000 528IDD6=0.000000 529IDD62=0.000000 530VDD=1.500000 531VDD2=0.000000 532activation_limit=4 |
| 527addr_mapping=RoRaBaChCo | 533addr_mapping=RoRaBaCoCh |
| 528bank_groups_per_rank=0 529banks_per_rank=8 530burst_length=8 531channels=1 532clk_domain=system.clk_domain 533conf_table_reported=true 534device_bus_width=8 535device_rowbuffer_size=1024 --- 58 unchanged lines hidden (view full) --- 594number=0 595output=true 596port=3456 597 598[system.toL2Bus] 599type=CoherentXBar 600clk_domain=system.cpu_clk_domain 601eventq_index=0 | 534bank_groups_per_rank=0 535banks_per_rank=8 536burst_length=8 537channels=1 538clk_domain=system.clk_domain 539conf_table_reported=true 540device_bus_width=8 541device_rowbuffer_size=1024 --- 58 unchanged lines hidden (view full) --- 600number=0 601output=true 602port=3456 603 604[system.toL2Bus] 605type=CoherentXBar 606clk_domain=system.cpu_clk_domain 607eventq_index=0 |
| 602header_cycles=1 | 608forward_latency=0 609frontend_latency=1 610response_latency=1 |
| 603snoop_filter=Null | 611snoop_filter=Null |
| 612snoop_response_latency=1 |
|
| 604system=system 605use_default_range=false | 613system=system 614use_default_range=false |
| 606width=8 | 615width=32 |
| 607master=system.l2c.cpu_side 608slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 609 610[system.tsunami] 611type=Tsunami 612children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 613eventq_index=0 614intrctrl=system.intrctrl --- 622 unchanged lines hidden --- | 616master=system.l2c.cpu_side 617slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 618 619[system.tsunami] 620type=Tsunami 621children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 622eventq_index=0 623intrctrl=system.intrctrl --- 622 unchanged lines hidden --- |