| stats.txt (9885:afd9ea6101d9) | stats.txt (9962:7aef35367a21) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated |
| 4sim_ticks 1870335643500 # Number of ticks simulated 5final_tick 1870335643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 2937220 # Simulator instruction rate (inst/s) 8host_op_rate 2937218 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 86986978503 # Simulator tick rate (ticks/s) 10host_mem_usage 308008 # Number of bytes of host memory used 11host_seconds 21.50 # Real time elapsed on the host | 7host_inst_rate 2234616 # Simulator instruction rate (inst/s) 8host_op_rate 2234615 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 66179117761 # Simulator tick rate (ticks/s) 10host_mem_usage 308940 # Number of bytes of host memory used 11host_seconds 28.26 # Real time elapsed on the host |
| 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory 19system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory --- 6 unchanged lines hidden (view full) --- 26system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) | 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory 19system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory --- 6 unchanged lines hidden (view full) --- 26system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::cpu0.data 35658336 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::total 37898823 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) | 39system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_write::writebacks 4203258 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4203258 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4203258 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s) |
| 45system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu0.data 35658336 # Total bandwidth to/from this memory (bytes/s) | 46system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller 52system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 53system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 54system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 55system.physmem.bytesRead 0 # Total number of bytes read from memory 56system.physmem.bytesWritten 0 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 60system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 95system.physmem.totGap 0 # Total gap between requests 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 0 # Categorize read packet sizes 99system.physmem.readPktSize::3 0 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes 102system.physmem.readPktSize::6 0 # Categorize read packet sizes 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 0 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes 109system.physmem.writePktSize::6 0 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 142system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 174system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation 175system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation 176system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation 177system.physmem.totQLat 0 # Total cycles spent in queuing delays 178system.physmem.totMemAccLat 0 # Sum of mem lat for all requests 179system.physmem.totBusLat 0 # Total cycles spent in databus access 180system.physmem.totBankLat 0 # Total cycles spent in bank access 181system.physmem.avgQLat nan # Average queueing delay per request 182system.physmem.avgBankLat nan # Average bank access latency per request 183system.physmem.avgBusLat nan # Average bus latency per request 184system.physmem.avgMemAccLat nan # Average memory access latency 185system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 186system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 187system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 188system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 189system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 190system.physmem.busUtil 0.00 # Data bus utilization in percentage 191system.physmem.avgRdQLen 0.00 # Average read queue length over time 192system.physmem.avgWrQLen 0.00 # Average write queue length over time 193system.physmem.readRowHits 0 # Number of row buffer hits during reads 194system.physmem.writeRowHits 0 # Number of row buffer hits during writes 195system.physmem.readRowHitRate nan # Row buffer hit rate for reads 196system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 197system.physmem.avgGap nan # Average gap between requests 198system.membus.throughput 42160246 # Throughput (bytes/s) | 50system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) 51system.membus.throughput 42160248 # Throughput (bytes/s) |
| 199system.membus.data_through_bus 78853810 # Total data (bytes) 200system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 201system.l2c.tags.replacements 1000626 # number of replacements | 52system.membus.data_through_bus 78853810 # Total data (bytes) 53system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 54system.l2c.tags.replacements 1000626 # number of replacements |
| 202system.l2c.tags.tagsinuse 65381.922487 # Cycle average of tags in use 203system.l2c.tags.total_refs 2464723 # Total number of references to valid blocks. | 55system.l2c.tags.tagsinuse 65381.922680 # Cycle average of tags in use 56system.l2c.tags.total_refs 2464737 # Total number of references to valid blocks. |
| 204system.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. | 57system.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks. |
| 205system.l2c.tags.avg_refs 2.312626 # Average number of references to valid blocks. | 58system.l2c.tags.avg_refs 2.312639 # Average number of references to valid blocks. |
| 206system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. | 59system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. |
| 207system.l2c.tags.occ_blocks::writebacks 56158.706931 # Average occupied blocks per requestor 208system.l2c.tags.occ_blocks::cpu0.inst 4894.235246 # Average occupied blocks per requestor 209system.l2c.tags.occ_blocks::cpu0.data 4134.598984 # Average occupied blocks per requestor 210system.l2c.tags.occ_blocks::cpu1.inst 174.423126 # Average occupied blocks per requestor 211system.l2c.tags.occ_blocks::cpu1.data 19.958201 # Average occupied blocks per requestor | 60system.l2c.tags.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor 61system.l2c.tags.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor 62system.l2c.tags.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor 63system.l2c.tags.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor 64system.l2c.tags.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor |
| 212system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 213system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 214system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 215system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 216system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 217system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy | 65system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 66system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 67system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 68system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 69system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 70system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy |
| 218system.l2c.ReadReq_hits::cpu0.inst 873088 # number of ReadReq hits 219system.l2c.ReadReq_hits::cpu0.data 763068 # number of ReadReq hits 220system.l2c.ReadReq_hits::cpu1.inst 101908 # number of ReadReq hits 221system.l2c.ReadReq_hits::cpu1.data 36743 # number of ReadReq hits 222system.l2c.ReadReq_hits::total 1774807 # number of ReadReq hits 223system.l2c.Writeback_hits::writebacks 816628 # number of Writeback hits 224system.l2c.Writeback_hits::total 816628 # number of Writeback hits | 71system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits 72system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits 73system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits 74system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits 75system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits 76system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits 77system.l2c.Writeback_hits::total 816653 # number of Writeback hits |
| 225system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits 226system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 227system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits 228system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 229system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 230system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits | 78system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits 79system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 80system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits 81system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 82system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 83system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits |
| 231system.l2c.ReadExReq_hits::cpu0.data 166235 # number of ReadExReq hits 232system.l2c.ReadExReq_hits::cpu1.data 14287 # number of ReadExReq hits 233system.l2c.ReadExReq_hits::total 180522 # number of ReadExReq hits 234system.l2c.demand_hits::cpu0.inst 873088 # number of demand (read+write) hits 235system.l2c.demand_hits::cpu0.data 929303 # number of demand (read+write) hits 236system.l2c.demand_hits::cpu1.inst 101908 # number of demand (read+write) hits 237system.l2c.demand_hits::cpu1.data 51030 # number of demand (read+write) hits 238system.l2c.demand_hits::total 1955329 # number of demand (read+write) hits 239system.l2c.overall_hits::cpu0.inst 873088 # number of overall hits 240system.l2c.overall_hits::cpu0.data 929303 # number of overall hits 241system.l2c.overall_hits::cpu1.inst 101908 # number of overall hits 242system.l2c.overall_hits::cpu1.data 51030 # number of overall hits 243system.l2c.overall_hits::total 1955329 # number of overall hits | 84system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits 85system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits 86system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits 87system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits 88system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits 89system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits 90system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits 91system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits 92system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits 93system.l2c.overall_hits::cpu0.data 929311 # number of overall hits 94system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits 95system.l2c.overall_hits::cpu1.data 51019 # number of overall hits 96system.l2c.overall_hits::total 1955312 # number of overall hits |
| 244system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses 245system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 246system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 247system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 248system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses 249system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 250system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 251system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses --- 8 unchanged lines hidden (view full) --- 260system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses 261system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 262system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses 263system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses 264system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 265system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 266system.l2c.overall_misses::cpu1.data 10570 # number of overall misses 267system.l2c.overall_misses::total 1066665 # number of overall misses | 97system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses 98system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 99system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 100system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 101system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses 102system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 103system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 104system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses --- 8 unchanged lines hidden (view full) --- 113system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses 114system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 115system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses 116system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses 117system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 118system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 119system.l2c.overall_misses::cpu1.data 10570 # number of overall misses 120system.l2c.overall_misses::total 1066665 # number of overall misses |
| 268system.l2c.ReadReq_accesses::cpu0.inst 884982 # number of ReadReq accesses(hits+misses) 269system.l2c.ReadReq_accesses::cpu0.data 1689829 # number of ReadReq accesses(hits+misses) 270system.l2c.ReadReq_accesses::cpu1.inst 103642 # number of ReadReq accesses(hits+misses) 271system.l2c.ReadReq_accesses::cpu1.data 37651 # number of ReadReq accesses(hits+misses) 272system.l2c.ReadReq_accesses::total 2716104 # number of ReadReq accesses(hits+misses) 273system.l2c.Writeback_accesses::writebacks 816628 # number of Writeback accesses(hits+misses) 274system.l2c.Writeback_accesses::total 816628 # number of Writeback accesses(hits+misses) | 121system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) 122system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) 123system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) 124system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) 125system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) 126system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) 127system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) |
| 275system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) 276system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 277system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) 278system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 279system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 280system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) | 128system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) 129system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 130system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) 131system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 132system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 133system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) |
| 281system.l2c.ReadExReq_accesses::cpu0.data 281941 # number of ReadExReq accesses(hits+misses) 282system.l2c.ReadExReq_accesses::cpu1.data 23949 # number of ReadExReq accesses(hits+misses) 283system.l2c.ReadExReq_accesses::total 305890 # number of ReadExReq accesses(hits+misses) 284system.l2c.demand_accesses::cpu0.inst 884982 # number of demand (read+write) accesses 285system.l2c.demand_accesses::cpu0.data 1971770 # number of demand (read+write) accesses 286system.l2c.demand_accesses::cpu1.inst 103642 # number of demand (read+write) accesses 287system.l2c.demand_accesses::cpu1.data 61600 # number of demand (read+write) accesses 288system.l2c.demand_accesses::total 3021994 # number of demand (read+write) accesses 289system.l2c.overall_accesses::cpu0.inst 884982 # number of overall (read+write) accesses 290system.l2c.overall_accesses::cpu0.data 1971770 # number of overall (read+write) accesses 291system.l2c.overall_accesses::cpu1.inst 103642 # number of overall (read+write) accesses 292system.l2c.overall_accesses::cpu1.data 61600 # number of overall (read+write) accesses 293system.l2c.overall_accesses::total 3021994 # number of overall (read+write) accesses | 134system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) 135system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) 136system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) 137system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses 138system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses 139system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses 140system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses 141system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses 142system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses 143system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses 144system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses 145system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses 146system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses |
| 294system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses | 147system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses |
| 295system.l2c.ReadReq_miss_rate::cpu0.data 0.548435 # miss rate for ReadReq accesses 296system.l2c.ReadReq_miss_rate::cpu1.inst 0.016731 # miss rate for ReadReq accesses 297system.l2c.ReadReq_miss_rate::cpu1.data 0.024116 # miss rate for ReadReq accesses 298system.l2c.ReadReq_miss_rate::total 0.346561 # miss rate for ReadReq accesses | 148system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses 149system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses 150system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses 151system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses |
| 299system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses 300system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses 301system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses 302system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 303system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 304system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses | 152system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses 153system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses 154system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses 155system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 156system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 157system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses |
| 305system.l2c.ReadExReq_miss_rate::cpu0.data 0.410391 # miss rate for ReadExReq accesses 306system.l2c.ReadExReq_miss_rate::cpu1.data 0.403441 # miss rate for ReadExReq accesses 307system.l2c.ReadExReq_miss_rate::total 0.409847 # miss rate for ReadExReq accesses | 158system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses 159system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses 160system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses |
| 308system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses | 161system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses |
| 309system.l2c.demand_miss_rate::cpu0.data 0.528696 # miss rate for demand accesses 310system.l2c.demand_miss_rate::cpu1.inst 0.016731 # miss rate for demand accesses 311system.l2c.demand_miss_rate::cpu1.data 0.171591 # miss rate for demand accesses 312system.l2c.demand_miss_rate::total 0.352967 # miss rate for demand accesses | 162system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses 163system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses 164system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses 165system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses |
| 313system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses | 166system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses |
| 314system.l2c.overall_miss_rate::cpu0.data 0.528696 # miss rate for overall accesses 315system.l2c.overall_miss_rate::cpu1.inst 0.016731 # miss rate for overall accesses 316system.l2c.overall_miss_rate::cpu1.data 0.171591 # miss rate for overall accesses 317system.l2c.overall_miss_rate::total 0.352967 # miss rate for overall accesses | 167system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses 168system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses 169system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses 170system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses |
| 318system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 321system.l2c.blocked::no_targets 0 # number of cycles access was blocked 322system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.l2c.fast_writes 0 # number of fast writes performed 325system.l2c.cache_copies 0 # number of cache copies performed 326system.l2c.writebacks::writebacks 81316 # number of writebacks 327system.l2c.writebacks::total 81316 # number of writebacks 328system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 329system.iocache.tags.replacements 41695 # number of replacements | 171system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 174system.l2c.blocked::no_targets 0 # number of cycles access was blocked 175system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 177system.l2c.fast_writes 0 # number of fast writes performed 178system.l2c.cache_copies 0 # number of cache copies performed 179system.l2c.writebacks::writebacks 81316 # number of writebacks 180system.l2c.writebacks::total 81316 # number of writebacks 181system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 182system.iocache.tags.replacements 41695 # number of replacements |
| 330system.iocache.tags.tagsinuse 0.435438 # Cycle average of tags in use | 183system.iocache.tags.tagsinuse 0.435437 # Cycle average of tags in use |
| 331system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 332system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 333system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 334system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. | 184system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 185system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. 186system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 187system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. |
| 335system.iocache.tags.occ_blocks::tsunami.ide 0.435438 # Average occupied blocks per requestor | 188system.iocache.tags.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor |
| 336system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy 337system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy 338system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 339system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 340system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 341system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 342system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 343system.iocache.demand_misses::total 41727 # number of demand (read+write) misses --- 65 unchanged lines hidden (view full) --- 409system.cpu0.itb.write_hits 0 # DTB write hits 410system.cpu0.itb.write_misses 0 # DTB write misses 411system.cpu0.itb.write_acv 0 # DTB write access violations 412system.cpu0.itb.write_accesses 0 # DTB write accesses 413system.cpu0.itb.data_hits 0 # DTB hits 414system.cpu0.itb.data_misses 0 # DTB misses 415system.cpu0.itb.data_acv 0 # DTB access violations 416system.cpu0.itb.data_accesses 0 # DTB accesses | 189system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy 190system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy 191system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses 192system.iocache.ReadReq_misses::total 175 # number of ReadReq misses 193system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 194system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 195system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses 196system.iocache.demand_misses::total 41727 # number of demand (read+write) misses --- 65 unchanged lines hidden (view full) --- 262system.cpu0.itb.write_hits 0 # DTB write hits 263system.cpu0.itb.write_misses 0 # DTB write misses 264system.cpu0.itb.write_acv 0 # DTB write access violations 265system.cpu0.itb.write_accesses 0 # DTB write accesses 266system.cpu0.itb.data_hits 0 # DTB hits 267system.cpu0.itb.data_misses 0 # DTB misses 268system.cpu0.itb.data_acv 0 # DTB access violations 269system.cpu0.itb.data_accesses 0 # DTB accesses |
| 417system.cpu0.numCycles 3740671175 # number of cpu cycles simulated | 270system.cpu0.numCycles 3740670933 # number of cpu cycles simulated |
| 418system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 419system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 420system.cpu0.committedInsts 57222076 # Number of instructions committed 421system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed 422system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses 423system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 424system.cpu0.num_func_calls 1399585 # number of times a function call or return occured 425system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls 426system.cpu0.num_int_insts 53249924 # number of integer instructions 427system.cpu0.num_fp_insts 299810 # number of float instructions 428system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read 429system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written 430system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 431system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 432system.cpu0.num_mem_refs 15135515 # number of memory refs 433system.cpu0.num_load_insts 9184477 # Number of load instructions 434system.cpu0.num_store_insts 5951038 # Number of store instructions | 271system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 273system.cpu0.committedInsts 57222076 # Number of instructions committed 274system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed 275system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses 276system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses 277system.cpu0.num_func_calls 1399585 # number of times a function call or return occured 278system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls 279system.cpu0.num_int_insts 53249924 # number of integer instructions 280system.cpu0.num_fp_insts 299810 # number of float instructions 281system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read 282system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written 283system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read 284system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written 285system.cpu0.num_mem_refs 15135515 # number of memory refs 286system.cpu0.num_load_insts 9184477 # Number of load instructions 287system.cpu0.num_store_insts 5951038 # Number of store instructions |
| 435system.cpu0.num_idle_cycles 3683437331.313678 # Number of idle cycles | 288system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles |
| 436system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles 437system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 438system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 439system.cpu0.kern.inst.arm 0 # number of arm instructions executed 440system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 441system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 442system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 443system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 444system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 445system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 446system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl 447system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 448system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 449system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 450system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 451system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 452system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 453system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl | 289system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles 290system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles 291system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles 292system.cpu0.kern.inst.arm 0 # number of arm instructions executed 293system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed 294system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed 295system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl 296system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl 297system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl 298system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl 299system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl 300system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl 301system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl 302system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 303system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 304system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 305system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl 306system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl |
| 454system.cpu0.kern.ipl_ticks::0 1852989887500 99.07% 99.07% # number of cycles we spent at this ipl | 307system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl |
| 455system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 456system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 457system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 458system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl | 308system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl 309system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl 310system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 311system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl |
| 459system.cpu0.kern.ipl_ticks::total 1870335436000 # number of cycles we spent at this ipl | 312system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl |
| 460system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 461system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 462system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 463system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 464system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 465system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl 466system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 467system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed --- 49 unchanged lines hidden (view full) --- 517system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 518system.cpu0.kern.mode_good::kernel 1157 519system.cpu0.kern.mode_good::user 1158 520system.cpu0.kern.mode_good::idle 0 521system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 522system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 523system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 524system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches | 313system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 314system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 315system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 316system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 317system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl 318system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl 319system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 320system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed --- 49 unchanged lines hidden (view full) --- 370system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 371system.cpu0.kern.mode_good::kernel 1157 372system.cpu0.kern.mode_good::user 1158 373system.cpu0.kern.mode_good::idle 0 374system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 375system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 376system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 377system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches |
| 525system.cpu0.kern.mode_ticks::kernel 1869378426000 99.95% 99.95% # number of ticks spent at the given mode | 378system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode |
| 526system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 527system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 528system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 529system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 530system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 531system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 532system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 533system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 18 unchanged lines hidden (view full) --- 552system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 553system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 554system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 555system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 556system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 557system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 558system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 559system.tsunami.ethernet.droppedPackets 0 # number of packets dropped | 379system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 380system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 381system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 382system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 383system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 384system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 385system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 386system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 18 unchanged lines hidden (view full) --- 405system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 406system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 407system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 408system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 409system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 410system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 411system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 412system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 560system.toL2Bus.throughput 131930075 # Throughput (bytes/s) 561system.toL2Bus.data_through_bus 246743154 # Total data (bytes) | 413system.toL2Bus.throughput 131930255 # Throughput (bytes/s) 414system.toL2Bus.data_through_bus 246743474 # Total data (bytes) |
| 562system.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) | 415system.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes) |
| 563system.iobus.throughput 1460500 # Throughput (bytes/s) | 416system.iobus.throughput 1460501 # Throughput (bytes/s) |
| 564system.iobus.data_through_bus 2731626 # Total data (bytes) | 417system.iobus.data_through_bus 2731626 # Total data (bytes) |
| 565system.cpu0.icache.tags.replacements 884406 # number of replacements | 418system.cpu0.icache.tags.replacements 884404 # number of replacements |
| 566system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use | 419system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use |
| 567system.cpu0.icache.tags.total_refs 56345130 # Total number of references to valid blocks. 568system.cpu0.icache.tags.sampled_refs 884918 # Sample count of references to valid blocks. 569system.cpu0.icache.tags.avg_refs 63.672713 # Average number of references to valid blocks. | 420system.cpu0.icache.tags.total_refs 56345132 # Total number of references to valid blocks. 421system.cpu0.icache.tags.sampled_refs 884916 # Sample count of references to valid blocks. 422system.cpu0.icache.tags.avg_refs 63.672859 # Average number of references to valid blocks. |
| 570system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 571system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor 572system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy 573system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy | 423system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 424system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor 425system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy 426system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy |
| 574system.cpu0.icache.ReadReq_hits::cpu0.inst 56345130 # number of ReadReq hits 575system.cpu0.icache.ReadReq_hits::total 56345130 # number of ReadReq hits 576system.cpu0.icache.demand_hits::cpu0.inst 56345130 # number of demand (read+write) hits 577system.cpu0.icache.demand_hits::total 56345130 # number of demand (read+write) hits 578system.cpu0.icache.overall_hits::cpu0.inst 56345130 # number of overall hits 579system.cpu0.icache.overall_hits::total 56345130 # number of overall hits 580system.cpu0.icache.ReadReq_misses::cpu0.inst 885002 # number of ReadReq misses 581system.cpu0.icache.ReadReq_misses::total 885002 # number of ReadReq misses 582system.cpu0.icache.demand_misses::cpu0.inst 885002 # number of demand (read+write) misses 583system.cpu0.icache.demand_misses::total 885002 # number of demand (read+write) misses 584system.cpu0.icache.overall_misses::cpu0.inst 885002 # number of overall misses 585system.cpu0.icache.overall_misses::total 885002 # number of overall misses | 427system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits 428system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits 429system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits 430system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits 431system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits 432system.cpu0.icache.overall_hits::total 56345132 # number of overall hits 433system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses 434system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses 435system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses 436system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses 437system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses 438system.cpu0.icache.overall_misses::total 885000 # number of overall misses |
| 586system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) 587system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 588system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses 589system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 590system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses 591system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 592system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 593system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses --- 5 unchanged lines hidden (view full) --- 599system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 600system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 601system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 602system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 603system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 604system.cpu0.icache.fast_writes 0 # number of fast writes performed 605system.cpu0.icache.cache_copies 0 # number of cache copies performed 606system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 439system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) 440system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 441system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses 442system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 443system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses 444system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 445system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 446system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses --- 5 unchanged lines hidden (view full) --- 452system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 453system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 454system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 455system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 456system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 457system.cpu0.icache.fast_writes 0 # number of fast writes performed 458system.cpu0.icache.cache_copies 0 # number of cache copies performed 459system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 607system.cpu0.dcache.tags.replacements 1978683 # number of replacements 608system.cpu0.dcache.tags.tagsinuse 507.129817 # Cycle average of tags in use 609system.cpu0.dcache.tags.total_refs 13123756 # Total number of references to valid blocks. 610system.cpu0.dcache.tags.sampled_refs 1979195 # Sample count of references to valid blocks. 611system.cpu0.dcache.tags.avg_refs 6.630855 # Average number of references to valid blocks. | 460system.cpu0.dcache.tags.replacements 1978686 # number of replacements 461system.cpu0.dcache.tags.tagsinuse 507.129778 # Cycle average of tags in use 462system.cpu0.dcache.tags.total_refs 13123753 # Total number of references to valid blocks. 463system.cpu0.dcache.tags.sampled_refs 1979198 # Sample count of references to valid blocks. 464system.cpu0.dcache.tags.avg_refs 6.630844 # Average number of references to valid blocks. |
| 612system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. | 465system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. |
| 613system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129817 # Average occupied blocks per requestor | 466system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor |
| 614system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy 615system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy | 467system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy 468system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy |
| 616system.cpu0.dcache.ReadReq_hits::cpu0.data 7298341 # number of ReadReq hits 617system.cpu0.dcache.ReadReq_hits::total 7298341 # number of ReadReq hits 618system.cpu0.dcache.WriteReq_hits::cpu0.data 5462261 # number of WriteReq hits 619system.cpu0.dcache.WriteReq_hits::total 5462261 # number of WriteReq hits | 469system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits 470system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits 471system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits 472system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits |
| 620system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits 621system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits | 473system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits 474system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits |
| 622system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186623 # number of StoreCondReq hits 623system.cpu0.dcache.StoreCondReq_hits::total 186623 # number of StoreCondReq hits 624system.cpu0.dcache.demand_hits::cpu0.data 12760602 # number of demand (read+write) hits 625system.cpu0.dcache.demand_hits::total 12760602 # number of demand (read+write) hits 626system.cpu0.dcache.overall_hits::cpu0.data 12760602 # number of overall hits 627system.cpu0.dcache.overall_hits::total 12760602 # number of overall hits 628system.cpu0.dcache.ReadReq_misses::cpu0.data 1683328 # number of ReadReq misses 629system.cpu0.dcache.ReadReq_misses::total 1683328 # number of ReadReq misses 630system.cpu0.dcache.WriteReq_misses::cpu0.data 286000 # number of WriteReq misses 631system.cpu0.dcache.WriteReq_misses::total 286000 # number of WriteReq misses | 475system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits 476system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits 477system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits 478system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits 479system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits 480system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits 481system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses 482system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses 483system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses 484system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses |
| 632system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses 633system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses | 485system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses 486system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses |
| 634system.cpu0.dcache.StoreCondReq_misses::cpu0.data 715 # number of StoreCondReq misses 635system.cpu0.dcache.StoreCondReq_misses::total 715 # number of StoreCondReq misses 636system.cpu0.dcache.demand_misses::cpu0.data 1969328 # number of demand (read+write) misses 637system.cpu0.dcache.demand_misses::total 1969328 # number of demand (read+write) misses 638system.cpu0.dcache.overall_misses::cpu0.data 1969328 # number of overall misses 639system.cpu0.dcache.overall_misses::total 1969328 # number of overall misses | 487system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses 488system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses 489system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses 490system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses 491system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses 492system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses |
| 640system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) 641system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) 642system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) 643system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) 644system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) 645system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 646system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 647system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 648system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses 649system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 650system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses 651system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses | 493system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) 494system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) 495system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) 496system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) 497system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) 498system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 499system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 500system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 501system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses 502system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 503system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses 504system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses |
| 652system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187418 # miss rate for ReadReq accesses 653system.cpu0.dcache.ReadReq_miss_rate::total 0.187418 # miss rate for ReadReq accesses | 505system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses 506system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses |
| 654system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses 655system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses 656system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses 657system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses | 507system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses 508system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses 509system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses 510system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses |
| 658system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003817 # miss rate for StoreCondReq accesses 659system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003817 # miss rate for StoreCondReq accesses | 511system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses 512system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses |
| 660system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses 661system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses 662system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses 663system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses 664system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 665system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 666system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 667system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 668system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 669system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 670system.cpu0.dcache.fast_writes 0 # number of fast writes performed 671system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 513system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses 514system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses 515system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses 516system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses 517system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 518system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 519system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 520system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 521system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 522system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 523system.cpu0.dcache.fast_writes 0 # number of fast writes performed 524system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 672system.cpu0.dcache.writebacks::writebacks 775614 # number of writebacks 673system.cpu0.dcache.writebacks::total 775614 # number of writebacks | 525system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks 526system.cpu0.dcache.writebacks::total 775641 # number of writebacks |
| 674system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 675system.cpu1.dtb.fetch_hits 0 # ITB hits 676system.cpu1.dtb.fetch_misses 0 # ITB misses 677system.cpu1.dtb.fetch_acv 0 # ITB acv 678system.cpu1.dtb.fetch_accesses 0 # ITB accesses 679system.cpu1.dtb.read_hits 1163439 # DTB read hits 680system.cpu1.dtb.read_misses 3277 # DTB read misses 681system.cpu1.dtb.read_acv 58 # DTB read access violations --- 17 unchanged lines hidden (view full) --- 699system.cpu1.itb.write_hits 0 # DTB write hits 700system.cpu1.itb.write_misses 0 # DTB write misses 701system.cpu1.itb.write_acv 0 # DTB write access violations 702system.cpu1.itb.write_accesses 0 # DTB write accesses 703system.cpu1.itb.data_hits 0 # DTB hits 704system.cpu1.itb.data_misses 0 # DTB misses 705system.cpu1.itb.data_acv 0 # DTB access violations 706system.cpu1.itb.data_accesses 0 # DTB accesses | 527system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 528system.cpu1.dtb.fetch_hits 0 # ITB hits 529system.cpu1.dtb.fetch_misses 0 # ITB misses 530system.cpu1.dtb.fetch_acv 0 # ITB acv 531system.cpu1.dtb.fetch_accesses 0 # ITB accesses 532system.cpu1.dtb.read_hits 1163439 # DTB read hits 533system.cpu1.dtb.read_misses 3277 # DTB read misses 534system.cpu1.dtb.read_acv 58 # DTB read access violations --- 17 unchanged lines hidden (view full) --- 552system.cpu1.itb.write_hits 0 # DTB write hits 553system.cpu1.itb.write_misses 0 # DTB write misses 554system.cpu1.itb.write_acv 0 # DTB write access violations 555system.cpu1.itb.write_accesses 0 # DTB write accesses 556system.cpu1.itb.data_hits 0 # DTB hits 557system.cpu1.itb.data_misses 0 # DTB misses 558system.cpu1.itb.data_acv 0 # DTB access violations 559system.cpu1.itb.data_accesses 0 # DTB accesses |
| 707system.cpu1.numCycles 3740249123 # number of cpu cycles simulated | 560system.cpu1.numCycles 3740248881 # number of cpu cycles simulated |
| 708system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 709system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 710system.cpu1.committedInsts 5931958 # Number of instructions committed 711system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed 712system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses 713system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 714system.cpu1.num_func_calls 182742 # number of times a function call or return occured 715system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls 716system.cpu1.num_int_insts 5550578 # number of integer instructions 717system.cpu1.num_fp_insts 28590 # number of float instructions 718system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read 719system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written 720system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 721system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 722system.cpu1.num_mem_refs 1926244 # number of memory refs 723system.cpu1.num_load_insts 1170888 # Number of load instructions 724system.cpu1.num_store_insts 755356 # Number of store instructions | 561system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 562system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 563system.cpu1.committedInsts 5931958 # Number of instructions committed 564system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed 565system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses 566system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses 567system.cpu1.num_func_calls 182742 # number of times a function call or return occured 568system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls 569system.cpu1.num_int_insts 5550578 # number of integer instructions 570system.cpu1.num_fp_insts 28590 # number of float instructions 571system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read 572system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written 573system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read 574system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written 575system.cpu1.num_mem_refs 1926244 # number of memory refs 576system.cpu1.num_load_insts 1170888 # Number of load instructions 577system.cpu1.num_store_insts 755356 # Number of store instructions |
| 725system.cpu1.num_idle_cycles 3734312432.077611 # Number of idle cycles 726system.cpu1.num_busy_cycles 5936690.922389 # Number of busy cycles | 578system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles 579system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles |
| 727system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 728system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 729system.cpu1.kern.inst.arm 0 # number of arm instructions executed 730system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 731system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 732system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 733system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 734system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 735system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 736system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 737system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 738system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 739system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 740system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 741system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl | 580system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 581system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 582system.cpu1.kern.inst.arm 0 # number of arm instructions executed 583system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 584system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 585system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl 586system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl 587system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl 588system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl 589system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl 590system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 591system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 592system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 593system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 594system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl |
| 742system.cpu1.kern.ipl_ticks::0 1859123129500 99.41% 99.41% # number of cycles we spent at this ipl | 595system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl |
| 743system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 744system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 745system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl | 596system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 597system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 598system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl |
| 746system.cpu1.kern.ipl_ticks::total 1870124548000 # number of cycles we spent at this ipl | 599system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl |
| 747system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 748system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 749system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 750system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 751system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl 752system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 753system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 754system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed --- 35 unchanged lines hidden (view full) --- 790system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 791system.cpu1.kern.mode_good::kernel 612 792system.cpu1.kern.mode_good::user 580 793system.cpu1.kern.mode_good::idle 32 794system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 795system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 796system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 797system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches | 600system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 601system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 602system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 603system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl 604system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl 605system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 606system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 607system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed --- 35 unchanged lines hidden (view full) --- 643system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 644system.cpu1.kern.mode_good::kernel 612 645system.cpu1.kern.mode_good::user 580 646system.cpu1.kern.mode_good::idle 32 647system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 648system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 649system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches 650system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches |
| 798system.cpu1.kern.mode_ticks::kernel 1373906500 0.07% 0.07% # number of ticks spent at the given mode | 651system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode |
| 799system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode | 652system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode |
| 800system.cpu1.kern.mode_ticks::idle 1868002681000 99.90% 100.00% # number of ticks spent at the given mode | 653system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode |
| 801system.cpu1.kern.swap_context 471 # number of times the context was actually changed | 654system.cpu1.kern.swap_context 471 # number of times the context was actually changed |
| 802system.cpu1.icache.tags.replacements 103103 # number of replacements | 655system.cpu1.icache.tags.replacements 103091 # number of replacements |
| 803system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use | 656system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use |
| 804system.cpu1.icache.tags.total_refs 5832124 # Total number of references to valid blocks. 805system.cpu1.icache.tags.sampled_refs 103615 # Sample count of references to valid blocks. 806system.cpu1.icache.tags.avg_refs 56.286484 # Average number of references to valid blocks. 807system.cpu1.icache.tags.warmup_cycle 1868933191000 # Cycle when the warmup percentage was hit. | 657system.cpu1.icache.tags.total_refs 5832136 # Total number of references to valid blocks. 658system.cpu1.icache.tags.sampled_refs 103603 # Sample count of references to valid blocks. 659system.cpu1.icache.tags.avg_refs 56.293119 # Average number of references to valid blocks. 660system.cpu1.icache.tags.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. |
| 808system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor 809system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy 810system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy | 661system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor 662system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy 663system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy |
| 811system.cpu1.icache.ReadReq_hits::cpu1.inst 5832124 # number of ReadReq hits 812system.cpu1.icache.ReadReq_hits::total 5832124 # number of ReadReq hits 813system.cpu1.icache.demand_hits::cpu1.inst 5832124 # number of demand (read+write) hits 814system.cpu1.icache.demand_hits::total 5832124 # number of demand (read+write) hits 815system.cpu1.icache.overall_hits::cpu1.inst 5832124 # number of overall hits 816system.cpu1.icache.overall_hits::total 5832124 # number of overall hits 817system.cpu1.icache.ReadReq_misses::cpu1.inst 103642 # number of ReadReq misses 818system.cpu1.icache.ReadReq_misses::total 103642 # number of ReadReq misses 819system.cpu1.icache.demand_misses::cpu1.inst 103642 # number of demand (read+write) misses 820system.cpu1.icache.demand_misses::total 103642 # number of demand (read+write) misses 821system.cpu1.icache.overall_misses::cpu1.inst 103642 # number of overall misses 822system.cpu1.icache.overall_misses::total 103642 # number of overall misses | 664system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits 665system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits 666system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits 667system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits 668system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits 669system.cpu1.icache.overall_hits::total 5832136 # number of overall hits 670system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses 671system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses 672system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses 673system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses 674system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses 675system.cpu1.icache.overall_misses::total 103630 # number of overall misses |
| 823system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) 824system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 825system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses 826system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 827system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses 828system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses | 676system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) 677system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 678system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses 679system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 680system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses 681system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses |
| 829system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017461 # miss rate for ReadReq accesses 830system.cpu1.icache.ReadReq_miss_rate::total 0.017461 # miss rate for ReadReq accesses 831system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017461 # miss rate for demand accesses 832system.cpu1.icache.demand_miss_rate::total 0.017461 # miss rate for demand accesses 833system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017461 # miss rate for overall accesses 834system.cpu1.icache.overall_miss_rate::total 0.017461 # miss rate for overall accesses | 682system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses 683system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses 684system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses 685system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses 686system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses 687system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses |
| 835system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 836system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 838system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 840system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu1.icache.fast_writes 0 # number of fast writes performed 842system.cpu1.icache.cache_copies 0 # number of cache copies performed 843system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 688system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 689system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 690system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 691system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 692system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 693system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 694system.cpu1.icache.fast_writes 0 # number of fast writes performed 695system.cpu1.icache.cache_copies 0 # number of cache copies performed 696system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 844system.cpu1.dcache.tags.replacements 62052 # number of replacements 845system.cpu1.dcache.tags.tagsinuse 421.569557 # Cycle average of tags in use 846system.cpu1.dcache.tags.total_refs 1836045 # Total number of references to valid blocks. 847system.cpu1.dcache.tags.sampled_refs 62390 # Sample count of references to valid blocks. 848system.cpu1.dcache.tags.avg_refs 29.428514 # Average number of references to valid blocks. 849system.cpu1.dcache.tags.warmup_cycle 1851115695500 # Cycle when the warmup percentage was hit. 850system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.569557 # Average occupied blocks per requestor 851system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823378 # Average percentage of cache occupancy 852system.cpu1.dcache.tags.occ_percent::total 0.823378 # Average percentage of cache occupancy 853system.cpu1.dcache.ReadReq_hits::cpu1.data 1109514 # number of ReadReq hits 854system.cpu1.dcache.ReadReq_hits::total 1109514 # number of ReadReq hits 855system.cpu1.dcache.WriteReq_hits::cpu1.data 707455 # number of WriteReq hits 856system.cpu1.dcache.WriteReq_hits::total 707455 # number of WriteReq hits | 697system.cpu1.dcache.tags.replacements 62044 # number of replacements 698system.cpu1.dcache.tags.tagsinuse 421.562730 # Cycle average of tags in use 699system.cpu1.dcache.tags.total_refs 1836054 # Total number of references to valid blocks. 700system.cpu1.dcache.tags.sampled_refs 62382 # Sample count of references to valid blocks. 701system.cpu1.dcache.tags.avg_refs 29.432432 # Average number of references to valid blocks. 702system.cpu1.dcache.tags.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. 703system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor 704system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy 705system.cpu1.dcache.tags.occ_percent::total 0.823365 # Average percentage of cache occupancy 706system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits 707system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits 708system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits 709system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits |
| 857system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits 858system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits 859system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits 860system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits | 710system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits 711system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits 712system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits 713system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits |
| 861system.cpu1.dcache.demand_hits::cpu1.data 1816969 # number of demand (read+write) hits 862system.cpu1.dcache.demand_hits::total 1816969 # number of demand (read+write) hits 863system.cpu1.dcache.overall_hits::cpu1.data 1816969 # number of overall hits 864system.cpu1.dcache.overall_hits::total 1816969 # number of overall hits 865system.cpu1.dcache.ReadReq_misses::cpu1.data 41451 # number of ReadReq misses 866system.cpu1.dcache.ReadReq_misses::total 41451 # number of ReadReq misses 867system.cpu1.dcache.WriteReq_misses::cpu1.data 25850 # number of WriteReq misses 868system.cpu1.dcache.WriteReq_misses::total 25850 # number of WriteReq misses | 714system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits 715system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits 716system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits 717system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits 718system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses 719system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses 720system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses 721system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses |
| 869system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses 870system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses 871system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses 872system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses | 722system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses 723system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses 724system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses 725system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses |
| 873system.cpu1.dcache.demand_misses::cpu1.data 67301 # number of demand (read+write) misses 874system.cpu1.dcache.demand_misses::total 67301 # number of demand (read+write) misses 875system.cpu1.dcache.overall_misses::cpu1.data 67301 # number of overall misses 876system.cpu1.dcache.overall_misses::total 67301 # number of overall misses | 726system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses 727system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses 728system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses 729system.cpu1.dcache.overall_misses::total 67292 # number of overall misses |
| 877system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) 878system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 879system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) 880system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 881system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) 882system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 883system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 884system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 885system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 886system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 887system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 888system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses | 730system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) 731system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) 732system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) 733system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) 734system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) 735system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 736system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 737system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 738system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 739system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 740system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 741system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses |
| 889system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036014 # miss rate for ReadReq accesses 890system.cpu1.dcache.ReadReq_miss_rate::total 0.036014 # miss rate for ReadReq accesses 891system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035251 # miss rate for WriteReq accesses 892system.cpu1.dcache.WriteReq_miss_rate::total 0.035251 # miss rate for WriteReq accesses | 742system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses 743system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses 744system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses 745system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses |
| 893system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses 894system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses 895system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses 896system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses | 746system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses 747system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses 748system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses 749system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses |
| 897system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035717 # miss rate for demand accesses 898system.cpu1.dcache.demand_miss_rate::total 0.035717 # miss rate for demand accesses 899system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035717 # miss rate for overall accesses 900system.cpu1.dcache.overall_miss_rate::total 0.035717 # miss rate for overall accesses | 750system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses 751system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses 752system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses 753system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses |
| 901system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 902system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 903system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 904system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 905system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 906system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 907system.cpu1.dcache.fast_writes 0 # number of fast writes performed 908system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 754system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 755system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 756system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 757system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 758system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 759system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 760system.cpu1.dcache.fast_writes 0 # number of fast writes performed 761system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 909system.cpu1.dcache.writebacks::writebacks 41014 # number of writebacks 910system.cpu1.dcache.writebacks::total 41014 # number of writebacks | 762system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks 763system.cpu1.dcache.writebacks::total 41012 # number of writebacks |
| 911system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 912 913---------- End Simulation Statistics ---------- | 764system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 765 766---------- End Simulation Statistics ---------- |