| stats.txt (9079:9a244ebdc3c9) | stats.txt (9134:275232ad377d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 4061827 # Simulator instruction rate (inst/s) 8host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 120292600618 # Simulator tick rate (ticks/s) 10host_mem_usage 301032 # Number of bytes of host memory used 11host_seconds 15.55 # Real time elapsed on the host | 7host_inst_rate 3051606 # Simulator instruction rate (inst/s) 8host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 90374561583 # Simulator tick rate (ticks/s) 10host_mem_usage 305448 # Number of bytes of host memory used 11host_seconds 20.70 # Real time elapsed on the host |
| 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory 19system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory --- 25 unchanged lines hidden (view full) --- 45system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 1000626 # number of replacements 52system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use | 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory 19system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory --- 25 unchanged lines hidden (view full) --- 45system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) 51system.l2c.replacements 1000626 # number of replacements 52system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use |
| 53system.l2c.total_refs 2464692 # Total number of references to valid blocks. | 53system.l2c.total_refs 2464737 # Total number of references to valid blocks. |
| 54system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. | 54system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. |
| 55system.l2c.avg_refs 2.312597 # Average number of references to valid blocks. | 55system.l2c.avg_refs 2.312639 # Average number of references to valid blocks. |
| 56system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits | 56system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor 60system.l2c.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor 61system.l2c.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor 62system.l2c.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy 65system.l2c.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy 66system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy 67system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy 68system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits |
| 69system.l2c.ReadReq_hits::cpu0.data 763047 # number of ReadReq hits | 69system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits |
| 70system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits | 70system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits |
| 71system.l2c.ReadReq_hits::cpu1.data 36724 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1774753 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 816766 # number of Writeback hits 74system.l2c.Writeback_hits::total 816766 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 169 # number of UpgradeReq hits | 71system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits 72system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits 73system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits 74system.l2c.Writeback_hits::total 816653 # number of Writeback hits 75system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits 76system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 77system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits |
| 78system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits | 78system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits 79system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits 80system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits |
| 81system.l2c.ReadExReq_hits::cpu0.data 166157 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 14260 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 180417 # number of ReadExReq hits | 81system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits 82system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits 83system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits |
| 84system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits | 84system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits |
| 85system.l2c.demand_hits::cpu0.data 929204 # number of demand (read+write) hits | 85system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits |
| 86system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits | 86system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits |
| 87system.l2c.demand_hits::cpu1.data 50984 # number of demand (read+write) hits 88system.l2c.demand_hits::total 1955170 # number of demand (read+write) hits | 87system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits 88system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits |
| 89system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits | 89system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits |
| 90system.l2c.overall_hits::cpu0.data 929204 # number of overall hits | 90system.l2c.overall_hits::cpu0.data 929311 # number of overall hits |
| 91system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits | 91system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits |
| 92system.l2c.overall_hits::cpu1.data 50984 # number of overall hits 93system.l2c.overall_hits::total 1955170 # number of overall hits | 92system.l2c.overall_hits::cpu1.data 51019 # number of overall hits 93system.l2c.overall_hits::total 1955312 # number of overall hits |
| 94system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses --- 9 unchanged lines hidden (view full) --- 111system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 112system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses 114system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 116system.l2c.overall_misses::cpu1.data 10570 # number of overall misses 117system.l2c.overall_misses::total 1066665 # number of overall misses 118system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) | 94system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses 95system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses 96system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses 97system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses 98system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses 99system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses 100system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses 101system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses --- 9 unchanged lines hidden (view full) --- 111system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses 112system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses 113system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses 114system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses 115system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses 116system.l2c.overall_misses::cpu1.data 10570 # number of overall misses 117system.l2c.overall_misses::total 1066665 # number of overall misses 118system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) |
| 119system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses) | 119system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) |
| 120system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) | 120system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) |
| 121system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses) 122system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses) 123system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses) 124system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses) 125system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses) 126system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses) 127system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) | 121system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) 122system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) 123system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) 124system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) 125system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) 126system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) 127system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) |
| 128system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 129system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 130system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) | 128system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) 129system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) 130system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) |
| 131system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses) 132system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses) 133system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses) | 131system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) 132system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) 133system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) |
| 134system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses | 134system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses |
| 135system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses | 135system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses |
| 136system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses | 136system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses |
| 137system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses 138system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses | 137system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses 138system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses |
| 139system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses | 139system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses |
| 140system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses | 140system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses |
| 141system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses | 141system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses |
| 142system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses 143system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses | 142system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses 143system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses |
| 144system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses | 144system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses |
| 145system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses | 145system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses |
| 146system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses | 146system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses |
| 147system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses 148system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses 149system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses 150system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses 151system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses | 147system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses 148system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses 149system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses 150system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses 151system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses |
| 152system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 153system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 154system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses | 152system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses 153system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses 154system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses |
| 155system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses 156system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses 157system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses | 155system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses 156system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses 157system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses |
| 158system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses | 158system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses |
| 159system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses | 159system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses |
| 160system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses | 160system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses |
| 161system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses 162system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses | 161system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses 162system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses |
| 163system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses | 163system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses |
| 164system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses | 164system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses |
| 165system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses | 165system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses |
| 166system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses 167system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses | 166system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses 167system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses |
| 168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 171system.l2c.blocked::no_targets 0 # number of cycles access was blocked 172system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.l2c.fast_writes 0 # number of fast writes performed 175system.l2c.cache_copies 0 # number of cache copies performed --- 267 unchanged lines hidden (view full) --- 443system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 444system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 445system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 446system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 447system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 448system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 449system.cpu0.icache.fast_writes 0 # number of fast writes performed 450system.cpu0.icache.cache_copies 0 # number of cache copies performed | 168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 171system.l2c.blocked::no_targets 0 # number of cycles access was blocked 172system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.l2c.fast_writes 0 # number of fast writes performed 175system.l2c.cache_copies 0 # number of cache copies performed --- 267 unchanged lines hidden (view full) --- 443system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 444system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 445system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 446system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 447system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 448system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 449system.cpu0.icache.fast_writes 0 # number of fast writes performed 450system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 451system.cpu0.icache.writebacks::writebacks 95 # number of writebacks 452system.cpu0.icache.writebacks::total 95 # number of writebacks | |
| 453system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 454system.cpu0.dcache.replacements 1978686 # number of replacements 455system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use 456system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. 457system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. 458system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. 459system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 460system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor --- 221 unchanged lines hidden (view full) --- 682system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 683system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 684system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 685system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 686system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 687system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 688system.cpu1.icache.fast_writes 0 # number of fast writes performed 689system.cpu1.icache.cache_copies 0 # number of cache copies performed | 451system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 452system.cpu0.dcache.replacements 1978686 # number of replacements 453system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use 454system.cpu0.dcache.total_refs 13123753 # Total number of references to valid blocks. 455system.cpu0.dcache.sampled_refs 1979198 # Sample count of references to valid blocks. 456system.cpu0.dcache.avg_refs 6.630844 # Average number of references to valid blocks. 457system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 458system.cpu0.dcache.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor --- 221 unchanged lines hidden (view full) --- 680system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 681system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 682system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 683system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 684system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 685system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 686system.cpu1.icache.fast_writes 0 # number of fast writes performed 687system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 690system.cpu1.icache.writebacks::writebacks 18 # number of writebacks 691system.cpu1.icache.writebacks::total 18 # number of writebacks | |
| 692system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 693system.cpu1.dcache.replacements 62044 # number of replacements 694system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use 695system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. 696system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. 697system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. 698system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. 699system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor --- 63 unchanged lines hidden --- | 688system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 689system.cpu1.dcache.replacements 62044 # number of replacements 690system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use 691system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks. 692system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks. 693system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks. 694system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit. 695system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor --- 63 unchanged lines hidden --- |