| stats.txt (8983:8800b05e1cb3) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1989571 # Simulator instruction rate (inst/s) 8host_op_rate 1989570 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58921958204 # Simulator tick rate (ticks/s) 10host_mem_usage 298304 # Number of bytes of host memory used 11host_seconds 31.74 # Real time elapsed on the host | 7host_inst_rate 2870976 # Simulator instruction rate (inst/s) 8host_op_rate 2870973 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 85025108641 # Simulator tick rate (ticks/s) 10host_mem_usage 298608 # Number of bytes of host memory used 11host_seconds 22.00 # Real time elapsed on the host |
| 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated | 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 72297472 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10452352 # Number of bytes written to this memory 17system.physmem.num_reads 1129648 # Number of read requests responded to by this memory 18system.physmem.num_writes 163318 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 38654814 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 531994 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 5588490 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 44243304 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu0.inst 855168 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.data 67882688 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu1.inst 139840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu1.data 770176 # Number of bytes read from this memory 19system.physmem.bytes_read::total 72297472 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu0.inst 855168 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::cpu1.inst 139840 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 995008 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 10452352 # Number of bytes written to this memory 24system.physmem.bytes_written::total 10452352 # Number of bytes written to this memory 25system.physmem.num_reads::cpu0.inst 13362 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu0.data 1060667 # Number of read requests responded to by this memory 27system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu1.inst 2185 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu1.data 12034 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 1129648 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 163318 # Number of write requests responded to by this memory 32system.physmem.num_writes::total 163318 # Number of write requests responded to by this memory 33system.physmem.bw_read::cpu0.inst 457227 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu0.data 36294391 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu1.inst 74767 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu1.data 411785 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::total 38654814 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::cpu0.inst 457227 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu1.inst 74767 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 531994 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 5588490 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 5588490 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 5588490 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu0.inst 457227 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu0.data 36294391 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu1.inst 74767 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu1.data 411785 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 44243304 # Total bandwidth to/from this memory (bytes/s) |
| 24system.l2c.replacements 1051788 # number of replacements 25system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use 26system.l2c.total_refs 2341203 # Total number of references to valid blocks. 27system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. 28system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor --- 81 unchanged lines hidden (view full) --- 113system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses 114system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses 115system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses 116system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses 117system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses 118system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses 119system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses 120system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses | 51system.l2c.replacements 1051788 # number of replacements 52system.l2c.tagsinuse 34117.721410 # Cycle average of tags in use 53system.l2c.total_refs 2341203 # Total number of references to valid blocks. 54system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. 55system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. 56system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. 57system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor --- 81 unchanged lines hidden (view full) --- 140system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses 141system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses 142system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses 143system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses 144system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses 145system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses 146system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses 147system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses |
| 148system.l2c.ReadReq_miss_rate::total 0.353588 # miss rate for ReadReq accesses |
|
| 121system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses 122system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses | 149system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses 150system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses |
| 151system.l2c.UpgradeReq_miss_rate::total 0.945615 # miss rate for UpgradeReq accesses |
|
| 123system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses 124system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses | 152system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses 153system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses |
| 154system.l2c.SCUpgradeReq_miss_rate::total 0.873684 # miss rate for SCUpgradeReq accesses |
|
| 125system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses 126system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses | 155system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses 156system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses |
| 157system.l2c.ReadExReq_miss_rate::total 0.416240 # miss rate for ReadExReq accesses |
|
| 127system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses 128system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses 129system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses 130system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses | 158system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses 159system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses 160system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses 161system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses |
| 162system.l2c.demand_miss_rate::total 0.359923 # miss rate for demand accesses |
|
| 131system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses 132system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses 133system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses 134system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses | 163system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses 164system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses 165system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses 166system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses |
| 167system.l2c.overall_miss_rate::total 0.359923 # miss rate for overall accesses |
|
| 135system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 136system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 137system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 138system.l2c.blocked::no_targets 0 # number of cycles access was blocked 139system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 140system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 141system.l2c.fast_writes 0 # number of fast writes performed 142system.l2c.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 164system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 165system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 166system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 167system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 168system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 169system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 170system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 171system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses | 168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 171system.l2c.blocked::no_targets 0 # number of cycles access was blocked 172system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.l2c.fast_writes 0 # number of fast writes performed 175system.l2c.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 197system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) 198system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 199system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 200system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses 201system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses 202system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses 203system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses 204system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses |
| 205system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
|
| 172system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses | 206system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses |
| 207system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses |
|
| 173system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses | 208system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses |
| 209system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses |
|
| 174system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses | 210system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses |
| 211system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
|
| 175system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.iocache.blocked::no_targets 0 # number of cycles access was blocked 179system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 181system.iocache.fast_writes 0 # number of fast writes performed 182system.iocache.cache_copies 0 # number of cache copies performed --- 87 unchanged lines hidden (view full) --- 270system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 271system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl 272system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl 273system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 274system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 275system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 276system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 277system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl | 212system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 214system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 215system.iocache.blocked::no_targets 0 # number of cycles access was blocked 216system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 217system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 218system.iocache.fast_writes 0 # number of fast writes performed 219system.iocache.cache_copies 0 # number of cache copies performed --- 87 unchanged lines hidden (view full) --- 307system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl 308system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl 309system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl 310system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl 311system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 312system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 313system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 314system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl |
| 315system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl |
|
| 278system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 279system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 280system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 281system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 282system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 283system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 284system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 285system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed --- 42 unchanged lines hidden (view full) --- 328system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 329system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 330system.cpu0.kern.mode_good::kernel 1157 331system.cpu0.kern.mode_good::user 1158 332system.cpu0.kern.mode_good::idle 0 333system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 334system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 335system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches | 316system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed 317system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed 318system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed 319system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed 320system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed 321system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed 322system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed 323system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed --- 42 unchanged lines hidden (view full) --- 366system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 367system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 368system.cpu0.kern.mode_good::kernel 1157 369system.cpu0.kern.mode_good::user 1158 370system.cpu0.kern.mode_good::idle 0 371system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 372system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 373system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches |
| 336system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches | 374system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches |
| 337system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 338system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 339system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 340system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 341system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 342system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 343system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 344system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA --- 47 unchanged lines hidden (view full) --- 392system.cpu0.icache.overall_misses::total 885000 # number of overall misses 393system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) 394system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 395system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses 396system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 397system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses 398system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 399system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses | 375system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 376system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 377system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 378system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 379system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 380system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 381system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 382system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA --- 47 unchanged lines hidden (view full) --- 430system.cpu0.icache.overall_misses::total 885000 # number of overall misses 431system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) 432system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) 433system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses 434system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses 435system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses 436system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 437system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses |
| 438system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses |
|
| 400system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses | 439system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses |
| 440system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses |
|
| 401system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses | 441system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses |
| 442system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses |
|
| 402system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 403system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 404system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 405system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 406system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 407system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 408system.cpu0.icache.fast_writes 0 # number of fast writes performed 409system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 41 unchanged lines hidden (view full) --- 451system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 452system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 453system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 454system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses 455system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 456system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses 457system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses 458system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses | 443system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 444system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 445system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 446system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 447system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 448system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 449system.cpu0.icache.fast_writes 0 # number of fast writes performed 450system.cpu0.icache.cache_copies 0 # number of cache copies performed --- 41 unchanged lines hidden (view full) --- 492system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) 493system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) 494system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) 495system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses 496system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses 497system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses 498system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses 499system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses |
| 500system.cpu0.dcache.ReadReq_miss_rate::total 0.187444 # miss rate for ReadReq accesses |
|
| 459system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses | 501system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses |
| 502system.cpu0.dcache.WriteReq_miss_rate::total 0.049753 # miss rate for WriteReq accesses |
|
| 460system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses | 503system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses |
| 504system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085817 # miss rate for LoadLockedReq accesses |
|
| 461system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses | 505system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses |
| 506system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003753 # miss rate for StoreCondReq accesses |
|
| 462system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses | 507system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses |
| 508system.cpu0.dcache.demand_miss_rate::total 0.133711 # miss rate for demand accesses |
|
| 463system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses | 509system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses |
| 510system.cpu0.dcache.overall_miss_rate::total 0.133711 # miss rate for overall accesses |
|
| 464system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 465system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 466system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 467system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 468system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 469system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 470system.cpu0.dcache.fast_writes 0 # number of fast writes performed 471system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 71 unchanged lines hidden (view full) --- 543system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 544system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 545system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 546system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl 547system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 548system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 549system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 550system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl | 511system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 512system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 513system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 514system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 515system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 516system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 517system.cpu0.dcache.fast_writes 0 # number of fast writes performed 518system.cpu0.dcache.cache_copies 0 # number of cache copies performed --- 71 unchanged lines hidden (view full) --- 590system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 591system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 592system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 593system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl 594system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl 595system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 596system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 597system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl |
| 598system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl |
|
| 551system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 552system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 553system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 554system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 555system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 556system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 557system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 558system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed --- 29 unchanged lines hidden (view full) --- 588system.cpu1.kern.mode_switch::user 580 # number of protection mode switches 589system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 590system.cpu1.kern.mode_good::kernel 612 591system.cpu1.kern.mode_good::user 580 592system.cpu1.kern.mode_good::idle 32 593system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 594system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 595system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches | 599system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed 600system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed 601system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed 602system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed 603system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed 604system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed 605system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed 606system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed --- 29 unchanged lines hidden (view full) --- 636system.cpu1.kern.mode_switch::user 580 # number of protection mode switches 637system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches 638system.cpu1.kern.mode_good::kernel 612 639system.cpu1.kern.mode_good::user 580 640system.cpu1.kern.mode_good::idle 32 641system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches 642system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 643system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches |
| 596system.cpu1.kern.mode_switch_good::total 1.608089 # fraction of useful protection mode switches | 644system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches |
| 597system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 598system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 599system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 600system.cpu1.kern.swap_context 471 # number of times the context was actually changed 601system.cpu1.icache.replacements 103091 # number of replacements 602system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use 603system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. 604system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. --- 16 unchanged lines hidden (view full) --- 621system.cpu1.icache.overall_misses::total 103630 # number of overall misses 622system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) 623system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 624system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses 625system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 626system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses 627system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 628system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses | 645system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 646system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode 647system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 648system.cpu1.kern.swap_context 471 # number of times the context was actually changed 649system.cpu1.icache.replacements 103091 # number of replacements 650system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use 651system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. 652system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. --- 16 unchanged lines hidden (view full) --- 669system.cpu1.icache.overall_misses::total 103630 # number of overall misses 670system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) 671system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) 672system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses 673system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses 674system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses 675system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 676system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses |
| 677system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses |
|
| 629system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses | 678system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses |
| 679system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses |
|
| 630system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses | 680system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses |
| 681system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses |
|
| 631system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 632system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 633system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 634system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 635system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 636system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 637system.cpu1.icache.fast_writes 0 # number of fast writes performed 638system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 41 unchanged lines hidden (view full) --- 680system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 681system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 682system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 683system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 684system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 685system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 686system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 687system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses | 682system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 683system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 684system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 685system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 686system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 687system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 688system.cpu1.icache.fast_writes 0 # number of fast writes performed 689system.cpu1.icache.cache_copies 0 # number of cache copies performed --- 41 unchanged lines hidden (view full) --- 731system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) 732system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) 733system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) 734system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses 735system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses 736system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses 737system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses 738system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses |
| 739system.cpu1.dcache.ReadReq_miss_rate::total 0.036187 # miss rate for ReadReq accesses |
|
| 688system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses | 740system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses |
| 741system.cpu1.dcache.WriteReq_miss_rate::total 0.035266 # miss rate for WriteReq accesses |
|
| 689system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses | 742system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses |
| 743system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078511 # miss rate for LoadLockedReq accesses |
|
| 690system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses | 744system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses |
| 745system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044784 # miss rate for StoreCondReq accesses |
|
| 691system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses | 746system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses |
| 747system.cpu1.dcache.demand_miss_rate::total 0.035829 # miss rate for demand accesses |
|
| 692system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses | 748system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses |
| 749system.cpu1.dcache.overall_miss_rate::total 0.035829 # miss rate for overall accesses |
|
| 693system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu1.dcache.fast_writes 0 # number of fast writes performed 700system.cpu1.dcache.cache_copies 0 # number of cache copies performed 701system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks 702system.cpu1.dcache.writebacks::total 39996 # number of writebacks 703system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 704 705---------- End Simulation Statistics ---------- | 750system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu1.dcache.fast_writes 0 # number of fast writes performed 757system.cpu1.dcache.cache_copies 0 # number of cache copies performed 758system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks 759system.cpu1.dcache.writebacks::total 39996 # number of writebacks 760system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 761 762---------- End Simulation Statistics ---------- |