| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.870336 # Number of seconds simulated 4sim_ticks 1870335522500 # Number of ticks simulated 5final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 4204751 # Simulator instruction rate (inst/s) 8host_op_rate 4204746 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 124525337361 # Simulator tick rate (ticks/s) 10host_mem_usage 293604 # Number of bytes of host memory used 11host_seconds 15.02 # Real time elapsed on the host | 7host_inst_rate 1989571 # Simulator instruction rate (inst/s) 8host_op_rate 1989570 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58921958204 # Simulator tick rate (ticks/s) 10host_mem_usage 298304 # Number of bytes of host memory used 11host_seconds 31.74 # Real time elapsed on the host |
| 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 72297472 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10452352 # Number of bytes written to this memory 17system.physmem.num_reads 1129648 # Number of read requests responded to by this memory 18system.physmem.num_writes 163318 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 111 unchanged lines hidden (view full) --- 131system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses 132system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses 133system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses 134system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses 135system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 136system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 137system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 138system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 63154034 # Number of instructions simulated 13sim_ops 63154034 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 72297472 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10452352 # Number of bytes written to this memory 17system.physmem.num_reads 1129648 # Number of read requests responded to by this memory 18system.physmem.num_writes 163318 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 111 unchanged lines hidden (view full) --- 131system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses 132system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses 133system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses 134system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses 135system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 136system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 137system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 138system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 139system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 140system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 139system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 140system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 141system.l2c.fast_writes 0 # number of fast writes performed 142system.l2c.cache_copies 0 # number of cache copies performed 143system.l2c.writebacks::writebacks 121798 # number of writebacks 144system.l2c.writebacks::total 121798 # number of writebacks 145system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 146system.iocache.replacements 41695 # number of replacements 147system.iocache.tagsinuse 0.435437 # Cycle average of tags in use 148system.iocache.total_refs 0 # Total number of references to valid blocks. --- 22 unchanged lines hidden (view full) --- 171system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 172system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 173system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 174system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 175system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 141system.l2c.fast_writes 0 # number of fast writes performed 142system.l2c.cache_copies 0 # number of cache copies performed 143system.l2c.writebacks::writebacks 121798 # number of writebacks 144system.l2c.writebacks::total 121798 # number of writebacks 145system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 146system.iocache.replacements 41695 # number of replacements 147system.iocache.tagsinuse 0.435437 # Cycle average of tags in use 148system.iocache.total_refs 0 # Total number of references to valid blocks. --- 22 unchanged lines hidden (view full) --- 171system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 172system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 173system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 174system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 175system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 176system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 177system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 178system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 179system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 180system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 179system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 180system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 181system.iocache.fast_writes 0 # number of fast writes performed 182system.iocache.cache_copies 0 # number of cache copies performed 183system.iocache.writebacks::writebacks 41520 # number of writebacks 184system.iocache.writebacks::total 41520 # number of writebacks 185system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 186system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 187system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 188system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 138 unchanged lines hidden (view full) --- 327system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 328system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 329system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 330system.cpu0.kern.mode_good::kernel 1157 331system.cpu0.kern.mode_good::user 1158 332system.cpu0.kern.mode_good::idle 0 333system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 334system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches | 181system.iocache.fast_writes 0 # number of fast writes performed 182system.iocache.cache_copies 0 # number of cache copies performed 183system.iocache.writebacks::writebacks 41520 # number of writebacks 184system.iocache.writebacks::total 41520 # number of writebacks 185system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 186system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 187system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 188system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 138 unchanged lines hidden (view full) --- 327system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches 328system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches 329system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 330system.cpu0.kern.mode_good::kernel 1157 331system.cpu0.kern.mode_good::user 1158 332system.cpu0.kern.mode_good::idle 0 333system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches 334system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches |
| 335system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches 336system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches | 335system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 336system.cpu0.kern.mode_switch_good::total nan # fraction of useful protection mode switches |
| 337system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 338system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 339system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 340system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 341system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 342system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 343system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 344system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 345system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU | 337system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 338system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode 339system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 340system.cpu0.kern.swap_context 3763 # number of times the context was actually changed 341system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 342system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 343system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 344system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 345system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| 346system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post | 346system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post |
| 347system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 348system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU | 347system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 348system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| 349system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post | 349system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post |
| 350system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 351system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU | 350system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 351system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| 352system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post | 352system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post |
| 353system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 354system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU | 353system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 354system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| 355system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post | 355system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post |
| 356system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 357system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU | 356system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 357system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| 358system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post | 358system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post |
| 359system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 360system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU | 359system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 360system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| 361system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post | 361system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post |
| 362system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 363system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU | 362system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 363system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| 364system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post | 364system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post |
| 365system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 366system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU | 365system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 366system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| 367system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post | 367system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post |
| 368system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR | 368system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| 369system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post | 369system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post |
| 370system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 371system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 372system.cpu0.icache.replacements 884404 # number of replacements 373system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use 374system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. 375system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. 376system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. 377system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. --- 20 unchanged lines hidden (view full) --- 398system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 399system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 400system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses 401system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses 402system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 403system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 404system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 405system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked | 370system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 371system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 372system.cpu0.icache.replacements 884404 # number of replacements 373system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use 374system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks. 375system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. 376system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. 377system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. --- 20 unchanged lines hidden (view full) --- 398system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses 399system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses 400system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses 401system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses 402system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 403system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 404system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 405system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 406system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 407system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 406system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 407system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 408system.cpu0.icache.fast_writes 0 # number of fast writes performed 409system.cpu0.icache.cache_copies 0 # number of cache copies performed 410system.cpu0.icache.writebacks::writebacks 95 # number of writebacks 411system.cpu0.icache.writebacks::total 95 # number of writebacks 412system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 413system.cpu0.dcache.replacements 1978962 # number of replacements 414system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use 415system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. --- 44 unchanged lines hidden (view full) --- 460system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses 461system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses 462system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses 463system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses 464system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 465system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 466system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 467system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked | 408system.cpu0.icache.fast_writes 0 # number of fast writes performed 409system.cpu0.icache.cache_copies 0 # number of cache copies performed 410system.cpu0.icache.writebacks::writebacks 95 # number of writebacks 411system.cpu0.icache.writebacks::total 95 # number of writebacks 412system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 413system.cpu0.dcache.replacements 1978962 # number of replacements 414system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use 415system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks. --- 44 unchanged lines hidden (view full) --- 460system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses 461system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses 462system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses 463system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses 464system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 465system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 466system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 467system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 468system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 469system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 468system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 469system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 470system.cpu0.dcache.fast_writes 0 # number of fast writes performed 471system.cpu0.dcache.cache_copies 0 # number of cache copies performed 472system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks 473system.cpu0.dcache.writebacks::total 771740 # number of writebacks 474system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 475system.cpu1.dtb.fetch_hits 0 # ITB hits 476system.cpu1.dtb.fetch_misses 0 # ITB misses 477system.cpu1.dtb.fetch_acv 0 # ITB acv --- 149 unchanged lines hidden (view full) --- 627system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 628system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses 629system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses 630system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses 631system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 632system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 633system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 634system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked | 470system.cpu0.dcache.fast_writes 0 # number of fast writes performed 471system.cpu0.dcache.cache_copies 0 # number of cache copies performed 472system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks 473system.cpu0.dcache.writebacks::total 771740 # number of writebacks 474system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 475system.cpu1.dtb.fetch_hits 0 # ITB hits 476system.cpu1.dtb.fetch_misses 0 # ITB misses 477system.cpu1.dtb.fetch_acv 0 # ITB acv --- 149 unchanged lines hidden (view full) --- 627system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses 628system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses 629system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses 630system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses 631system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 632system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 633system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 634system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 635system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 636system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 635system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 636system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 637system.cpu1.icache.fast_writes 0 # number of fast writes performed 638system.cpu1.icache.cache_copies 0 # number of cache copies performed 639system.cpu1.icache.writebacks::writebacks 15 # number of writebacks 640system.cpu1.icache.writebacks::total 15 # number of writebacks 641system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 642system.cpu1.dcache.replacements 62338 # number of replacements 643system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use 644system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. --- 44 unchanged lines hidden (view full) --- 689system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses 690system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses 691system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses 692system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses 693system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked | 637system.cpu1.icache.fast_writes 0 # number of fast writes performed 638system.cpu1.icache.cache_copies 0 # number of cache copies performed 639system.cpu1.icache.writebacks::writebacks 15 # number of writebacks 640system.cpu1.icache.writebacks::total 15 # number of writebacks 641system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 642system.cpu1.dcache.replacements 62338 # number of replacements 643system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use 644system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. --- 44 unchanged lines hidden (view full) --- 689system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses 690system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses 691system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses 692system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses 693system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 697system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 698system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 697system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 699system.cpu1.dcache.fast_writes 0 # number of fast writes performed 700system.cpu1.dcache.cache_copies 0 # number of cache copies performed 701system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks 702system.cpu1.dcache.writebacks::total 39996 # number of writebacks 703system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 704 705---------- End Simulation Statistics ---------- | 699system.cpu1.dcache.fast_writes 0 # number of fast writes performed 700system.cpu1.dcache.cache_copies 0 # number of cache copies performed 701system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks 702system.cpu1.dcache.writebacks::total 39996 # number of writebacks 703system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 704 705---------- End Simulation Statistics ---------- |