7,11c7,11
< host_inst_rate 4061827 # Simulator instruction rate (inst/s)
< host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 120292600618 # Simulator tick rate (ticks/s)
< host_mem_usage 301032 # Number of bytes of host memory used
< host_seconds 15.55 # Real time elapsed on the host
---
> host_inst_rate 3051606 # Simulator instruction rate (inst/s)
> host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 90374561583 # Simulator tick rate (ticks/s)
> host_mem_usage 305448 # Number of bytes of host memory used
> host_seconds 20.70 # Real time elapsed on the host
53c53
< system.l2c.total_refs 2464692 # Total number of references to valid blocks.
---
> system.l2c.total_refs 2464737 # Total number of references to valid blocks.
55c55
< system.l2c.avg_refs 2.312597 # Average number of references to valid blocks.
---
> system.l2c.avg_refs 2.312639 # Average number of references to valid blocks.
69c69
< system.l2c.ReadReq_hits::cpu0.data 763047 # number of ReadReq hits
---
> system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits
71,77c71,77
< system.l2c.ReadReq_hits::cpu1.data 36724 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1774753 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 816766 # number of Writeback hits
< system.l2c.Writeback_hits::total 816766 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 169 # number of UpgradeReq hits
---
> system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits
> system.l2c.Writeback_hits::total 816653 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits
81,83c81,83
< system.l2c.ReadExReq_hits::cpu0.data 166157 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 14260 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 180417 # number of ReadExReq hits
---
> system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits
85c85
< system.l2c.demand_hits::cpu0.data 929204 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits
87,88c87,88
< system.l2c.demand_hits::cpu1.data 50984 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1955170 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits
90c90
< system.l2c.overall_hits::cpu0.data 929204 # number of overall hits
---
> system.l2c.overall_hits::cpu0.data 929311 # number of overall hits
92,93c92,93
< system.l2c.overall_hits::cpu1.data 50984 # number of overall hits
< system.l2c.overall_hits::total 1955170 # number of overall hits
---
> system.l2c.overall_hits::cpu1.data 51019 # number of overall hits
> system.l2c.overall_hits::total 1955312 # number of overall hits
119c119
< system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses)
121,127c121,127
< system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses)
131,133c131,133
< system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses)
---
> system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses)
135c135
< system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses
---
> system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses
137,138c137,138
< system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses
---
> system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses
140c140
< system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses
---
> system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses
142,143c142,143
< system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses
---
> system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses
145c145
< system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses
147,151c147,151
< system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses
155,157c155,157
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses
---
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses
159c159
< system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses
161,162c161,162
< system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses
164c164
< system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses
166,167c166,167
< system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses
451,452d450
< system.cpu0.icache.writebacks::writebacks 95 # number of writebacks
< system.cpu0.icache.writebacks::total 95 # number of writebacks
690,691d687
< system.cpu1.icache.writebacks::writebacks 18 # number of writebacks
< system.cpu1.icache.writebacks::total 18 # number of writebacks
< host_inst_rate 4061827 # Simulator instruction rate (inst/s)
< host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 120292600618 # Simulator tick rate (ticks/s)
< host_mem_usage 301032 # Number of bytes of host memory used
< host_seconds 15.55 # Real time elapsed on the host
---
> host_inst_rate 3051606 # Simulator instruction rate (inst/s)
> host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 90374561583 # Simulator tick rate (ticks/s)
> host_mem_usage 305448 # Number of bytes of host memory used
> host_seconds 20.70 # Real time elapsed on the host
53c53
< system.l2c.total_refs 2464692 # Total number of references to valid blocks.
---
> system.l2c.total_refs 2464737 # Total number of references to valid blocks.
55c55
< system.l2c.avg_refs 2.312597 # Average number of references to valid blocks.
---
> system.l2c.avg_refs 2.312639 # Average number of references to valid blocks.
69c69
< system.l2c.ReadReq_hits::cpu0.data 763047 # number of ReadReq hits
---
> system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits
71,77c71,77
< system.l2c.ReadReq_hits::cpu1.data 36724 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1774753 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 816766 # number of Writeback hits
< system.l2c.Writeback_hits::total 816766 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 169 # number of UpgradeReq hits
---
> system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits
> system.l2c.Writeback_hits::total 816653 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits
81,83c81,83
< system.l2c.ReadExReq_hits::cpu0.data 166157 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 14260 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 180417 # number of ReadExReq hits
---
> system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits
85c85
< system.l2c.demand_hits::cpu0.data 929204 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits
87,88c87,88
< system.l2c.demand_hits::cpu1.data 50984 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1955170 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits
90c90
< system.l2c.overall_hits::cpu0.data 929204 # number of overall hits
---
> system.l2c.overall_hits::cpu0.data 929311 # number of overall hits
92,93c92,93
< system.l2c.overall_hits::cpu1.data 50984 # number of overall hits
< system.l2c.overall_hits::total 1955170 # number of overall hits
---
> system.l2c.overall_hits::cpu1.data 51019 # number of overall hits
> system.l2c.overall_hits::total 1955312 # number of overall hits
119c119
< system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses)
121,127c121,127
< system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses)
131,133c131,133
< system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses)
---
> system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses)
135c135
< system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses
---
> system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses
137,138c137,138
< system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses
---
> system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses
140c140
< system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses
---
> system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses
142,143c142,143
< system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses
---
> system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses
145c145
< system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses
147,151c147,151
< system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses
---
> system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses
155,157c155,157
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses
---
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses
159c159
< system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses
161,162c161,162
< system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses
---
> system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses
164c164
< system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses
166,167c166,167
< system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses
---
> system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses
451,452d450
< system.cpu0.icache.writebacks::writebacks 95 # number of writebacks
< system.cpu0.icache.writebacks::total 95 # number of writebacks
690,691d687
< system.cpu1.icache.writebacks::writebacks 18 # number of writebacks
< system.cpu1.icache.writebacks::total 18 # number of writebacks