Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.869358 # Number of seconds simulated

4sim_ticks 1869357999000 # Number of ticks simulated
5final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 1869358054000 # Number of ticks simulated
5final_tick 1869358054000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 2913867 # Simulator instruction rate (inst/s)
8host_op_rate 2913866 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 83800980413 # Simulator tick rate (ticks/s)
10host_mem_usage 338264 # Number of bytes of host memory used
11host_seconds 22.31 # Real time elapsed on the host

7host_inst_rate 2951277 # Simulator instruction rate (inst/s)
8host_op_rate 2951276 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 84876880961 # Simulator tick rate (ticks/s)
10host_mem_usage 336132 # Number of bytes of host memory used
11host_seconds 22.02 # Real time elapsed on the host

12sim_insts 64999904 # Number of instructions simulated
13sim_ops 64999904 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 66535744 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 766400 # Number of bytes read from this memory
21system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
22system.physmem.bytes_read::total 68167488 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory
26system.physmem.bytes_written::writebacks 7837888 # Number of bytes written to this memory
27system.physmem.bytes_written::total 7837888 # Number of bytes written to this memory
28system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 1039621 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.data 11975 # Number of read requests responded to by this memory
32system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
33system.physmem.num_reads::total 1065117 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 122467 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 122467 # Number of write requests responded to by this memory
36system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s)

37system.physmem.bw_read::cpu0.data 35592831 # Total read bandwidth from this memory (bytes/s)

37system.physmem.bw_read::cpu0.data 35592830 # Total read bandwidth from this memory (bytes/s)

38system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu1.data 409980 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s)

41system.physmem.bw_read::total 36465721 # Total read bandwidth from this memory (bytes/s)

41system.physmem.bw_read::total 36465720 # Total read bandwidth from this memory (bytes/s)

42system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_write::writebacks 4192823 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 4192823 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 4192823 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu0.data 35592831 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu0.data 35592830 # Total bandwidth to/from this memory (bytes/s)

50system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu1.data 409980 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)

53system.physmem.bw_total::total 40658545 # Total bandwidth to/from this memory (bytes/s)
54system.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
55system.bridge.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

53system.physmem.bw_total::total 40658544 # Total bandwidth to/from this memory (bytes/s)
54system.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
55system.bridge.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

56system.cpu_clk_domain.clock 500 # Clock period in ticks
57system.cpu0.dtb.fetch_hits 0 # ITB hits
58system.cpu0.dtb.fetch_misses 0 # ITB misses
59system.cpu0.dtb.fetch_acv 0 # ITB acv
60system.cpu0.dtb.fetch_accesses 0 # ITB accesses
61system.cpu0.dtb.read_hits 7758808 # DTB read hits
62system.cpu0.dtb.read_misses 7155 # DTB read misses
63system.cpu0.dtb.read_acv 152 # DTB read access violations
64system.cpu0.dtb.read_accesses 531148 # DTB read accesses
65system.cpu0.dtb.write_hits 4740251 # DTB write hits
66system.cpu0.dtb.write_misses 732 # DTB write misses
67system.cpu0.dtb.write_acv 102 # DTB write access violations
68system.cpu0.dtb.write_accesses 201714 # DTB write accesses
69system.cpu0.dtb.data_hits 12499059 # DTB hits
70system.cpu0.dtb.data_misses 7887 # DTB misses
71system.cpu0.dtb.data_acv 254 # DTB access violations
72system.cpu0.dtb.data_accesses 732862 # DTB accesses
73system.cpu0.itb.fetch_hits 3525726 # ITB hits
74system.cpu0.itb.fetch_misses 3572 # ITB misses
75system.cpu0.itb.fetch_acv 127 # ITB acv
76system.cpu0.itb.fetch_accesses 3529298 # ITB accesses
77system.cpu0.itb.read_hits 0 # DTB read hits
78system.cpu0.itb.read_misses 0 # DTB read misses
79system.cpu0.itb.read_acv 0 # DTB read access violations
80system.cpu0.itb.read_accesses 0 # DTB read accesses
81system.cpu0.itb.write_hits 0 # DTB write hits
82system.cpu0.itb.write_misses 0 # DTB write misses
83system.cpu0.itb.write_acv 0 # DTB write access violations
84system.cpu0.itb.write_accesses 0 # DTB write accesses
85system.cpu0.itb.data_hits 0 # DTB hits
86system.cpu0.itb.data_misses 0 # DTB misses
87system.cpu0.itb.data_acv 0 # DTB access violations
88system.cpu0.itb.data_accesses 0 # DTB accesses
89system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions
90system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state

91system.cpu0.pwrStateClkGateDist::mean 271506704.857374 # Distribution of time spent in the clock gated state
92system.cpu0.pwrStateClkGateDist::stdev 434955692.191892 # Distribution of time spent in the clock gated state

91system.cpu0.pwrStateClkGateDist::mean 271506712.952752 # Distribution of time spent in the clock gated state
92system.cpu0.pwrStateClkGateDist::stdev 434955679.637595 # Distribution of time spent in the clock gated state

93system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state
94system.cpu0.pwrStateClkGateDist::min_value 21000 # Distribution of time spent in the clock gated state
95system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
96system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state
97system.cpu0.pwrStateResidencyTicks::ON 24741446199 # Cumulative time (in ticks) in various power states

98system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616552801 # Cumulative time (in ticks) in various power states
99system.cpu0.numCycles 3738722793 # number of cpu cycles simulated

98system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616607801 # Cumulative time (in ticks) in various power states
99system.cpu0.numCycles 3738722903 # number of cpu cycles simulated

100system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
101system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
102system.cpu0.kern.inst.arm 0 # number of arm instructions executed
103system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
104system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed
105system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl
106system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl
107system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl
108system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl
109system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl
110system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl
111system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl
112system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl
113system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl
114system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl
115system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl
116system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl

117system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl

117system.cpu0.kern.ipl_ticks::0 1853222787000 99.14% 99.14% # number of cycles we spent at this ipl

118system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl
119system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl
120system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl
121system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl

122system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl

122system.cpu0.kern.ipl_ticks::total 1869357846500 # number of cycles we spent at this ipl

123system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl
124system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
125system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
126system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
127system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl
128system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl
129system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
130system.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed
131system.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed
132system.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed
133system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed
134system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed
135system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed
136system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed
137system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed
138system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed
139system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed
140system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed
141system.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed
142system.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed
143system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed
144system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed
145system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed
146system.cpu0.kern.callpal::total 135929 # number of callpals executed
147system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches
148system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches
149system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
150system.cpu0.kern.mode_good::kernel 1172
151system.cpu0.kern.mode_good::user 1173
152system.cpu0.kern.mode_good::idle 0
153system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches
154system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
155system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
156system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches

157system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode

157system.cpu0.kern.mode_ticks::kernel 1868349218500 99.95% 99.95% # number of ticks spent at the given mode

158system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode
159system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
160system.cpu0.kern.swap_context 2744 # number of times the context was actually changed
161system.cpu0.committedInsts 49477745 # Number of instructions committed
162system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed
163system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses
164system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses
165system.cpu0.num_func_calls 1124633 # number of times a function call or return occured
166system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls
167system.cpu0.num_int_insts 46201705 # number of integer instructions
168system.cpu0.num_fp_insts 197598 # number of float instructions
169system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read
170system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written
171system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read
172system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written
173system.cpu0.num_mem_refs 12536107 # number of memory refs
174system.cpu0.num_load_insts 7783754 # Number of load instructions
175system.cpu0.num_store_insts 4752353 # Number of store instructions

176system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles
177system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles

176system.cpu0.num_idle_cycles 3689239920.666412 # Number of idle cycles
177system.cpu0.num_busy_cycles 49482982.333588 # Number of busy cycles

178system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
179system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
180system.cpu0.Branches 7530826 # Number of branches fetched
181system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction
182system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction
183system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction
184system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction
185system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction
186system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction
187system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction
188system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction
189system.cpu0.op_class::FloatMultAcc 0 0.00% 72.96% # Class of executed instruction
190system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction
191system.cpu0.op_class::FloatMisc 0 0.00% 72.96% # Class of executed instruction
192system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction
193system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction
194system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction
195system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction
196system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction
197system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction
198system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction
199system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction
200system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction
201system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction
202system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction
203system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction
204system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction
205system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction
206system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction
207system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction
208system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction
209system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction
210system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction
211system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction
212system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction
213system.cpu0.op_class::MemRead 7859946 15.88% 88.85% # Class of executed instruction
214system.cpu0.op_class::MemWrite 4676411 9.45% 98.30% # Class of executed instruction
215system.cpu0.op_class::FloatMemRead 85644 0.17% 98.47% # Class of executed instruction
216system.cpu0.op_class::FloatMemWrite 81881 0.17% 98.63% # Class of executed instruction
217system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction
218system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
219system.cpu0.op_class::total 49485886 # Class of executed instruction

220system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

220system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

221system.cpu0.dcache.tags.replacements 1781367 # number of replacements

222system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use

222system.cpu0.dcache.tags.tagsinuse 506.187332 # Cycle average of tags in use

223system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks.
224system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks.
225system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks.
226system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.

227system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor

227system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187332 # Average occupied blocks per requestor

228system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy
229system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy
230system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
231system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id
232system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
233system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
234system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
235system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses
236system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses

237system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

237system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

238system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits
239system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits
240system.cpu0.dcache.WriteReq_hits::cpu0.data 4360096 # number of WriteReq hits
241system.cpu0.dcache.WriteReq_hits::total 4360096 # number of WriteReq hits
242system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits
243system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits
244system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132871 # number of StoreCondReq hits
245system.cpu0.dcache.StoreCondReq_hits::total 132871 # number of StoreCondReq hits
246system.cpu0.dcache.demand_hits::cpu0.data 10428981 # number of demand (read+write) hits
247system.cpu0.dcache.demand_hits::total 10428981 # number of demand (read+write) hits
248system.cpu0.dcache.overall_hits::cpu0.data 10428981 # number of overall hits
249system.cpu0.dcache.overall_hits::total 10428981 # number of overall hits
250system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses
251system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses
252system.cpu0.dcache.WriteReq_misses::cpu0.data 236527 # number of WriteReq misses
253system.cpu0.dcache.WriteReq_misses::total 236527 # number of WriteReq misses
254system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses
255system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses
256system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6899 # number of StoreCondReq misses
257system.cpu0.dcache.StoreCondReq_misses::total 6899 # number of StoreCondReq misses
258system.cpu0.dcache.demand_misses::cpu0.data 1796592 # number of demand (read+write) misses
259system.cpu0.dcache.demand_misses::total 1796592 # number of demand (read+write) misses
260system.cpu0.dcache.overall_misses::cpu0.data 1796592 # number of overall misses
261system.cpu0.dcache.overall_misses::total 1796592 # number of overall misses
262system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses)
263system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses)
264system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses)
265system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses)
266system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses)
267system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses)
268system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses)
269system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses)
270system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses
271system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses
272system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses
273system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses
274system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses
275system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses
276system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051457 # miss rate for WriteReq accesses
277system.cpu0.dcache.WriteReq_miss_rate::total 0.051457 # miss rate for WriteReq accesses
278system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses
279system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses
280system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049360 # miss rate for StoreCondReq accesses
281system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049360 # miss rate for StoreCondReq accesses
282system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses
283system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses
284system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses
285system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses
286system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
287system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
288system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
289system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
290system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
291system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
292system.cpu0.dcache.writebacks::writebacks 633925 # number of writebacks
293system.cpu0.dcache.writebacks::total 633925 # number of writebacks

294system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

294system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

295system.cpu0.icache.tags.replacements 618292 # number of replacements
296system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use
297system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks.
298system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks.
299system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks.
300system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit.
301system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor
302system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy
303system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy
304system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
305system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
306system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
307system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id
308system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
309system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses
310system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses

311system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

311system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

312system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits
313system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits
314system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits
315system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits
316system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits
317system.cpu0.icache.overall_hits::total 48866947 # number of overall hits
318system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses
319system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses
320system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses
321system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses
322system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses
323system.cpu0.icache.overall_misses::total 618939 # number of overall misses
324system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses)
325system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses)
326system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses
327system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses
328system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses
329system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses
330system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses
331system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses
332system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses
333system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses
334system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses
335system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses
336system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
337system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
338system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
339system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
340system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
341system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
342system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks
343system.cpu0.icache.writebacks::total 618292 # number of writebacks
344system.cpu1.dtb.fetch_hits 0 # ITB hits
345system.cpu1.dtb.fetch_misses 0 # ITB misses
346system.cpu1.dtb.fetch_acv 0 # ITB acv
347system.cpu1.dtb.fetch_accesses 0 # ITB accesses
348system.cpu1.dtb.read_hits 2831559 # DTB read hits
349system.cpu1.dtb.read_misses 3191 # DTB read misses
350system.cpu1.dtb.read_acv 58 # DTB read access violations
351system.cpu1.dtb.read_accesses 198160 # DTB read accesses
352system.cpu1.dtb.write_hits 2101673 # DTB write hits
353system.cpu1.dtb.write_misses 412 # DTB write misses
354system.cpu1.dtb.write_acv 55 # DTB write access violations
355system.cpu1.dtb.write_accesses 90619 # DTB write accesses
356system.cpu1.dtb.data_hits 4933232 # DTB hits
357system.cpu1.dtb.data_misses 3603 # DTB misses
358system.cpu1.dtb.data_acv 113 # DTB access violations
359system.cpu1.dtb.data_accesses 288779 # DTB accesses
360system.cpu1.itb.fetch_hits 1950883 # ITB hits
361system.cpu1.itb.fetch_misses 1451 # ITB misses
362system.cpu1.itb.fetch_acv 57 # ITB acv
363system.cpu1.itb.fetch_accesses 1952334 # ITB accesses
364system.cpu1.itb.read_hits 0 # DTB read hits
365system.cpu1.itb.read_misses 0 # DTB read misses
366system.cpu1.itb.read_acv 0 # DTB read access violations
367system.cpu1.itb.read_accesses 0 # DTB read accesses
368system.cpu1.itb.write_hits 0 # DTB write hits
369system.cpu1.itb.write_misses 0 # DTB write misses
370system.cpu1.itb.write_acv 0 # DTB write access violations
371system.cpu1.itb.write_accesses 0 # DTB write accesses
372system.cpu1.itb.data_hits 0 # DTB hits
373system.cpu1.itb.data_misses 0 # DTB misses
374system.cpu1.itb.data_acv 0 # DTB access violations
375system.cpu1.itb.data_accesses 0 # DTB accesses
376system.cpu1.numPwrStateTransitions 5407 # Number of power state transitions
377system.cpu1.pwrStateClkGateDist::samples 2704 # Distribution of time spent in the clock gated state

378system.cpu1.pwrStateClkGateDist::mean 688459933.247041 # Distribution of time spent in the clock gated state
379system.cpu1.pwrStateClkGateDist::stdev 437290592.854298 # Distribution of time spent in the clock gated state

378system.cpu1.pwrStateClkGateDist::mean 688459953.587278 # Distribution of time spent in the clock gated state
379system.cpu1.pwrStateClkGateDist::stdev 437290552.872181 # Distribution of time spent in the clock gated state

380system.cpu1.pwrStateClkGateDist::1000-5e+10 2704 100.00% 100.00% # Distribution of time spent in the clock gated state
381system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state
382system.cpu1.pwrStateClkGateDist::max_value 976035500 # Distribution of time spent in the clock gated state
383system.cpu1.pwrStateClkGateDist::total 2704 # Distribution of time spent in the clock gated state
384system.cpu1.pwrStateResidencyTicks::ON 7762339500 # Cumulative time (in ticks) in various power states

385system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595659500 # Cumulative time (in ticks) in various power states
386system.cpu1.numCycles 3738296609 # number of cpu cycles simulated

385system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595714500 # Cumulative time (in ticks) in various power states
386system.cpu1.numCycles 3738296719 # number of cpu cycles simulated

387system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
388system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
389system.cpu1.kern.inst.arm 0 # number of arm instructions executed
390system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed
391system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed
392system.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl
393system.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl
394system.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl
395system.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl
396system.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl
397system.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl
398system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl
399system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl
400system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl
401system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl

402system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl

402system.cpu1.kern.ipl_ticks::0 1856123556500 99.30% 99.30% # number of cycles we spent at this ipl

403system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl
404system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl
405system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl

406system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl

406system.cpu1.kern.ipl_ticks::total 1869146994500 # number of cycles we spent at this ipl

407system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl
408system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
409system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
410system.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl
411system.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl
412system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
413system.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed
414system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
415system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed
416system.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed
417system.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed
418system.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed
419system.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed
420system.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed
421system.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed
422system.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed
423system.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed
424system.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed
425system.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed
426system.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed
427system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed
428system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
429system.cpu1.kern.callpal::total 84542 # number of callpals executed
430system.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches
431system.cpu1.kern.mode_switch::user 564 # number of protection mode switches
432system.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches
433system.cpu1.kern.mode_good::kernel 1106
434system.cpu1.kern.mode_good::user 564
435system.cpu1.kern.mode_good::idle 542
436system.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches
437system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
438system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches
439system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches
440system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode
441system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode

442system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode

442system.cpu1.kern.mode_ticks::idle 1862102446500 99.66% 100.00% # number of ticks spent at the given mode

443system.cpu1.kern.swap_context 2507 # number of times the context was actually changed
444system.cpu1.committedInsts 15522159 # Number of instructions committed
445system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed
446system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses
447system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses
448system.cpu1.num_func_calls 493140 # number of times a function call or return occured
449system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls
450system.cpu1.num_int_insts 14295544 # number of integer instructions
451system.cpu1.num_fp_insts 198941 # number of float instructions
452system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read
453system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written
454system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read
455system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written
456system.cpu1.num_mem_refs 4961786 # number of memory refs
457system.cpu1.num_load_insts 2849090 # Number of load instructions
458system.cpu1.num_store_insts 2112696 # Number of store instructions

459system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles
460system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles

459system.cpu1.num_idle_cycles 3722773781.474732 # Number of idle cycles
460system.cpu1.num_busy_cycles 15522937.525268 # Number of busy cycles

461system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
462system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
463system.cpu1.Branches 2214163 # Number of branches fetched
464system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction
465system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction
466system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction
467system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction
468system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction
469system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
470system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
471system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
472system.cpu1.op_class::FloatMultAcc 0 0.00% 64.73% # Class of executed instruction
473system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction
474system.cpu1.op_class::FloatMisc 0 0.00% 64.74% # Class of executed instruction
475system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction
476system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction
477system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction
478system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction
479system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction
480system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction
481system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction
482system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction
483system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction
484system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction
485system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction
486system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction
487system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction
488system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
489system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
490system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
491system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
492system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
493system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
494system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
495system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
496system.cpu1.op_class::MemRead 2842559 18.31% 83.05% # Class of executed instruction
497system.cpu1.op_class::MemWrite 2023248 13.03% 96.08% # Class of executed instruction
498system.cpu1.op_class::FloatMemRead 94457 0.61% 96.69% # Class of executed instruction
499system.cpu1.op_class::FloatMemWrite 90649 0.58% 97.27% # Class of executed instruction
500system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction
501system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
502system.cpu1.op_class::total 15525875 # Class of executed instruction

503system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

503system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

504system.cpu1.dcache.tags.replacements 201757 # number of replacements

505system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use

505system.cpu1.dcache.tags.tagsinuse 497.601957 # Cycle average of tags in use

506system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks.
507system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks.
508system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks.
509system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit.

510system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor

510system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601957 # Average occupied blocks per requestor

511system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy
512system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy
513system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
514system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
515system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
516system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id
517system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses
518system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses

519system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

519system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

520system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits
521system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits
522system.cpu1.dcache.WriteReq_hits::cpu1.data 1954647 # number of WriteReq hits
523system.cpu1.dcache.WriteReq_hits::total 1954647 # number of WriteReq hits
524system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits
525system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits
526system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64211 # number of StoreCondReq hits
527system.cpu1.dcache.StoreCondReq_hits::total 64211 # number of StoreCondReq hits
528system.cpu1.dcache.demand_hits::cpu1.data 4587335 # number of demand (read+write) hits
529system.cpu1.dcache.demand_hits::total 4587335 # number of demand (read+write) hits
530system.cpu1.dcache.overall_hits::cpu1.data 4587335 # number of overall hits
531system.cpu1.dcache.overall_hits::total 4587335 # number of overall hits
532system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses
533system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses
534system.cpu1.dcache.WriteReq_misses::cpu1.data 78313 # number of WriteReq misses
535system.cpu1.dcache.WriteReq_misses::total 78313 # number of WriteReq misses
536system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses
537system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses
538system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7304 # number of StoreCondReq misses
539system.cpu1.dcache.StoreCondReq_misses::total 7304 # number of StoreCondReq misses
540system.cpu1.dcache.demand_misses::cpu1.data 219198 # number of demand (read+write) misses
541system.cpu1.dcache.demand_misses::total 219198 # number of demand (read+write) misses
542system.cpu1.dcache.overall_misses::cpu1.data 219198 # number of overall misses
543system.cpu1.dcache.overall_misses::total 219198 # number of overall misses
544system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses)
545system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses)
546system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses)
547system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses)
548system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses)
549system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses)
550system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses)
551system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses)
552system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses
553system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses
554system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses
555system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses
556system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses
557system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses
558system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038522 # miss rate for WriteReq accesses
559system.cpu1.dcache.WriteReq_miss_rate::total 0.038522 # miss rate for WriteReq accesses
560system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses
561system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses
562system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102132 # miss rate for StoreCondReq accesses
563system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102132 # miss rate for StoreCondReq accesses
564system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045604 # miss rate for demand accesses
565system.cpu1.dcache.demand_miss_rate::total 0.045604 # miss rate for demand accesses
566system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045604 # miss rate for overall accesses
567system.cpu1.dcache.overall_miss_rate::total 0.045604 # miss rate for overall accesses
568system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
569system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
570system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
571system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
572system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
573system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
574system.cpu1.dcache.writebacks::writebacks 144832 # number of writebacks
575system.cpu1.dcache.writebacks::total 144832 # number of writebacks

576system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

576system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

577system.cpu1.icache.tags.replacements 380647 # number of replacements

578system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use

578system.cpu1.icache.tags.tagsinuse 453.133721 # Cycle average of tags in use

579system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks.
580system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks.
581system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks.

582system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit.
583system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor

582system.cpu1.icache.tags.warmup_cycle 1859777228500 # Cycle when the warmup percentage was hit.
583system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133721 # Average occupied blocks per requestor

584system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy
585system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy
586system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
587system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id
588system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
589system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
590system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses
591system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses

592system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

592system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

593system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits
594system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits
595system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits
596system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits
597system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits
598system.cpu1.icache.overall_hits::total 15144687 # number of overall hits
599system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses
600system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses
601system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses
602system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses
603system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses
604system.cpu1.icache.overall_misses::total 381188 # number of overall misses
605system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses)
606system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses)
607system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses
608system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses
609system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses
610system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses
611system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses
612system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses
613system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses
614system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses
615system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses
616system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses
617system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
618system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
619system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
620system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
621system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
622system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
623system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks
624system.cpu1.icache.writebacks::total 380647 # number of writebacks
625system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
626system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
627system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
628system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
629system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
630system.disk0.dma_write_txs 395 # Number of DMA write transactions.
631system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
632system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
633system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
634system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
635system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
636system.disk2.dma_write_txs 1 # Number of DMA write transactions.

637system.iobus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

637system.iobus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

638system.iobus.trans_dist::ReadReq 7628 # Transaction distribution
639system.iobus.trans_dist::ReadResp 7628 # Transaction distribution
640system.iobus.trans_dist::WriteReq 56140 # Transaction distribution
641system.iobus.trans_dist::WriteResp 56140 # Transaction distribution
642system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes)
643system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes)
644system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
645system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
646system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
647system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes)
648system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
649system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
650system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
651system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes)
652system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes)
653system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes)
654system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes)
655system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes)
656system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes)
657system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
658system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
659system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
660system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes)
661system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
662system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
663system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
664system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes)
665system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes)
666system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes)
667system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes)

668system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

668system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

669system.iocache.tags.replacements 41699 # number of replacements
670system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use
671system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
672system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
673system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
674system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit.
675system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor
676system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy
677system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy
678system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
679system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
680system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
681system.iocache.tags.tag_accesses 375579 # Number of tag accesses
682system.iocache.tags.data_accesses 375579 # Number of data accesses

683system.iocache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

683system.iocache.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

684system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses
685system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
686system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
687system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
688system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses
689system.iocache.demand_misses::total 41731 # number of demand (read+write) misses
690system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses
691system.iocache.overall_misses::total 41731 # number of overall misses
692system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses)
693system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
694system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
695system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
696system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses
697system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses
698system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses
699system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses
700system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
701system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
702system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
703system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
704system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
705system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
706system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
707system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
708system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
709system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
710system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
711system.iocache.blocked::no_targets 0 # number of cycles access was blocked
712system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
713system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
714system.iocache.writebacks::writebacks 41520 # number of writebacks
715system.iocache.writebacks::total 41520 # number of writebacks

716system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

716system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

717system.l2c.tags.replacements 999962 # number of replacements

718system.l2c.tags.tagsinuse 65520.418446 # Cycle average of tags in use
719system.l2c.tags.total_refs 4560628 # Total number of references to valid blocks.

718system.l2c.tags.tagsinuse 65520.418445 # Cycle average of tags in use
719system.l2c.tags.total_refs 4560627 # Total number of references to valid blocks.

720system.l2c.tags.sampled_refs 1065470 # Sample count of references to valid blocks.

721system.l2c.tags.avg_refs 4.280391 # Average number of references to valid blocks.

721system.l2c.tags.avg_refs 4.280390 # Average number of references to valid blocks.

722system.l2c.tags.warmup_cycle 618103500 # Cycle when the warmup percentage was hit.

723system.l2c.tags.occ_blocks::writebacks 304.654016 # Average occupied blocks per requestor
724system.l2c.tags.occ_blocks::cpu0.inst 4865.757369 # Average occupied blocks per requestor
725system.l2c.tags.occ_blocks::cpu0.data 58473.870947 # Average occupied blocks per requestor
726system.l2c.tags.occ_blocks::cpu1.inst 175.171504 # Average occupied blocks per requestor
727system.l2c.tags.occ_blocks::cpu1.data 1700.964609 # Average occupied blocks per requestor

723system.l2c.tags.occ_blocks::writebacks 304.654012 # Average occupied blocks per requestor
724system.l2c.tags.occ_blocks::cpu0.inst 4865.757484 # Average occupied blocks per requestor
725system.l2c.tags.occ_blocks::cpu0.data 58473.870624 # Average occupied blocks per requestor
726system.l2c.tags.occ_blocks::cpu1.inst 175.171542 # Average occupied blocks per requestor
727system.l2c.tags.occ_blocks::cpu1.data 1700.964784 # Average occupied blocks per requestor

728system.l2c.tags.occ_percent::writebacks 0.004649 # Average percentage of cache occupancy
729system.l2c.tags.occ_percent::cpu0.inst 0.074246 # Average percentage of cache occupancy
730system.l2c.tags.occ_percent::cpu0.data 0.892240 # Average percentage of cache occupancy
731system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy
732system.l2c.tags.occ_percent::cpu1.data 0.025955 # Average percentage of cache occupancy
733system.l2c.tags.occ_percent::total 0.999762 # Average percentage of cache occupancy
734system.l2c.tags.occ_task_id_blocks::1024 65508 # Occupied blocks per task id
735system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id
736system.l2c.tags.age_task_id_blocks_1024::1 2411 # Occupied blocks per task id
737system.l2c.tags.age_task_id_blocks_1024::2 2462 # Occupied blocks per task id
738system.l2c.tags.age_task_id_blocks_1024::3 9328 # Occupied blocks per task id
739system.l2c.tags.age_task_id_blocks_1024::4 50633 # Occupied blocks per task id
740system.l2c.tags.occ_task_id_percent::1024 0.999573 # Percentage of cache occupancy per task id

741system.l2c.tags.tag_accesses 46077158 # Number of tag accesses
742system.l2c.tags.data_accesses 46077158 # Number of data accesses
743system.l2c.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

741system.l2c.tags.tag_accesses 46077150 # Number of tag accesses
742system.l2c.tags.data_accesses 46077150 # Number of data accesses
743system.l2c.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

744system.l2c.WritebackDirty_hits::writebacks 778757 # number of WritebackDirty hits
745system.l2c.WritebackDirty_hits::total 778757 # number of WritebackDirty hits

746system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits
747system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits

746system.l2c.WritebackClean_hits::writebacks 721479 # number of WritebackClean hits
747system.l2c.WritebackClean_hits::total 721479 # number of WritebackClean hits

748system.l2c.UpgradeReq_hits::cpu0.data 3102 # number of UpgradeReq hits
749system.l2c.UpgradeReq_hits::cpu1.data 2744 # number of UpgradeReq hits
750system.l2c.UpgradeReq_hits::total 5846 # number of UpgradeReq hits
751system.l2c.SCUpgradeReq_hits::cpu0.data 1187 # number of SCUpgradeReq hits
752system.l2c.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits
753system.l2c.SCUpgradeReq_hits::total 2308 # number of SCUpgradeReq hits
754system.l2c.ReadExReq_hits::cpu0.data 111978 # number of ReadExReq hits
755system.l2c.ReadExReq_hits::cpu1.data 56627 # number of ReadExReq hits
756system.l2c.ReadExReq_hits::total 168605 # number of ReadExReq hits
757system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits
758system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits
759system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits
760system.l2c.ReadSharedReq_hits::cpu0.data 626251 # number of ReadSharedReq hits
761system.l2c.ReadSharedReq_hits::cpu1.data 128790 # number of ReadSharedReq hits
762system.l2c.ReadSharedReq_hits::total 755041 # number of ReadSharedReq hits
763system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits
764system.l2c.demand_hits::cpu0.data 738229 # number of demand (read+write) hits
765system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits
766system.l2c.demand_hits::cpu1.data 185417 # number of demand (read+write) hits
767system.l2c.demand_hits::total 1910246 # number of demand (read+write) hits
768system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits
769system.l2c.overall_hits::cpu0.data 738229 # number of overall hits
770system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits
771system.l2c.overall_hits::cpu1.data 185417 # number of overall hits
772system.l2c.overall_hits::total 1910246 # number of overall hits
773system.l2c.UpgradeReq_misses::cpu0.data 4 # number of UpgradeReq misses
774system.l2c.UpgradeReq_misses::cpu1.data 2 # number of UpgradeReq misses
775system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses
776system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
777system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
778system.l2c.ReadExReq_misses::cpu0.data 113307 # number of ReadExReq misses
779system.l2c.ReadExReq_misses::cpu1.data 11044 # number of ReadExReq misses
780system.l2c.ReadExReq_misses::total 124351 # number of ReadExReq misses
781system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses
782system.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses
783system.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses
784system.l2c.ReadSharedReq_misses::cpu0.data 926616 # number of ReadSharedReq misses
785system.l2c.ReadSharedReq_misses::cpu1.data 1036 # number of ReadSharedReq misses
786system.l2c.ReadSharedReq_misses::total 927652 # number of ReadSharedReq misses
787system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses
788system.l2c.demand_misses::cpu0.data 1039923 # number of demand (read+write) misses
789system.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses
790system.l2c.demand_misses::cpu1.data 12080 # number of demand (read+write) misses
791system.l2c.demand_misses::total 1065509 # number of demand (read+write) misses
792system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses
793system.l2c.overall_misses::cpu0.data 1039923 # number of overall misses
794system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses
795system.l2c.overall_misses::cpu1.data 12080 # number of overall misses
796system.l2c.overall_misses::total 1065509 # number of overall misses
797system.l2c.WritebackDirty_accesses::writebacks 778757 # number of WritebackDirty accesses(hits+misses)
798system.l2c.WritebackDirty_accesses::total 778757 # number of WritebackDirty accesses(hits+misses)

799system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses)
800system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses)

799system.l2c.WritebackClean_accesses::writebacks 721479 # number of WritebackClean accesses(hits+misses)
800system.l2c.WritebackClean_accesses::total 721479 # number of WritebackClean accesses(hits+misses)

801system.l2c.UpgradeReq_accesses::cpu0.data 3106 # number of UpgradeReq accesses(hits+misses)
802system.l2c.UpgradeReq_accesses::cpu1.data 2746 # number of UpgradeReq accesses(hits+misses)
803system.l2c.UpgradeReq_accesses::total 5852 # number of UpgradeReq accesses(hits+misses)
804system.l2c.SCUpgradeReq_accesses::cpu0.data 1187 # number of SCUpgradeReq accesses(hits+misses)
805system.l2c.SCUpgradeReq_accesses::cpu1.data 1122 # number of SCUpgradeReq accesses(hits+misses)
806system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses)
807system.l2c.ReadExReq_accesses::cpu0.data 225285 # number of ReadExReq accesses(hits+misses)
808system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses)
809system.l2c.ReadExReq_accesses::total 292956 # number of ReadExReq accesses(hits+misses)
810system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses)
811system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses)
812system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses)
813system.l2c.ReadSharedReq_accesses::cpu0.data 1552867 # number of ReadSharedReq accesses(hits+misses)
814system.l2c.ReadSharedReq_accesses::cpu1.data 129826 # number of ReadSharedReq accesses(hits+misses)
815system.l2c.ReadSharedReq_accesses::total 1682693 # number of ReadSharedReq accesses(hits+misses)
816system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses
817system.l2c.demand_accesses::cpu0.data 1778152 # number of demand (read+write) accesses
818system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses
819system.l2c.demand_accesses::cpu1.data 197497 # number of demand (read+write) accesses
820system.l2c.demand_accesses::total 2975755 # number of demand (read+write) accesses
821system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses
822system.l2c.overall_accesses::cpu0.data 1778152 # number of overall (read+write) accesses
823system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses
824system.l2c.overall_accesses::cpu1.data 197497 # number of overall (read+write) accesses
825system.l2c.overall_accesses::total 2975755 # number of overall (read+write) accesses
826system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001288 # miss rate for UpgradeReq accesses
827system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000728 # miss rate for UpgradeReq accesses
828system.l2c.UpgradeReq_miss_rate::total 0.001025 # miss rate for UpgradeReq accesses
829system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.000891 # miss rate for SCUpgradeReq accesses
830system.l2c.SCUpgradeReq_miss_rate::total 0.000433 # miss rate for SCUpgradeReq accesses
831system.l2c.ReadExReq_miss_rate::cpu0.data 0.502950 # miss rate for ReadExReq accesses
832system.l2c.ReadExReq_miss_rate::cpu1.data 0.163201 # miss rate for ReadExReq accesses
833system.l2c.ReadExReq_miss_rate::total 0.424470 # miss rate for ReadExReq accesses
834system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses
835system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses
836system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses
837system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596713 # miss rate for ReadSharedReq accesses
838system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007980 # miss rate for ReadSharedReq accesses
839system.l2c.ReadSharedReq_miss_rate::total 0.551290 # miss rate for ReadSharedReq accesses
840system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses
841system.l2c.demand_miss_rate::cpu0.data 0.584834 # miss rate for demand accesses
842system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses
843system.l2c.demand_miss_rate::cpu1.data 0.061165 # miss rate for demand accesses
844system.l2c.demand_miss_rate::total 0.358063 # miss rate for demand accesses
845system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses
846system.l2c.overall_miss_rate::cpu0.data 0.584834 # miss rate for overall accesses
847system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses
848system.l2c.overall_miss_rate::cpu1.data 0.061165 # miss rate for overall accesses
849system.l2c.overall_miss_rate::total 0.358063 # miss rate for overall accesses
850system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
851system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
852system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
853system.l2c.blocked::no_targets 0 # number of cycles access was blocked
854system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
855system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
856system.l2c.writebacks::writebacks 80947 # number of writebacks
857system.l2c.writebacks::total 80947 # number of writebacks
858system.membus.snoop_filter.tot_requests 2174394 # Total number of requests made to the snoop filter.

859system.membus.snoop_filter.hit_single_requests 1068384 # Number of requests hitting in the snoop filter with a single holder of the requested data.
860system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

859system.membus.snoop_filter.hit_single_requests 1068314 # Number of requests hitting in the snoop filter with a single holder of the requested data.
860system.membus.snoop_filter.hit_multi_requests 544 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

861system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
862system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
863system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

864system.membus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

864system.membus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

865system.membus.trans_dist::ReadReq 7449 # Transaction distribution
866system.membus.trans_dist::ReadResp 948786 # Transaction distribution
867system.membus.trans_dist::WriteReq 14588 # Transaction distribution
868system.membus.trans_dist::WriteResp 14588 # Transaction distribution
869system.membus.trans_dist::WritebackDirty 122467 # Transaction distribution
870system.membus.trans_dist::CleanEvict 918018 # Transaction distribution
871system.membus.trans_dist::UpgradeReq 13880 # Transaction distribution
872system.membus.trans_dist::SCUpgradeReq 11895 # Transaction distribution
873system.membus.trans_dist::UpgradeResp 135 # Transaction distribution
874system.membus.trans_dist::ReadExReq 125245 # Transaction distribution
875system.membus.trans_dist::ReadExResp 124223 # Transaction distribution
876system.membus.trans_dist::ReadSharedReq 941337 # Transaction distribution
877system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
878system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
879system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
880system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3156480 # Packet count per connected master and slave (bytes)
881system.membus.pkt_count_system.l2c.mem_side::total 3200554 # Packet count per connected master and slave (bytes)
882system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes)
883system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes)
884system.membus.pkt_count::total 3325715 # Packet count per connected master and slave (bytes)
885system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
886system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73364992 # Cumulative packet size per connected master and slave (bytes)
887system.membus.pkt_size_system.l2c.mem_side::total 73451154 # Cumulative packet size per connected master and slave (bytes)
888system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes)
889system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes)
890system.membus.pkt_size::total 76119890 # Cumulative packet size per connected master and slave (bytes)
891system.membus.snoops 0 # Total snoops (count)
892system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
893system.membus.snoop_fanout::samples 2196431 # Request fanout histogram

894system.membus.snoop_fanout::mean 0.000519 # Request fanout histogram
895system.membus.snoop_fanout::stdev 0.022766 # Request fanout histogram

894system.membus.snoop_fanout::mean 0.000560 # Request fanout histogram
895system.membus.snoop_fanout::stdev 0.023658 # Request fanout histogram

896system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

897system.membus.snoop_fanout::0 2195292 99.95% 99.95% # Request fanout histogram
898system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram

897system.membus.snoop_fanout::0 2195201 99.94% 99.94% # Request fanout histogram
898system.membus.snoop_fanout::1 1230 0.06% 100.00% # Request fanout histogram

899system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
900system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
901system.membus.snoop_fanout::min_value 0 # Request fanout histogram
902system.membus.snoop_fanout::max_value 1 # Request fanout histogram
903system.membus.snoop_fanout::total 2196431 # Request fanout histogram

904system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

904system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

905system.toL2Bus.snoop_filter.tot_requests 6035809 # Total number of requests made to the snoop filter.

906system.toL2Bus.snoop_filter.hit_single_requests 3018662 # Number of requests hitting in the snoop filter with a single holder of the requested data.
907system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
908system.toL2Bus.snoop_filter.tot_snoops 1621 # Total number of snoops made to the snoop filter.
909system.toL2Bus.snoop_filter.hit_single_snoops 1531 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

906system.toL2Bus.snoop_filter.hit_single_requests 3010644 # Number of requests hitting in the snoop filter with a single holder of the requested data.
907system.toL2Bus.snoop_filter.hit_multi_requests 386637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
908system.toL2Bus.snoop_filter.tot_snoops 1627 # Total number of snoops made to the snoop filter.
909system.toL2Bus.snoop_filter.hit_single_snoops 1537 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

910system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

911system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

911system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

912system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution
913system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution
914system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
915system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
916system.toL2Bus.trans_dist::WritebackDirty 778757 # Transaction distribution
917system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution
918system.toL2Bus.trans_dist::CleanEvict 1204367 # Transaction distribution
919system.toL2Bus.trans_dist::UpgradeReq 19598 # Transaction distribution
920system.toL2Bus.trans_dist::SCUpgradeReq 14203 # Transaction distribution
921system.toL2Bus.trans_dist::UpgradeResp 33801 # Transaction distribution
922system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution
923system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution
924system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution
925system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution
926system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes)
927system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450061 # Packet count per connected master and slave (bytes)
928system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes)
929system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684375 # Packet count per connected master and slave (bytes)
930system.toL2Bus.pkt_count::total 9133629 # Packet count per connected master and slave (bytes)
931system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes)
932system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155817595 # Cumulative packet size per connected master and slave (bytes)
933system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes)
934system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23377367 # Cumulative packet size per connected master and slave (bytes)
935system.toL2Bus.pkt_size::total 307135186 # Cumulative packet size per connected master and slave (bytes)

936system.toL2Bus.snoops 1000983 # Total snoops (count)
937system.toL2Bus.snoopTraffic 5197312 # Total snoop traffic (bytes)
938system.toL2Bus.snoop_fanout::samples 7058665 # Request fanout histogram
939system.toL2Bus.snoop_fanout::mean 0.106769 # Request fanout histogram
940system.toL2Bus.snoop_fanout::stdev 0.309069 # Request fanout histogram

936system.toL2Bus.snoops 1001076 # Total snoops (count)
937system.toL2Bus.snoopTraffic 5203008 # Total snoop traffic (bytes)
938system.toL2Bus.snoop_fanout::samples 7058756 # Request fanout histogram
939system.toL2Bus.snoop_fanout::mean 0.107956 # Request fanout histogram
940system.toL2Bus.snoop_fanout::stdev 0.310579 # Request fanout histogram

941system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

942system.toL2Bus.snoop_fanout::0 6305559 89.33% 89.33% # Request fanout histogram
943system.toL2Bus.snoop_fanout::1 752566 10.66% 99.99% # Request fanout histogram
944system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram

942system.toL2Bus.snoop_fanout::0 6297275 89.21% 89.21% # Request fanout histogram
943system.toL2Bus.snoop_fanout::1 760929 10.78% 99.99% # Request fanout histogram
944system.toL2Bus.snoop_fanout::2 550 0.01% 100.00% # Request fanout histogram

945system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram
946system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
947system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
948system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
949system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

950system.toL2Bus.snoop_fanout::total 7058665 # Request fanout histogram
951system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
952system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
953system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
954system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

950system.toL2Bus.snoop_fanout::total 7058756 # Request fanout histogram
951system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
952system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
953system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
954system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states

955system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
956system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
957system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
958system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
959system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
960system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
961system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
962system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
963system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
964system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
965system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
966system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
967system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
968system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
969system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
970system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
971system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
972system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
973system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
974system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
975system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
976system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
977system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
978system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
979system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
980system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
981system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
982system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
983system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
984system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
985system.tsunami.ethernet.droppedPackets 0 # number of packets dropped

986system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
987system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
988system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
989system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
990system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
991system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
992system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
993system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
994system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
995system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
996system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
997system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
998system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
999system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1000system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1001system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1002system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1003system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1004system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1005system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1006system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1007system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states
1008system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states

986system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
987system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
988system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
989system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
990system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
991system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
992system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
993system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
994system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
995system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
996system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
997system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
998system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
999system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1000system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1001system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1002system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1003system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1004system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1005system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1006system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1007system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states
1008system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869358054000 # Cumulative time (in ticks) in various power states