1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.870335 # Number of seconds simulated
4sim_ticks 1870335131500 # Number of ticks simulated
5final_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1824221 # Simulator instruction rate (inst/s)
8host_op_rate 1824220 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 54024573563 # Simulator tick rate (ticks/s)
10host_mem_usage 318368 # Number of bytes of host memory used
11host_seconds 34.62 # Real time elapsed on the host
12sim_insts 63154606 # Number of instructions simulated
13sim_ops 63154606 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory
21system.physmem.bytes_read::total 68252608 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory
26system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
27system.physmem.bytes_written::total 7863424 # Number of bytes written to this memory
28system.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory
30system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory
33system.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory
35system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
36system.physmem.num_writes::total 122866 # Number of write requests responded to by this memory
37system.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s)
46system.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s)
48system.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s)
49system.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s)
56system.membus.throughput 40739369 # Throughput (bytes/s)
57system.membus.data_through_bus 76196274 # Total data (bytes)
58system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
59system.cpu_clk_domain.clock 500 # Clock period in ticks
60system.l2c.tags.replacements 1000624 # number of replacements
61system.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use
62system.l2c.tags.total_refs 2464778 # Total number of references to valid blocks.
63system.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks.
64system.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks.
65system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
66system.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor
67system.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor
68system.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor
69system.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor
70system.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor
71system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy
72system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy
73system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy
74system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy
75system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy
76system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy
77system.l2c.tags.occ_task_id_blocks::1024 65142 # Occupied blocks per task id
78system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id
79system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id
80system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id
81system.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id
82system.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id
83system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id
84system.l2c.tags.tag_accesses 32109770 # Number of tag accesses
85system.l2c.tags.data_accesses 32109770 # Number of data accesses
86system.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits
87system.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits
88system.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits
89system.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits
90system.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits
91system.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits
92system.l2c.Writeback_hits::total 816663 # number of Writeback hits
93system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits
94system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
95system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits
96system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits
97system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
98system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits
99system.l2c.ReadExReq_hits::cpu0.data 166232 # number of ReadExReq hits
100system.l2c.ReadExReq_hits::cpu1.data 14288 # number of ReadExReq hits
101system.l2c.ReadExReq_hits::total 180520 # number of ReadExReq hits
102system.l2c.demand_hits::cpu0.inst 873092 # number of demand (read+write) hits
103system.l2c.demand_hits::cpu0.data 929323 # number of demand (read+write) hits
104system.l2c.demand_hits::cpu1.inst 101902 # number of demand (read+write) hits
105system.l2c.demand_hits::cpu1.data 51028 # number of demand (read+write) hits
106system.l2c.demand_hits::total 1955345 # number of demand (read+write) hits
107system.l2c.overall_hits::cpu0.inst 873092 # number of overall hits
108system.l2c.overall_hits::cpu0.data 929323 # number of overall hits
109system.l2c.overall_hits::cpu1.inst 101902 # number of overall hits
110system.l2c.overall_hits::cpu1.data 51028 # number of overall hits
111system.l2c.overall_hits::total 1955345 # number of overall hits
112system.l2c.ReadReq_misses::cpu0.inst 11892 # number of ReadReq misses
113system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses
114system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses
115system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses
116system.l2c.ReadReq_misses::total 941295 # number of ReadReq misses
117system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses
118system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses
119system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses
120system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses
121system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses
122system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses
123system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses
124system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses
125system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses
126system.l2c.demand_misses::cpu0.inst 11892 # number of demand (read+write) misses
127system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses
128system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses
129system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses
130system.l2c.demand_misses::total 1066663 # number of demand (read+write) misses
131system.l2c.overall_misses::cpu0.inst 11892 # number of overall misses
132system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses
133system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses
134system.l2c.overall_misses::cpu1.data 10570 # number of overall misses
135system.l2c.overall_misses::total 1066663 # number of overall misses
136system.l2c.ReadReq_accesses::cpu0.inst 884984 # number of ReadReq accesses(hits+misses)
137system.l2c.ReadReq_accesses::cpu0.data 1689852 # number of ReadReq accesses(hits+misses)
138system.l2c.ReadReq_accesses::cpu1.inst 103636 # number of ReadReq accesses(hits+misses)
139system.l2c.ReadReq_accesses::cpu1.data 37648 # number of ReadReq accesses(hits+misses)
140system.l2c.ReadReq_accesses::total 2716120 # number of ReadReq accesses(hits+misses)
141system.l2c.Writeback_accesses::writebacks 816663 # number of Writeback accesses(hits+misses)
142system.l2c.Writeback_accesses::total 816663 # number of Writeback accesses(hits+misses)
143system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses)
144system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses)
145system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses)
146system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses)
147system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses)
148system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses)
149system.l2c.ReadExReq_accesses::cpu0.data 281938 # number of ReadExReq accesses(hits+misses)
150system.l2c.ReadExReq_accesses::cpu1.data 23950 # number of ReadExReq accesses(hits+misses)
151system.l2c.ReadExReq_accesses::total 305888 # number of ReadExReq accesses(hits+misses)
152system.l2c.demand_accesses::cpu0.inst 884984 # number of demand (read+write) accesses
153system.l2c.demand_accesses::cpu0.data 1971790 # number of demand (read+write) accesses
154system.l2c.demand_accesses::cpu1.inst 103636 # number of demand (read+write) accesses
155system.l2c.demand_accesses::cpu1.data 61598 # number of demand (read+write) accesses
156system.l2c.demand_accesses::total 3022008 # number of demand (read+write) accesses
157system.l2c.overall_accesses::cpu0.inst 884984 # number of overall (read+write) accesses
158system.l2c.overall_accesses::cpu0.data 1971790 # number of overall (read+write) accesses
159system.l2c.overall_accesses::cpu1.inst 103636 # number of overall (read+write) accesses
160system.l2c.overall_accesses::cpu1.data 61598 # number of overall (read+write) accesses
161system.l2c.overall_accesses::total 3022008 # number of overall (read+write) accesses
162system.l2c.ReadReq_miss_rate::cpu0.inst 0.013438 # miss rate for ReadReq accesses
163system.l2c.ReadReq_miss_rate::cpu0.data 0.548427 # miss rate for ReadReq accesses
164system.l2c.ReadReq_miss_rate::cpu1.inst 0.016732 # miss rate for ReadReq accesses
165system.l2c.ReadReq_miss_rate::cpu1.data 0.024118 # miss rate for ReadReq accesses
166system.l2c.ReadReq_miss_rate::total 0.346559 # miss rate for ReadReq accesses
167system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses
168system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses
169system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses
170system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses
171system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses
172system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses
173system.l2c.ReadExReq_miss_rate::cpu0.data 0.410395 # miss rate for ReadExReq accesses
174system.l2c.ReadExReq_miss_rate::cpu1.data 0.403424 # miss rate for ReadExReq accesses
175system.l2c.ReadExReq_miss_rate::total 0.409849 # miss rate for ReadExReq accesses
176system.l2c.demand_miss_rate::cpu0.inst 0.013438 # miss rate for demand accesses
177system.l2c.demand_miss_rate::cpu0.data 0.528691 # miss rate for demand accesses
178system.l2c.demand_miss_rate::cpu1.inst 0.016732 # miss rate for demand accesses
179system.l2c.demand_miss_rate::cpu1.data 0.171596 # miss rate for demand accesses
180system.l2c.demand_miss_rate::total 0.352965 # miss rate for demand accesses
181system.l2c.overall_miss_rate::cpu0.inst 0.013438 # miss rate for overall accesses
182system.l2c.overall_miss_rate::cpu0.data 0.528691 # miss rate for overall accesses
183system.l2c.overall_miss_rate::cpu1.inst 0.016732 # miss rate for overall accesses
184system.l2c.overall_miss_rate::cpu1.data 0.171596 # miss rate for overall accesses
185system.l2c.overall_miss_rate::total 0.352965 # miss rate for overall accesses
186system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
187system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
188system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
189system.l2c.blocked::no_targets 0 # number of cycles access was blocked
190system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
191system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
192system.l2c.fast_writes 0 # number of fast writes performed
193system.l2c.cache_copies 0 # number of cache copies performed
194system.l2c.writebacks::writebacks 81314 # number of writebacks
195system.l2c.writebacks::total 81314 # number of writebacks
196system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
197system.iocache.tags.replacements 41695 # number of replacements
198system.iocache.tags.tagsinuse 0.435433 # Cycle average of tags in use
199system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
200system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
201system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
202system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
203system.iocache.tags.occ_blocks::tsunami.ide 0.435433 # Average occupied blocks per requestor
204system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy
205system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy
206system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
207system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
208system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
209system.iocache.tags.tag_accesses 375543 # Number of tag accesses
210system.iocache.tags.data_accesses 375543 # Number of data accesses
211system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
212system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
213system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
214system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
215system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
216system.iocache.demand_misses::total 175 # number of demand (read+write) misses
217system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
218system.iocache.overall_misses::total 175 # number of overall misses
219system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
220system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
221system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
222system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
223system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
224system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
225system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
226system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
227system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
228system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
229system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
231system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
233system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
234system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
--- 15 unchanged lines hidden (view full) ---
250system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
251system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
252system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
253system.disk2.dma_write_txs 1 # Number of DMA write transactions.
254system.cpu0.dtb.fetch_hits 0 # ITB hits
255system.cpu0.dtb.fetch_misses 0 # ITB misses
256system.cpu0.dtb.fetch_acv 0 # ITB acv
257system.cpu0.dtb.fetch_accesses 0 # ITB accesses
258system.cpu0.dtb.read_hits 9154569 # DTB read hits
259system.cpu0.dtb.read_misses 7079 # DTB read misses
260system.cpu0.dtb.read_acv 152 # DTB read access violations
261system.cpu0.dtb.read_accesses 508987 # DTB read accesses
262system.cpu0.dtb.write_hits 5936918 # DTB write hits
263system.cpu0.dtb.write_misses 726 # DTB write misses
264system.cpu0.dtb.write_acv 99 # DTB write access violations
265system.cpu0.dtb.write_accesses 189050 # DTB write accesses
266system.cpu0.dtb.data_hits 15091487 # DTB hits
267system.cpu0.dtb.data_misses 7805 # DTB misses
268system.cpu0.dtb.data_acv 251 # DTB access violations
269system.cpu0.dtb.data_accesses 698037 # DTB accesses
270system.cpu0.itb.fetch_hits 3855534 # ITB hits
271system.cpu0.itb.fetch_misses 3485 # ITB misses
272system.cpu0.itb.fetch_acv 127 # ITB acv
273system.cpu0.itb.fetch_accesses 3859019 # ITB accesses
274system.cpu0.itb.read_hits 0 # DTB read hits
275system.cpu0.itb.read_misses 0 # DTB read misses
276system.cpu0.itb.read_acv 0 # DTB read access violations
277system.cpu0.itb.read_accesses 0 # DTB read accesses
278system.cpu0.itb.write_hits 0 # DTB write hits
279system.cpu0.itb.write_misses 0 # DTB write misses
280system.cpu0.itb.write_acv 0 # DTB write access violations
281system.cpu0.itb.write_accesses 0 # DTB write accesses
282system.cpu0.itb.data_hits 0 # DTB hits
283system.cpu0.itb.data_misses 0 # DTB misses
284system.cpu0.itb.data_acv 0 # DTB access violations
285system.cpu0.itb.data_accesses 0 # DTB accesses
286system.cpu0.numCycles 3740670264 # number of cpu cycles simulated
287system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
288system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
289system.cpu0.committedInsts 57222643 # Number of instructions committed
290system.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed
291system.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses
292system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
293system.cpu0.num_func_calls 1399593 # number of times a function call or return occured
294system.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls
295system.cpu0.num_int_insts 53250480 # number of integer instructions
296system.cpu0.num_fp_insts 299810 # number of float instructions
297system.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read
298system.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written
299system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
300system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
301system.cpu0.num_mem_refs 15135573 # number of memory refs
302system.cpu0.num_load_insts 9184516 # Number of load instructions
303system.cpu0.num_store_insts 5951057 # Number of store instructions
304system.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles
305system.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles
306system.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles
307system.cpu0.idle_fraction 0.984699 # Percentage of idle cycles
308system.cpu0.Branches 8650822 # Number of branches fetched
309system.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction
310system.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction
311system.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction
312system.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction
313system.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction
314system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction
315system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction
316system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction
317system.cpu0.op_class::FloatDiv 2221 0.00% 71.65% # Class of executed instruction
318system.cpu0.op_class::FloatSqrt 0 0.00% 71.65% # Class of executed instruction
319system.cpu0.op_class::SimdAdd 0 0.00% 71.65% # Class of executed instruction
320system.cpu0.op_class::SimdAddAcc 0 0.00% 71.65% # Class of executed instruction
321system.cpu0.op_class::SimdAlu 0 0.00% 71.65% # Class of executed instruction
322system.cpu0.op_class::SimdCmp 0 0.00% 71.65% # Class of executed instruction
323system.cpu0.op_class::SimdCvt 0 0.00% 71.65% # Class of executed instruction
324system.cpu0.op_class::SimdMisc 0 0.00% 71.65% # Class of executed instruction
325system.cpu0.op_class::SimdMult 0 0.00% 71.65% # Class of executed instruction
326system.cpu0.op_class::SimdMultAcc 0 0.00% 71.65% # Class of executed instruction
327system.cpu0.op_class::SimdShift 0 0.00% 71.65% # Class of executed instruction
328system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.65% # Class of executed instruction
329system.cpu0.op_class::SimdSqrt 0 0.00% 71.65% # Class of executed instruction
330system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.65% # Class of executed instruction
331system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.65% # Class of executed instruction
332system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.65% # Class of executed instruction
333system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.65% # Class of executed instruction
334system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.65% # Class of executed instruction
335system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Class of executed instruction
336system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction
337system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction
338system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction
339system.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction
340system.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction
341system.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction
342system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
343system.cpu0.op_class::total 57230699 # Class of executed instruction
344system.cpu0.kern.inst.arm 0 # number of arm instructions executed
345system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
346system.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed
347system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl
348system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
349system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
350system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl
351system.cpu0.kern.ipl_count::31 101703 58.16% 100.00% # number of times we switched to this ipl
352system.cpu0.kern.ipl_count::total 174866 # number of times we switched to this ipl
353system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl
354system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
355system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
356system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
357system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl
358system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
359system.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl
360system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl
361system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl
362system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl
363system.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl
364system.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl
365system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl
366system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
367system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
368system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
369system.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl
370system.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl
371system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
372system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
373system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
374system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed
375system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed
376system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed
377system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed
378system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed
379system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed
380system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed
381system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed
382system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed
383system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed
384system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed
385system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed
386system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed
387system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed
388system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed
389system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed
390system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed
391system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed
392system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed
393system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed
394system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed
395system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed
396system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed
397system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed
398system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed
399system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
400system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
401system.cpu0.kern.syscall::total 226 # number of syscalls executed
402system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
403system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed
404system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed
405system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
406system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
407system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed
408system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
409system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
410system.cpu0.kern.callpal::swpipl 168033 91.68% 93.82% # number of callpals executed
411system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed
412system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
413system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
414system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed
415system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed
416system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
417system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
418system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
419system.cpu0.kern.callpal::total 183289 # number of callpals executed
420system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
421system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches
422system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
423system.cpu0.kern.mode_good::kernel 1155
424system.cpu0.kern.mode_good::user 1156
425system.cpu0.kern.mode_good::idle 0
426system.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches
427system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
428system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
429system.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches
430system.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode
431system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode
432system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
433system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
434system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
435system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
436system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
437system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
438system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
439system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
440system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
441system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
--- 15 unchanged lines hidden (view full) ---
457system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
458system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
459system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
460system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
461system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
462system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
463system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
464system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
465system.toL2Bus.throughput 133353257 # Throughput (bytes/s)
466system.toL2Bus.data_through_bus 246745714 # Total data (bytes)
467system.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes)
468system.iobus.throughput 1460501 # Throughput (bytes/s)
469system.iobus.data_through_bus 2731626 # Total data (bytes)
470system.cpu0.icache.tags.replacements 884408 # number of replacements
471system.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use
472system.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks.
473system.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks.
474system.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks.
475system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
476system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor
477system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy
478system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy
479system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
480system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
481system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
482system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id
483system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
484system.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses
485system.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses
486system.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits
487system.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits
488system.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits
489system.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits
490system.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits
491system.cpu0.icache.overall_hits::total 56345695 # number of overall hits
492system.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses
493system.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses
494system.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses
495system.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses
496system.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses
497system.cpu0.icache.overall_misses::total 885004 # number of overall misses
498system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses)
499system.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses)
500system.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses
501system.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses
502system.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses
503system.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses
504system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses
505system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses
506system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses
507system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses
508system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses
509system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses
510system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
511system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
512system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
513system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
514system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
515system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
516system.cpu0.icache.fast_writes 0 # number of fast writes performed
517system.cpu0.icache.cache_copies 0 # number of cache copies performed
518system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
519system.cpu0.dcache.tags.replacements 1978697 # number of replacements
520system.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use
521system.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks.
522system.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks.
523system.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks.
524system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
525system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor
526system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy
527system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy
528system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
529system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
530system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
531system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
532system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
533system.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses
534system.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses
535system.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits
536system.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits
537system.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits
538system.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits
539system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits
540system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits
541system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits
542system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits
543system.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits
544system.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits
545system.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits
546system.cpu0.dcache.overall_hits::total 12760647 # number of overall hits
547system.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses
548system.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses
549system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses
550system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses
551system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses
552system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses
553system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses
554system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses
555system.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses
556system.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses
557system.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses
558system.cpu0.dcache.overall_misses::total 1969341 # number of overall misses
559system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses)
560system.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses)
561system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses)
562system.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses)
563system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses)
564system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
565system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses)
566system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
567system.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses
568system.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses
569system.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses
570system.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses
571system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses
572system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses
573system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses
574system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses
575system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses
576system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses
577system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses
578system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses
579system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses
580system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses
581system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses
582system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses
583system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
584system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
585system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
586system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
587system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
588system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
589system.cpu0.dcache.fast_writes 0 # number of fast writes performed
590system.cpu0.dcache.cache_copies 0 # number of cache copies performed
591system.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks
592system.cpu0.dcache.writebacks::total 775643 # number of writebacks
593system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
594system.cpu1.dtb.fetch_hits 0 # ITB hits
595system.cpu1.dtb.fetch_misses 0 # ITB misses
596system.cpu1.dtb.fetch_acv 0 # ITB acv
597system.cpu1.dtb.fetch_accesses 0 # ITB accesses
598system.cpu1.dtb.read_hits 1163439 # DTB read hits
599system.cpu1.dtb.read_misses 3277 # DTB read misses
600system.cpu1.dtb.read_acv 58 # DTB read access violations
601system.cpu1.dtb.read_accesses 220342 # DTB read accesses
602system.cpu1.dtb.write_hits 751446 # DTB write hits
603system.cpu1.dtb.write_misses 415 # DTB write misses
604system.cpu1.dtb.write_acv 58 # DTB write access violations
605system.cpu1.dtb.write_accesses 103280 # DTB write accesses
606system.cpu1.dtb.data_hits 1914885 # DTB hits
607system.cpu1.dtb.data_misses 3692 # DTB misses
608system.cpu1.dtb.data_acv 116 # DTB access violations
609system.cpu1.dtb.data_accesses 323622 # DTB accesses
610system.cpu1.itb.fetch_hits 1468399 # ITB hits
611system.cpu1.itb.fetch_misses 1539 # ITB misses
612system.cpu1.itb.fetch_acv 57 # ITB acv
613system.cpu1.itb.fetch_accesses 1469938 # ITB accesses
614system.cpu1.itb.read_hits 0 # DTB read hits
615system.cpu1.itb.read_misses 0 # DTB read misses
616system.cpu1.itb.read_acv 0 # DTB read access violations
617system.cpu1.itb.read_accesses 0 # DTB read accesses
618system.cpu1.itb.write_hits 0 # DTB write hits
619system.cpu1.itb.write_misses 0 # DTB write misses
620system.cpu1.itb.write_acv 0 # DTB write access violations
621system.cpu1.itb.write_accesses 0 # DTB write accesses
622system.cpu1.itb.data_hits 0 # DTB hits
623system.cpu1.itb.data_misses 0 # DTB misses
624system.cpu1.itb.data_acv 0 # DTB access violations
625system.cpu1.itb.data_accesses 0 # DTB accesses
626system.cpu1.numCycles 3740248099 # number of cpu cycles simulated
627system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
628system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
629system.cpu1.committedInsts 5931963 # Number of instructions committed
630system.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed
631system.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses
632system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
633system.cpu1.num_func_calls 182742 # number of times a function call or return occured
634system.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls
635system.cpu1.num_int_insts 5550581 # number of integer instructions
636system.cpu1.num_fp_insts 28590 # number of float instructions
637system.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read
638system.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written
639system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
640system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
641system.cpu1.num_mem_refs 1926244 # number of memory refs
642system.cpu1.num_load_insts 1170888 # Number of load instructions
643system.cpu1.num_store_insts 755356 # Number of store instructions
644system.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles
645system.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles
646system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
647system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
648system.cpu1.Branches 836749 # Number of branches fetched
649system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction
650system.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction
651system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction
652system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction
653system.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction
654system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction
655system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction
656system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction
657system.cpu1.op_class::FloatDiv 1421 0.02% 63.88% # Class of executed instruction
658system.cpu1.op_class::FloatSqrt 0 0.00% 63.88% # Class of executed instruction
659system.cpu1.op_class::SimdAdd 0 0.00% 63.88% # Class of executed instruction
660system.cpu1.op_class::SimdAddAcc 0 0.00% 63.88% # Class of executed instruction
661system.cpu1.op_class::SimdAlu 0 0.00% 63.88% # Class of executed instruction
662system.cpu1.op_class::SimdCmp 0 0.00% 63.88% # Class of executed instruction
663system.cpu1.op_class::SimdCvt 0 0.00% 63.88% # Class of executed instruction
664system.cpu1.op_class::SimdMisc 0 0.00% 63.88% # Class of executed instruction
665system.cpu1.op_class::SimdMult 0 0.00% 63.88% # Class of executed instruction
666system.cpu1.op_class::SimdMultAcc 0 0.00% 63.88% # Class of executed instruction
667system.cpu1.op_class::SimdShift 0 0.00% 63.88% # Class of executed instruction
668system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.88% # Class of executed instruction
669system.cpu1.op_class::SimdSqrt 0 0.00% 63.88% # Class of executed instruction
670system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.88% # Class of executed instruction
671system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.88% # Class of executed instruction
672system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.88% # Class of executed instruction
673system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.88% # Class of executed instruction
674system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.88% # Class of executed instruction
675system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.88% # Class of executed instruction
676system.cpu1.op_class::SimdFloatMult 0 0.00% 63.88% # Class of executed instruction
677system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.88% # Class of executed instruction
678system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.88% # Class of executed instruction
679system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Class of executed instruction
680system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction
681system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction
682system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
683system.cpu1.op_class::total 5935771 # Class of executed instruction
684system.cpu1.kern.inst.arm 0 # number of arm instructions executed
685system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed
686system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
687system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl
688system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl
689system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl
690system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl
691system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl
692system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
693system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
694system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
695system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
696system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
697system.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl
698system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
699system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
700system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
701system.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl
702system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
703system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
704system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
705system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
706system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl
707system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
708system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
709system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
710system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed
711system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed
712system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed
713system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed
714system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed
715system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed
716system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed
717system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed
718system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed
719system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed
720system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed
721system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed
722system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed
723system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed
724system.cpu1.kern.syscall::total 100 # number of syscalls executed
725system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
726system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed
727system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
728system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
729system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed
730system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed
731system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed
732system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed
733system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed
734system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed
735system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed
736system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed
737system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed
738system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed
739system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed
740system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed
741system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
742system.cpu1.kern.callpal::total 32131 # number of callpals executed
743system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches
744system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
745system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
746system.cpu1.kern.mode_good::kernel 612
747system.cpu1.kern.mode_good::user 580
748system.cpu1.kern.mode_good::idle 32
749system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
750system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
751system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
752system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches
753system.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode
754system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
755system.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode
756system.cpu1.kern.swap_context 471 # number of times the context was actually changed
757system.cpu1.icache.tags.replacements 103097 # number of replacements
758system.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use
759system.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks.
760system.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks.
761system.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks.
762system.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit.
763system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor
764system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy
765system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy
766system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
767system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
768system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
769system.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses
770system.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses
771system.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits
772system.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits
773system.cpu1.icache.demand_hits::cpu1.inst 5832135 # number of demand (read+write) hits
774system.cpu1.icache.demand_hits::total 5832135 # number of demand (read+write) hits
775system.cpu1.icache.overall_hits::cpu1.inst 5832135 # number of overall hits
776system.cpu1.icache.overall_hits::total 5832135 # number of overall hits
777system.cpu1.icache.ReadReq_misses::cpu1.inst 103636 # number of ReadReq misses
778system.cpu1.icache.ReadReq_misses::total 103636 # number of ReadReq misses
779system.cpu1.icache.demand_misses::cpu1.inst 103636 # number of demand (read+write) misses
780system.cpu1.icache.demand_misses::total 103636 # number of demand (read+write) misses
781system.cpu1.icache.overall_misses::cpu1.inst 103636 # number of overall misses
782system.cpu1.icache.overall_misses::total 103636 # number of overall misses
783system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935771 # number of ReadReq accesses(hits+misses)
784system.cpu1.icache.ReadReq_accesses::total 5935771 # number of ReadReq accesses(hits+misses)
785system.cpu1.icache.demand_accesses::cpu1.inst 5935771 # number of demand (read+write) accesses
786system.cpu1.icache.demand_accesses::total 5935771 # number of demand (read+write) accesses
787system.cpu1.icache.overall_accesses::cpu1.inst 5935771 # number of overall (read+write) accesses
788system.cpu1.icache.overall_accesses::total 5935771 # number of overall (read+write) accesses
789system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017460 # miss rate for ReadReq accesses
790system.cpu1.icache.ReadReq_miss_rate::total 0.017460 # miss rate for ReadReq accesses
791system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017460 # miss rate for demand accesses
792system.cpu1.icache.demand_miss_rate::total 0.017460 # miss rate for demand accesses
793system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017460 # miss rate for overall accesses
794system.cpu1.icache.overall_miss_rate::total 0.017460 # miss rate for overall accesses
795system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
796system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
797system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
798system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
799system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
800system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
801system.cpu1.icache.fast_writes 0 # number of fast writes performed
802system.cpu1.icache.cache_copies 0 # number of cache copies performed
803system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
804system.cpu1.dcache.tags.replacements 62047 # number of replacements
805system.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use
806system.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks.
807system.cpu1.dcache.tags.sampled_refs 62385 # Sample count of references to valid blocks.
808system.cpu1.dcache.tags.avg_refs 29.430953 # Average number of references to valid blocks.
809system.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit.
810system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.558473 # Average occupied blocks per requestor
811system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823356 # Average percentage of cache occupancy
812system.cpu1.dcache.tags.occ_percent::total 0.823356 # Average percentage of cache occupancy
813system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
814system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id
815system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
816system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id
817system.cpu1.dcache.tags.tag_accesses 7735314 # Number of tag accesses
818system.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses
819system.cpu1.dcache.ReadReq_hits::cpu1.data 1109520 # number of ReadReq hits
820system.cpu1.dcache.ReadReq_hits::total 1109520 # number of ReadReq hits
821system.cpu1.dcache.WriteReq_hits::cpu1.data 707454 # number of WriteReq hits
822system.cpu1.dcache.WriteReq_hits::total 707454 # number of WriteReq hits
823system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits
824system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits
825system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits
826system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits
827system.cpu1.dcache.demand_hits::cpu1.data 1816974 # number of demand (read+write) hits
828system.cpu1.dcache.demand_hits::total 1816974 # number of demand (read+write) hits
829system.cpu1.dcache.overall_hits::cpu1.data 1816974 # number of overall hits
830system.cpu1.dcache.overall_hits::total 1816974 # number of overall hits
831system.cpu1.dcache.ReadReq_misses::cpu1.data 41445 # number of ReadReq misses
832system.cpu1.dcache.ReadReq_misses::total 41445 # number of ReadReq misses
833system.cpu1.dcache.WriteReq_misses::cpu1.data 25851 # number of WriteReq misses
834system.cpu1.dcache.WriteReq_misses::total 25851 # number of WriteReq misses
835system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses
836system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses
837system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses
838system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses
839system.cpu1.dcache.demand_misses::cpu1.data 67296 # number of demand (read+write) misses
840system.cpu1.dcache.demand_misses::total 67296 # number of demand (read+write) misses
841system.cpu1.dcache.overall_misses::cpu1.data 67296 # number of overall misses
842system.cpu1.dcache.overall_misses::total 67296 # number of overall misses
843system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses)
844system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
845system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses)
846system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
847system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses)
848system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
849system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses)
850system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
851system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses
852system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
853system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses
854system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
855system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036009 # miss rate for ReadReq accesses
856system.cpu1.dcache.ReadReq_miss_rate::total 0.036009 # miss rate for ReadReq accesses
857system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035253 # miss rate for WriteReq accesses
858system.cpu1.dcache.WriteReq_miss_rate::total 0.035253 # miss rate for WriteReq accesses
859system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses
860system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses
861system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses
862system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses
863system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035715 # miss rate for demand accesses
864system.cpu1.dcache.demand_miss_rate::total 0.035715 # miss rate for demand accesses
865system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035715 # miss rate for overall accesses
866system.cpu1.dcache.overall_miss_rate::total 0.035715 # miss rate for overall accesses
867system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
868system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
869system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
870system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
871system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
872system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
873system.cpu1.dcache.fast_writes 0 # number of fast writes performed
874system.cpu1.dcache.cache_copies 0 # number of cache copies performed
875system.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks
876system.cpu1.dcache.writebacks::total 41020 # number of writebacks
877system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
878
879---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.870335 # Number of seconds simulated
4sim_ticks 1870335131500 # Number of ticks simulated
5final_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1824221 # Simulator instruction rate (inst/s)
8host_op_rate 1824220 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 54024573563 # Simulator tick rate (ticks/s)
10host_mem_usage 318368 # Number of bytes of host memory used
11host_seconds 34.62 # Real time elapsed on the host
12sim_insts 63154606 # Number of instructions simulated
13sim_ops 63154606 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory
21system.physmem.bytes_read::total 68252608 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory
26system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
27system.physmem.bytes_written::total 7863424 # Number of bytes written to this memory
28system.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory
30system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory
33system.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory
34system.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory
35system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
36system.physmem.num_writes::total 122866 # Number of write requests responded to by this memory
37system.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s)
45system.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s)
46system.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s)
48system.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s)
49system.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s)
54system.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s)
55system.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s)
56system.membus.throughput 40739369 # Throughput (bytes/s)
57system.membus.data_through_bus 76196274 # Total data (bytes)
58system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
59system.cpu_clk_domain.clock 500 # Clock period in ticks
60system.l2c.tags.replacements 1000624 # number of replacements
61system.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use
62system.l2c.tags.total_refs 2464778 # Total number of references to valid blocks.
63system.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks.
64system.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks.
65system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
66system.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor
67system.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor
68system.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor
69system.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor
70system.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor
71system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy
72system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy
73system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy
74system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy
75system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy
76system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy
77system.l2c.tags.occ_task_id_blocks::1024 65142 # Occupied blocks per task id
78system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id
79system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id
80system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id
81system.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id
82system.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id
83system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id
84system.l2c.tags.tag_accesses 32109770 # Number of tag accesses
85system.l2c.tags.data_accesses 32109770 # Number of data accesses
86system.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits
87system.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits
88system.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits
89system.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits
90system.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits
91system.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits
92system.l2c.Writeback_hits::total 816663 # number of Writeback hits
93system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits
94system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
95system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits
96system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits
97system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
98system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits
99system.l2c.ReadExReq_hits::cpu0.data 166232 # number of ReadExReq hits
100system.l2c.ReadExReq_hits::cpu1.data 14288 # number of ReadExReq hits
101system.l2c.ReadExReq_hits::total 180520 # number of ReadExReq hits
102system.l2c.demand_hits::cpu0.inst 873092 # number of demand (read+write) hits
103system.l2c.demand_hits::cpu0.data 929323 # number of demand (read+write) hits
104system.l2c.demand_hits::cpu1.inst 101902 # number of demand (read+write) hits
105system.l2c.demand_hits::cpu1.data 51028 # number of demand (read+write) hits
106system.l2c.demand_hits::total 1955345 # number of demand (read+write) hits
107system.l2c.overall_hits::cpu0.inst 873092 # number of overall hits
108system.l2c.overall_hits::cpu0.data 929323 # number of overall hits
109system.l2c.overall_hits::cpu1.inst 101902 # number of overall hits
110system.l2c.overall_hits::cpu1.data 51028 # number of overall hits
111system.l2c.overall_hits::total 1955345 # number of overall hits
112system.l2c.ReadReq_misses::cpu0.inst 11892 # number of ReadReq misses
113system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses
114system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses
115system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses
116system.l2c.ReadReq_misses::total 941295 # number of ReadReq misses
117system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses
118system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses
119system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses
120system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses
121system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses
122system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses
123system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses
124system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses
125system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses
126system.l2c.demand_misses::cpu0.inst 11892 # number of demand (read+write) misses
127system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses
128system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses
129system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses
130system.l2c.demand_misses::total 1066663 # number of demand (read+write) misses
131system.l2c.overall_misses::cpu0.inst 11892 # number of overall misses
132system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses
133system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses
134system.l2c.overall_misses::cpu1.data 10570 # number of overall misses
135system.l2c.overall_misses::total 1066663 # number of overall misses
136system.l2c.ReadReq_accesses::cpu0.inst 884984 # number of ReadReq accesses(hits+misses)
137system.l2c.ReadReq_accesses::cpu0.data 1689852 # number of ReadReq accesses(hits+misses)
138system.l2c.ReadReq_accesses::cpu1.inst 103636 # number of ReadReq accesses(hits+misses)
139system.l2c.ReadReq_accesses::cpu1.data 37648 # number of ReadReq accesses(hits+misses)
140system.l2c.ReadReq_accesses::total 2716120 # number of ReadReq accesses(hits+misses)
141system.l2c.Writeback_accesses::writebacks 816663 # number of Writeback accesses(hits+misses)
142system.l2c.Writeback_accesses::total 816663 # number of Writeback accesses(hits+misses)
143system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses)
144system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses)
145system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses)
146system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses)
147system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses)
148system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses)
149system.l2c.ReadExReq_accesses::cpu0.data 281938 # number of ReadExReq accesses(hits+misses)
150system.l2c.ReadExReq_accesses::cpu1.data 23950 # number of ReadExReq accesses(hits+misses)
151system.l2c.ReadExReq_accesses::total 305888 # number of ReadExReq accesses(hits+misses)
152system.l2c.demand_accesses::cpu0.inst 884984 # number of demand (read+write) accesses
153system.l2c.demand_accesses::cpu0.data 1971790 # number of demand (read+write) accesses
154system.l2c.demand_accesses::cpu1.inst 103636 # number of demand (read+write) accesses
155system.l2c.demand_accesses::cpu1.data 61598 # number of demand (read+write) accesses
156system.l2c.demand_accesses::total 3022008 # number of demand (read+write) accesses
157system.l2c.overall_accesses::cpu0.inst 884984 # number of overall (read+write) accesses
158system.l2c.overall_accesses::cpu0.data 1971790 # number of overall (read+write) accesses
159system.l2c.overall_accesses::cpu1.inst 103636 # number of overall (read+write) accesses
160system.l2c.overall_accesses::cpu1.data 61598 # number of overall (read+write) accesses
161system.l2c.overall_accesses::total 3022008 # number of overall (read+write) accesses
162system.l2c.ReadReq_miss_rate::cpu0.inst 0.013438 # miss rate for ReadReq accesses
163system.l2c.ReadReq_miss_rate::cpu0.data 0.548427 # miss rate for ReadReq accesses
164system.l2c.ReadReq_miss_rate::cpu1.inst 0.016732 # miss rate for ReadReq accesses
165system.l2c.ReadReq_miss_rate::cpu1.data 0.024118 # miss rate for ReadReq accesses
166system.l2c.ReadReq_miss_rate::total 0.346559 # miss rate for ReadReq accesses
167system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses
168system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses
169system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses
170system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses
171system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses
172system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses
173system.l2c.ReadExReq_miss_rate::cpu0.data 0.410395 # miss rate for ReadExReq accesses
174system.l2c.ReadExReq_miss_rate::cpu1.data 0.403424 # miss rate for ReadExReq accesses
175system.l2c.ReadExReq_miss_rate::total 0.409849 # miss rate for ReadExReq accesses
176system.l2c.demand_miss_rate::cpu0.inst 0.013438 # miss rate for demand accesses
177system.l2c.demand_miss_rate::cpu0.data 0.528691 # miss rate for demand accesses
178system.l2c.demand_miss_rate::cpu1.inst 0.016732 # miss rate for demand accesses
179system.l2c.demand_miss_rate::cpu1.data 0.171596 # miss rate for demand accesses
180system.l2c.demand_miss_rate::total 0.352965 # miss rate for demand accesses
181system.l2c.overall_miss_rate::cpu0.inst 0.013438 # miss rate for overall accesses
182system.l2c.overall_miss_rate::cpu0.data 0.528691 # miss rate for overall accesses
183system.l2c.overall_miss_rate::cpu1.inst 0.016732 # miss rate for overall accesses
184system.l2c.overall_miss_rate::cpu1.data 0.171596 # miss rate for overall accesses
185system.l2c.overall_miss_rate::total 0.352965 # miss rate for overall accesses
186system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
187system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
188system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
189system.l2c.blocked::no_targets 0 # number of cycles access was blocked
190system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
191system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
192system.l2c.fast_writes 0 # number of fast writes performed
193system.l2c.cache_copies 0 # number of cache copies performed
194system.l2c.writebacks::writebacks 81314 # number of writebacks
195system.l2c.writebacks::total 81314 # number of writebacks
196system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
197system.iocache.tags.replacements 41695 # number of replacements
198system.iocache.tags.tagsinuse 0.435433 # Cycle average of tags in use
199system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
200system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
201system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
202system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
203system.iocache.tags.occ_blocks::tsunami.ide 0.435433 # Average occupied blocks per requestor
204system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy
205system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy
206system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
207system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
208system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
209system.iocache.tags.tag_accesses 375543 # Number of tag accesses
210system.iocache.tags.data_accesses 375543 # Number of data accesses
211system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
212system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
213system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
214system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
215system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
216system.iocache.demand_misses::total 175 # number of demand (read+write) misses
217system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
218system.iocache.overall_misses::total 175 # number of overall misses
219system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
220system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
221system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
222system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
223system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
224system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
225system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
226system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
227system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
228system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
229system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
231system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
233system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
234system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
--- 15 unchanged lines hidden (view full) ---
250system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
251system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
252system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
253system.disk2.dma_write_txs 1 # Number of DMA write transactions.
254system.cpu0.dtb.fetch_hits 0 # ITB hits
255system.cpu0.dtb.fetch_misses 0 # ITB misses
256system.cpu0.dtb.fetch_acv 0 # ITB acv
257system.cpu0.dtb.fetch_accesses 0 # ITB accesses
258system.cpu0.dtb.read_hits 9154569 # DTB read hits
259system.cpu0.dtb.read_misses 7079 # DTB read misses
260system.cpu0.dtb.read_acv 152 # DTB read access violations
261system.cpu0.dtb.read_accesses 508987 # DTB read accesses
262system.cpu0.dtb.write_hits 5936918 # DTB write hits
263system.cpu0.dtb.write_misses 726 # DTB write misses
264system.cpu0.dtb.write_acv 99 # DTB write access violations
265system.cpu0.dtb.write_accesses 189050 # DTB write accesses
266system.cpu0.dtb.data_hits 15091487 # DTB hits
267system.cpu0.dtb.data_misses 7805 # DTB misses
268system.cpu0.dtb.data_acv 251 # DTB access violations
269system.cpu0.dtb.data_accesses 698037 # DTB accesses
270system.cpu0.itb.fetch_hits 3855534 # ITB hits
271system.cpu0.itb.fetch_misses 3485 # ITB misses
272system.cpu0.itb.fetch_acv 127 # ITB acv
273system.cpu0.itb.fetch_accesses 3859019 # ITB accesses
274system.cpu0.itb.read_hits 0 # DTB read hits
275system.cpu0.itb.read_misses 0 # DTB read misses
276system.cpu0.itb.read_acv 0 # DTB read access violations
277system.cpu0.itb.read_accesses 0 # DTB read accesses
278system.cpu0.itb.write_hits 0 # DTB write hits
279system.cpu0.itb.write_misses 0 # DTB write misses
280system.cpu0.itb.write_acv 0 # DTB write access violations
281system.cpu0.itb.write_accesses 0 # DTB write accesses
282system.cpu0.itb.data_hits 0 # DTB hits
283system.cpu0.itb.data_misses 0 # DTB misses
284system.cpu0.itb.data_acv 0 # DTB access violations
285system.cpu0.itb.data_accesses 0 # DTB accesses
286system.cpu0.numCycles 3740670264 # number of cpu cycles simulated
287system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
288system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
289system.cpu0.committedInsts 57222643 # Number of instructions committed
290system.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed
291system.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses
292system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
293system.cpu0.num_func_calls 1399593 # number of times a function call or return occured
294system.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls
295system.cpu0.num_int_insts 53250480 # number of integer instructions
296system.cpu0.num_fp_insts 299810 # number of float instructions
297system.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read
298system.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written
299system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
300system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
301system.cpu0.num_mem_refs 15135573 # number of memory refs
302system.cpu0.num_load_insts 9184516 # Number of load instructions
303system.cpu0.num_store_insts 5951057 # Number of store instructions
304system.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles
305system.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles
306system.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles
307system.cpu0.idle_fraction 0.984699 # Percentage of idle cycles
308system.cpu0.Branches 8650822 # Number of branches fetched
309system.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction
310system.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction
311system.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction
312system.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction
313system.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction
314system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction
315system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction
316system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction
317system.cpu0.op_class::FloatDiv 2221 0.00% 71.65% # Class of executed instruction
318system.cpu0.op_class::FloatSqrt 0 0.00% 71.65% # Class of executed instruction
319system.cpu0.op_class::SimdAdd 0 0.00% 71.65% # Class of executed instruction
320system.cpu0.op_class::SimdAddAcc 0 0.00% 71.65% # Class of executed instruction
321system.cpu0.op_class::SimdAlu 0 0.00% 71.65% # Class of executed instruction
322system.cpu0.op_class::SimdCmp 0 0.00% 71.65% # Class of executed instruction
323system.cpu0.op_class::SimdCvt 0 0.00% 71.65% # Class of executed instruction
324system.cpu0.op_class::SimdMisc 0 0.00% 71.65% # Class of executed instruction
325system.cpu0.op_class::SimdMult 0 0.00% 71.65% # Class of executed instruction
326system.cpu0.op_class::SimdMultAcc 0 0.00% 71.65% # Class of executed instruction
327system.cpu0.op_class::SimdShift 0 0.00% 71.65% # Class of executed instruction
328system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.65% # Class of executed instruction
329system.cpu0.op_class::SimdSqrt 0 0.00% 71.65% # Class of executed instruction
330system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.65% # Class of executed instruction
331system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.65% # Class of executed instruction
332system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.65% # Class of executed instruction
333system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.65% # Class of executed instruction
334system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.65% # Class of executed instruction
335system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Class of executed instruction
336system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction
337system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction
338system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction
339system.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction
340system.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction
341system.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction
342system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
343system.cpu0.op_class::total 57230699 # Class of executed instruction
344system.cpu0.kern.inst.arm 0 # number of arm instructions executed
345system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
346system.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed
347system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl
348system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
349system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
350system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl
351system.cpu0.kern.ipl_count::31 101703 58.16% 100.00% # number of times we switched to this ipl
352system.cpu0.kern.ipl_count::total 174866 # number of times we switched to this ipl
353system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl
354system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
355system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
356system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
357system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl
358system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
359system.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl
360system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl
361system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl
362system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl
363system.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl
364system.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl
365system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl
366system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
367system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
368system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
369system.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl
370system.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl
371system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
372system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
373system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
374system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed
375system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed
376system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed
377system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed
378system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed
379system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed
380system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed
381system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed
382system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed
383system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed
384system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed
385system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed
386system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed
387system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed
388system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed
389system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed
390system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed
391system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed
392system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed
393system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed
394system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed
395system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed
396system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed
397system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed
398system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed
399system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed
400system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
401system.cpu0.kern.syscall::total 226 # number of syscalls executed
402system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
403system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed
404system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed
405system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
406system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
407system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed
408system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
409system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
410system.cpu0.kern.callpal::swpipl 168033 91.68% 93.82% # number of callpals executed
411system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed
412system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
413system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
414system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed
415system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed
416system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
417system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
418system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
419system.cpu0.kern.callpal::total 183289 # number of callpals executed
420system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
421system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches
422system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
423system.cpu0.kern.mode_good::kernel 1155
424system.cpu0.kern.mode_good::user 1156
425system.cpu0.kern.mode_good::idle 0
426system.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches
427system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
428system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
429system.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches
430system.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode
431system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode
432system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
433system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
434system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
435system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
436system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
437system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
438system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
439system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
440system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
441system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
--- 15 unchanged lines hidden (view full) ---
457system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
458system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
459system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
460system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
461system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
462system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
463system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
464system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
465system.toL2Bus.throughput 133353257 # Throughput (bytes/s)
466system.toL2Bus.data_through_bus 246745714 # Total data (bytes)
467system.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes)
468system.iobus.throughput 1460501 # Throughput (bytes/s)
469system.iobus.data_through_bus 2731626 # Total data (bytes)
470system.cpu0.icache.tags.replacements 884408 # number of replacements
471system.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use
472system.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks.
473system.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks.
474system.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks.
475system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
476system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor
477system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy
478system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy
479system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
480system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
481system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
482system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id
483system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
484system.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses
485system.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses
486system.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits
487system.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits
488system.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits
489system.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits
490system.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits
491system.cpu0.icache.overall_hits::total 56345695 # number of overall hits
492system.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses
493system.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses
494system.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses
495system.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses
496system.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses
497system.cpu0.icache.overall_misses::total 885004 # number of overall misses
498system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses)
499system.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses)
500system.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses
501system.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses
502system.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses
503system.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses
504system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses
505system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses
506system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses
507system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses
508system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses
509system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses
510system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
511system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
512system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
513system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
514system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
515system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
516system.cpu0.icache.fast_writes 0 # number of fast writes performed
517system.cpu0.icache.cache_copies 0 # number of cache copies performed
518system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
519system.cpu0.dcache.tags.replacements 1978697 # number of replacements
520system.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use
521system.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks.
522system.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks.
523system.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks.
524system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
525system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor
526system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy
527system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy
528system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
529system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
530system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
531system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
532system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
533system.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses
534system.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses
535system.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits
536system.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits
537system.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits
538system.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits
539system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits
540system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits
541system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits
542system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits
543system.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits
544system.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits
545system.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits
546system.cpu0.dcache.overall_hits::total 12760647 # number of overall hits
547system.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses
548system.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses
549system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses
550system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses
551system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses
552system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses
553system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses
554system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses
555system.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses
556system.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses
557system.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses
558system.cpu0.dcache.overall_misses::total 1969341 # number of overall misses
559system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses)
560system.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses)
561system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses)
562system.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses)
563system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses)
564system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
565system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses)
566system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
567system.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses
568system.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses
569system.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses
570system.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses
571system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses
572system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses
573system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses
574system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses
575system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses
576system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses
577system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses
578system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses
579system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses
580system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses
581system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses
582system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses
583system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
584system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
585system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
586system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
587system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
588system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
589system.cpu0.dcache.fast_writes 0 # number of fast writes performed
590system.cpu0.dcache.cache_copies 0 # number of cache copies performed
591system.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks
592system.cpu0.dcache.writebacks::total 775643 # number of writebacks
593system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
594system.cpu1.dtb.fetch_hits 0 # ITB hits
595system.cpu1.dtb.fetch_misses 0 # ITB misses
596system.cpu1.dtb.fetch_acv 0 # ITB acv
597system.cpu1.dtb.fetch_accesses 0 # ITB accesses
598system.cpu1.dtb.read_hits 1163439 # DTB read hits
599system.cpu1.dtb.read_misses 3277 # DTB read misses
600system.cpu1.dtb.read_acv 58 # DTB read access violations
601system.cpu1.dtb.read_accesses 220342 # DTB read accesses
602system.cpu1.dtb.write_hits 751446 # DTB write hits
603system.cpu1.dtb.write_misses 415 # DTB write misses
604system.cpu1.dtb.write_acv 58 # DTB write access violations
605system.cpu1.dtb.write_accesses 103280 # DTB write accesses
606system.cpu1.dtb.data_hits 1914885 # DTB hits
607system.cpu1.dtb.data_misses 3692 # DTB misses
608system.cpu1.dtb.data_acv 116 # DTB access violations
609system.cpu1.dtb.data_accesses 323622 # DTB accesses
610system.cpu1.itb.fetch_hits 1468399 # ITB hits
611system.cpu1.itb.fetch_misses 1539 # ITB misses
612system.cpu1.itb.fetch_acv 57 # ITB acv
613system.cpu1.itb.fetch_accesses 1469938 # ITB accesses
614system.cpu1.itb.read_hits 0 # DTB read hits
615system.cpu1.itb.read_misses 0 # DTB read misses
616system.cpu1.itb.read_acv 0 # DTB read access violations
617system.cpu1.itb.read_accesses 0 # DTB read accesses
618system.cpu1.itb.write_hits 0 # DTB write hits
619system.cpu1.itb.write_misses 0 # DTB write misses
620system.cpu1.itb.write_acv 0 # DTB write access violations
621system.cpu1.itb.write_accesses 0 # DTB write accesses
622system.cpu1.itb.data_hits 0 # DTB hits
623system.cpu1.itb.data_misses 0 # DTB misses
624system.cpu1.itb.data_acv 0 # DTB access violations
625system.cpu1.itb.data_accesses 0 # DTB accesses
626system.cpu1.numCycles 3740248099 # number of cpu cycles simulated
627system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
628system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
629system.cpu1.committedInsts 5931963 # Number of instructions committed
630system.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed
631system.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses
632system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
633system.cpu1.num_func_calls 182742 # number of times a function call or return occured
634system.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls
635system.cpu1.num_int_insts 5550581 # number of integer instructions
636system.cpu1.num_fp_insts 28590 # number of float instructions
637system.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read
638system.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written
639system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
640system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
641system.cpu1.num_mem_refs 1926244 # number of memory refs
642system.cpu1.num_load_insts 1170888 # Number of load instructions
643system.cpu1.num_store_insts 755356 # Number of store instructions
644system.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles
645system.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles
646system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
647system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
648system.cpu1.Branches 836749 # Number of branches fetched
649system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction
650system.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction
651system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction
652system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction
653system.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction
654system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction
655system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction
656system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction
657system.cpu1.op_class::FloatDiv 1421 0.02% 63.88% # Class of executed instruction
658system.cpu1.op_class::FloatSqrt 0 0.00% 63.88% # Class of executed instruction
659system.cpu1.op_class::SimdAdd 0 0.00% 63.88% # Class of executed instruction
660system.cpu1.op_class::SimdAddAcc 0 0.00% 63.88% # Class of executed instruction
661system.cpu1.op_class::SimdAlu 0 0.00% 63.88% # Class of executed instruction
662system.cpu1.op_class::SimdCmp 0 0.00% 63.88% # Class of executed instruction
663system.cpu1.op_class::SimdCvt 0 0.00% 63.88% # Class of executed instruction
664system.cpu1.op_class::SimdMisc 0 0.00% 63.88% # Class of executed instruction
665system.cpu1.op_class::SimdMult 0 0.00% 63.88% # Class of executed instruction
666system.cpu1.op_class::SimdMultAcc 0 0.00% 63.88% # Class of executed instruction
667system.cpu1.op_class::SimdShift 0 0.00% 63.88% # Class of executed instruction
668system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.88% # Class of executed instruction
669system.cpu1.op_class::SimdSqrt 0 0.00% 63.88% # Class of executed instruction
670system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.88% # Class of executed instruction
671system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.88% # Class of executed instruction
672system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.88% # Class of executed instruction
673system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.88% # Class of executed instruction
674system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.88% # Class of executed instruction
675system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.88% # Class of executed instruction
676system.cpu1.op_class::SimdFloatMult 0 0.00% 63.88% # Class of executed instruction
677system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.88% # Class of executed instruction
678system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.88% # Class of executed instruction
679system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Class of executed instruction
680system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction
681system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction
682system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
683system.cpu1.op_class::total 5935771 # Class of executed instruction
684system.cpu1.kern.inst.arm 0 # number of arm instructions executed
685system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed
686system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
687system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl
688system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl
689system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl
690system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl
691system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl
692system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
693system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl
694system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
695system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
696system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
697system.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl
698system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
699system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
700system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
701system.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl
702system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
703system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
704system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
705system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
706system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl
707system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
708system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
709system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
710system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed
711system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed
712system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed
713system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed
714system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed
715system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed
716system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed
717system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed
718system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed
719system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed
720system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed
721system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed
722system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed
723system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed
724system.cpu1.kern.syscall::total 100 # number of syscalls executed
725system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
726system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed
727system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
728system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
729system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed
730system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed
731system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed
732system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed
733system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed
734system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed
735system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed
736system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed
737system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed
738system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed
739system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed
740system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed
741system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
742system.cpu1.kern.callpal::total 32131 # number of callpals executed
743system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches
744system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
745system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
746system.cpu1.kern.mode_good::kernel 612
747system.cpu1.kern.mode_good::user 580
748system.cpu1.kern.mode_good::idle 32
749system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
750system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
751system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
752system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches
753system.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode
754system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
755system.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode
756system.cpu1.kern.swap_context 471 # number of times the context was actually changed
757system.cpu1.icache.tags.replacements 103097 # number of replacements
758system.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use
759system.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks.
760system.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks.
761system.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks.
762system.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit.
763system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor
764system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy
765system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy
766system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
767system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
768system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
769system.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses
770system.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses
771system.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits
772system.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits
773system.cpu1.icache.demand_hits::cpu1.inst 5832135 # number of demand (read+write) hits
774system.cpu1.icache.demand_hits::total 5832135 # number of demand (read+write) hits
775system.cpu1.icache.overall_hits::cpu1.inst 5832135 # number of overall hits
776system.cpu1.icache.overall_hits::total 5832135 # number of overall hits
777system.cpu1.icache.ReadReq_misses::cpu1.inst 103636 # number of ReadReq misses
778system.cpu1.icache.ReadReq_misses::total 103636 # number of ReadReq misses
779system.cpu1.icache.demand_misses::cpu1.inst 103636 # number of demand (read+write) misses
780system.cpu1.icache.demand_misses::total 103636 # number of demand (read+write) misses
781system.cpu1.icache.overall_misses::cpu1.inst 103636 # number of overall misses
782system.cpu1.icache.overall_misses::total 103636 # number of overall misses
783system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935771 # number of ReadReq accesses(hits+misses)
784system.cpu1.icache.ReadReq_accesses::total 5935771 # number of ReadReq accesses(hits+misses)
785system.cpu1.icache.demand_accesses::cpu1.inst 5935771 # number of demand (read+write) accesses
786system.cpu1.icache.demand_accesses::total 5935771 # number of demand (read+write) accesses
787system.cpu1.icache.overall_accesses::cpu1.inst 5935771 # number of overall (read+write) accesses
788system.cpu1.icache.overall_accesses::total 5935771 # number of overall (read+write) accesses
789system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017460 # miss rate for ReadReq accesses
790system.cpu1.icache.ReadReq_miss_rate::total 0.017460 # miss rate for ReadReq accesses
791system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017460 # miss rate for demand accesses
792system.cpu1.icache.demand_miss_rate::total 0.017460 # miss rate for demand accesses
793system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017460 # miss rate for overall accesses
794system.cpu1.icache.overall_miss_rate::total 0.017460 # miss rate for overall accesses
795system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
796system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
797system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
798system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
799system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
800system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
801system.cpu1.icache.fast_writes 0 # number of fast writes performed
802system.cpu1.icache.cache_copies 0 # number of cache copies performed
803system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
804system.cpu1.dcache.tags.replacements 62047 # number of replacements
805system.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use
806system.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks.
807system.cpu1.dcache.tags.sampled_refs 62385 # Sample count of references to valid blocks.
808system.cpu1.dcache.tags.avg_refs 29.430953 # Average number of references to valid blocks.
809system.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit.
810system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.558473 # Average occupied blocks per requestor
811system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823356 # Average percentage of cache occupancy
812system.cpu1.dcache.tags.occ_percent::total 0.823356 # Average percentage of cache occupancy
813system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
814system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id
815system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
816system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id
817system.cpu1.dcache.tags.tag_accesses 7735314 # Number of tag accesses
818system.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses
819system.cpu1.dcache.ReadReq_hits::cpu1.data 1109520 # number of ReadReq hits
820system.cpu1.dcache.ReadReq_hits::total 1109520 # number of ReadReq hits
821system.cpu1.dcache.WriteReq_hits::cpu1.data 707454 # number of WriteReq hits
822system.cpu1.dcache.WriteReq_hits::total 707454 # number of WriteReq hits
823system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits
824system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits
825system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits
826system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits
827system.cpu1.dcache.demand_hits::cpu1.data 1816974 # number of demand (read+write) hits
828system.cpu1.dcache.demand_hits::total 1816974 # number of demand (read+write) hits
829system.cpu1.dcache.overall_hits::cpu1.data 1816974 # number of overall hits
830system.cpu1.dcache.overall_hits::total 1816974 # number of overall hits
831system.cpu1.dcache.ReadReq_misses::cpu1.data 41445 # number of ReadReq misses
832system.cpu1.dcache.ReadReq_misses::total 41445 # number of ReadReq misses
833system.cpu1.dcache.WriteReq_misses::cpu1.data 25851 # number of WriteReq misses
834system.cpu1.dcache.WriteReq_misses::total 25851 # number of WriteReq misses
835system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses
836system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses
837system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses
838system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses
839system.cpu1.dcache.demand_misses::cpu1.data 67296 # number of demand (read+write) misses
840system.cpu1.dcache.demand_misses::total 67296 # number of demand (read+write) misses
841system.cpu1.dcache.overall_misses::cpu1.data 67296 # number of overall misses
842system.cpu1.dcache.overall_misses::total 67296 # number of overall misses
843system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses)
844system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
845system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses)
846system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
847system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses)
848system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
849system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses)
850system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
851system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses
852system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
853system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses
854system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
855system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036009 # miss rate for ReadReq accesses
856system.cpu1.dcache.ReadReq_miss_rate::total 0.036009 # miss rate for ReadReq accesses
857system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035253 # miss rate for WriteReq accesses
858system.cpu1.dcache.WriteReq_miss_rate::total 0.035253 # miss rate for WriteReq accesses
859system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses
860system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses
861system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses
862system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses
863system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035715 # miss rate for demand accesses
864system.cpu1.dcache.demand_miss_rate::total 0.035715 # miss rate for demand accesses
865system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035715 # miss rate for overall accesses
866system.cpu1.dcache.overall_miss_rate::total 0.035715 # miss rate for overall accesses
867system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
868system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
869system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
870system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
871system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
872system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
873system.cpu1.dcache.fast_writes 0 # number of fast writes performed
874system.cpu1.dcache.cache_copies 0 # number of cache copies performed
875system.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks
876system.cpu1.dcache.writebacks::total 41020 # number of writebacks
877system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
878
879---------- End Simulation Statistics ----------