1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.869358 # Number of seconds simulated
4sim_ticks 1869358498000 # Number of ticks simulated
5final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1825215 # Simulator instruction rate (inst/s)
8host_op_rate 1825215 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 52491614317 # Simulator tick rate (ticks/s)
10host_mem_usage 318168 # Number of bytes of host memory used
11host_seconds 35.61 # Real time elapsed on the host
12sim_insts 65000470 # Number of instructions simulated
13sim_ops 65000470 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.data 66539648 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu1.inst 106432 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.data 766208 # Number of bytes read from this memory
20system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
21system.physmem.bytes_read::total 68179008 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::cpu1.inst 106432 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 7831360 # Number of bytes written to this memory
26system.physmem.bytes_written::total 7831360 # Number of bytes written to this memory
27system.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu0.data 1039682 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu1.inst 1663 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu1.data 11972 # Number of read requests responded to by this memory
31system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 1065297 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 122365 # Number of write requests responded to by this memory
34system.physmem.num_writes::total 122365 # Number of write requests responded to by this memory
35system.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu0.data 35594910 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu1.inst 56935 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu1.data 409878 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::total 36471874 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu1.inst 56935 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 466573 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 4189330 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::total 4189330 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_total::writebacks 4189330 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu0.data 35594910 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu1.inst 56935 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu1.data 409878 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::total 40661204 # Total bandwidth to/from this memory (bytes/s)
53system.cpu_clk_domain.clock 500 # Clock period in ticks
54system.cpu0.dtb.fetch_hits 0 # ITB hits
55system.cpu0.dtb.fetch_misses 0 # ITB misses
56system.cpu0.dtb.fetch_acv 0 # ITB acv
57system.cpu0.dtb.fetch_accesses 0 # ITB accesses
58system.cpu0.dtb.read_hits 7758839 # DTB read hits
59system.cpu0.dtb.read_misses 7155 # DTB read misses
60system.cpu0.dtb.read_acv 152 # DTB read access violations
61system.cpu0.dtb.read_accesses 531148 # DTB read accesses
62system.cpu0.dtb.write_hits 4740268 # DTB write hits
63system.cpu0.dtb.write_misses 732 # DTB write misses
64system.cpu0.dtb.write_acv 102 # DTB write access violations
65system.cpu0.dtb.write_accesses 201714 # DTB write accesses
66system.cpu0.dtb.data_hits 12499107 # DTB hits
67system.cpu0.dtb.data_misses 7887 # DTB misses
68system.cpu0.dtb.data_acv 254 # DTB access violations
69system.cpu0.dtb.data_accesses 732862 # DTB accesses
70system.cpu0.itb.fetch_hits 3525737 # ITB hits
71system.cpu0.itb.fetch_misses 3572 # ITB misses
72system.cpu0.itb.fetch_acv 127 # ITB acv
73system.cpu0.itb.fetch_accesses 3529309 # ITB accesses
74system.cpu0.itb.read_hits 0 # DTB read hits
75system.cpu0.itb.read_misses 0 # DTB read misses
76system.cpu0.itb.read_acv 0 # DTB read access violations
77system.cpu0.itb.read_accesses 0 # DTB read accesses
78system.cpu0.itb.write_hits 0 # DTB write hits
79system.cpu0.itb.write_misses 0 # DTB write misses
80system.cpu0.itb.write_acv 0 # DTB write access violations
81system.cpu0.itb.write_accesses 0 # DTB write accesses
82system.cpu0.itb.data_hits 0 # DTB hits
83system.cpu0.itb.data_misses 0 # DTB misses
84system.cpu0.itb.data_acv 0 # DTB access violations
85system.cpu0.itb.data_accesses 0 # DTB accesses
86system.cpu0.numCycles 3738723791 # number of cpu cycles simulated
87system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
88system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
89system.cpu0.committedInsts 49478313 # Number of instructions committed
90system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed
91system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses
92system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses
93system.cpu0.num_func_calls 1124639 # number of times a function call or return occured
94system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls
95system.cpu0.num_int_insts 46202260 # number of integer instructions
96system.cpu0.num_fp_insts 197598 # number of float instructions
97system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read
98system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written
99system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read
100system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written
101system.cpu0.num_mem_refs 12536155 # number of memory refs
102system.cpu0.num_load_insts 7783785 # Number of load instructions
103system.cpu0.num_store_insts 4752370 # Number of store instructions
104system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles
105system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles
106system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles
107system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles
108system.cpu0.Branches 7530941 # Number of branches fetched
109system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction
110system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction
111system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction
112system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction
113system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction
114system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction
115system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction
116system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction
117system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction
118system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction
119system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction

--- 11 unchanged lines hidden (view full) ---

131system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction
132system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction
133system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction
134system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction
135system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction
136system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction
137system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction
138system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction
139system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction
140system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction
141system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction
142system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
143system.cpu0.op_class::total 49486454 # Class of executed instruction
144system.cpu0.kern.inst.arm 0 # number of arm instructions executed
145system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed
146system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed
147system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl
148system.cpu0.kern.ipl_count::21 243 0.19% 40.18% # number of times we switched to this ipl
149system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl
150system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl
151system.cpu0.kern.ipl_count::31 74447 57.93% 100.00% # number of times we switched to this ipl
152system.cpu0.kern.ipl_count::total 128509 # number of times we switched to this ipl
153system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl
154system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl
155system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl
156system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl
157system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl
158system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl
159system.cpu0.kern.ipl_ticks::0 1853222948500 99.14% 99.14% # number of cycles we spent at this ipl
160system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl
161system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl
162system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl
163system.cpu0.kern.ipl_ticks::31 15975609500 0.85% 100.00% # number of cycles we spent at this ipl
164system.cpu0.kern.ipl_ticks::total 1869358290500 # number of cycles we spent at this ipl
165system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl
166system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
167system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
168system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
169system.cpu0.kern.ipl_used::31 0.678818 # fraction of swpipl calls that actually changed the ipl
170system.cpu0.kern.ipl_used::total 0.811227 # fraction of swpipl calls that actually changed the ipl
171system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed
172system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed
173system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed
174system.cpu0.kern.syscall::6 32 14.04% 26.32% # number of syscalls executed
175system.cpu0.kern.syscall::12 1 0.44% 26.75% # number of syscalls executed
176system.cpu0.kern.syscall::15 1 0.44% 27.19% # number of syscalls executed
177system.cpu0.kern.syscall::17 9 3.95% 31.14% # number of syscalls executed
178system.cpu0.kern.syscall::19 8 3.51% 34.65% # number of syscalls executed

--- 23 unchanged lines hidden (view full) ---

202system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
203system.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed
204system.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed
205system.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed
206system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed
207system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed
208system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed
209system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed
210system.cpu0.kern.callpal::swpipl 121669 89.51% 92.02% # number of callpals executed
211system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed
212system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed
213system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed
214system.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed
215system.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed
216system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed
217system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed
218system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed
219system.cpu0.kern.callpal::total 135930 # number of callpals executed
220system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches
221system.cpu0.kern.mode_switch::user 1174 # number of protection mode switches
222system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
223system.cpu0.kern.mode_good::kernel 1173
224system.cpu0.kern.mode_good::user 1174
225system.cpu0.kern.mode_good::idle 0
226system.cpu0.kern.mode_switch_good::kernel 0.177916 # fraction of useful protection mode switches
227system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
228system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
229system.cpu0.kern.mode_switch_good::total 0.302176 # fraction of useful protection mode switches
230system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # number of ticks spent at the given mode
231system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode
232system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
233system.cpu0.kern.swap_context 2744 # number of times the context was actually changed
234system.cpu0.dcache.tags.replacements 1781373 # number of replacements
235system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use
236system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks.
237system.cpu0.dcache.tags.sampled_refs 1781885 # Sample count of references to valid blocks.
238system.cpu0.dcache.tags.avg_refs 6.008137 # Average number of references to valid blocks.
239system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
240system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187448 # Average occupied blocks per requestor
241system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy
242system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy
243system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
244system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id
245system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
246system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
247system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
248system.cpu0.dcache.tags.tag_accesses 51822236 # Number of tag accesses
249system.cpu0.dcache.tags.data_accesses 51822236 # Number of data accesses
250system.cpu0.dcache.ReadReq_hits::cpu0.data 6068914 # number of ReadReq hits
251system.cpu0.dcache.ReadReq_hits::total 6068914 # number of ReadReq hits
252system.cpu0.dcache.WriteReq_hits::cpu0.data 4360098 # number of WriteReq hits
253system.cpu0.dcache.WriteReq_hits::total 4360098 # number of WriteReq hits
254system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127591 # number of LoadLockedReq hits
255system.cpu0.dcache.LoadLockedReq_hits::total 127591 # number of LoadLockedReq hits
256system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132845 # number of StoreCondReq hits
257system.cpu0.dcache.StoreCondReq_hits::total 132845 # number of StoreCondReq hits
258system.cpu0.dcache.demand_hits::cpu0.data 10429012 # number of demand (read+write) hits
259system.cpu0.dcache.demand_hits::total 10429012 # number of demand (read+write) hits
260system.cpu0.dcache.overall_hits::cpu0.data 10429012 # number of overall hits
261system.cpu0.dcache.overall_hits::total 10429012 # number of overall hits
262system.cpu0.dcache.ReadReq_misses::cpu0.data 1560067 # number of ReadReq misses
263system.cpu0.dcache.ReadReq_misses::total 1560067 # number of ReadReq misses
264system.cpu0.dcache.WriteReq_misses::cpu0.data 236542 # number of WriteReq misses
265system.cpu0.dcache.WriteReq_misses::total 236542 # number of WriteReq misses
266system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12627 # number of LoadLockedReq misses
267system.cpu0.dcache.LoadLockedReq_misses::total 12627 # number of LoadLockedReq misses
268system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6925 # number of StoreCondReq misses
269system.cpu0.dcache.StoreCondReq_misses::total 6925 # number of StoreCondReq misses
270system.cpu0.dcache.demand_misses::cpu0.data 1796609 # number of demand (read+write) misses
271system.cpu0.dcache.demand_misses::total 1796609 # number of demand (read+write) misses
272system.cpu0.dcache.overall_misses::cpu0.data 1796609 # number of overall misses
273system.cpu0.dcache.overall_misses::total 1796609 # number of overall misses
274system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628981 # number of ReadReq accesses(hits+misses)
275system.cpu0.dcache.ReadReq_accesses::total 7628981 # number of ReadReq accesses(hits+misses)
276system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596640 # number of WriteReq accesses(hits+misses)
277system.cpu0.dcache.WriteReq_accesses::total 4596640 # number of WriteReq accesses(hits+misses)
278system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses)
279system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses)
280system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses)
281system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses)
282system.cpu0.dcache.demand_accesses::cpu0.data 12225621 # number of demand (read+write) accesses
283system.cpu0.dcache.demand_accesses::total 12225621 # number of demand (read+write) accesses
284system.cpu0.dcache.overall_accesses::cpu0.data 12225621 # number of overall (read+write) accesses
285system.cpu0.dcache.overall_accesses::total 12225621 # number of overall (read+write) accesses
286system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204492 # miss rate for ReadReq accesses
287system.cpu0.dcache.ReadReq_miss_rate::total 0.204492 # miss rate for ReadReq accesses
288system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses
289system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses
290system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090053 # miss rate for LoadLockedReq accesses
291system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090053 # miss rate for LoadLockedReq accesses
292system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049546 # miss rate for StoreCondReq accesses
293system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049546 # miss rate for StoreCondReq accesses
294system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses
295system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses
296system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses
297system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses
298system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
299system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
300system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
301system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
302system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
303system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
304system.cpu0.dcache.fast_writes 0 # number of fast writes performed
305system.cpu0.dcache.cache_copies 0 # number of cache copies performed
306system.cpu0.dcache.writebacks::writebacks 632997 # number of writebacks
307system.cpu0.dcache.writebacks::total 632997 # number of writebacks
308system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
309system.cpu0.icache.tags.replacements 618298 # number of replacements
310system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use
311system.cpu0.icache.tags.total_refs 48867509 # Total number of references to valid blocks.
312system.cpu0.icache.tags.sampled_refs 618810 # Sample count of references to valid blocks.
313system.cpu0.icache.tags.avg_refs 78.970135 # Average number of references to valid blocks.
314system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit.
315system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240646 # Average occupied blocks per requestor
316system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy
317system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy
318system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
319system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
320system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id
321system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id
322system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
323system.cpu0.icache.tags.tag_accesses 50105399 # Number of tag accesses
324system.cpu0.icache.tags.data_accesses 50105399 # Number of data accesses
325system.cpu0.icache.ReadReq_hits::cpu0.inst 48867509 # number of ReadReq hits
326system.cpu0.icache.ReadReq_hits::total 48867509 # number of ReadReq hits
327system.cpu0.icache.demand_hits::cpu0.inst 48867509 # number of demand (read+write) hits
328system.cpu0.icache.demand_hits::total 48867509 # number of demand (read+write) hits
329system.cpu0.icache.overall_hits::cpu0.inst 48867509 # number of overall hits
330system.cpu0.icache.overall_hits::total 48867509 # number of overall hits
331system.cpu0.icache.ReadReq_misses::cpu0.inst 618945 # number of ReadReq misses
332system.cpu0.icache.ReadReq_misses::total 618945 # number of ReadReq misses
333system.cpu0.icache.demand_misses::cpu0.inst 618945 # number of demand (read+write) misses
334system.cpu0.icache.demand_misses::total 618945 # number of demand (read+write) misses
335system.cpu0.icache.overall_misses::cpu0.inst 618945 # number of overall misses
336system.cpu0.icache.overall_misses::total 618945 # number of overall misses
337system.cpu0.icache.ReadReq_accesses::cpu0.inst 49486454 # number of ReadReq accesses(hits+misses)
338system.cpu0.icache.ReadReq_accesses::total 49486454 # number of ReadReq accesses(hits+misses)
339system.cpu0.icache.demand_accesses::cpu0.inst 49486454 # number of demand (read+write) accesses
340system.cpu0.icache.demand_accesses::total 49486454 # number of demand (read+write) accesses
341system.cpu0.icache.overall_accesses::cpu0.inst 49486454 # number of overall (read+write) accesses
342system.cpu0.icache.overall_accesses::total 49486454 # number of overall (read+write) accesses
343system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses
344system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses
345system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses
346system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses
347system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses
348system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses
349system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
350system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
351system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
352system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
353system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
354system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
355system.cpu0.icache.fast_writes 0 # number of fast writes performed
356system.cpu0.icache.cache_copies 0 # number of cache copies performed
357system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
358system.cpu1.dtb.fetch_hits 0 # ITB hits
359system.cpu1.dtb.fetch_misses 0 # ITB misses
360system.cpu1.dtb.fetch_acv 0 # ITB acv
361system.cpu1.dtb.fetch_accesses 0 # ITB accesses
362system.cpu1.dtb.read_hits 2831558 # DTB read hits
363system.cpu1.dtb.read_misses 3191 # DTB read misses
364system.cpu1.dtb.read_acv 58 # DTB read access violations
365system.cpu1.dtb.read_accesses 198160 # DTB read accesses
366system.cpu1.dtb.write_hits 2101673 # DTB write hits
367system.cpu1.dtb.write_misses 412 # DTB write misses
368system.cpu1.dtb.write_acv 55 # DTB write access violations
369system.cpu1.dtb.write_accesses 90619 # DTB write accesses
370system.cpu1.dtb.data_hits 4933231 # DTB hits
371system.cpu1.dtb.data_misses 3603 # DTB misses
372system.cpu1.dtb.data_acv 113 # DTB access violations
373system.cpu1.dtb.data_accesses 288779 # DTB accesses
374system.cpu1.itb.fetch_hits 1950883 # ITB hits
375system.cpu1.itb.fetch_misses 1451 # ITB misses
376system.cpu1.itb.fetch_acv 57 # ITB acv
377system.cpu1.itb.fetch_accesses 1952334 # ITB accesses
378system.cpu1.itb.read_hits 0 # DTB read hits
379system.cpu1.itb.read_misses 0 # DTB read misses
380system.cpu1.itb.read_acv 0 # DTB read access violations
381system.cpu1.itb.read_accesses 0 # DTB read accesses
382system.cpu1.itb.write_hits 0 # DTB write hits
383system.cpu1.itb.write_misses 0 # DTB write misses
384system.cpu1.itb.write_acv 0 # DTB write access violations
385system.cpu1.itb.write_accesses 0 # DTB write accesses
386system.cpu1.itb.data_hits 0 # DTB hits
387system.cpu1.itb.data_misses 0 # DTB misses
388system.cpu1.itb.data_acv 0 # DTB access violations
389system.cpu1.itb.data_accesses 0 # DTB accesses
390system.cpu1.numCycles 3738297607 # number of cpu cycles simulated
391system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
392system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
393system.cpu1.committedInsts 15522157 # Number of instructions committed
394system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed
395system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses
396system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses
397system.cpu1.num_func_calls 493140 # number of times a function call or return occured
398system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls
399system.cpu1.num_int_insts 14295542 # number of integer instructions
400system.cpu1.num_fp_insts 198941 # number of float instructions
401system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read
402system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written
403system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read
404system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written
405system.cpu1.num_mem_refs 4961785 # number of memory refs
406system.cpu1.num_load_insts 2849089 # Number of load instructions
407system.cpu1.num_store_insts 2112696 # Number of store instructions
408system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles
409system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles
410system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles
411system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles
412system.cpu1.Branches 2214162 # Number of branches fetched
413system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction
414system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction
415system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction
416system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction
417system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction
418system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction
419system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction
420system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction
421system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction
422system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction

--- 12 unchanged lines hidden (view full) ---

435system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction
436system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction
437system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction
438system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction
439system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction
440system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction
441system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction
442system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction
443system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction
444system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction
445system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction
446system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
447system.cpu1.op_class::total 15525873 # Class of executed instruction
448system.cpu1.kern.inst.arm 0 # number of arm instructions executed
449system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed
450system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed
451system.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl
452system.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl
453system.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl
454system.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl
455system.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl
456system.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl
457system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl
458system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl
459system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl
460system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl
461system.cpu1.kern.ipl_ticks::0 1856124001500 99.30% 99.30% # number of cycles we spent at this ipl
462system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl
463system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl
464system.cpu1.kern.ipl_ticks::31 12870742500 0.69% 100.00% # number of cycles we spent at this ipl
465system.cpu1.kern.ipl_ticks::total 1869147438500 # number of cycles we spent at this ipl
466system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl
467system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
468system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
469system.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl
470system.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl
471system.cpu1.kern.syscall::2 2 2.04% 2.04% # number of syscalls executed
472system.cpu1.kern.syscall::3 10 10.20% 12.24% # number of syscalls executed
473system.cpu1.kern.syscall::4 2 2.04% 14.29% # number of syscalls executed

--- 35 unchanged lines hidden (view full) ---

509system.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches
510system.cpu1.kern.mode_good::kernel 1106
511system.cpu1.kern.mode_good::user 564
512system.cpu1.kern.mode_good::idle 542
513system.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches
514system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
515system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches
516system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches
517system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # number of ticks spent at the given mode
518system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode
519system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode
520system.cpu1.kern.swap_context 2507 # number of times the context was actually changed
521system.cpu1.dcache.tags.replacements 201756 # number of replacements
522system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use
523system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks.
524system.cpu1.dcache.tags.sampled_refs 202064 # Sample count of references to valid blocks.
525system.cpu1.dcache.tags.avg_refs 23.351027 # Average number of references to valid blocks.
526system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit.
527system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.613037 # Average occupied blocks per requestor
528system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971900 # Average percentage of cache occupancy
529system.cpu1.dcache.tags.occ_percent::total 0.971900 # Average percentage of cache occupancy
530system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id
531system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
532system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
533system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id
534system.cpu1.dcache.tags.tag_accesses 20020602 # Number of tag accesses
535system.cpu1.dcache.tags.data_accesses 20020602 # Number of data accesses
536system.cpu1.dcache.ReadReq_hits::cpu1.data 2632689 # number of ReadReq hits
537system.cpu1.dcache.ReadReq_hits::total 2632689 # number of ReadReq hits
538system.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits
539system.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits
540system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61099 # number of LoadLockedReq hits
541system.cpu1.dcache.LoadLockedReq_hits::total 61099 # number of LoadLockedReq hits
542system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits
543system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits
544system.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits
545system.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits
546system.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits
547system.cpu1.dcache.overall_hits::total 4587331 # number of overall hits
548system.cpu1.dcache.ReadReq_misses::cpu1.data 140883 # number of ReadReq misses
549system.cpu1.dcache.ReadReq_misses::total 140883 # number of ReadReq misses
550system.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses
551system.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses
552system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10999 # number of LoadLockedReq misses
553system.cpu1.dcache.LoadLockedReq_misses::total 10999 # number of LoadLockedReq misses
554system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses
555system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses
556system.cpu1.dcache.demand_misses::cpu1.data 219201 # number of demand (read+write) misses
557system.cpu1.dcache.demand_misses::total 219201 # number of demand (read+write) misses
558system.cpu1.dcache.overall_misses::cpu1.data 219201 # number of overall misses
559system.cpu1.dcache.overall_misses::total 219201 # number of overall misses
560system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773572 # number of ReadReq accesses(hits+misses)
561system.cpu1.dcache.ReadReq_accesses::total 2773572 # number of ReadReq accesses(hits+misses)
562system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses)
563system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses)
564system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses)
565system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses)
566system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses)
567system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses)
568system.cpu1.dcache.demand_accesses::cpu1.data 4806532 # number of demand (read+write) accesses
569system.cpu1.dcache.demand_accesses::total 4806532 # number of demand (read+write) accesses
570system.cpu1.dcache.overall_accesses::cpu1.data 4806532 # number of overall (read+write) accesses
571system.cpu1.dcache.overall_accesses::total 4806532 # number of overall (read+write) accesses
572system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses
573system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses
574system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses
575system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses
576system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152556 # miss rate for LoadLockedReq accesses
577system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152556 # miss rate for LoadLockedReq accesses
578system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses
579system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses
580system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses
581system.cpu1.dcache.demand_miss_rate::total 0.045605 # miss rate for demand accesses
582system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045605 # miss rate for overall accesses
583system.cpu1.dcache.overall_miss_rate::total 0.045605 # miss rate for overall accesses
584system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
585system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
586system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
587system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
588system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
589system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
590system.cpu1.dcache.fast_writes 0 # number of fast writes performed
591system.cpu1.dcache.cache_copies 0 # number of cache copies performed
592system.cpu1.dcache.writebacks::writebacks 144531 # number of writebacks
593system.cpu1.dcache.writebacks::total 144531 # number of writebacks
594system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
595system.cpu1.icache.tags.replacements 380671 # number of replacements
596system.cpu1.icache.tags.tagsinuse 453.133725 # Cycle average of tags in use
597system.cpu1.icache.tags.total_refs 15144661 # Total number of references to valid blocks.
598system.cpu1.icache.tags.sampled_refs 381183 # Sample count of references to valid blocks.
599system.cpu1.icache.tags.avg_refs 39.730683 # Average number of references to valid blocks.
600system.cpu1.icache.tags.warmup_cycle 1859779767500 # Cycle when the warmup percentage was hit.
601system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133725 # Average occupied blocks per requestor
602system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy
603system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy
604system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
605system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id
606system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
607system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
608system.cpu1.icache.tags.tag_accesses 15907085 # Number of tag accesses
609system.cpu1.icache.tags.data_accesses 15907085 # Number of data accesses
610system.cpu1.icache.ReadReq_hits::cpu1.inst 15144661 # number of ReadReq hits
611system.cpu1.icache.ReadReq_hits::total 15144661 # number of ReadReq hits
612system.cpu1.icache.demand_hits::cpu1.inst 15144661 # number of demand (read+write) hits
613system.cpu1.icache.demand_hits::total 15144661 # number of demand (read+write) hits
614system.cpu1.icache.overall_hits::cpu1.inst 15144661 # number of overall hits
615system.cpu1.icache.overall_hits::total 15144661 # number of overall hits
616system.cpu1.icache.ReadReq_misses::cpu1.inst 381212 # number of ReadReq misses
617system.cpu1.icache.ReadReq_misses::total 381212 # number of ReadReq misses
618system.cpu1.icache.demand_misses::cpu1.inst 381212 # number of demand (read+write) misses
619system.cpu1.icache.demand_misses::total 381212 # number of demand (read+write) misses
620system.cpu1.icache.overall_misses::cpu1.inst 381212 # number of overall misses
621system.cpu1.icache.overall_misses::total 381212 # number of overall misses
622system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525873 # number of ReadReq accesses(hits+misses)
623system.cpu1.icache.ReadReq_accesses::total 15525873 # number of ReadReq accesses(hits+misses)
624system.cpu1.icache.demand_accesses::cpu1.inst 15525873 # number of demand (read+write) accesses
625system.cpu1.icache.demand_accesses::total 15525873 # number of demand (read+write) accesses
626system.cpu1.icache.overall_accesses::cpu1.inst 15525873 # number of overall (read+write) accesses
627system.cpu1.icache.overall_accesses::total 15525873 # number of overall (read+write) accesses
628system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024553 # miss rate for ReadReq accesses
629system.cpu1.icache.ReadReq_miss_rate::total 0.024553 # miss rate for ReadReq accesses
630system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024553 # miss rate for demand accesses
631system.cpu1.icache.demand_miss_rate::total 0.024553 # miss rate for demand accesses
632system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024553 # miss rate for overall accesses
633system.cpu1.icache.overall_miss_rate::total 0.024553 # miss rate for overall accesses
634system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
635system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
636system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
637system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
638system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
639system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
640system.cpu1.icache.fast_writes 0 # number of fast writes performed
641system.cpu1.icache.cache_copies 0 # number of cache copies performed
642system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
643system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
644system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
645system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
646system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
647system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
648system.disk0.dma_write_txs 395 # Number of DMA write transactions.
649system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
650system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
651system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
652system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
653system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
654system.disk2.dma_write_txs 1 # Number of DMA write transactions.
655system.iobus.trans_dist::ReadReq 7628 # Transaction distribution
656system.iobus.trans_dist::ReadResp 7628 # Transaction distribution
657system.iobus.trans_dist::WriteReq 56140 # Transaction distribution
658system.iobus.trans_dist::WriteResp 14588 # Transaction distribution
659system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
660system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes)
661system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
662system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
663system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
664system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
665system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes)
666system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
667system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
668system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
669system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
670system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
671system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
672system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes)
673system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes)
674system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes)
675system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes)
676system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes)
677system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes)
678system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
679system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
680system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
681system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes)
682system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
683system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
684system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
685system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
686system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
687system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
688system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes)
689system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes)
690system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes)
691system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes)
692system.iocache.tags.replacements 41699 # number of replacements
693system.iocache.tags.tagsinuse 0.434101 # Cycle average of tags in use
694system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
695system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
696system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
697system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit.
698system.iocache.tags.occ_blocks::tsunami.ide 0.434101 # Average occupied blocks per requestor
699system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy
700system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy
701system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
702system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
703system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
704system.iocache.tags.tag_accesses 375579 # Number of tag accesses
705system.iocache.tags.data_accesses 375579 # Number of data accesses
706system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses
707system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
708system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses
709system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses
710system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses
711system.iocache.demand_misses::total 179 # number of demand (read+write) misses
712system.iocache.overall_misses::tsunami.ide 179 # number of overall misses
713system.iocache.overall_misses::total 179 # number of overall misses
714system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses)
715system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
716system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
717system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
718system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses
719system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses
720system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses
721system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses
722system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
723system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
724system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses
725system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
726system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
727system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
728system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
729system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
730system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
731system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
732system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
733system.iocache.blocked::no_targets 0 # number of cycles access was blocked
734system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
735system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
736system.iocache.fast_writes 0 # number of fast writes performed
737system.iocache.cache_copies 0 # number of cache copies performed
738system.iocache.writebacks::writebacks 41520 # number of writebacks
739system.iocache.writebacks::total 41520 # number of writebacks
740system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
741system.l2c.tags.replacements 999763 # number of replacements
742system.l2c.tags.tagsinuse 65320.982513 # Cycle average of tags in use
743system.l2c.tags.total_refs 2387511 # Total number of references to valid blocks.
744system.l2c.tags.sampled_refs 1064813 # Sample count of references to valid blocks.
745system.l2c.tags.avg_refs 2.242188 # Average number of references to valid blocks.
746system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
747system.l2c.tags.occ_blocks::writebacks 56016.894287 # Average occupied blocks per requestor
748system.l2c.tags.occ_blocks::cpu0.inst 4834.499535 # Average occupied blocks per requestor
749system.l2c.tags.occ_blocks::cpu0.data 4176.023150 # Average occupied blocks per requestor
750system.l2c.tags.occ_blocks::cpu1.inst 178.992489 # Average occupied blocks per requestor
751system.l2c.tags.occ_blocks::cpu1.data 114.573052 # Average occupied blocks per requestor
752system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy
753system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy
754system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy
755system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy
756system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy
757system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy
758system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id
759system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id
760system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id
761system.l2c.tags.age_task_id_blocks_1024::2 6125 # Occupied blocks per task id
762system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id
763system.l2c.tags.age_task_id_blocks_1024::4 48943 # Occupied blocks per task id
764system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id
765system.l2c.tags.tag_accesses 31464842 # Number of tag accesses
766system.l2c.tags.data_accesses 31464842 # Number of data accesses
767system.l2c.ReadReq_hits::cpu0.inst 606959 # number of ReadReq hits
768system.l2c.ReadReq_hits::cpu0.data 626686 # number of ReadReq hits
769system.l2c.ReadReq_hits::cpu1.inst 379549 # number of ReadReq hits
770system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits
771system.l2c.ReadReq_hits::total 1742207 # number of ReadReq hits
772system.l2c.Writeback_hits::writebacks 777528 # number of Writeback hits
773system.l2c.Writeback_hits::total 777528 # number of Writeback hits
774system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits
775system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits
776system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits
777system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits
778system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits
779system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits
780system.l2c.ReadExReq_hits::cpu0.data 111433 # number of ReadExReq hits
781system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits
782system.l2c.ReadExReq_hits::total 168036 # number of ReadExReq hits
783system.l2c.demand_hits::cpu0.inst 606959 # number of demand (read+write) hits
784system.l2c.demand_hits::cpu0.data 738119 # number of demand (read+write) hits
785system.l2c.demand_hits::cpu1.inst 379549 # number of demand (read+write) hits
786system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits
787system.l2c.demand_hits::total 1910243 # number of demand (read+write) hits
788system.l2c.overall_hits::cpu0.inst 606959 # number of overall hits
789system.l2c.overall_hits::cpu0.data 738119 # number of overall hits
790system.l2c.overall_hits::cpu1.inst 379549 # number of overall hits
791system.l2c.overall_hits::cpu1.data 185616 # number of overall hits
792system.l2c.overall_hits::total 1910243 # number of overall hits
793system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses
794system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses
795system.l2c.ReadReq_misses::cpu1.inst 1663 # number of ReadReq misses
796system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses
797system.l2c.ReadReq_misses::total 941271 # number of ReadReq misses
798system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses
799system.l2c.UpgradeReq_misses::cpu1.data 2174 # number of UpgradeReq misses
800system.l2c.UpgradeReq_misses::total 5180 # number of UpgradeReq misses
801system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses
802system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses
803system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses
804system.l2c.ReadExReq_misses::cpu0.data 113916 # number of ReadExReq misses
805system.l2c.ReadExReq_misses::cpu1.data 11069 # number of ReadExReq misses
806system.l2c.ReadExReq_misses::total 124985 # number of ReadExReq misses
807system.l2c.demand_misses::cpu0.inst 11965 # number of demand (read+write) misses
808system.l2c.demand_misses::cpu0.data 1040526 # number of demand (read+write) misses
809system.l2c.demand_misses::cpu1.inst 1663 # number of demand (read+write) misses
810system.l2c.demand_misses::cpu1.data 12102 # number of demand (read+write) misses
811system.l2c.demand_misses::total 1066256 # number of demand (read+write) misses
812system.l2c.overall_misses::cpu0.inst 11965 # number of overall misses
813system.l2c.overall_misses::cpu0.data 1040526 # number of overall misses
814system.l2c.overall_misses::cpu1.inst 1663 # number of overall misses
815system.l2c.overall_misses::cpu1.data 12102 # number of overall misses
816system.l2c.overall_misses::total 1066256 # number of overall misses
817system.l2c.ReadReq_accesses::cpu0.inst 618924 # number of ReadReq accesses(hits+misses)
818system.l2c.ReadReq_accesses::cpu0.data 1553296 # number of ReadReq accesses(hits+misses)
819system.l2c.ReadReq_accesses::cpu1.inst 381212 # number of ReadReq accesses(hits+misses)
820system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses)
821system.l2c.ReadReq_accesses::total 2683478 # number of ReadReq accesses(hits+misses)
822system.l2c.Writeback_accesses::writebacks 777528 # number of Writeback accesses(hits+misses)
823system.l2c.Writeback_accesses::total 777528 # number of Writeback accesses(hits+misses)
824system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses)
825system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses)
826system.l2c.UpgradeReq_accesses::total 5873 # number of UpgradeReq accesses(hits+misses)
827system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses)
828system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses)
829system.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses)
830system.l2c.ReadExReq_accesses::cpu0.data 225349 # number of ReadExReq accesses(hits+misses)
831system.l2c.ReadExReq_accesses::cpu1.data 67672 # number of ReadExReq accesses(hits+misses)
832system.l2c.ReadExReq_accesses::total 293021 # number of ReadExReq accesses(hits+misses)
833system.l2c.demand_accesses::cpu0.inst 618924 # number of demand (read+write) accesses
834system.l2c.demand_accesses::cpu0.data 1778645 # number of demand (read+write) accesses
835system.l2c.demand_accesses::cpu1.inst 381212 # number of demand (read+write) accesses
836system.l2c.demand_accesses::cpu1.data 197718 # number of demand (read+write) accesses
837system.l2c.demand_accesses::total 2976499 # number of demand (read+write) accesses
838system.l2c.overall_accesses::cpu0.inst 618924 # number of overall (read+write) accesses
839system.l2c.overall_accesses::cpu0.data 1778645 # number of overall (read+write) accesses
840system.l2c.overall_accesses::cpu1.inst 381212 # number of overall (read+write) accesses
841system.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses
842system.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses
843system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses
844system.l2c.ReadReq_miss_rate::cpu0.data 0.596544 # miss rate for ReadReq accesses
845system.l2c.ReadReq_miss_rate::cpu1.inst 0.004362 # miss rate for ReadReq accesses
846system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses
847system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses
848system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses
849system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses
850system.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses
851system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses
852system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses
853system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses
854system.l2c.ReadExReq_miss_rate::cpu0.data 0.505509 # miss rate for ReadExReq accesses
855system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses
856system.l2c.ReadExReq_miss_rate::total 0.426539 # miss rate for ReadExReq accesses
857system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses
858system.l2c.demand_miss_rate::cpu0.data 0.585010 # miss rate for demand accesses
859system.l2c.demand_miss_rate::cpu1.inst 0.004362 # miss rate for demand accesses
860system.l2c.demand_miss_rate::cpu1.data 0.061208 # miss rate for demand accesses
861system.l2c.demand_miss_rate::total 0.358225 # miss rate for demand accesses
862system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses
863system.l2c.overall_miss_rate::cpu0.data 0.585010 # miss rate for overall accesses
864system.l2c.overall_miss_rate::cpu1.inst 0.004362 # miss rate for overall accesses
865system.l2c.overall_miss_rate::cpu1.data 0.061208 # miss rate for overall accesses
866system.l2c.overall_miss_rate::total 0.358225 # miss rate for overall accesses
867system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
868system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
869system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
870system.l2c.blocked::no_targets 0 # number of cycles access was blocked
871system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
872system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
873system.l2c.fast_writes 0 # number of fast writes performed
874system.l2c.cache_copies 0 # number of cache copies performed
875system.l2c.writebacks::writebacks 80845 # number of writebacks
876system.l2c.writebacks::total 80845 # number of writebacks
877system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
878system.membus.trans_dist::ReadReq 948899 # Transaction distribution
879system.membus.trans_dist::ReadResp 948899 # Transaction distribution
880system.membus.trans_dist::WriteReq 14588 # Transaction distribution
881system.membus.trans_dist::WriteResp 14588 # Transaction distribution
882system.membus.trans_dist::Writeback 122365 # Transaction distribution
883system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
884system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
885system.membus.trans_dist::UpgradeReq 19616 # Transaction distribution
886system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution
887system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution
888system.membus.trans_dist::ReadExReq 126515 # Transaction distribution
889system.membus.trans_dist::ReadExResp 124290 # Transaction distribution
890system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes)
891system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256148 # Packet count per connected master and slave (bytes)
892system.membus.pkt_count_system.l2c.mem_side::total 2300222 # Packet count per connected master and slave (bytes)
893system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124982 # Packet count per connected master and slave (bytes)
894system.membus.pkt_count_system.iocache.mem_side::total 124982 # Packet count per connected master and slave (bytes)
895system.membus.pkt_count::total 2425204 # Packet count per connected master and slave (bytes)
896system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes)
897system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73369984 # Cumulative packet size per connected master and slave (bytes)
898system.membus.pkt_size_system.l2c.mem_side::total 73456146 # Cumulative packet size per connected master and slave (bytes)
899system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5328064 # Cumulative packet size per connected master and slave (bytes)
900system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes)
901system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes)
902system.membus.snoops 0 # Total snoops (count)
903system.membus.snoop_fanout::samples 1265678 # Request fanout histogram
904system.membus.snoop_fanout::mean 1 # Request fanout histogram
905system.membus.snoop_fanout::stdev 0 # Request fanout histogram
906system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
907system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
908system.membus.snoop_fanout::1 1265678 100.00% 100.00% # Request fanout histogram
909system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
910system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
911system.membus.snoop_fanout::min_value 1 # Request fanout histogram
912system.membus.snoop_fanout::max_value 1 # Request fanout histogram
913system.membus.snoop_fanout::total 1265678 # Request fanout histogram
914system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution
915system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution
916system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
917system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution
918system.toL2Bus.trans_dist::Writeback 777528 # Transaction distribution
919system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution
920system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution
921system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution
922system.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution
923system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution
924system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237890 # Packet count per connected master and slave (bytes)
925system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301779 # Packet count per connected master and slave (bytes)
926system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762424 # Packet count per connected master and slave (bytes)
927system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627155 # Packet count per connected master and slave (bytes)
928system.toL2Bus.pkt_count::total 6929248 # Packet count per connected master and slave (bytes)
929system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612480 # Cumulative packet size per connected master and slave (bytes)
930system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758587 # Cumulative packet size per connected master and slave (bytes)
931system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24397568 # Cumulative packet size per connected master and slave (bytes)
932system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes)
933system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes)
934system.toL2Bus.snoops 41895 # Total snoops (count)
935system.toL2Bus.snoop_fanout::samples 3873082 # Request fanout histogram
936system.toL2Bus.snoop_fanout::mean 3.010775 # Request fanout histogram
937system.toL2Bus.snoop_fanout::stdev 0.103240 # Request fanout histogram
938system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
939system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
940system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
941system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
942system.toL2Bus.snoop_fanout::3 3831351 98.92% 98.92% # Request fanout histogram
943system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram
944system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
945system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
946system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
947system.toL2Bus.snoop_fanout::total 3873082 # Request fanout histogram
948system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
949system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
950system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
951system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
952system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
953system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
954system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
955system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
956system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
957system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
958system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
959system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
960system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
961system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
962system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
963system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
964system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
965system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
966system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
967system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
968system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
969system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
970system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
971system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
972system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
973system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
974system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
975system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
976system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
977system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
978system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
979
980---------- End Simulation Statistics ----------