| config.ini (8983:8800b05e1cb3) | config.ini (9055:38f1926fb599) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 268 unchanged lines hidden (view full) --- 277image_file=/dist/m5/system/disks/linux-bigswap2.img 278read_only=true 279 280[system.intrctrl] 281type=IntrControl 282sys=system 283 284[system.iobus] | 1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 268 unchanged lines hidden (view full) --- 277image_file=/dist/m5/system/disks/linux-bigswap2.img 278read_only=true 279 280[system.intrctrl] 281type=IntrControl 282sys=system 283 284[system.iobus] |
| 285type=Bus | 285type=NoncoherentBus |
| 286block_size=64 | 286block_size=64 |
| 287bus_id=0 | |
| 288clock=1000 289header_cycles=1 290use_default_range=true 291width=64 292default=system.tsunami.pciconfig.pio 293master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 294slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 295 --- 43 unchanged lines hidden (view full) --- 339tgts_per_mshr=16 340trace_addr=0 341two_queue=false 342write_buffers=8 343cpu_side=system.toL2Bus.master[0] 344mem_side=system.membus.slave[2] 345 346[system.membus] | 287clock=1000 288header_cycles=1 289use_default_range=true 290width=64 291default=system.tsunami.pciconfig.pio 292master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 293slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 294 --- 43 unchanged lines hidden (view full) --- 338tgts_per_mshr=16 339trace_addr=0 340two_queue=false 341write_buffers=8 342cpu_side=system.toL2Bus.master[0] 343mem_side=system.membus.slave[2] 344 345[system.membus] |
| 347type=Bus | 346type=CoherentBus |
| 348children=badaddr_responder 349block_size=64 | 347children=badaddr_responder 348block_size=64 |
| 350bus_id=1 | |
| 351clock=1000 352header_cycles=1 353use_default_range=false 354width=64 355default=system.membus.badaddr_responder.pio 356master=system.bridge.slave system.physmem.port[0] 357slave=system.system_port system.iocache.mem_side system.l2c.mem_side 358 --- 39 unchanged lines hidden (view full) --- 398[system.terminal] 399type=Terminal 400intr_control=system.intrctrl 401number=0 402output=true 403port=3456 404 405[system.toL2Bus] | 349clock=1000 350header_cycles=1 351use_default_range=false 352width=64 353default=system.membus.badaddr_responder.pio 354master=system.bridge.slave system.physmem.port[0] 355slave=system.system_port system.iocache.mem_side system.l2c.mem_side 356 --- 39 unchanged lines hidden (view full) --- 396[system.terminal] 397type=Terminal 398intr_control=system.intrctrl 399number=0 400output=true 401port=3456 402 403[system.toL2Bus] |
| 406type=Bus | 404type=CoherentBus |
| 407block_size=64 | 405block_size=64 |
| 408bus_id=0 | |
| 409clock=1000 410header_cycles=1 411use_default_range=false 412width=64 413master=system.l2c.cpu_side 414slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 415 416[system.tsunami] --- 500 unchanged lines hidden --- | 406clock=1000 407header_cycles=1 408use_default_range=false 409width=64 410master=system.l2c.cpu_side 411slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 412 413[system.tsunami] --- 500 unchanged lines hidden --- |