1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 273 unchanged lines hidden (view full) --- 282sys=system 283 284[system.iobus] 285type=NoncoherentBus 286block_size=64 287clock=1000 288header_cycles=1 289use_default_range=true |
290width=8 |
291default=system.tsunami.pciconfig.pio 292master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side 293slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 294 295[system.iocache] 296type=BaseCache 297addr_ranges=0:8589934591 298assoc=8 --- 45 unchanged lines hidden (view full) --- 344 345[system.membus] 346type=CoherentBus 347children=badaddr_responder 348block_size=64 349clock=1000 350header_cycles=1 351use_default_range=false |
352width=8 |
353default=system.membus.badaddr_responder.pio |
354master=system.bridge.slave system.physmem.port |
355slave=system.system_port system.iocache.mem_side system.l2c.mem_side 356 357[system.membus.badaddr_responder] 358type=IsaFake 359fake_mem=false 360pio_addr=0 361pio_latency=1000 362pio_size=8 --- 38 unchanged lines hidden (view full) --- 401port=3456 402 403[system.toL2Bus] 404type=CoherentBus 405block_size=64 406clock=1000 407header_cycles=1 408use_default_range=false |
409width=8 |
410master=system.l2c.cpu_side 411slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side 412 413[system.tsunami] 414type=Tsunami 415children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart 416intrctrl=system.intrctrl 417system=system --- 496 unchanged lines hidden --- |