1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain |
18console=/arm/projectscratch/randd/systems/dist/binaries/console 19default_p_state=UNDEFINED |
20eventq_index=0 21exit_on_work_items=false 22init_param=0 |
23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux |
24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=atomic 28mem_ranges=0:134217727 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 |
33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal 37power_model=Null 38readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh |
39symbolfile= 40system_rev=1024 41system_type=34 42thermal_components= 43thermal_model=Null 44work_begin_ckpt_count=0 45work_begin_cpu_id_exit=-1 46work_begin_exit_count=0 47work_cpus_ckpt_count=0 48work_end_ckpt_count=0 49work_end_exit_count=0 50work_item_id=-1 51system_port=system.membus.slave[0] 52 53[system.bridge] 54type=Bridge 55clk_domain=system.clk_domain |
56default_p_state=UNDEFINED |
57delay=50000 58eventq_index=0 |
59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null |
63ranges=8796093022208:18446744073709551615 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain --- 5 unchanged lines hidden (view full) --- 76 77[system.cpu0] 78type=AtomicSimpleCPU 79children=dcache dtb icache interrupts isa itb tracer 80branchPred=Null 81checker=Null 82clk_domain=system.cpu_clk_domain 83cpu_id=0 |
84default_p_state=UNDEFINED |
85do_checkpoint_insts=true 86do_quiesce=true 87do_statistics_insts=true 88dtb=system.cpu0.dtb 89eventq_index=0 90fastmem=false 91function_trace=false 92function_trace_start=0 93interrupts=system.cpu0.interrupts 94isa=system.cpu0.isa 95itb=system.cpu0.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100numThreads=1 |
101p_state_clk_gate_bins=20 102p_state_clk_gate_max=1000000000000 103p_state_clk_gate_min=1000 104power_model=Null |
105profile=0 106progress_interval=0 107simpoint_start_insts= 108simulate_data_stalls=false 109simulate_inst_stalls=false 110socket_id=0 111switched_out=false 112system=system --- 5 unchanged lines hidden (view full) --- 118 119[system.cpu0.dcache] 120type=Cache 121children=tags 122addr_ranges=0:18446744073709551615 123assoc=4 124clk_domain=system.cpu_clk_domain 125clusivity=mostly_incl |
126default_p_state=UNDEFINED |
127demand_mshr_reserve=1 128eventq_index=0 129hit_latency=2 130is_read_only=false 131max_miss_count=0 132mshrs=4 |
133p_state_clk_gate_bins=20 134p_state_clk_gate_max=1000000000000 135p_state_clk_gate_min=1000 136power_model=Null |
137prefetch_on_access=false 138prefetcher=Null 139response_latency=2 140sequential_access=false 141size=32768 142system=system 143tags=system.cpu0.dcache.tags 144tgts_per_mshr=20 145write_buffers=8 146writeback_clean=false 147cpu_side=system.cpu0.dcache_port 148mem_side=system.toL2Bus.slave[1] 149 150[system.cpu0.dcache.tags] 151type=LRU 152assoc=4 153block_size=64 154clk_domain=system.cpu_clk_domain |
155default_p_state=UNDEFINED |
156eventq_index=0 157hit_latency=2 |
158p_state_clk_gate_bins=20 159p_state_clk_gate_max=1000000000000 160p_state_clk_gate_min=1000 161power_model=Null |
162sequential_access=false 163size=32768 164 165[system.cpu0.dtb] 166type=AlphaTLB 167eventq_index=0 168size=64 169 170[system.cpu0.icache] 171type=Cache 172children=tags 173addr_ranges=0:18446744073709551615 174assoc=1 175clk_domain=system.cpu_clk_domain 176clusivity=mostly_incl |
177default_p_state=UNDEFINED |
178demand_mshr_reserve=1 179eventq_index=0 180hit_latency=2 181is_read_only=true 182max_miss_count=0 183mshrs=4 |
184p_state_clk_gate_bins=20 185p_state_clk_gate_max=1000000000000 186p_state_clk_gate_min=1000 187power_model=Null |
188prefetch_on_access=false 189prefetcher=Null 190response_latency=2 191sequential_access=false 192size=32768 193system=system 194tags=system.cpu0.icache.tags 195tgts_per_mshr=20 196write_buffers=8 197writeback_clean=true 198cpu_side=system.cpu0.icache_port 199mem_side=system.toL2Bus.slave[0] 200 201[system.cpu0.icache.tags] 202type=LRU 203assoc=1 204block_size=64 205clk_domain=system.cpu_clk_domain |
206default_p_state=UNDEFINED |
207eventq_index=0 208hit_latency=2 |
209p_state_clk_gate_bins=20 210p_state_clk_gate_max=1000000000000 211p_state_clk_gate_min=1000 212power_model=Null |
213sequential_access=false 214size=32768 215 216[system.cpu0.interrupts] 217type=AlphaInterrupts 218eventq_index=0 219 220[system.cpu0.isa] --- 12 unchanged lines hidden (view full) --- 233 234[system.cpu1] 235type=AtomicSimpleCPU 236children=dcache dtb icache interrupts isa itb tracer 237branchPred=Null 238checker=Null 239clk_domain=system.cpu_clk_domain 240cpu_id=1 |
241default_p_state=UNDEFINED |
242do_checkpoint_insts=true 243do_quiesce=true 244do_statistics_insts=true 245dtb=system.cpu1.dtb 246eventq_index=0 247fastmem=false 248function_trace=false 249function_trace_start=0 250interrupts=system.cpu1.interrupts 251isa=system.cpu1.isa 252itb=system.cpu1.itb 253max_insts_all_threads=0 254max_insts_any_thread=0 255max_loads_all_threads=0 256max_loads_any_thread=0 257numThreads=1 |
258p_state_clk_gate_bins=20 259p_state_clk_gate_max=1000000000000 260p_state_clk_gate_min=1000 261power_model=Null |
262profile=0 263progress_interval=0 264simpoint_start_insts= 265simulate_data_stalls=false 266simulate_inst_stalls=false 267socket_id=0 268switched_out=false 269system=system --- 5 unchanged lines hidden (view full) --- 275 276[system.cpu1.dcache] 277type=Cache 278children=tags 279addr_ranges=0:18446744073709551615 280assoc=4 281clk_domain=system.cpu_clk_domain 282clusivity=mostly_incl |
283default_p_state=UNDEFINED |
284demand_mshr_reserve=1 285eventq_index=0 286hit_latency=2 287is_read_only=false 288max_miss_count=0 289mshrs=4 |
290p_state_clk_gate_bins=20 291p_state_clk_gate_max=1000000000000 292p_state_clk_gate_min=1000 293power_model=Null |
294prefetch_on_access=false 295prefetcher=Null 296response_latency=2 297sequential_access=false 298size=32768 299system=system 300tags=system.cpu1.dcache.tags 301tgts_per_mshr=20 302write_buffers=8 303writeback_clean=false 304cpu_side=system.cpu1.dcache_port 305mem_side=system.toL2Bus.slave[3] 306 307[system.cpu1.dcache.tags] 308type=LRU 309assoc=4 310block_size=64 311clk_domain=system.cpu_clk_domain |
312default_p_state=UNDEFINED |
313eventq_index=0 314hit_latency=2 |
315p_state_clk_gate_bins=20 316p_state_clk_gate_max=1000000000000 317p_state_clk_gate_min=1000 318power_model=Null |
319sequential_access=false 320size=32768 321 322[system.cpu1.dtb] 323type=AlphaTLB 324eventq_index=0 325size=64 326 327[system.cpu1.icache] 328type=Cache 329children=tags 330addr_ranges=0:18446744073709551615 331assoc=1 332clk_domain=system.cpu_clk_domain 333clusivity=mostly_incl |
334default_p_state=UNDEFINED |
335demand_mshr_reserve=1 336eventq_index=0 337hit_latency=2 338is_read_only=true 339max_miss_count=0 340mshrs=4 |
341p_state_clk_gate_bins=20 342p_state_clk_gate_max=1000000000000 343p_state_clk_gate_min=1000 344power_model=Null |
345prefetch_on_access=false 346prefetcher=Null 347response_latency=2 348sequential_access=false 349size=32768 350system=system 351tags=system.cpu1.icache.tags 352tgts_per_mshr=20 353write_buffers=8 354writeback_clean=true 355cpu_side=system.cpu1.icache_port 356mem_side=system.toL2Bus.slave[2] 357 358[system.cpu1.icache.tags] 359type=LRU 360assoc=1 361block_size=64 362clk_domain=system.cpu_clk_domain |
363default_p_state=UNDEFINED |
364eventq_index=0 365hit_latency=2 |
366p_state_clk_gate_bins=20 367p_state_clk_gate_max=1000000000000 368p_state_clk_gate_min=1000 369power_model=Null |
370sequential_access=false 371size=32768 372 373[system.cpu1.interrupts] 374type=AlphaInterrupts 375eventq_index=0 376 377[system.cpu1.isa] --- 33 unchanged lines hidden (view full) --- 411eventq_index=0 412image_file= 413read_only=false 414table_size=65536 415 416[system.disk0.image.child] 417type=RawDiskImage 418eventq_index=0 |
419image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img |
420read_only=true 421 422[system.disk2] 423type=IdeDisk 424children=image 425delay=1000000 426driveID=master 427eventq_index=0 --- 6 unchanged lines hidden (view full) --- 434eventq_index=0 435image_file= 436read_only=false 437table_size=65536 438 439[system.disk2.image.child] 440type=RawDiskImage 441eventq_index=0 |
442image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img |
443read_only=true 444 445[system.dvfs_handler] 446type=DVFSHandler 447domains= 448enable=false 449eventq_index=0 450sys_clk_domain=system.clk_domain 451transition_latency=100000000 452 453[system.intrctrl] 454type=IntrControl 455eventq_index=0 456sys=system 457 458[system.iobus] 459type=NoncoherentXBar 460clk_domain=system.clk_domain |
461default_p_state=UNDEFINED |
462eventq_index=0 463forward_latency=1 464frontend_latency=2 |
465p_state_clk_gate_bins=20 466p_state_clk_gate_max=1000000000000 467p_state_clk_gate_min=1000 468power_model=Null |
469response_latency=2 470use_default_range=false 471width=16 472master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 473slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 474 475[system.iocache] 476type=Cache 477children=tags 478addr_ranges=0:134217727 479assoc=8 480clk_domain=system.clk_domain 481clusivity=mostly_incl |
482default_p_state=UNDEFINED |
483demand_mshr_reserve=1 484eventq_index=0 485hit_latency=50 486is_read_only=false 487max_miss_count=0 488mshrs=20 |
489p_state_clk_gate_bins=20 490p_state_clk_gate_max=1000000000000 491p_state_clk_gate_min=1000 492power_model=Null |
493prefetch_on_access=false 494prefetcher=Null 495response_latency=50 496sequential_access=false 497size=1024 498system=system 499tags=system.iocache.tags 500tgts_per_mshr=12 501write_buffers=8 502writeback_clean=false 503cpu_side=system.iobus.master[27] 504mem_side=system.membus.slave[2] 505 506[system.iocache.tags] 507type=LRU 508assoc=8 509block_size=64 510clk_domain=system.clk_domain |
511default_p_state=UNDEFINED |
512eventq_index=0 513hit_latency=50 |
514p_state_clk_gate_bins=20 515p_state_clk_gate_max=1000000000000 516p_state_clk_gate_min=1000 517power_model=Null |
518sequential_access=false 519size=1024 520 521[system.l2c] 522type=Cache 523children=tags 524addr_ranges=0:18446744073709551615 525assoc=8 526clk_domain=system.cpu_clk_domain 527clusivity=mostly_incl |
528default_p_state=UNDEFINED |
529demand_mshr_reserve=1 530eventq_index=0 531hit_latency=20 532is_read_only=false 533max_miss_count=0 534mshrs=20 |
535p_state_clk_gate_bins=20 536p_state_clk_gate_max=1000000000000 537p_state_clk_gate_min=1000 538power_model=Null |
539prefetch_on_access=false 540prefetcher=Null 541response_latency=20 542sequential_access=false 543size=4194304 544system=system 545tags=system.l2c.tags 546tgts_per_mshr=12 547write_buffers=8 548writeback_clean=false 549cpu_side=system.toL2Bus.master[0] 550mem_side=system.membus.slave[1] 551 552[system.l2c.tags] 553type=LRU 554assoc=8 555block_size=64 556clk_domain=system.cpu_clk_domain |
557default_p_state=UNDEFINED |
558eventq_index=0 559hit_latency=20 |
560p_state_clk_gate_bins=20 561p_state_clk_gate_max=1000000000000 562p_state_clk_gate_min=1000 563power_model=Null |
564sequential_access=false 565size=4194304 566 567[system.membus] 568type=CoherentXBar |
569children=badaddr_responder snoop_filter |
570clk_domain=system.clk_domain |
571default_p_state=UNDEFINED |
572eventq_index=0 573forward_latency=4 574frontend_latency=3 |
575p_state_clk_gate_bins=20 576p_state_clk_gate_max=1000000000000 577p_state_clk_gate_min=1000 |
578point_of_coherency=true |
579power_model=Null |
580response_latency=2 |
581snoop_filter=system.membus.snoop_filter |
582snoop_response_latency=4 583system=system 584use_default_range=false 585width=16 586default=system.membus.badaddr_responder.pio 587master=system.bridge.slave system.physmem.port 588slave=system.system_port system.l2c.mem_side system.iocache.mem_side 589 590[system.membus.badaddr_responder] 591type=IsaFake 592clk_domain=system.clk_domain |
593default_p_state=UNDEFINED |
594eventq_index=0 595fake_mem=false |
596p_state_clk_gate_bins=20 597p_state_clk_gate_max=1000000000000 598p_state_clk_gate_min=1000 |
599pio_addr=0 600pio_latency=100000 601pio_size=8 |
602power_model=Null |
603ret_bad_addr=true 604ret_data16=65535 605ret_data32=4294967295 606ret_data64=18446744073709551615 607ret_data8=255 608system=system 609update_data=false 610warn_access= 611pio=system.membus.default 612 |
613[system.membus.snoop_filter] 614type=SnoopFilter 615eventq_index=0 616lookup_latency=1 617max_capacity=8388608 618system=system 619 |
620[system.physmem] 621type=SimpleMemory 622bandwidth=73.000000 623clk_domain=system.clk_domain 624conf_table_reported=true |
625default_p_state=UNDEFINED |
626eventq_index=0 627in_addr_map=true 628latency=30000 629latency_var=0 630null=false |
631p_state_clk_gate_bins=20 632p_state_clk_gate_max=1000000000000 633p_state_clk_gate_min=1000 634power_model=Null |
635range=0:134217727 636port=system.membus.master[1] 637 638[system.simple_disk] 639type=SimpleDisk 640children=disk 641disk=system.simple_disk.disk 642eventq_index=0 643system=system 644 645[system.simple_disk.disk] 646type=RawDiskImage 647eventq_index=0 |
648image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img |
649read_only=true 650 651[system.terminal] 652type=Terminal 653eventq_index=0 654intr_control=system.intrctrl 655number=0 656output=true 657port=3456 658 659[system.toL2Bus] 660type=CoherentXBar 661children=snoop_filter 662clk_domain=system.cpu_clk_domain |
663default_p_state=UNDEFINED |
664eventq_index=0 665forward_latency=0 666frontend_latency=1 |
667p_state_clk_gate_bins=20 668p_state_clk_gate_max=1000000000000 669p_state_clk_gate_min=1000 |
670point_of_coherency=false |
671power_model=Null |
672response_latency=1 673snoop_filter=system.toL2Bus.snoop_filter 674snoop_response_latency=1 675system=system 676use_default_range=false 677width=32 678master=system.l2c.cpu_side 679slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side --- 11 unchanged lines hidden (view full) --- 691eventq_index=0 692intrctrl=system.intrctrl 693system=system 694 695[system.tsunami.backdoor] 696type=AlphaBackdoor 697clk_domain=system.clk_domain 698cpu=system.cpu0 |
699default_p_state=UNDEFINED |
700disk=system.simple_disk 701eventq_index=0 |
702p_state_clk_gate_bins=20 703p_state_clk_gate_max=1000000000000 704p_state_clk_gate_min=1000 |
705pio_addr=8804682956800 706pio_latency=100000 707platform=system.tsunami |
708power_model=Null |
709system=system 710terminal=system.terminal 711pio=system.iobus.master[24] 712 713[system.tsunami.cchip] 714type=TsunamiCChip 715clk_domain=system.clk_domain |
716default_p_state=UNDEFINED |
717eventq_index=0 |
718p_state_clk_gate_bins=20 719p_state_clk_gate_max=1000000000000 720p_state_clk_gate_min=1000 |
721pio_addr=8803072344064 722pio_latency=100000 |
723power_model=Null |
724system=system 725tsunami=system.tsunami 726pio=system.iobus.master[0] 727 728[system.tsunami.ethernet] 729type=NSGigE 730BAR0=1 731BAR0LegacyIO=false --- 64 unchanged lines hidden (view full) --- 796Revision=0 797Status=656 798SubClassCode=0 799SubsystemID=0 800SubsystemVendorID=0 801VendorID=4107 802clk_domain=system.clk_domain 803config_latency=20000 |
804default_p_state=UNDEFINED |
805dma_data_free=false 806dma_desc_free=false 807dma_no_allocate=true 808dma_read_delay=0 809dma_read_factor=0 810dma_write_delay=0 811dma_write_factor=0 812eventq_index=0 813hardware_address=00:90:00:00:00:01 814host=system.tsunami.pchip 815intr_delay=10000000 |
816p_state_clk_gate_bins=20 817p_state_clk_gate_max=1000000000000 818p_state_clk_gate_min=1000 |
819pci_bus=0 820pci_dev=1 821pci_func=0 822pio_latency=30000 |
823power_model=Null |
824rss=false 825rx_delay=1000000 826rx_fifo_size=524288 827rx_filter=true 828rx_thread=false 829system=system 830tx_delay=1000000 831tx_fifo_size=524288 832tx_thread=false 833dma=system.iobus.slave[2] 834pio=system.iobus.master[26] 835 836[system.tsunami.fake_OROM] 837type=IsaFake 838clk_domain=system.clk_domain |
839default_p_state=UNDEFINED |
840eventq_index=0 841fake_mem=false |
842p_state_clk_gate_bins=20 843p_state_clk_gate_max=1000000000000 844p_state_clk_gate_min=1000 |
845pio_addr=8796093677568 846pio_latency=100000 847pio_size=393216 |
848power_model=Null |
849ret_bad_addr=false 850ret_data16=65535 851ret_data32=4294967295 852ret_data64=18446744073709551615 853ret_data8=255 854system=system 855update_data=false 856warn_access= 857pio=system.iobus.master[8] 858 859[system.tsunami.fake_ata0] 860type=IsaFake 861clk_domain=system.clk_domain |
862default_p_state=UNDEFINED |
863eventq_index=0 864fake_mem=false |
865p_state_clk_gate_bins=20 866p_state_clk_gate_max=1000000000000 867p_state_clk_gate_min=1000 |
868pio_addr=8804615848432 869pio_latency=100000 870pio_size=8 |
871power_model=Null |
872ret_bad_addr=false 873ret_data16=65535 874ret_data32=4294967295 875ret_data64=18446744073709551615 876ret_data8=255 877system=system 878update_data=false 879warn_access= 880pio=system.iobus.master[19] 881 882[system.tsunami.fake_ata1] 883type=IsaFake 884clk_domain=system.clk_domain |
885default_p_state=UNDEFINED |
886eventq_index=0 887fake_mem=false |
888p_state_clk_gate_bins=20 889p_state_clk_gate_max=1000000000000 890p_state_clk_gate_min=1000 |
891pio_addr=8804615848304 892pio_latency=100000 893pio_size=8 |
894power_model=Null |
895ret_bad_addr=false 896ret_data16=65535 897ret_data32=4294967295 898ret_data64=18446744073709551615 899ret_data8=255 900system=system 901update_data=false 902warn_access= 903pio=system.iobus.master[20] 904 905[system.tsunami.fake_pnp_addr] 906type=IsaFake 907clk_domain=system.clk_domain |
908default_p_state=UNDEFINED |
909eventq_index=0 910fake_mem=false |
911p_state_clk_gate_bins=20 912p_state_clk_gate_max=1000000000000 913p_state_clk_gate_min=1000 |
914pio_addr=8804615848569 915pio_latency=100000 916pio_size=8 |
917power_model=Null |
918ret_bad_addr=false 919ret_data16=65535 920ret_data32=4294967295 921ret_data64=18446744073709551615 922ret_data8=255 923system=system 924update_data=false 925warn_access= 926pio=system.iobus.master[9] 927 928[system.tsunami.fake_pnp_read0] 929type=IsaFake 930clk_domain=system.clk_domain |
931default_p_state=UNDEFINED |
932eventq_index=0 933fake_mem=false |
934p_state_clk_gate_bins=20 935p_state_clk_gate_max=1000000000000 936p_state_clk_gate_min=1000 |
937pio_addr=8804615848451 938pio_latency=100000 939pio_size=8 |
940power_model=Null |
941ret_bad_addr=false 942ret_data16=65535 943ret_data32=4294967295 944ret_data64=18446744073709551615 945ret_data8=255 946system=system 947update_data=false 948warn_access= 949pio=system.iobus.master[11] 950 951[system.tsunami.fake_pnp_read1] 952type=IsaFake 953clk_domain=system.clk_domain |
954default_p_state=UNDEFINED |
955eventq_index=0 956fake_mem=false |
957p_state_clk_gate_bins=20 958p_state_clk_gate_max=1000000000000 959p_state_clk_gate_min=1000 |
960pio_addr=8804615848515 961pio_latency=100000 962pio_size=8 |
963power_model=Null |
964ret_bad_addr=false 965ret_data16=65535 966ret_data32=4294967295 967ret_data64=18446744073709551615 968ret_data8=255 969system=system 970update_data=false 971warn_access= 972pio=system.iobus.master[12] 973 974[system.tsunami.fake_pnp_read2] 975type=IsaFake 976clk_domain=system.clk_domain |
977default_p_state=UNDEFINED |
978eventq_index=0 979fake_mem=false |
980p_state_clk_gate_bins=20 981p_state_clk_gate_max=1000000000000 982p_state_clk_gate_min=1000 |
983pio_addr=8804615848579 984pio_latency=100000 985pio_size=8 |
986power_model=Null |
987ret_bad_addr=false 988ret_data16=65535 989ret_data32=4294967295 990ret_data64=18446744073709551615 991ret_data8=255 992system=system 993update_data=false 994warn_access= 995pio=system.iobus.master[13] 996 997[system.tsunami.fake_pnp_read3] 998type=IsaFake 999clk_domain=system.clk_domain |
1000default_p_state=UNDEFINED |
1001eventq_index=0 1002fake_mem=false |
1003p_state_clk_gate_bins=20 1004p_state_clk_gate_max=1000000000000 1005p_state_clk_gate_min=1000 |
1006pio_addr=8804615848643 1007pio_latency=100000 1008pio_size=8 |
1009power_model=Null |
1010ret_bad_addr=false 1011ret_data16=65535 1012ret_data32=4294967295 1013ret_data64=18446744073709551615 1014ret_data8=255 1015system=system 1016update_data=false 1017warn_access= 1018pio=system.iobus.master[14] 1019 1020[system.tsunami.fake_pnp_read4] 1021type=IsaFake 1022clk_domain=system.clk_domain |
1023default_p_state=UNDEFINED |
1024eventq_index=0 1025fake_mem=false |
1026p_state_clk_gate_bins=20 1027p_state_clk_gate_max=1000000000000 1028p_state_clk_gate_min=1000 |
1029pio_addr=8804615848707 1030pio_latency=100000 1031pio_size=8 |
1032power_model=Null |
1033ret_bad_addr=false 1034ret_data16=65535 1035ret_data32=4294967295 1036ret_data64=18446744073709551615 1037ret_data8=255 1038system=system 1039update_data=false 1040warn_access= 1041pio=system.iobus.master[15] 1042 1043[system.tsunami.fake_pnp_read5] 1044type=IsaFake 1045clk_domain=system.clk_domain |
1046default_p_state=UNDEFINED |
1047eventq_index=0 1048fake_mem=false |
1049p_state_clk_gate_bins=20 1050p_state_clk_gate_max=1000000000000 1051p_state_clk_gate_min=1000 |
1052pio_addr=8804615848771 1053pio_latency=100000 1054pio_size=8 |
1055power_model=Null |
1056ret_bad_addr=false 1057ret_data16=65535 1058ret_data32=4294967295 1059ret_data64=18446744073709551615 1060ret_data8=255 1061system=system 1062update_data=false 1063warn_access= 1064pio=system.iobus.master[16] 1065 1066[system.tsunami.fake_pnp_read6] 1067type=IsaFake 1068clk_domain=system.clk_domain |
1069default_p_state=UNDEFINED |
1070eventq_index=0 1071fake_mem=false |
1072p_state_clk_gate_bins=20 1073p_state_clk_gate_max=1000000000000 1074p_state_clk_gate_min=1000 |
1075pio_addr=8804615848835 1076pio_latency=100000 1077pio_size=8 |
1078power_model=Null |
1079ret_bad_addr=false 1080ret_data16=65535 1081ret_data32=4294967295 1082ret_data64=18446744073709551615 1083ret_data8=255 1084system=system 1085update_data=false 1086warn_access= 1087pio=system.iobus.master[17] 1088 1089[system.tsunami.fake_pnp_read7] 1090type=IsaFake 1091clk_domain=system.clk_domain |
1092default_p_state=UNDEFINED |
1093eventq_index=0 1094fake_mem=false |
1095p_state_clk_gate_bins=20 1096p_state_clk_gate_max=1000000000000 1097p_state_clk_gate_min=1000 |
1098pio_addr=8804615848899 1099pio_latency=100000 1100pio_size=8 |
1101power_model=Null |
1102ret_bad_addr=false 1103ret_data16=65535 1104ret_data32=4294967295 1105ret_data64=18446744073709551615 1106ret_data8=255 1107system=system 1108update_data=false 1109warn_access= 1110pio=system.iobus.master[18] 1111 1112[system.tsunami.fake_pnp_write] 1113type=IsaFake 1114clk_domain=system.clk_domain |
1115default_p_state=UNDEFINED |
1116eventq_index=0 1117fake_mem=false |
1118p_state_clk_gate_bins=20 1119p_state_clk_gate_max=1000000000000 1120p_state_clk_gate_min=1000 |
1121pio_addr=8804615850617 1122pio_latency=100000 1123pio_size=8 |
1124power_model=Null |
1125ret_bad_addr=false 1126ret_data16=65535 1127ret_data32=4294967295 1128ret_data64=18446744073709551615 1129ret_data8=255 1130system=system 1131update_data=false 1132warn_access= 1133pio=system.iobus.master[10] 1134 1135[system.tsunami.fake_ppc] 1136type=IsaFake 1137clk_domain=system.clk_domain |
1138default_p_state=UNDEFINED |
1139eventq_index=0 1140fake_mem=false |
1141p_state_clk_gate_bins=20 1142p_state_clk_gate_max=1000000000000 1143p_state_clk_gate_min=1000 |
1144pio_addr=8804615848891 1145pio_latency=100000 1146pio_size=8 |
1147power_model=Null |
1148ret_bad_addr=false 1149ret_data16=65535 1150ret_data32=4294967295 1151ret_data64=18446744073709551615 1152ret_data8=255 1153system=system 1154update_data=false 1155warn_access= 1156pio=system.iobus.master[7] 1157 1158[system.tsunami.fake_sm_chip] 1159type=IsaFake 1160clk_domain=system.clk_domain |
1161default_p_state=UNDEFINED |
1162eventq_index=0 1163fake_mem=false |
1164p_state_clk_gate_bins=20 1165p_state_clk_gate_max=1000000000000 1166p_state_clk_gate_min=1000 |
1167pio_addr=8804615848816 1168pio_latency=100000 1169pio_size=8 |
1170power_model=Null |
1171ret_bad_addr=false 1172ret_data16=65535 1173ret_data32=4294967295 1174ret_data64=18446744073709551615 1175ret_data8=255 1176system=system 1177update_data=false 1178warn_access= 1179pio=system.iobus.master[2] 1180 1181[system.tsunami.fake_uart1] 1182type=IsaFake 1183clk_domain=system.clk_domain |
1184default_p_state=UNDEFINED |
1185eventq_index=0 1186fake_mem=false |
1187p_state_clk_gate_bins=20 1188p_state_clk_gate_max=1000000000000 1189p_state_clk_gate_min=1000 |
1190pio_addr=8804615848696 1191pio_latency=100000 1192pio_size=8 |
1193power_model=Null |
1194ret_bad_addr=false 1195ret_data16=65535 1196ret_data32=4294967295 1197ret_data64=18446744073709551615 1198ret_data8=255 1199system=system 1200update_data=false 1201warn_access= 1202pio=system.iobus.master[3] 1203 1204[system.tsunami.fake_uart2] 1205type=IsaFake 1206clk_domain=system.clk_domain |
1207default_p_state=UNDEFINED |
1208eventq_index=0 1209fake_mem=false |
1210p_state_clk_gate_bins=20 1211p_state_clk_gate_max=1000000000000 1212p_state_clk_gate_min=1000 |
1213pio_addr=8804615848936 1214pio_latency=100000 1215pio_size=8 |
1216power_model=Null |
1217ret_bad_addr=false 1218ret_data16=65535 1219ret_data32=4294967295 1220ret_data64=18446744073709551615 1221ret_data8=255 1222system=system 1223update_data=false 1224warn_access= 1225pio=system.iobus.master[4] 1226 1227[system.tsunami.fake_uart3] 1228type=IsaFake 1229clk_domain=system.clk_domain |
1230default_p_state=UNDEFINED |
1231eventq_index=0 1232fake_mem=false |
1233p_state_clk_gate_bins=20 1234p_state_clk_gate_max=1000000000000 1235p_state_clk_gate_min=1000 |
1236pio_addr=8804615848680 1237pio_latency=100000 1238pio_size=8 |
1239power_model=Null |
1240ret_bad_addr=false 1241ret_data16=65535 1242ret_data32=4294967295 1243ret_data64=18446744073709551615 1244ret_data8=255 1245system=system 1246update_data=false 1247warn_access= 1248pio=system.iobus.master[5] 1249 1250[system.tsunami.fake_uart4] 1251type=IsaFake 1252clk_domain=system.clk_domain |
1253default_p_state=UNDEFINED |
1254eventq_index=0 1255fake_mem=false |
1256p_state_clk_gate_bins=20 1257p_state_clk_gate_max=1000000000000 1258p_state_clk_gate_min=1000 |
1259pio_addr=8804615848944 1260pio_latency=100000 1261pio_size=8 |
1262power_model=Null |
1263ret_bad_addr=false 1264ret_data16=65535 1265ret_data32=4294967295 1266ret_data64=18446744073709551615 1267ret_data8=255 1268system=system 1269update_data=false 1270warn_access= 1271pio=system.iobus.master[6] 1272 1273[system.tsunami.fb] 1274type=BadDevice 1275clk_domain=system.clk_domain |
1276default_p_state=UNDEFINED |
1277devicename=FrameBuffer 1278eventq_index=0 |
1279p_state_clk_gate_bins=20 1280p_state_clk_gate_max=1000000000000 1281p_state_clk_gate_min=1000 |
1282pio_addr=8804615848912 1283pio_latency=100000 |
1284power_model=Null |
1285system=system 1286pio=system.iobus.master[21] 1287 1288[system.tsunami.ide] 1289type=IdeController 1290BAR0=1 1291BAR0LegacyIO=false 1292BAR0Size=8 --- 64 unchanged lines hidden (view full) --- 1357Status=640 1358SubClassCode=1 1359SubsystemID=0 1360SubsystemVendorID=0 1361VendorID=32902 1362clk_domain=system.clk_domain 1363config_latency=20000 1364ctrl_offset=0 |
1365default_p_state=UNDEFINED |
1366disks=system.disk0 system.disk2 1367eventq_index=0 1368host=system.tsunami.pchip 1369io_shift=0 |
1370p_state_clk_gate_bins=20 1371p_state_clk_gate_max=1000000000000 1372p_state_clk_gate_min=1000 |
1373pci_bus=0 1374pci_dev=0 1375pci_func=0 1376pio_latency=30000 |
1377power_model=Null |
1378system=system 1379dma=system.iobus.slave[1] 1380pio=system.iobus.master[25] 1381 1382[system.tsunami.io] 1383type=TsunamiIO 1384clk_domain=system.clk_domain |
1385default_p_state=UNDEFINED |
1386eventq_index=0 1387frequency=976562500 |
1388p_state_clk_gate_bins=20 1389p_state_clk_gate_max=1000000000000 1390p_state_clk_gate_min=1000 |
1391pio_addr=8804615847936 1392pio_latency=100000 |
1393power_model=Null |
1394system=system 1395time=Thu Jan 1 00:00:00 2009 1396tsunami=system.tsunami 1397year_is_bcd=false 1398pio=system.iobus.master[22] 1399 1400[system.tsunami.pchip] 1401type=TsunamiPChip 1402clk_domain=system.clk_domain 1403conf_base=8804649402368 1404conf_device_bits=8 1405conf_size=16777216 |
1406default_p_state=UNDEFINED |
1407eventq_index=0 |
1408p_state_clk_gate_bins=20 1409p_state_clk_gate_max=1000000000000 1410p_state_clk_gate_min=1000 |
1411pci_dma_base=0 1412pci_mem_base=8796093022208 1413pci_pio_base=8804615847936 1414pio_addr=8802535473152 1415pio_latency=100000 1416platform=system.tsunami |
1417power_model=Null |
1418system=system 1419tsunami=system.tsunami 1420pio=system.iobus.master[1] 1421 1422[system.tsunami.uart] 1423type=Uart8250 1424clk_domain=system.clk_domain |
1425default_p_state=UNDEFINED |
1426eventq_index=0 |
1427p_state_clk_gate_bins=20 1428p_state_clk_gate_max=1000000000000 1429p_state_clk_gate_min=1000 |
1430pio_addr=8804615848952 1431pio_latency=100000 1432platform=system.tsunami |
1433power_model=Null |
1434system=system 1435terminal=system.terminal 1436pio=system.iobus.master[23] 1437 1438[system.voltage_domain] 1439type=VoltageDomain 1440eventq_index=0 1441voltage=1.000000 1442 |