| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.144463 # Number of seconds simulated 4sim_ticks 144463317000 # Number of ticks simulated 5final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.144463 # Number of seconds simulated 4sim_ticks 144463317000 # Number of ticks simulated 5final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 66822 # Simulator instruction rate (inst/s) 8host_op_rate 111999 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 73091533 # Simulator tick rate (ticks/s) 10host_mem_usage 308580 # Number of bytes of host memory used 11host_seconds 1976.47 # Real time elapsed on the host | 7host_inst_rate 55445 # Simulator instruction rate (inst/s) 8host_op_rate 92931 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60647702 # Simulator tick rate (ticks/s) 10host_mem_usage 328672 # Number of bytes of host memory used 11host_seconds 2382.01 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory 16system.physmem.bytes_read::total 342656 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory --- 182 unchanged lines hidden (view full) --- 202system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221363384 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory 16system.physmem.bytes_read::total 342656 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217088 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217088 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3392 # Number of read requests responded to by this memory --- 182 unchanged lines hidden (view full) --- 202system.physmem.bytesPerActivate::3584 1 0.10% 99.37% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::4160 1 0.10% 99.48% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::4352 1 0.10% 99.58% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::4736 1 0.10% 99.69% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::5312 1 0.10% 99.79% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::5696 1 0.10% 99.90% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::5952 1 0.10% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 957 # Bytes accessed per row activation |
| 210system.physmem.totQLat 28805000 # Total ticks spent queuing 211system.physmem.totMemAccLat 137868750 # Total ticks spent from burst creation until serviced by the DRAM | 210system.physmem.totQLat 28783000 # Total ticks spent queuing 211system.physmem.totMemAccLat 137846750 # Total ticks spent from burst creation until serviced by the DRAM |
| 212system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers 213system.physmem.totBankLat 82293750 # Total ticks spent accessing banks | 212system.physmem.totBusLat 26770000 # Total ticks spent in databus transfers 213system.physmem.totBankLat 82293750 # Total ticks spent accessing banks |
| 214system.physmem.avgQLat 5380.09 # Average queueing delay per DRAM burst | 214system.physmem.avgQLat 5375.98 # Average queueing delay per DRAM burst |
| 215system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst 216system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 215system.physmem.avgBankLat 15370.52 # Average bank access latency per DRAM burst 216system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 217system.physmem.avgMemAccLat 25750.61 # Average memory access latency per DRAM burst | 217system.physmem.avgMemAccLat 25746.50 # Average memory access latency per DRAM burst |
| 218system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s 219system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 220system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s 221system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 222system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 223system.physmem.busUtil 0.02 # Data bus utilization in percentage 224system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 225system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 16 unchanged lines hidden (view full) --- 242system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes) 243system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes) 244system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes) 245system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes) 246system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes) 247system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) 248system.membus.data_through_bus 342656 # Total data (bytes) 249system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 218system.physmem.avgRdBW 2.37 # Average DRAM read bandwidth in MiByte/s 219system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 220system.physmem.avgRdBWSys 2.37 # Average system read bandwidth in MiByte/s 221system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 222system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 223system.physmem.busUtil 0.02 # Data bus utilization in percentage 224system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 225system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 16 unchanged lines hidden (view full) --- 242system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11034 # Packet count per connected master and slave (bytes) 243system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11034 # Packet count per connected master and slave (bytes) 244system.membus.pkt_count::total 11034 # Packet count per connected master and slave (bytes) 245system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342656 # Cumulative packet size per connected master and slave (bytes) 246system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342656 # Cumulative packet size per connected master and slave (bytes) 247system.membus.tot_pkt_size::total 342656 # Cumulative packet size per connected master and slave (bytes) 248system.membus.data_through_bus 342656 # Total data (bytes) 249system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 250system.membus.reqLayer0.occupancy 6948500 # Layer occupancy (ticks) | 250system.membus.reqLayer0.occupancy 6950000 # Layer occupancy (ticks) |
| 251system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 252system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) 253system.membus.respLayer1.utilization 0.0 # Layer utilization (%) | 251system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 252system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) 253system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 254system.cpu.branchPred.lookups 18648234 # Number of BP lookups 255system.cpu.branchPred.condPredicted 18648234 # Number of conditional branches predicted | 254system.cpu.branchPred.lookups 18648233 # Number of BP lookups 255system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted |
| 256system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. 262system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. 263system.cpu.workload.num_syscalls 400 # Number of system calls 264system.cpu.numCycles 289221873 # number of cpu cycles simulated 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 256system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 11407549 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 10790529 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. 262system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. 263system.cpu.workload.num_syscalls 400 # Number of system calls 264system.cpu.numCycles 289221873 # number of cpu cycles simulated 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 267system.cpu.fetch.icacheStallCycles 23458037 # Number of cycles fetch is stalled on an Icache miss 268system.cpu.fetch.Insts 206724223 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 18648234 # Number of branches that fetch encountered | 267system.cpu.fetch.icacheStallCycles 23458043 # Number of cycles fetch is stalled on an Icache miss 268system.cpu.fetch.Insts 206724218 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 18648233 # Number of branches that fetch encountered |
| 270system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken | 270system.cpu.fetch.predictedBranches 12110896 # Number of branches that fetch has predicted taken |
| 271system.cpu.fetch.Cycles 54209099 # Number of cycles fetch has run and was not squashing or blocked 272system.cpu.fetch.SquashCycles 15518775 # Number of cycles fetch has spent squashing | 271system.cpu.fetch.Cycles 54209097 # Number of cycles fetch has run and was not squashing or blocked 272system.cpu.fetch.SquashCycles 15518774 # Number of cycles fetch has spent squashing |
| 273system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked 274system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 275system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps 276system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR | 273system.cpu.fetch.BlockedCycles 178161359 # Number of cycles fetch has spent blocked 274system.cpu.fetch.MiscStallCycles 1571 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 275system.cpu.fetch.PendingTrapStallCycles 9111 # Number of stall cycles due to pending traps 276system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR |
| 277system.cpu.fetch.CacheLines 22353213 # Number of cache lines fetched 278system.cpu.fetch.IcacheSquashes 224062 # Number of outstanding Icache misses that were squashed 279system.cpu.fetch.rateDist::samples 269612466 # Number of instructions fetched each cycle (Total) | 277system.cpu.fetch.CacheLines 22353211 # Number of cache lines fetched 278system.cpu.fetch.IcacheSquashes 224061 # Number of outstanding Icache misses that were squashed 279system.cpu.fetch.rateDist::samples 269612469 # Number of instructions fetched each cycle (Total) |
| 280system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 280system.cpu.fetch.rateDist::mean 1.268180 # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::stdev 2.756310 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 283system.cpu.fetch.rateDist::0 216842558 80.43% 80.43% # Number of instructions fetched each cycle (Total) | 283system.cpu.fetch.rateDist::0 216842563 80.43% 80.43% # Number of instructions fetched each cycle (Total) |
| 284system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) | 284system.cpu.fetch.rateDist::1 2848142 1.06% 81.48% # Number of instructions fetched each cycle (Total) |
| 285system.cpu.fetch.rateDist::2 2312056 0.86% 82.34% # Number of instructions fetched each cycle (Total) | 285system.cpu.fetch.rateDist::2 2312055 0.86% 82.34% # Number of instructions fetched each cycle (Total) |
| 286system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) | 286system.cpu.fetch.rateDist::3 2633842 0.98% 83.32% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::4 3218714 1.19% 84.51% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::5 3388946 1.26% 85.77% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::6 3831195 1.42% 87.19% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::7 2559437 0.95% 88.14% # Number of instructions fetched each cycle (Total) |
| 291system.cpu.fetch.rateDist::8 31977576 11.86% 100.00% # Number of instructions fetched each cycle (Total) | 291system.cpu.fetch.rateDist::8 31977575 11.86% 100.00% # Number of instructions fetched each cycle (Total) |
| 292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 292system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 295system.cpu.fetch.rateDist::total 269612466 # Number of instructions fetched each cycle (Total) | 295system.cpu.fetch.rateDist::total 269612469 # Number of instructions fetched each cycle (Total) |
| 296system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle 297system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle | 296system.cpu.fetch.branchRate 0.064477 # Number of branch fetches per cycle 297system.cpu.fetch.rate 0.714760 # Number of inst fetches per cycle |
| 298system.cpu.decode.IdleCycles 36899349 # Number of cycles decode is idle 299system.cpu.decode.BlockedCycles 167130008 # Number of cycles decode is blocked 300system.cpu.decode.RunCycles 41545231 # Number of cycles decode is running | 298system.cpu.decode.IdleCycles 36899359 # Number of cycles decode is idle 299system.cpu.decode.BlockedCycles 167130004 # Number of cycles decode is blocked 300system.cpu.decode.RunCycles 41545229 # Number of cycles decode is running |
| 301system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking | 301system.cpu.decode.UnblockCycles 10264627 # Number of cycles decode is unblocking |
| 302system.cpu.decode.SquashCycles 13773251 # Number of cycles decode is squashing 303system.cpu.decode.DecodedInsts 336001478 # Number of instructions handled by decode 304system.cpu.rename.SquashCycles 13773251 # Number of cycles rename is squashing 305system.cpu.rename.IdleCycles 44972476 # Number of cycles rename is idle 306system.cpu.rename.BlockCycles 116686700 # Number of cycles rename is blocking | 302system.cpu.decode.SquashCycles 13773250 # Number of cycles decode is squashing 303system.cpu.decode.DecodedInsts 336001462 # Number of instructions handled by decode 304system.cpu.rename.SquashCycles 13773250 # Number of cycles rename is squashing 305system.cpu.rename.IdleCycles 44972487 # Number of cycles rename is idle 306system.cpu.rename.BlockCycles 116686698 # Number of cycles rename is blocking |
| 307system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst | 307system.cpu.rename.serializeStallCycles 32545 # count of cycles rename stalled for serializing inst |
| 308system.cpu.rename.RunCycles 42701692 # Number of cycles rename is running 309system.cpu.rename.UnblockCycles 51445802 # Number of cycles rename is unblocking 310system.cpu.rename.RenamedInsts 329633797 # Number of instructions processed by rename | 308system.cpu.rename.RunCycles 42701689 # Number of cycles rename is running 309system.cpu.rename.UnblockCycles 51445800 # Number of cycles rename is unblocking 310system.cpu.rename.RenamedInsts 329633775 # Number of instructions processed by rename |
| 311system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full 312system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full | 311system.cpu.rename.ROBFullEvents 10827 # Number of times rename has blocked due to ROB full 312system.cpu.rename.IQFullEvents 26123597 # Number of times rename has blocked due to IQ full |
| 313system.cpu.rename.LSQFullEvents 22730551 # Number of times rename has blocked due to LSQ full 314system.cpu.rename.RenamedOperands 382342114 # Number of destination operands rename has renamed 315system.cpu.rename.RenameLookups 917586762 # Number of register rename lookups that rename has made 316system.cpu.rename.int_rename_lookups 605878307 # Number of integer rename lookups | 313system.cpu.rename.LSQFullEvents 22730549 # Number of times rename has blocked due to LSQ full 314system.cpu.rename.RenamedOperands 382342090 # Number of destination operands rename has renamed 315system.cpu.rename.RenameLookups 917586713 # Number of register rename lookups that rename has made 316system.cpu.rename.int_rename_lookups 605878272 # Number of integer rename lookups |
| 317system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups 318system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed | 317system.cpu.rename.fp_rename_lookups 4127660 # Number of floating rename lookups 318system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed |
| 319system.cpu.rename.UndoneMaps 122912664 # Number of HB maps that are undone due to squashing | 319system.cpu.rename.UndoneMaps 122912640 # Number of HB maps that are undone due to squashing |
| 320system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed 321system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed | 320system.cpu.rename.serializingInsts 2051 # count of serializing insts renamed 321system.cpu.rename.tempSerializingInsts 2042 # count of temporary serializing insts renamed |
| 322system.cpu.rename.skidInsts 105140053 # count of insts added to the skid buffer 323system.cpu.memDep0.insertedLoads 84507278 # Number of loads inserted to the mem dependence unit. | 322system.cpu.rename.skidInsts 105140052 # count of insts added to the skid buffer 323system.cpu.memDep0.insertedLoads 84507276 # Number of loads inserted to the mem dependence unit. |
| 324system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. 325system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. 326system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. | 324system.cpu.memDep0.insertedStores 30107186 # Number of stores inserted to the mem dependence unit. 325system.cpu.memDep0.conflictingLoads 58355212 # Number of conflicting loads. 326system.cpu.memDep0.conflictingStores 18979888 # Number of conflicting stores. |
| 327system.cpu.iq.iqInstsAdded 322730912 # Number of instructions added to the IQ (excludes non-spec) | 327system.cpu.iq.iqInstsAdded 322730905 # Number of instructions added to the IQ (excludes non-spec) |
| 328system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ | 328system.cpu.iq.iqNonSpecInstsAdded 4069 # Number of non-speculative instructions added to the IQ |
| 329system.cpu.iq.iqInstsIssued 260501997 # Number of instructions issued | 329system.cpu.iq.iqInstsIssued 260501994 # Number of instructions issued |
| 330system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued | 330system.cpu.iq.iqSquashedInstsIssued 116055 # Number of squashed instructions issued |
| 331system.cpu.iq.iqSquashedInstsExamined 100987198 # Number of squashed instructions iterated over during squash; mainly for profiling 332system.cpu.iq.iqSquashedOperandsExamined 210203666 # Number of squashed operands that are examined and possibly removed from graph | 331system.cpu.iq.iqSquashedInstsExamined 100987191 # Number of squashed instructions iterated over during squash; mainly for profiling 332system.cpu.iq.iqSquashedOperandsExamined 210203655 # Number of squashed operands that are examined and possibly removed from graph |
| 333system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed | 333system.cpu.iq.iqSquashedNonSpecRemoved 2824 # Number of squashed non-spec instructions that were removed |
| 334system.cpu.iq.issued_per_cycle::samples 269612466 # Number of insts issued each cycle | 334system.cpu.iq.issued_per_cycle::samples 269612469 # Number of insts issued each cycle |
| 335system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 335system.cpu.iq.issued_per_cycle::mean 0.966209 # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::stdev 1.343680 # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 338system.cpu.iq.issued_per_cycle::0 143429906 53.20% 53.20% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::1 55567349 20.61% 73.81% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::2 34108146 12.65% 86.46% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::3 19044984 7.06% 93.52% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::4 10887633 4.04% 97.56% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::5 4152281 1.54% 99.10% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::6 1816698 0.67% 99.78% # Number of insts issued each cycle | 338system.cpu.iq.issued_per_cycle::0 143429912 53.20% 53.20% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::1 55567346 20.61% 73.81% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::2 34108148 12.65% 86.46% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::3 19044980 7.06% 93.52% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::4 10887634 4.04% 97.56% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::5 4152283 1.54% 99.10% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::6 1816697 0.67% 99.78% # Number of insts issued each cycle |
| 345system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 345system.cpu.iq.issued_per_cycle::7 472473 0.18% 99.95% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::8 132996 0.05% 100.00% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 350system.cpu.iq.issued_per_cycle::total 269612466 # Number of insts issued each cycle | 350system.cpu.iq.issued_per_cycle::total 269612469 # Number of insts issued each cycle |
| 351system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 352system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available 353system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available 354system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 378system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available 381system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available 382system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available 383system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 384system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 385system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued | 351system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 352system.cpu.iq.fu_full::IntAlu 130605 4.82% 4.82% # attempts to use FU when none available 353system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available 354system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 378system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available 381system.cpu.iq.fu_full::MemRead 2279077 84.03% 88.85% # attempts to use FU when none available 382system.cpu.iq.fu_full::MemWrite 302412 11.15% 100.00% # attempts to use FU when none available 383system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 384system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 385system.cpu.iq.FU_type_0::No_OpClass 1210810 0.46% 0.46% # Type of FU issued |
| 386system.cpu.iq.FU_type_0::IntAlu 162055945 62.21% 62.67% # Type of FU issued | 386system.cpu.iq.FU_type_0::IntAlu 162055944 62.21% 62.67% # Type of FU issued |
| 387system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued 388system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 407system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued | 387system.cpu.iq.FU_type_0::IntMult 789191 0.30% 62.98% # Type of FU issued 388system.cpu.iq.FU_type_0::IntDiv 7035649 2.70% 65.68% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatAdd 1445882 0.56% 66.23% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 407system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued |
| 415system.cpu.iq.FU_type_0::MemRead 65414515 25.11% 91.34% # Type of FU issued | 415system.cpu.iq.FU_type_0::MemRead 65414513 25.11% 91.34% # Type of FU issued |
| 416system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued 417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 416system.cpu.iq.FU_type_0::MemWrite 22550005 8.66% 100.00% # Type of FU issued 417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 419system.cpu.iq.FU_type_0::total 260501997 # Type of FU issued 420system.cpu.iq.rate 0.900700 # Inst issue rate | 419system.cpu.iq.FU_type_0::total 260501994 # Type of FU issued 420system.cpu.iq.rate 0.900699 # Inst issue rate |
| 421system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested 422system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) | 421system.cpu.iq.fu_busy_cnt 2712094 # FU busy when requested 422system.cpu.iq.fu_busy_rate 0.010411 # FU busy rate (busy events/executed inst) |
| 423system.cpu.iq.int_inst_queue_reads 788557581 # Number of integer instruction queue reads 424system.cpu.iq.int_inst_queue_writes 420384882 # Number of integer instruction queue writes 425system.cpu.iq.int_inst_queue_wakeup_accesses 255147074 # Number of integer instruction queue wakeup accesses | 423system.cpu.iq.int_inst_queue_reads 788557578 # Number of integer instruction queue reads 424system.cpu.iq.int_inst_queue_writes 420384868 # Number of integer instruction queue writes 425system.cpu.iq.int_inst_queue_wakeup_accesses 255147075 # Number of integer instruction queue wakeup accesses |
| 426system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads 427system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes 428system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses | 426system.cpu.iq.fp_inst_queue_reads 4887028 # Number of floating instruction queue reads 427system.cpu.iq.fp_inst_queue_writes 3615221 # Number of floating instruction queue writes 428system.cpu.iq.fp_inst_queue_wakeup_accesses 2349564 # Number of floating instruction queue wakeup accesses |
| 429system.cpu.iq.int_alu_accesses 259544029 # Number of integer alu accesses | 429system.cpu.iq.int_alu_accesses 259544026 # Number of integer alu accesses |
| 430system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses | 430system.cpu.iq.fp_alu_accesses 2459252 # Number of floating point alu accesses |
| 431system.cpu.iew.lsq.thread0.forwLoads 18903383 # Number of loads that had data forwarded from stores | 431system.cpu.iew.lsq.thread0.forwLoads 18903382 # Number of loads that had data forwarded from stores |
| 432system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 432system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 433system.cpu.iew.lsq.thread0.squashedLoads 27857691 # Number of loads squashed 434system.cpu.iew.lsq.thread0.ignoredResponses 25993 # Number of memory responses ignored because the instruction is squashed | 433system.cpu.iew.lsq.thread0.squashedLoads 27857689 # Number of loads squashed 434system.cpu.iew.lsq.thread0.ignoredResponses 25992 # Number of memory responses ignored because the instruction is squashed |
| 435system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations 436system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed 437system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 438system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 439system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled 440system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked 441system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 435system.cpu.iew.lsq.thread0.memOrderViolation 283319 # Number of memory ordering violations 436system.cpu.iew.lsq.thread0.squashedStores 9591469 # Number of stores squashed 437system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 438system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 439system.cpu.iew.lsq.thread0.rescheduledLoads 49752 # Number of loads that were rescheduled 440system.cpu.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked 441system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 442system.cpu.iew.iewSquashCycles 13773251 # Number of cycles IEW is squashing 443system.cpu.iew.iewBlockCycles 85040641 # Number of cycles IEW is blocking | 442system.cpu.iew.iewSquashCycles 13773250 # Number of cycles IEW is squashing 443system.cpu.iew.iewBlockCycles 85040639 # Number of cycles IEW is blocking |
| 444system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking | 444system.cpu.iew.iewUnblockCycles 5471570 # Number of cycles IEW is unblocking |
| 445system.cpu.iew.iewDispatchedInsts 322734981 # Number of instructions dispatched to IQ | 445system.cpu.iew.iewDispatchedInsts 322734974 # Number of instructions dispatched to IQ |
| 446system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch | 446system.cpu.iew.iewDispSquashedInsts 133239 # Number of squashed instructions skipped by dispatch |
| 447system.cpu.iew.iewDispLoadInsts 84507278 # Number of dispatched load instructions | 447system.cpu.iew.iewDispLoadInsts 84507276 # Number of dispatched load instructions |
| 448system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions 449system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions 450system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall 451system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall 452system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations 453system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly | 448system.cpu.iew.iewDispStoreInsts 30107186 # Number of dispatched store instructions 449system.cpu.iew.iewDispNonSpecInsts 1979 # Number of dispatched non-speculative instructions 450system.cpu.iew.iewIQFullEvents 2708196 # Number of times the IQ has become full, causing a stall 451system.cpu.iew.iewLSQFullEvents 13910 # Number of times the LSQ has become full, causing a stall 452system.cpu.iew.memOrderViolationEvents 283319 # Number of memory order violations 453system.cpu.iew.predictedTakenIncorrect 639398 # Number of branches that were predicted taken incorrectly |
| 454system.cpu.iew.predictedNotTakenIncorrect 901241 # Number of branches that were predicted not taken incorrectly 455system.cpu.iew.branchMispredicts 1540639 # Number of branch mispredicts detected at execute | 454system.cpu.iew.predictedNotTakenIncorrect 901242 # Number of branches that were predicted not taken incorrectly 455system.cpu.iew.branchMispredicts 1540640 # Number of branch mispredicts detected at execute |
| 456system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions 457system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed | 456system.cpu.iew.iewExecutedInsts 258732431 # Number of executed instructions 457system.cpu.iew.iewExecLoadInsts 64645019 # Number of load instructions executed |
| 458system.cpu.iew.iewExecSquashedInsts 1769566 # Number of squashed instructions skipped in execute | 458system.cpu.iew.iewExecSquashedInsts 1769563 # Number of squashed instructions skipped in execute |
| 459system.cpu.iew.exec_swp 0 # number of swp insts executed 460system.cpu.iew.exec_nop 0 # number of nop insts executed 461system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed | 459system.cpu.iew.exec_swp 0 # number of swp insts executed 460system.cpu.iew.exec_nop 0 # number of nop insts executed 461system.cpu.iew.exec_refs 86992194 # number of memory reference insts executed |
| 462system.cpu.iew.exec_branches 14265860 # Number of branches executed | 462system.cpu.iew.exec_branches 14265859 # Number of branches executed |
| 463system.cpu.iew.exec_stores 22347175 # Number of stores executed 464system.cpu.iew.exec_rate 0.894581 # Inst execution rate | 463system.cpu.iew.exec_stores 22347175 # Number of stores executed 464system.cpu.iew.exec_rate 0.894581 # Inst execution rate |
| 465system.cpu.iew.wb_sent 258096694 # cumulative count of insts sent to commit 466system.cpu.iew.wb_count 257496638 # cumulative count of insts written-back | 465system.cpu.iew.wb_sent 258096693 # cumulative count of insts sent to commit 466system.cpu.iew.wb_count 257496639 # cumulative count of insts written-back |
| 467system.cpu.iew.wb_producers 205928299 # num instructions producing a value | 467system.cpu.iew.wb_producers 205928299 # num instructions producing a value |
| 468system.cpu.iew.wb_consumers 369130532 # num instructions consuming a value | 468system.cpu.iew.wb_consumers 369130530 # num instructions consuming a value |
| 469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 470system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle 471system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back 472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 469system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 470system.cpu.iew.wb_rate 0.890308 # insts written-back per cycle 471system.cpu.iew.wb_fanout 0.557874 # average fanout of values written-back 472system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 473system.cpu.commit.commitSquashedInsts 101448847 # The number of squashed insts skipped by commit | 473system.cpu.commit.commitSquashedInsts 101448840 # The number of squashed insts skipped by commit |
| 474system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 475system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted | 474system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards 475system.cpu.commit.branchMispredicts 1491529 # The number of times a branch was mispredicted |
| 476system.cpu.commit.committed_per_cycle::samples 255839215 # Number of insts commited each cycle | 476system.cpu.commit.committed_per_cycle::samples 255839219 # Number of insts commited each cycle |
| 477system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 477system.cpu.commit.committed_per_cycle::mean 0.865244 # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::stdev 1.654327 # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 480system.cpu.commit.committed_per_cycle::0 156486613 61.17% 61.17% # Number of insts commited each cycle | 480system.cpu.commit.committed_per_cycle::0 156486617 61.17% 61.17% # Number of insts commited each cycle |
| 481system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle | 481system.cpu.commit.committed_per_cycle::1 57197635 22.36% 83.52% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::2 14067876 5.50% 89.02% # Number of insts commited each cycle |
| 483system.cpu.commit.committed_per_cycle::3 12054069 4.71% 93.73% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::4 4176262 1.63% 95.37% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::5 2944385 1.15% 96.52% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::6 904563 0.35% 96.87% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::7 1049057 0.41% 97.28% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::8 6958755 2.72% 100.00% # Number of insts commited each cycle | 483system.cpu.commit.committed_per_cycle::3 12054068 4.71% 93.73% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::4 4176261 1.63% 95.37% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::5 2944387 1.15% 96.52% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::6 904564 0.35% 96.87% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::7 1049058 0.41% 97.28% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::8 6958753 2.72% 100.00% # Number of insts commited each cycle |
| 489system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 489system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 492system.cpu.commit.committed_per_cycle::total 255839215 # Number of insts commited each cycle | 492system.cpu.commit.committed_per_cycle::total 255839219 # Number of insts commited each cycle |
| 493system.cpu.commit.committedInsts 132071192 # Number of instructions committed 494system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 495system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 496system.cpu.commit.refs 77165304 # Number of memory references committed 497system.cpu.commit.loads 56649587 # Number of loads committed 498system.cpu.commit.membars 0 # Number of memory barriers committed 499system.cpu.commit.branches 12326938 # Number of branches committed 500system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 501system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. 502system.cpu.commit.function_calls 797818 # Number of function calls committed. | 493system.cpu.commit.committedInsts 132071192 # Number of instructions committed 494system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed 495system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 496system.cpu.commit.refs 77165304 # Number of memory references committed 497system.cpu.commit.loads 56649587 # Number of loads committed 498system.cpu.commit.membars 0 # Number of memory barriers committed 499system.cpu.commit.branches 12326938 # Number of branches committed 500system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. 501system.cpu.commit.int_insts 219019985 # Number of committed integer instructions. 502system.cpu.commit.function_calls 797818 # Number of function calls committed. |
| 503system.cpu.commit.bw_lim_events 6958755 # number cycles where commit BW limit reached | 503system.cpu.commit.bw_lim_events 6958753 # number cycles where commit BW limit reached |
| 504system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 504system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 505system.cpu.rob.rob_reads 571692691 # The number of ROB reads 506system.cpu.rob.rob_writes 659422929 # The number of ROB writes | 505system.cpu.rob.rob_reads 571692690 # The number of ROB reads 506system.cpu.rob.rob_writes 659422914 # The number of ROB writes |
| 507system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself | 507system.cpu.timesIdled 5933064 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 508system.cpu.idleCycles 19609407 # Total number of cycles that the CPU has spent unscheduled due to idling | 508system.cpu.idleCycles 19609404 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 509system.cpu.committedInsts 132071192 # Number of Instructions Simulated 510system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 511system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated 512system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction 513system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads 514system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle 515system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads | 509system.cpu.committedInsts 132071192 # Number of Instructions Simulated 510system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated 511system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated 512system.cpu.cpi 2.189894 # CPI: Cycles Per Instruction 513system.cpu.cpi_total 2.189894 # CPI: Total CPI of All Threads 514system.cpu.ipc 0.456643 # IPC: Instructions Per Cycle 515system.cpu.ipc_total 0.456643 # IPC: Total IPC of All Threads |
| 516system.cpu.int_regfile_reads 451224157 # number of integer regfile reads | 516system.cpu.int_regfile_reads 451224153 # number of integer regfile reads |
| 517system.cpu.int_regfile_writes 233957254 # number of integer regfile writes 518system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads 519system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes | 517system.cpu.int_regfile_writes 233957254 # number of integer regfile writes 518system.cpu.fp_regfile_reads 3215586 # number of floating regfile reads 519system.cpu.fp_regfile_writes 2009211 # number of floating regfile writes |
| 520system.cpu.cc_regfile_reads 102809518 # number of cc regfile reads 521system.cpu.cc_regfile_writes 59799385 # number of cc regfile writes 522system.cpu.misc_regfile_reads 133324418 # number of misc regfile reads | 520system.cpu.cc_regfile_reads 102809513 # number of cc regfile reads 521system.cpu.cc_regfile_writes 59799383 # number of cc regfile writes 522system.cpu.misc_regfile_reads 133324417 # number of misc regfile reads |
| 523system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 524system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) 525system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution 526system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution 527system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution 528system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution 529system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution 530system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution --- 9 unchanged lines hidden (view full) --- 540system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks) 541system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 542system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks) 543system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 544system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks) 545system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 546system.cpu.icache.tags.replacements 4653 # number of replacements 547system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use | 523system.cpu.misc_regfile_writes 1689 # number of misc regfile writes 524system.cpu.toL2Bus.throughput 3898568 # Throughput (bytes/s) 525system.cpu.toL2Bus.trans_dist::ReadReq 7250 # Transaction distribution 526system.cpu.toL2Bus.trans_dist::ReadResp 7248 # Transaction distribution 527system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution 528system.cpu.toL2Bus.trans_dist::UpgradeReq 163 # Transaction distribution 529system.cpu.toL2Bus.trans_dist::UpgradeResp 163 # Transaction distribution 530system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution --- 9 unchanged lines hidden (view full) --- 540system.cpu.toL2Bus.reqLayer0.occupancy 4495500 # Layer occupancy (ticks) 541system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 542system.cpu.toL2Bus.respLayer0.occupancy 10760250 # Layer occupancy (ticks) 543system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 544system.cpu.toL2Bus.respLayer1.occupancy 3467413 # Layer occupancy (ticks) 545system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 546system.cpu.icache.tags.replacements 4653 # number of replacements 547system.cpu.icache.tags.tagsinuse 1619.938452 # Cycle average of tags in use |
| 548system.cpu.icache.tags.total_refs 22344301 # Total number of references to valid blocks. | 548system.cpu.icache.tags.total_refs 22344300 # Total number of references to valid blocks. |
| 549system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. | 549system.cpu.icache.tags.sampled_refs 6620 # Sample count of references to valid blocks. |
| 550system.cpu.icache.tags.avg_refs 3375.272054 # Average number of references to valid blocks. | 550system.cpu.icache.tags.avg_refs 3375.271903 # Average number of references to valid blocks. |
| 551system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 552system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor 553system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy 554system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy | 551system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 552system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor 553system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy 554system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy |
| 555system.cpu.icache.ReadReq_hits::cpu.inst 22344301 # number of ReadReq hits 556system.cpu.icache.ReadReq_hits::total 22344301 # number of ReadReq hits 557system.cpu.icache.demand_hits::cpu.inst 22344301 # number of demand (read+write) hits 558system.cpu.icache.demand_hits::total 22344301 # number of demand (read+write) hits 559system.cpu.icache.overall_hits::cpu.inst 22344301 # number of overall hits 560system.cpu.icache.overall_hits::total 22344301 # number of overall hits 561system.cpu.icache.ReadReq_misses::cpu.inst 8911 # number of ReadReq misses 562system.cpu.icache.ReadReq_misses::total 8911 # number of ReadReq misses 563system.cpu.icache.demand_misses::cpu.inst 8911 # number of demand (read+write) misses 564system.cpu.icache.demand_misses::total 8911 # number of demand (read+write) misses 565system.cpu.icache.overall_misses::cpu.inst 8911 # number of overall misses 566system.cpu.icache.overall_misses::total 8911 # number of overall misses 567system.cpu.icache.ReadReq_miss_latency::cpu.inst 368225749 # number of ReadReq miss cycles 568system.cpu.icache.ReadReq_miss_latency::total 368225749 # number of ReadReq miss cycles 569system.cpu.icache.demand_miss_latency::cpu.inst 368225749 # number of demand (read+write) miss cycles 570system.cpu.icache.demand_miss_latency::total 368225749 # number of demand (read+write) miss cycles 571system.cpu.icache.overall_miss_latency::cpu.inst 368225749 # number of overall miss cycles 572system.cpu.icache.overall_miss_latency::total 368225749 # number of overall miss cycles 573system.cpu.icache.ReadReq_accesses::cpu.inst 22353212 # number of ReadReq accesses(hits+misses) 574system.cpu.icache.ReadReq_accesses::total 22353212 # number of ReadReq accesses(hits+misses) 575system.cpu.icache.demand_accesses::cpu.inst 22353212 # number of demand (read+write) accesses 576system.cpu.icache.demand_accesses::total 22353212 # number of demand (read+write) accesses 577system.cpu.icache.overall_accesses::cpu.inst 22353212 # number of overall (read+write) accesses 578system.cpu.icache.overall_accesses::total 22353212 # number of overall (read+write) accesses | 555system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits 556system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits 557system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits 558system.cpu.icache.demand_hits::total 22344300 # number of demand (read+write) hits 559system.cpu.icache.overall_hits::cpu.inst 22344300 # number of overall hits 560system.cpu.icache.overall_hits::total 22344300 # number of overall hits 561system.cpu.icache.ReadReq_misses::cpu.inst 8910 # number of ReadReq misses 562system.cpu.icache.ReadReq_misses::total 8910 # number of ReadReq misses 563system.cpu.icache.demand_misses::cpu.inst 8910 # number of demand (read+write) misses 564system.cpu.icache.demand_misses::total 8910 # number of demand (read+write) misses 565system.cpu.icache.overall_misses::cpu.inst 8910 # number of overall misses 566system.cpu.icache.overall_misses::total 8910 # number of overall misses 567system.cpu.icache.ReadReq_miss_latency::cpu.inst 368144999 # number of ReadReq miss cycles 568system.cpu.icache.ReadReq_miss_latency::total 368144999 # number of ReadReq miss cycles 569system.cpu.icache.demand_miss_latency::cpu.inst 368144999 # number of demand (read+write) miss cycles 570system.cpu.icache.demand_miss_latency::total 368144999 # number of demand (read+write) miss cycles 571system.cpu.icache.overall_miss_latency::cpu.inst 368144999 # number of overall miss cycles 572system.cpu.icache.overall_miss_latency::total 368144999 # number of overall miss cycles 573system.cpu.icache.ReadReq_accesses::cpu.inst 22353210 # number of ReadReq accesses(hits+misses) 574system.cpu.icache.ReadReq_accesses::total 22353210 # number of ReadReq accesses(hits+misses) 575system.cpu.icache.demand_accesses::cpu.inst 22353210 # number of demand (read+write) accesses 576system.cpu.icache.demand_accesses::total 22353210 # number of demand (read+write) accesses 577system.cpu.icache.overall_accesses::cpu.inst 22353210 # number of overall (read+write) accesses 578system.cpu.icache.overall_accesses::total 22353210 # number of overall (read+write) accesses |
| 579system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses 580system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses 581system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses 582system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses 583system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses 584system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses | 579system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000399 # miss rate for ReadReq accesses 580system.cpu.icache.ReadReq_miss_rate::total 0.000399 # miss rate for ReadReq accesses 581system.cpu.icache.demand_miss_rate::cpu.inst 0.000399 # miss rate for demand accesses 582system.cpu.icache.demand_miss_rate::total 0.000399 # miss rate for demand accesses 583system.cpu.icache.overall_miss_rate::cpu.inst 0.000399 # miss rate for overall accesses 584system.cpu.icache.overall_miss_rate::total 0.000399 # miss rate for overall accesses |
| 585system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41322.606778 # average ReadReq miss latency 586system.cpu.icache.ReadReq_avg_miss_latency::total 41322.606778 # average ReadReq miss latency 587system.cpu.icache.demand_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency 588system.cpu.icache.demand_avg_miss_latency::total 41322.606778 # average overall miss latency 589system.cpu.icache.overall_avg_miss_latency::cpu.inst 41322.606778 # average overall miss latency 590system.cpu.icache.overall_avg_miss_latency::total 41322.606778 # average overall miss latency | 585system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41318.181706 # average ReadReq miss latency 586system.cpu.icache.ReadReq_avg_miss_latency::total 41318.181706 # average ReadReq miss latency 587system.cpu.icache.demand_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency 588system.cpu.icache.demand_avg_miss_latency::total 41318.181706 # average overall miss latency 589system.cpu.icache.overall_avg_miss_latency::cpu.inst 41318.181706 # average overall miss latency 590system.cpu.icache.overall_avg_miss_latency::total 41318.181706 # average overall miss latency |
| 591system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked 592system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked 594system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked 596system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 597system.cpu.icache.fast_writes 0 # number of fast writes performed 598system.cpu.icache.cache_copies 0 # number of cache copies performed | 591system.cpu.icache.blocked_cycles::no_mshrs 877 # number of cycles access was blocked 592system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked 594system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.icache.avg_blocked_cycles::no_mshrs 43.850000 # average number of cycles each access was blocked 596system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 597system.cpu.icache.fast_writes 0 # number of fast writes performed 598system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 599system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2127 # number of ReadReq MSHR hits 600system.cpu.icache.ReadReq_mshr_hits::total 2127 # number of ReadReq MSHR hits 601system.cpu.icache.demand_mshr_hits::cpu.inst 2127 # number of demand (read+write) MSHR hits 602system.cpu.icache.demand_mshr_hits::total 2127 # number of demand (read+write) MSHR hits 603system.cpu.icache.overall_mshr_hits::cpu.inst 2127 # number of overall MSHR hits 604system.cpu.icache.overall_mshr_hits::total 2127 # number of overall MSHR hits | 599system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2126 # number of ReadReq MSHR hits 600system.cpu.icache.ReadReq_mshr_hits::total 2126 # number of ReadReq MSHR hits 601system.cpu.icache.demand_mshr_hits::cpu.inst 2126 # number of demand (read+write) MSHR hits 602system.cpu.icache.demand_mshr_hits::total 2126 # number of demand (read+write) MSHR hits 603system.cpu.icache.overall_mshr_hits::cpu.inst 2126 # number of overall MSHR hits 604system.cpu.icache.overall_mshr_hits::total 2126 # number of overall MSHR hits |
| 605system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses 606system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses 607system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses 608system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses 609system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses 610system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses | 605system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6784 # number of ReadReq MSHR misses 606system.cpu.icache.ReadReq_mshr_misses::total 6784 # number of ReadReq MSHR misses 607system.cpu.icache.demand_mshr_misses::cpu.inst 6784 # number of demand (read+write) MSHR misses 608system.cpu.icache.demand_mshr_misses::total 6784 # number of demand (read+write) MSHR misses 609system.cpu.icache.overall_mshr_misses::cpu.inst 6784 # number of overall MSHR misses 610system.cpu.icache.overall_mshr_misses::total 6784 # number of overall MSHR misses |
| 611system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271661249 # number of ReadReq MSHR miss cycles 612system.cpu.icache.ReadReq_mshr_miss_latency::total 271661249 # number of ReadReq MSHR miss cycles 613system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271661249 # number of demand (read+write) MSHR miss cycles 614system.cpu.icache.demand_mshr_miss_latency::total 271661249 # number of demand (read+write) MSHR miss cycles 615system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271661249 # number of overall MSHR miss cycles 616system.cpu.icache.overall_mshr_miss_latency::total 271661249 # number of overall MSHR miss cycles | 611system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 271638749 # number of ReadReq MSHR miss cycles 612system.cpu.icache.ReadReq_mshr_miss_latency::total 271638749 # number of ReadReq MSHR miss cycles 613system.cpu.icache.demand_mshr_miss_latency::cpu.inst 271638749 # number of demand (read+write) MSHR miss cycles 614system.cpu.icache.demand_mshr_miss_latency::total 271638749 # number of demand (read+write) MSHR miss cycles 615system.cpu.icache.overall_mshr_miss_latency::cpu.inst 271638749 # number of overall MSHR miss cycles 616system.cpu.icache.overall_mshr_miss_latency::total 271638749 # number of overall MSHR miss cycles |
| 617system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses 618system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses 619system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses 620system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses 621system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses 622system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses | 617system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for ReadReq accesses 618system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000303 # mshr miss rate for ReadReq accesses 619system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for demand accesses 620system.cpu.icache.demand_mshr_miss_rate::total 0.000303 # mshr miss rate for demand accesses 621system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000303 # mshr miss rate for overall accesses 622system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses |
| 623system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.405808 # average ReadReq mshr miss latency 624system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40044.405808 # average ReadReq mshr miss latency 625system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency 626system.cpu.icache.demand_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency 627system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40044.405808 # average overall mshr miss latency 628system.cpu.icache.overall_avg_mshr_miss_latency::total 40044.405808 # average overall mshr miss latency | 623system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40041.089180 # average ReadReq mshr miss latency 624system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40041.089180 # average ReadReq mshr miss latency 625system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency 626system.cpu.icache.demand_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency 627system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40041.089180 # average overall mshr miss latency 628system.cpu.icache.overall_avg_mshr_miss_latency::total 40041.089180 # average overall mshr miss latency |
| 629system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 630system.cpu.l2cache.tags.replacements 0 # number of replacements | 629system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 630system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 631system.cpu.l2cache.tags.tagsinuse 2543.926921 # Cycle average of tags in use | 631system.cpu.l2cache.tags.tagsinuse 2543.926920 # Cycle average of tags in use |
| 632system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. 633system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks. 634system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks. 635system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 636system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor | 632system.cpu.l2cache.tags.total_refs 3266 # Total number of references to valid blocks. 633system.cpu.l2cache.tags.sampled_refs 3826 # Sample count of references to valid blocks. 634system.cpu.l2cache.tags.avg_refs 0.853633 # Average number of references to valid blocks. 635system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 636system.cpu.l2cache.tags.occ_blocks::writebacks 1.725256 # Average occupied blocks per requestor |
| 637system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334816 # Average occupied blocks per requestor | 637system.cpu.l2cache.tags.occ_blocks::cpu.inst 2230.334814 # Average occupied blocks per requestor |
| 638system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor 639system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy 640system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy 641system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy 642system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy 643system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits 644system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits 645system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits --- 15 unchanged lines hidden (view full) --- 661system.cpu.l2cache.ReadExReq_misses::cpu.data 1532 # number of ReadExReq misses 662system.cpu.l2cache.ReadExReq_misses::total 1532 # number of ReadExReq misses 663system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses 664system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses 665system.cpu.l2cache.demand_misses::total 5355 # number of demand (read+write) misses 666system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses 667system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses 668system.cpu.l2cache.overall_misses::total 5355 # number of overall misses | 638system.cpu.l2cache.tags.occ_blocks::cpu.data 311.866849 # Average occupied blocks per requestor 639system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 # Average percentage of cache occupancy 640system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy 641system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy 642system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy 643system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits 644system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits 645system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits --- 15 unchanged lines hidden (view full) --- 661system.cpu.l2cache.ReadExReq_misses::cpu.data 1532 # number of ReadExReq misses 662system.cpu.l2cache.ReadExReq_misses::total 1532 # number of ReadExReq misses 663system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses 664system.cpu.l2cache.demand_misses::cpu.data 1962 # number of demand (read+write) misses 665system.cpu.l2cache.demand_misses::total 5355 # number of demand (read+write) misses 666system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses 667system.cpu.l2cache.overall_misses::cpu.data 1962 # number of overall misses 668system.cpu.l2cache.overall_misses::total 5355 # number of overall misses |
| 669system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232439500 # number of ReadReq miss cycles | 669system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232417000 # number of ReadReq miss cycles |
| 670system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles | 670system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32755500 # number of ReadReq miss cycles |
| 671system.cpu.l2cache.ReadReq_miss_latency::total 265195000 # number of ReadReq miss cycles | 671system.cpu.l2cache.ReadReq_miss_latency::total 265172500 # number of ReadReq miss cycles |
| 672system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles 673system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles | 672system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104434000 # number of ReadExReq miss cycles 673system.cpu.l2cache.ReadExReq_miss_latency::total 104434000 # number of ReadExReq miss cycles |
| 674system.cpu.l2cache.demand_miss_latency::cpu.inst 232439500 # number of demand (read+write) miss cycles | 674system.cpu.l2cache.demand_miss_latency::cpu.inst 232417000 # number of demand (read+write) miss cycles |
| 675system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles | 675system.cpu.l2cache.demand_miss_latency::cpu.data 137189500 # number of demand (read+write) miss cycles |
| 676system.cpu.l2cache.demand_miss_latency::total 369629000 # number of demand (read+write) miss cycles 677system.cpu.l2cache.overall_miss_latency::cpu.inst 232439500 # number of overall miss cycles | 676system.cpu.l2cache.demand_miss_latency::total 369606500 # number of demand (read+write) miss cycles 677system.cpu.l2cache.overall_miss_latency::cpu.inst 232417000 # number of overall miss cycles |
| 678system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles | 678system.cpu.l2cache.overall_miss_latency::cpu.data 137189500 # number of overall miss cycles |
| 679system.cpu.l2cache.overall_miss_latency::total 369629000 # number of overall miss cycles | 679system.cpu.l2cache.overall_miss_latency::total 369606500 # number of overall miss cycles |
| 680system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses) 681system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses) 682system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses) 683system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) 684system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) 685system.cpu.l2cache.UpgradeReq_accesses::cpu.data 163 # number of UpgradeReq accesses(hits+misses) 686system.cpu.l2cache.UpgradeReq_accesses::total 163 # number of UpgradeReq accesses(hits+misses) 687system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 700system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995452 # miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_miss_rate::total 0.995452 # miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_miss_rate::cpu.inst 0.512538 # miss rate for demand accesses 703system.cpu.l2cache.demand_miss_rate::cpu.data 0.978554 # miss rate for demand accesses 704system.cpu.l2cache.demand_miss_rate::total 0.620870 # miss rate for demand accesses 705system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses 706system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses 707system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses | 680system.cpu.l2cache.ReadReq_accesses::cpu.inst 6620 # number of ReadReq accesses(hits+misses) 681system.cpu.l2cache.ReadReq_accesses::cpu.data 466 # number of ReadReq accesses(hits+misses) 682system.cpu.l2cache.ReadReq_accesses::total 7086 # number of ReadReq accesses(hits+misses) 683system.cpu.l2cache.Writeback_accesses::writebacks 13 # number of Writeback accesses(hits+misses) 684system.cpu.l2cache.Writeback_accesses::total 13 # number of Writeback accesses(hits+misses) 685system.cpu.l2cache.UpgradeReq_accesses::cpu.data 163 # number of UpgradeReq accesses(hits+misses) 686system.cpu.l2cache.UpgradeReq_accesses::total 163 # number of UpgradeReq accesses(hits+misses) 687system.cpu.l2cache.ReadExReq_accesses::cpu.data 1539 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 700system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995452 # miss rate for ReadExReq accesses 701system.cpu.l2cache.ReadExReq_miss_rate::total 0.995452 # miss rate for ReadExReq accesses 702system.cpu.l2cache.demand_miss_rate::cpu.inst 0.512538 # miss rate for demand accesses 703system.cpu.l2cache.demand_miss_rate::cpu.data 0.978554 # miss rate for demand accesses 704system.cpu.l2cache.demand_miss_rate::total 0.620870 # miss rate for demand accesses 705system.cpu.l2cache.overall_miss_rate::cpu.inst 0.512538 # miss rate for overall accesses 706system.cpu.l2cache.overall_miss_rate::cpu.data 0.978554 # miss rate for overall accesses 707system.cpu.l2cache.overall_miss_rate::total 0.620870 # miss rate for overall accesses |
| 708system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68505.599764 # average ReadReq miss latency | 708system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68498.968464 # average ReadReq miss latency |
| 709system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency | 709system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76175.581395 # average ReadReq miss latency |
| 710system.cpu.l2cache.ReadReq_avg_miss_latency::total 69368.297149 # average ReadReq miss latency | 710system.cpu.l2cache.ReadReq_avg_miss_latency::total 69362.411719 # average ReadReq miss latency |
| 711system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency 712system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency | 711system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68168.407311 # average ReadExReq miss latency 712system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68168.407311 # average ReadExReq miss latency |
| 713system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency | 713system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency |
| 714system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency | 714system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency |
| 715system.cpu.l2cache.demand_avg_miss_latency::total 69025.023343 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68505.599764 # average overall miss latency | 715system.cpu.l2cache.demand_avg_miss_latency::total 69020.821662 # average overall miss latency 716system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68498.968464 # average overall miss latency |
| 717system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency | 717system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69923.292559 # average overall miss latency |
| 718system.cpu.l2cache.overall_avg_miss_latency::total 69025.023343 # average overall miss latency | 718system.cpu.l2cache.overall_avg_miss_latency::total 69020.821662 # average overall miss latency |
| 719system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 722system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 724system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.l2cache.fast_writes 0 # number of fast writes performed 726system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 732system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses 733system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses 734system.cpu.l2cache.demand_mshr_misses::cpu.inst 3393 # number of demand (read+write) MSHR misses 735system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses 736system.cpu.l2cache.demand_mshr_misses::total 5355 # number of demand (read+write) MSHR misses 737system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses 738system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses 739system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses | 719system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 720system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 721system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 722system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 723system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 724system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 725system.cpu.l2cache.fast_writes 0 # number of fast writes performed 726system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 732system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1532 # number of ReadExReq MSHR misses 733system.cpu.l2cache.ReadExReq_mshr_misses::total 1532 # number of ReadExReq MSHR misses 734system.cpu.l2cache.demand_mshr_misses::cpu.inst 3393 # number of demand (read+write) MSHR misses 735system.cpu.l2cache.demand_mshr_misses::cpu.data 1962 # number of demand (read+write) MSHR misses 736system.cpu.l2cache.demand_mshr_misses::total 5355 # number of demand (read+write) MSHR misses 737system.cpu.l2cache.overall_mshr_misses::cpu.inst 3393 # number of overall MSHR misses 738system.cpu.l2cache.overall_mshr_misses::cpu.data 1962 # number of overall MSHR misses 739system.cpu.l2cache.overall_mshr_misses::total 5355 # number of overall MSHR misses |
| 740system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189922000 # number of ReadReq MSHR miss cycles | 740system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 189899500 # number of ReadReq MSHR miss cycles |
| 741system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles | 741system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27426500 # number of ReadReq MSHR miss cycles |
| 742system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217348500 # number of ReadReq MSHR miss cycles | 742system.cpu.l2cache.ReadReq_mshr_miss_latency::total 217326000 # number of ReadReq MSHR miss cycles |
| 743system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles 744system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles 745system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles 746system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles | 743system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1630163 # number of UpgradeReq MSHR miss cycles 744system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1630163 # number of UpgradeReq MSHR miss cycles 745system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 84874000 # number of ReadExReq MSHR miss cycles 746system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 84874000 # number of ReadExReq MSHR miss cycles |
| 747system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189922000 # number of demand (read+write) MSHR miss cycles | 747system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189899500 # number of demand (read+write) MSHR miss cycles |
| 748system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles | 748system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 112300500 # number of demand (read+write) MSHR miss cycles |
| 749system.cpu.l2cache.demand_mshr_miss_latency::total 302222500 # number of demand (read+write) MSHR miss cycles 750system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189922000 # number of overall MSHR miss cycles | 749system.cpu.l2cache.demand_mshr_miss_latency::total 302200000 # number of demand (read+write) MSHR miss cycles 750system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189899500 # number of overall MSHR miss cycles |
| 751system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles | 751system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 112300500 # number of overall MSHR miss cycles |
| 752system.cpu.l2cache.overall_mshr_miss_latency::total 302222500 # number of overall MSHR miss cycles | 752system.cpu.l2cache.overall_mshr_miss_latency::total 302200000 # number of overall MSHR miss cycles |
| 753system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses 754system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses 755system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses 756system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 757system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 758system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses 759system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses 760system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses 761system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses 762system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses 763system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses 764system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses 765system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses | 753system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for ReadReq accesses 754system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.922747 # mshr miss rate for ReadReq accesses 755system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.539515 # mshr miss rate for ReadReq accesses 756system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 757system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 758system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995452 # mshr miss rate for ReadExReq accesses 759system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995452 # mshr miss rate for ReadExReq accesses 760system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for demand accesses 761system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for demand accesses 762system.cpu.l2cache.demand_mshr_miss_rate::total 0.620870 # mshr miss rate for demand accesses 763system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.512538 # mshr miss rate for overall accesses 764system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.978554 # mshr miss rate for overall accesses 765system.cpu.l2cache.overall_mshr_miss_rate::total 0.620870 # mshr miss rate for overall accesses |
| 766system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55974.653699 # average ReadReq mshr miss latency | 766system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55968.022399 # average ReadReq mshr miss latency |
| 767system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency | 767system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63782.558140 # average ReadReq mshr miss latency |
| 768system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56852.864243 # average ReadReq mshr miss latency | 768system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56846.978812 # average ReadReq mshr miss latency |
| 769system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 770system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency 772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency | 769system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 770system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 771system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55400.783290 # average ReadExReq mshr miss latency 772system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55400.783290 # average ReadExReq mshr miss latency |
| 773system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency | 773system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency |
| 774system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency | 774system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency |
| 775system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency 776system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55974.653699 # average overall mshr miss latency | 775system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency 776system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55968.022399 # average overall mshr miss latency |
| 777system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency | 777system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57237.767584 # average overall mshr miss latency |
| 778system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56437.441643 # average overall mshr miss latency | 778system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56433.239963 # average overall mshr miss latency |
| 779system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 780system.cpu.dcache.tags.replacements 57 # number of replacements 781system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use | 779system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 780system.cpu.dcache.tags.replacements 57 # number of replacements 781system.cpu.dcache.tags.tagsinuse 1438.861304 # Cycle average of tags in use |
| 782system.cpu.dcache.tags.total_refs 66102355 # Total number of references to valid blocks. | 782system.cpu.dcache.tags.total_refs 66102356 # Total number of references to valid blocks. |
| 783system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. | 783system.cpu.dcache.tags.sampled_refs 2004 # Sample count of references to valid blocks. |
| 784system.cpu.dcache.tags.avg_refs 32985.207086 # Average number of references to valid blocks. | 784system.cpu.dcache.tags.avg_refs 32985.207585 # Average number of references to valid blocks. |
| 785system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 786system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor 787system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy 788system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy | 785system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 786system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor 787system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy 788system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy |
| 789system.cpu.dcache.ReadReq_hits::cpu.data 45588096 # number of ReadReq hits 790system.cpu.dcache.ReadReq_hits::total 45588096 # number of ReadReq hits | 789system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits 790system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits |
| 791system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits 792system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits | 791system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits 792system.cpu.dcache.WriteReq_hits::total 20514029 # number of WriteReq hits |
| 793system.cpu.dcache.demand_hits::cpu.data 66102125 # number of demand (read+write) hits 794system.cpu.dcache.demand_hits::total 66102125 # number of demand (read+write) hits 795system.cpu.dcache.overall_hits::cpu.data 66102125 # number of overall hits 796system.cpu.dcache.overall_hits::total 66102125 # number of overall hits | 793system.cpu.dcache.demand_hits::cpu.data 66102126 # number of demand (read+write) hits 794system.cpu.dcache.demand_hits::total 66102126 # number of demand (read+write) hits 795system.cpu.dcache.overall_hits::cpu.data 66102126 # number of overall hits 796system.cpu.dcache.overall_hits::total 66102126 # number of overall hits |
| 797system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses 798system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses 799system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses 800system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses 801system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses 802system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses 803system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses 804system.cpu.dcache.overall_misses::total 2637 # number of overall misses 805system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles 806system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles 807system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles 808system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles 809system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles 810system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles 811system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles 812system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles | 797system.cpu.dcache.ReadReq_misses::cpu.data 935 # number of ReadReq misses 798system.cpu.dcache.ReadReq_misses::total 935 # number of ReadReq misses 799system.cpu.dcache.WriteReq_misses::cpu.data 1702 # number of WriteReq misses 800system.cpu.dcache.WriteReq_misses::total 1702 # number of WriteReq misses 801system.cpu.dcache.demand_misses::cpu.data 2637 # number of demand (read+write) misses 802system.cpu.dcache.demand_misses::total 2637 # number of demand (read+write) misses 803system.cpu.dcache.overall_misses::cpu.data 2637 # number of overall misses 804system.cpu.dcache.overall_misses::total 2637 # number of overall misses 805system.cpu.dcache.ReadReq_miss_latency::cpu.data 62763567 # number of ReadReq miss cycles 806system.cpu.dcache.ReadReq_miss_latency::total 62763567 # number of ReadReq miss cycles 807system.cpu.dcache.WriteReq_miss_latency::cpu.data 113907163 # number of WriteReq miss cycles 808system.cpu.dcache.WriteReq_miss_latency::total 113907163 # number of WriteReq miss cycles 809system.cpu.dcache.demand_miss_latency::cpu.data 176670730 # number of demand (read+write) miss cycles 810system.cpu.dcache.demand_miss_latency::total 176670730 # number of demand (read+write) miss cycles 811system.cpu.dcache.overall_miss_latency::cpu.data 176670730 # number of overall miss cycles 812system.cpu.dcache.overall_miss_latency::total 176670730 # number of overall miss cycles |
| 813system.cpu.dcache.ReadReq_accesses::cpu.data 45589031 # number of ReadReq accesses(hits+misses) 814system.cpu.dcache.ReadReq_accesses::total 45589031 # number of ReadReq accesses(hits+misses) | 813system.cpu.dcache.ReadReq_accesses::cpu.data 45589032 # number of ReadReq accesses(hits+misses) 814system.cpu.dcache.ReadReq_accesses::total 45589032 # number of ReadReq accesses(hits+misses) |
| 815system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 816system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) | 815system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 816system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) |
| 817system.cpu.dcache.demand_accesses::cpu.data 66104762 # number of demand (read+write) accesses 818system.cpu.dcache.demand_accesses::total 66104762 # number of demand (read+write) accesses 819system.cpu.dcache.overall_accesses::cpu.data 66104762 # number of overall (read+write) accesses 820system.cpu.dcache.overall_accesses::total 66104762 # number of overall (read+write) accesses | 817system.cpu.dcache.demand_accesses::cpu.data 66104763 # number of demand (read+write) accesses 818system.cpu.dcache.demand_accesses::total 66104763 # number of demand (read+write) accesses 819system.cpu.dcache.overall_accesses::cpu.data 66104763 # number of overall (read+write) accesses 820system.cpu.dcache.overall_accesses::total 66104763 # number of overall (read+write) accesses |
| 821system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses 823system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses 825system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses 826system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses 827system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses 828system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses --- 61 unchanged lines hidden --- | 821system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses 823system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses 825system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses 826system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses 827system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses 828system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses --- 61 unchanged lines hidden --- |