| stats.txt (9373:26ba525347fe) | stats.txt (9449:56610ab73040) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.082648 # Number of seconds simulated 4sim_ticks 82648140000 # Number of ticks simulated 5final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.082648 # Number of seconds simulated 4sim_ticks 82648140000 # Number of ticks simulated 5final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 58118 # Simulator instruction rate (inst/s) 8host_op_rate 97410 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36369167 # Simulator tick rate (ticks/s) 10host_mem_usage 286740 # Number of bytes of host memory used 11host_seconds 2272.48 # Real time elapsed on the host | 7host_inst_rate 31465 # Simulator instruction rate (inst/s) 8host_op_rate 52738 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19690094 # Simulator tick rate (ticks/s) 10host_mem_usage 268216 # Number of bytes of host memory used 11host_seconds 4197.45 # Real time elapsed on the host |
| 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221362961 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory 16system.physmem.bytes_read::total 342144 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory --- 45 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 12sim_insts 132071192 # Number of instructions simulated 13sim_ops 221362961 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 124416 # Number of bytes read from this memory 16system.physmem.bytes_read::total 342144 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 217728 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 217728 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 3402 # Number of read requests responded to by this memory --- 45 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 82648108000 # Total gap between requests | 73system.physmem.totGap 82648109000 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 5348 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 5348 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 77 unchanged lines hidden (view full) --- 159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 167system.physmem.totQLat 16873322 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 122447322 # Sum of mem lat for all requests | 167system.physmem.totQLat 16873822 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 122447822 # Sum of mem lat for all requests |
| 169system.physmem.totBusLat 21392000 # Total cycles spent in databus access 170system.physmem.totBankLat 84182000 # Total cycles spent in bank access | 169system.physmem.totBusLat 21392000 # Total cycles spent in databus access 170system.physmem.totBankLat 84182000 # Total cycles spent in bank access |
| 171system.physmem.avgQLat 3155.07 # Average queueing delay per request | 171system.physmem.avgQLat 3155.16 # Average queueing delay per request |
| 172system.physmem.avgBankLat 15740.84 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request | 172system.physmem.avgBankLat 15740.84 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 174system.physmem.avgMemAccLat 22895.91 # Average memory access latency | 174system.physmem.avgMemAccLat 22896.00 # Average memory access latency |
| 175system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.03 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 4742 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 175system.physmem.avgRdBW 4.14 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 4.14 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.03 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 4742 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 15454021.69 # Average gap between requests | 187system.physmem.avgGap 15454021.88 # Average gap between requests |
| 188system.cpu.workload.num_syscalls 400 # Number of system calls 189system.cpu.numCycles 165296281 # number of cpu cycles simulated 190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 192system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups 193system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted 194system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect 195system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups 196system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits 197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 198system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 199system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. | 188system.cpu.workload.num_syscalls 400 # Number of system calls 189system.cpu.numCycles 165296281 # number of cpu cycles simulated 190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 192system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups 193system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted 194system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect 195system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups 196system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits 197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 198system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 199system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 200system.cpu.fetch.icacheStallCycles 25830999 # Number of cycles fetch is stalled on an Icache miss | 200system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss |
| 201system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed 202system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered 203system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken 204system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked 205system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing 206system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked | 201system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed 202system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered 203system.cpu.fetch.predictedBranches 13098591 # Number of branches that fetch has predicted taken 204system.cpu.fetch.Cycles 57573712 # Number of cycles fetch has run and was not squashing or blocked 205system.cpu.fetch.SquashCycles 17632764 # Number of cycles fetch has spent squashing 206system.cpu.fetch.BlockedCycles 66415443 # Number of cycles fetch has spent blocked |
| 207system.cpu.fetch.MiscStallCycles 241 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 207system.cpu.fetch.MiscStallCycles 240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 208system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps 209system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR | 208system.cpu.fetch.PendingTrapStallCycles 1579 # Number of stall cycles due to pending traps 209system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR |
| 210system.cpu.fetch.CacheLines 24446052 # Number of cache lines fetched 211system.cpu.fetch.IcacheSquashes 431778 # Number of outstanding Icache misses that were squashed | 210system.cpu.fetch.CacheLines 24446053 # Number of cache lines fetched 211system.cpu.fetch.IcacheSquashes 431779 # Number of outstanding Icache misses that were squashed |
| 212system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total) --- 229 unchanged lines hidden (view full) --- 449system.cpu.ipc_total 0.798997 # IPC: Total IPC of All Threads 450system.cpu.int_regfile_reads 562635091 # number of integer regfile reads 451system.cpu.int_regfile_writes 298739906 # number of integer regfile writes 452system.cpu.fp_regfile_reads 3520410 # number of floating regfile reads 453system.cpu.fp_regfile_writes 2230055 # number of floating regfile writes 454system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads 455system.cpu.misc_regfile_writes 844 # number of misc regfile writes 456system.cpu.icache.replacements 4732 # number of replacements | 212system.cpu.fetch.rateDist::samples 165175969 # Number of instructions fetched each cycle (Total) 213system.cpu.fetch.rateDist::mean 2.190116 # Number of instructions fetched each cycle (Total) 214system.cpu.fetch.rateDist::stdev 3.327383 # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::0 109199449 66.11% 66.11% # Number of instructions fetched each cycle (Total) 217system.cpu.fetch.rateDist::1 3061509 1.85% 67.96% # Number of instructions fetched each cycle (Total) 218system.cpu.fetch.rateDist::2 2383315 1.44% 69.41% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::3 2892599 1.75% 71.16% # Number of instructions fetched each cycle (Total) --- 229 unchanged lines hidden (view full) --- 449system.cpu.ipc_total 0.798997 # IPC: Total IPC of All Threads 450system.cpu.int_regfile_reads 562635091 # number of integer regfile reads 451system.cpu.int_regfile_writes 298739906 # number of integer regfile writes 452system.cpu.fp_regfile_reads 3520410 # number of floating regfile reads 453system.cpu.fp_regfile_writes 2230055 # number of floating regfile writes 454system.cpu.misc_regfile_reads 137014018 # number of misc regfile reads 455system.cpu.misc_regfile_writes 844 # number of misc regfile writes 456system.cpu.icache.replacements 4732 # number of replacements |
| 457system.cpu.icache.tagsinuse 1624.168421 # Cycle average of tags in use | 457system.cpu.icache.tagsinuse 1624.168426 # Cycle average of tags in use |
| 458system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. 459system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. 460system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. 461system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 458system.cpu.icache.total_refs 24437101 # Total number of references to valid blocks. 459system.cpu.icache.sampled_refs 6701 # Sample count of references to valid blocks. 460system.cpu.icache.avg_refs 3646.784211 # Average number of references to valid blocks. 461system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 462system.cpu.icache.occ_blocks::cpu.inst 1624.168421 # Average occupied blocks per requestor | 462system.cpu.icache.occ_blocks::cpu.inst 1624.168426 # Average occupied blocks per requestor |
| 463system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy 464system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy 465system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits 466system.cpu.icache.ReadReq_hits::total 24437101 # number of ReadReq hits 467system.cpu.icache.demand_hits::cpu.inst 24437101 # number of demand (read+write) hits 468system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits 469system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits 470system.cpu.icache.overall_hits::total 24437101 # number of overall hits | 463system.cpu.icache.occ_percent::cpu.inst 0.793051 # Average percentage of cache occupancy 464system.cpu.icache.occ_percent::total 0.793051 # Average percentage of cache occupancy 465system.cpu.icache.ReadReq_hits::cpu.inst 24437101 # number of ReadReq hits 466system.cpu.icache.ReadReq_hits::total 24437101 # number of ReadReq hits 467system.cpu.icache.demand_hits::cpu.inst 24437101 # number of demand (read+write) hits 468system.cpu.icache.demand_hits::total 24437101 # number of demand (read+write) hits 469system.cpu.icache.overall_hits::cpu.inst 24437101 # number of overall hits 470system.cpu.icache.overall_hits::total 24437101 # number of overall hits |
| 471system.cpu.icache.ReadReq_misses::cpu.inst 8951 # number of ReadReq misses 472system.cpu.icache.ReadReq_misses::total 8951 # number of ReadReq misses 473system.cpu.icache.demand_misses::cpu.inst 8951 # number of demand (read+write) misses 474system.cpu.icache.demand_misses::total 8951 # number of demand (read+write) misses 475system.cpu.icache.overall_misses::cpu.inst 8951 # number of overall misses 476system.cpu.icache.overall_misses::total 8951 # number of overall misses 477system.cpu.icache.ReadReq_miss_latency::cpu.inst 259393998 # number of ReadReq miss cycles 478system.cpu.icache.ReadReq_miss_latency::total 259393998 # number of ReadReq miss cycles 479system.cpu.icache.demand_miss_latency::cpu.inst 259393998 # number of demand (read+write) miss cycles 480system.cpu.icache.demand_miss_latency::total 259393998 # number of demand (read+write) miss cycles 481system.cpu.icache.overall_miss_latency::cpu.inst 259393998 # number of overall miss cycles 482system.cpu.icache.overall_miss_latency::total 259393998 # number of overall miss cycles 483system.cpu.icache.ReadReq_accesses::cpu.inst 24446052 # number of ReadReq accesses(hits+misses) 484system.cpu.icache.ReadReq_accesses::total 24446052 # number of ReadReq accesses(hits+misses) 485system.cpu.icache.demand_accesses::cpu.inst 24446052 # number of demand (read+write) accesses 486system.cpu.icache.demand_accesses::total 24446052 # number of demand (read+write) accesses 487system.cpu.icache.overall_accesses::cpu.inst 24446052 # number of overall (read+write) accesses 488system.cpu.icache.overall_accesses::total 24446052 # number of overall (read+write) accesses | 471system.cpu.icache.ReadReq_misses::cpu.inst 8952 # number of ReadReq misses 472system.cpu.icache.ReadReq_misses::total 8952 # number of ReadReq misses 473system.cpu.icache.demand_misses::cpu.inst 8952 # number of demand (read+write) misses 474system.cpu.icache.demand_misses::total 8952 # number of demand (read+write) misses 475system.cpu.icache.overall_misses::cpu.inst 8952 # number of overall misses 476system.cpu.icache.overall_misses::total 8952 # number of overall misses 477system.cpu.icache.ReadReq_miss_latency::cpu.inst 259465998 # number of ReadReq miss cycles 478system.cpu.icache.ReadReq_miss_latency::total 259465998 # number of ReadReq miss cycles 479system.cpu.icache.demand_miss_latency::cpu.inst 259465998 # number of demand (read+write) miss cycles 480system.cpu.icache.demand_miss_latency::total 259465998 # number of demand (read+write) miss cycles 481system.cpu.icache.overall_miss_latency::cpu.inst 259465998 # number of overall miss cycles 482system.cpu.icache.overall_miss_latency::total 259465998 # number of overall miss cycles 483system.cpu.icache.ReadReq_accesses::cpu.inst 24446053 # number of ReadReq accesses(hits+misses) 484system.cpu.icache.ReadReq_accesses::total 24446053 # number of ReadReq accesses(hits+misses) 485system.cpu.icache.demand_accesses::cpu.inst 24446053 # number of demand (read+write) accesses 486system.cpu.icache.demand_accesses::total 24446053 # number of demand (read+write) accesses 487system.cpu.icache.overall_accesses::cpu.inst 24446053 # number of overall (read+write) accesses 488system.cpu.icache.overall_accesses::total 24446053 # number of overall (read+write) accesses |
| 489system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses 490system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses 491system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses 492system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses 493system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses 494system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses | 489system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses 490system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses 491system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses 492system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses 493system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses 494system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses |
| 495system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28979.331695 # average ReadReq miss latency 496system.cpu.icache.ReadReq_avg_miss_latency::total 28979.331695 # average ReadReq miss latency 497system.cpu.icache.demand_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency 498system.cpu.icache.demand_avg_miss_latency::total 28979.331695 # average overall miss latency 499system.cpu.icache.overall_avg_miss_latency::cpu.inst 28979.331695 # average overall miss latency 500system.cpu.icache.overall_avg_miss_latency::total 28979.331695 # average overall miss latency | 495system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28984.137399 # average ReadReq miss latency 496system.cpu.icache.ReadReq_avg_miss_latency::total 28984.137399 # average ReadReq miss latency 497system.cpu.icache.demand_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency 498system.cpu.icache.demand_avg_miss_latency::total 28984.137399 # average overall miss latency 499system.cpu.icache.overall_avg_miss_latency::cpu.inst 28984.137399 # average overall miss latency 500system.cpu.icache.overall_avg_miss_latency::total 28984.137399 # average overall miss latency |
| 501system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked 502system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 503system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked 504system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 505system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 # average number of cycles each access was blocked 506system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 507system.cpu.icache.fast_writes 0 # number of fast writes performed 508system.cpu.icache.cache_copies 0 # number of cache copies performed | 501system.cpu.icache.blocked_cycles::no_mshrs 676 # number of cycles access was blocked 502system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 503system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked 504system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 505system.cpu.icache.avg_blocked_cycles::no_mshrs 32.190476 # average number of cycles each access was blocked 506system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 507system.cpu.icache.fast_writes 0 # number of fast writes performed 508system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 509system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2096 # number of ReadReq MSHR hits 510system.cpu.icache.ReadReq_mshr_hits::total 2096 # number of ReadReq MSHR hits 511system.cpu.icache.demand_mshr_hits::cpu.inst 2096 # number of demand (read+write) MSHR hits 512system.cpu.icache.demand_mshr_hits::total 2096 # number of demand (read+write) MSHR hits 513system.cpu.icache.overall_mshr_hits::cpu.inst 2096 # number of overall MSHR hits 514system.cpu.icache.overall_mshr_hits::total 2096 # number of overall MSHR hits | 509system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2097 # number of ReadReq MSHR hits 510system.cpu.icache.ReadReq_mshr_hits::total 2097 # number of ReadReq MSHR hits 511system.cpu.icache.demand_mshr_hits::cpu.inst 2097 # number of demand (read+write) MSHR hits 512system.cpu.icache.demand_mshr_hits::total 2097 # number of demand (read+write) MSHR hits 513system.cpu.icache.overall_mshr_hits::cpu.inst 2097 # number of overall MSHR hits 514system.cpu.icache.overall_mshr_hits::total 2097 # number of overall MSHR hits |
| 515system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses 516system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses 517system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses 518system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses 519system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses 520system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses | 515system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6855 # number of ReadReq MSHR misses 516system.cpu.icache.ReadReq_mshr_misses::total 6855 # number of ReadReq MSHR misses 517system.cpu.icache.demand_mshr_misses::cpu.inst 6855 # number of demand (read+write) MSHR misses 518system.cpu.icache.demand_mshr_misses::total 6855 # number of demand (read+write) MSHR misses 519system.cpu.icache.overall_mshr_misses::cpu.inst 6855 # number of overall MSHR misses 520system.cpu.icache.overall_mshr_misses::total 6855 # number of overall MSHR misses |
| 521system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198301998 # number of ReadReq MSHR miss cycles 522system.cpu.icache.ReadReq_mshr_miss_latency::total 198301998 # number of ReadReq MSHR miss cycles 523system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198301998 # number of demand (read+write) MSHR miss cycles 524system.cpu.icache.demand_mshr_miss_latency::total 198301998 # number of demand (read+write) MSHR miss cycles 525system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198301998 # number of overall MSHR miss cycles 526system.cpu.icache.overall_mshr_miss_latency::total 198301998 # number of overall MSHR miss cycles | 521system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198302998 # number of ReadReq MSHR miss cycles 522system.cpu.icache.ReadReq_mshr_miss_latency::total 198302998 # number of ReadReq MSHR miss cycles 523system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198302998 # number of demand (read+write) MSHR miss cycles 524system.cpu.icache.demand_mshr_miss_latency::total 198302998 # number of demand (read+write) MSHR miss cycles 525system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198302998 # number of overall MSHR miss cycles 526system.cpu.icache.overall_mshr_miss_latency::total 198302998 # number of overall MSHR miss cycles |
| 527system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses 528system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses 529system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses 530system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses 531system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses 532system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses | 527system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for ReadReq accesses 528system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000280 # mshr miss rate for ReadReq accesses 529system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for demand accesses 530system.cpu.icache.demand_mshr_miss_rate::total 0.000280 # mshr miss rate for demand accesses 531system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000280 # mshr miss rate for overall accesses 532system.cpu.icache.overall_mshr_miss_rate::total 0.000280 # mshr miss rate for overall accesses |
| 533system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.081400 # average ReadReq mshr miss latency 534system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.081400 # average ReadReq mshr miss latency 535system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency 536system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency 537system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.081400 # average overall mshr miss latency 538system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.081400 # average overall mshr miss latency | 533system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28928.227279 # average ReadReq mshr miss latency 534system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28928.227279 # average ReadReq mshr miss latency 535system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency 536system.cpu.icache.demand_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency 537system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28928.227279 # average overall mshr miss latency 538system.cpu.icache.overall_avg_mshr_miss_latency::total 28928.227279 # average overall mshr miss latency |
| 539system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 539system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 540system.cpu.dcache.replacements 55 # number of replacements 541system.cpu.dcache.tagsinuse 1411.367255 # Cycle average of tags in use 542system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. 543system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. 544system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. 545system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 546system.cpu.dcache.occ_blocks::cpu.data 1411.367255 # Average occupied blocks per requestor 547system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy 548system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy 549system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits 550system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits 551system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits 552system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits 553system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits 554system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits 555system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits 556system.cpu.dcache.overall_hits::total 67560798 # number of overall hits 557system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses 558system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses 559system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses 560system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses 561system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses 562system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses 563system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses 564system.cpu.dcache.overall_misses::total 2513 # number of overall misses 565system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144500 # number of ReadReq miss cycles 566system.cpu.dcache.ReadReq_miss_latency::total 37144500 # number of ReadReq miss cycles 567system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles 568system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles 569system.cpu.dcache.demand_miss_latency::cpu.data 113997500 # number of demand (read+write) miss cycles 570system.cpu.dcache.demand_miss_latency::total 113997500 # number of demand (read+write) miss cycles 571system.cpu.dcache.overall_miss_latency::cpu.data 113997500 # number of overall miss cycles 572system.cpu.dcache.overall_miss_latency::total 113997500 # number of overall miss cycles 573system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses) 574system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses) 575system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 576system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 577system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses 578system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses 579system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses 580system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses 581system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 582system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 583system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses 584system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses 585system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses 586system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses 587system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses 588system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses 589system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.912769 # average ReadReq miss latency 590system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.912769 # average ReadReq miss latency 591system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency 592system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency 593system.cpu.dcache.demand_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency 594system.cpu.dcache.demand_avg_miss_latency::total 45363.111819 # average overall miss latency 595system.cpu.dcache.overall_avg_miss_latency::cpu.data 45363.111819 # average overall miss latency 596system.cpu.dcache.overall_avg_miss_latency::total 45363.111819 # average overall miss latency 597system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked 598system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 599system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 600system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 601system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked 602system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 603system.cpu.dcache.fast_writes 0 # number of fast writes performed 604system.cpu.dcache.cache_copies 0 # number of cache copies performed 605system.cpu.dcache.writebacks::writebacks 14 # number of writebacks 606system.cpu.dcache.writebacks::total 14 # number of writebacks 607system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits 608system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits 609system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 610system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits 611system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits 612system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits 613system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits 614system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits 615system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses 616system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses 617system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses 618system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses 619system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses 620system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses 621system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses 622system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses 623system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474500 # number of ReadReq MSHR miss cycles 624system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474500 # number of ReadReq MSHR miss cycles 625system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles 626system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles 627system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95774000 # number of demand (read+write) MSHR miss cycles 628system.cpu.dcache.demand_mshr_miss_latency::total 95774000 # number of demand (read+write) MSHR miss cycles 629system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95774000 # number of overall MSHR miss cycles 630system.cpu.dcache.overall_mshr_miss_latency::total 95774000 # number of overall MSHR miss cycles 631system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 632system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 633system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses 634system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses 635system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 636system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 637system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 638system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 639system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53895.683453 # average ReadReq mshr miss latency 640system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53895.683453 # average ReadReq mshr miss latency 641system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency 642system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency 643system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency 644system.cpu.dcache.demand_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency 645system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44817.033224 # average overall mshr miss latency 646system.cpu.dcache.overall_avg_mshr_miss_latency::total 44817.033224 # average overall mshr miss latency 647system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 648system.cpu.l2cache.replacements 0 # number of replacements | 540system.cpu.l2cache.replacements 0 # number of replacements |
| 649system.cpu.l2cache.tagsinuse 2509.913634 # Cycle average of tags in use | 541system.cpu.l2cache.tagsinuse 2509.913640 # Cycle average of tags in use |
| 650system.cpu.l2cache.total_refs 3332 # Total number of references to valid blocks. 651system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks. 652system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks. 653system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 654system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor | 542system.cpu.l2cache.total_refs 3332 # Total number of references to valid blocks. 543system.cpu.l2cache.sampled_refs 3792 # Sample count of references to valid blocks. 544system.cpu.l2cache.avg_refs 0.878692 # Average number of references to valid blocks. 545system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 546system.cpu.l2cache.occ_blocks::writebacks 0.902701 # Average occupied blocks per requestor |
| 655system.cpu.l2cache.occ_blocks::cpu.inst 2234.774408 # Average occupied blocks per requestor 656system.cpu.l2cache.occ_blocks::cpu.data 274.236525 # Average occupied blocks per requestor | 547system.cpu.l2cache.occ_blocks::cpu.inst 2234.774413 # Average occupied blocks per requestor 548system.cpu.l2cache.occ_blocks::cpu.data 274.236526 # Average occupied blocks per requestor |
| 657system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy 658system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy 659system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy 660system.cpu.l2cache.occ_percent::total 0.076596 # Average percentage of cache occupancy 661system.cpu.l2cache.ReadReq_hits::cpu.inst 3299 # number of ReadReq hits 662system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits 663system.cpu.l2cache.ReadReq_hits::total 3329 # number of ReadReq hits 664system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits --- 14 unchanged lines hidden (view full) --- 679system.cpu.l2cache.ReadExReq_misses::cpu.data 1560 # number of ReadExReq misses 680system.cpu.l2cache.ReadExReq_misses::total 1560 # number of ReadExReq misses 681system.cpu.l2cache.demand_misses::cpu.inst 3402 # number of demand (read+write) misses 682system.cpu.l2cache.demand_misses::cpu.data 1946 # number of demand (read+write) misses 683system.cpu.l2cache.demand_misses::total 5348 # number of demand (read+write) misses 684system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses 685system.cpu.l2cache.overall_misses::cpu.data 1946 # number of overall misses 686system.cpu.l2cache.overall_misses::total 5348 # number of overall misses | 549system.cpu.l2cache.occ_percent::writebacks 0.000028 # Average percentage of cache occupancy 550system.cpu.l2cache.occ_percent::cpu.inst 0.068200 # Average percentage of cache occupancy 551system.cpu.l2cache.occ_percent::cpu.data 0.008369 # Average percentage of cache occupancy 552system.cpu.l2cache.occ_percent::total 0.076596 # Average percentage of cache occupancy 553system.cpu.l2cache.ReadReq_hits::cpu.inst 3299 # number of ReadReq hits 554system.cpu.l2cache.ReadReq_hits::cpu.data 30 # number of ReadReq hits 555system.cpu.l2cache.ReadReq_hits::total 3329 # number of ReadReq hits 556system.cpu.l2cache.Writeback_hits::writebacks 14 # number of Writeback hits --- 14 unchanged lines hidden (view full) --- 571system.cpu.l2cache.ReadExReq_misses::cpu.data 1560 # number of ReadExReq misses 572system.cpu.l2cache.ReadExReq_misses::total 1560 # number of ReadExReq misses 573system.cpu.l2cache.demand_misses::cpu.inst 3402 # number of demand (read+write) misses 574system.cpu.l2cache.demand_misses::cpu.data 1946 # number of demand (read+write) misses 575system.cpu.l2cache.demand_misses::total 5348 # number of demand (read+write) misses 576system.cpu.l2cache.overall_misses::cpu.inst 3402 # number of overall misses 577system.cpu.l2cache.overall_misses::cpu.data 1946 # number of overall misses 578system.cpu.l2cache.overall_misses::total 5348 # number of overall misses |
| 687system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158303000 # number of ReadReq miss cycles 688system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677500 # number of ReadReq miss cycles 689system.cpu.l2cache.ReadReq_miss_latency::total 179980500 # number of ReadReq miss cycles | 579system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 158304000 # number of ReadReq miss cycles 580system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21677000 # number of ReadReq miss cycles 581system.cpu.l2cache.ReadReq_miss_latency::total 179981000 # number of ReadReq miss cycles |
| 690system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68234000 # number of ReadExReq miss cycles 691system.cpu.l2cache.ReadExReq_miss_latency::total 68234000 # number of ReadExReq miss cycles | 582system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68234000 # number of ReadExReq miss cycles 583system.cpu.l2cache.ReadExReq_miss_latency::total 68234000 # number of ReadExReq miss cycles |
| 692system.cpu.l2cache.demand_miss_latency::cpu.inst 158303000 # number of demand (read+write) miss cycles 693system.cpu.l2cache.demand_miss_latency::cpu.data 89911500 # number of demand (read+write) miss cycles 694system.cpu.l2cache.demand_miss_latency::total 248214500 # number of demand (read+write) miss cycles 695system.cpu.l2cache.overall_miss_latency::cpu.inst 158303000 # number of overall miss cycles 696system.cpu.l2cache.overall_miss_latency::cpu.data 89911500 # number of overall miss cycles 697system.cpu.l2cache.overall_miss_latency::total 248214500 # number of overall miss cycles | 584system.cpu.l2cache.demand_miss_latency::cpu.inst 158304000 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::cpu.data 89911000 # number of demand (read+write) miss cycles 586system.cpu.l2cache.demand_miss_latency::total 248215000 # number of demand (read+write) miss cycles 587system.cpu.l2cache.overall_miss_latency::cpu.inst 158304000 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::cpu.data 89911000 # number of overall miss cycles 589system.cpu.l2cache.overall_miss_latency::total 248215000 # number of overall miss cycles |
| 698system.cpu.l2cache.ReadReq_accesses::cpu.inst 6701 # number of ReadReq accesses(hits+misses) 699system.cpu.l2cache.ReadReq_accesses::cpu.data 416 # number of ReadReq accesses(hits+misses) 700system.cpu.l2cache.ReadReq_accesses::total 7117 # number of ReadReq accesses(hits+misses) 701system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) 702system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) 703system.cpu.l2cache.UpgradeReq_accesses::cpu.data 154 # number of UpgradeReq accesses(hits+misses) 704system.cpu.l2cache.UpgradeReq_accesses::total 154 # number of UpgradeReq accesses(hits+misses) 705system.cpu.l2cache.ReadExReq_accesses::cpu.data 1567 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 718system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995533 # miss rate for ReadExReq accesses 719system.cpu.l2cache.ReadExReq_miss_rate::total 0.995533 # miss rate for ReadExReq accesses 720system.cpu.l2cache.demand_miss_rate::cpu.inst 0.507685 # miss rate for demand accesses 721system.cpu.l2cache.demand_miss_rate::cpu.data 0.981341 # miss rate for demand accesses 722system.cpu.l2cache.demand_miss_rate::total 0.615845 # miss rate for demand accesses 723system.cpu.l2cache.overall_miss_rate::cpu.inst 0.507685 # miss rate for overall accesses 724system.cpu.l2cache.overall_miss_rate::cpu.data 0.981341 # miss rate for overall accesses 725system.cpu.l2cache.overall_miss_rate::total 0.615845 # miss rate for overall accesses | 590system.cpu.l2cache.ReadReq_accesses::cpu.inst 6701 # number of ReadReq accesses(hits+misses) 591system.cpu.l2cache.ReadReq_accesses::cpu.data 416 # number of ReadReq accesses(hits+misses) 592system.cpu.l2cache.ReadReq_accesses::total 7117 # number of ReadReq accesses(hits+misses) 593system.cpu.l2cache.Writeback_accesses::writebacks 14 # number of Writeback accesses(hits+misses) 594system.cpu.l2cache.Writeback_accesses::total 14 # number of Writeback accesses(hits+misses) 595system.cpu.l2cache.UpgradeReq_accesses::cpu.data 154 # number of UpgradeReq accesses(hits+misses) 596system.cpu.l2cache.UpgradeReq_accesses::total 154 # number of UpgradeReq accesses(hits+misses) 597system.cpu.l2cache.ReadExReq_accesses::cpu.data 1567 # number of ReadExReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 610system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.995533 # miss rate for ReadExReq accesses 611system.cpu.l2cache.ReadExReq_miss_rate::total 0.995533 # miss rate for ReadExReq accesses 612system.cpu.l2cache.demand_miss_rate::cpu.inst 0.507685 # miss rate for demand accesses 613system.cpu.l2cache.demand_miss_rate::cpu.data 0.981341 # miss rate for demand accesses 614system.cpu.l2cache.demand_miss_rate::total 0.615845 # miss rate for demand accesses 615system.cpu.l2cache.overall_miss_rate::cpu.inst 0.507685 # miss rate for overall accesses 616system.cpu.l2cache.overall_miss_rate::cpu.data 0.981341 # miss rate for overall accesses 617system.cpu.l2cache.overall_miss_rate::total 0.615845 # miss rate for overall accesses |
| 726system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.333921 # average ReadReq miss latency 727system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56159.326425 # average ReadReq miss latency 728system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.331573 # average ReadReq miss latency | 618system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46532.627866 # average ReadReq miss latency 619system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56158.031088 # average ReadReq miss latency 620system.cpu.l2cache.ReadReq_avg_miss_latency::total 47513.463569 # average ReadReq miss latency |
| 729system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43739.743590 # average ReadExReq miss latency 730system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43739.743590 # average ReadExReq miss latency | 621system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43739.743590 # average ReadExReq miss latency 622system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43739.743590 # average ReadExReq miss latency |
| 731system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency 732system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency 733system.cpu.l2cache.demand_avg_miss_latency::total 46412.584144 # average overall miss latency 734system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.333921 # average overall miss latency 735system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46203.237410 # average overall miss latency 736system.cpu.l2cache.overall_avg_miss_latency::total 46412.584144 # average overall miss latency | 623system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency 624system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency 625system.cpu.l2cache.demand_avg_miss_latency::total 46412.677636 # average overall miss latency 626system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46532.627866 # average overall miss latency 627system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46202.980473 # average overall miss latency 628system.cpu.l2cache.overall_avg_miss_latency::total 46412.677636 # average overall miss latency |
| 737system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 738system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 740system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 741system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 742system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu.l2cache.fast_writes 0 # number of fast writes performed 744system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 750system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1560 # number of ReadExReq MSHR misses 751system.cpu.l2cache.ReadExReq_mshr_misses::total 1560 # number of ReadExReq MSHR misses 752system.cpu.l2cache.demand_mshr_misses::cpu.inst 3402 # number of demand (read+write) MSHR misses 753system.cpu.l2cache.demand_mshr_misses::cpu.data 1946 # number of demand (read+write) MSHR misses 754system.cpu.l2cache.demand_mshr_misses::total 5348 # number of demand (read+write) MSHR misses 755system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses 756system.cpu.l2cache.overall_mshr_misses::cpu.data 1946 # number of overall MSHR misses 757system.cpu.l2cache.overall_mshr_misses::total 5348 # number of overall MSHR misses | 629system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 630system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 631system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 632system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 633system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 634system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 635system.cpu.l2cache.fast_writes 0 # number of fast writes performed 636system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 5 unchanged lines hidden (view full) --- 642system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1560 # number of ReadExReq MSHR misses 643system.cpu.l2cache.ReadExReq_mshr_misses::total 1560 # number of ReadExReq MSHR misses 644system.cpu.l2cache.demand_mshr_misses::cpu.inst 3402 # number of demand (read+write) MSHR misses 645system.cpu.l2cache.demand_mshr_misses::cpu.data 1946 # number of demand (read+write) MSHR misses 646system.cpu.l2cache.demand_mshr_misses::total 5348 # number of demand (read+write) MSHR misses 647system.cpu.l2cache.overall_mshr_misses::cpu.inst 3402 # number of overall MSHR misses 648system.cpu.l2cache.overall_mshr_misses::cpu.data 1946 # number of overall MSHR misses 649system.cpu.l2cache.overall_mshr_misses::total 5348 # number of overall MSHR misses |
| 758system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394483 # number of ReadReq MSHR miss cycles 759system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844598 # number of ReadReq MSHR miss cycles | 650system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115394983 # number of ReadReq MSHR miss cycles 651system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16844098 # number of ReadReq MSHR miss cycles |
| 760system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles 761system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles 762system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles 763system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles 764system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles | 652system.cpu.l2cache.ReadReq_mshr_miss_latency::total 132239081 # number of ReadReq MSHR miss cycles 653system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1540154 # number of UpgradeReq MSHR miss cycles 654system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1540154 # number of UpgradeReq MSHR miss cycles 655system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48432493 # number of ReadExReq MSHR miss cycles 656system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48432493 # number of ReadExReq MSHR miss cycles |
| 765system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394483 # number of demand (read+write) MSHR miss cycles 766system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65277091 # number of demand (read+write) MSHR miss cycles | 657system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115394983 # number of demand (read+write) MSHR miss cycles 658system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65276591 # number of demand (read+write) MSHR miss cycles |
| 767system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles | 659system.cpu.l2cache.demand_mshr_miss_latency::total 180671574 # number of demand (read+write) MSHR miss cycles |
| 768system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394483 # number of overall MSHR miss cycles 769system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65277091 # number of overall MSHR miss cycles | 660system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115394983 # number of overall MSHR miss cycles 661system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65276591 # number of overall MSHR miss cycles |
| 770system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles 771system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses 772system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses 773system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532247 # mshr miss rate for ReadReq accesses 774system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 775system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 776system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995533 # mshr miss rate for ReadExReq accesses 777system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995533 # mshr miss rate for ReadExReq accesses 778system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for demand accesses 779system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for demand accesses 780system.cpu.l2cache.demand_mshr_miss_rate::total 0.615845 # mshr miss rate for demand accesses 781system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for overall accesses 782system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for overall accesses 783system.cpu.l2cache.overall_mshr_miss_rate::total 0.615845 # mshr miss rate for overall accesses | 662system.cpu.l2cache.overall_mshr_miss_latency::total 180671574 # number of overall MSHR miss cycles 663system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for ReadReq accesses 664system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927885 # mshr miss rate for ReadReq accesses 665system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532247 # mshr miss rate for ReadReq accesses 666system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 667system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 668system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995533 # mshr miss rate for ReadExReq accesses 669system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995533 # mshr miss rate for ReadExReq accesses 670system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for demand accesses 671system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for demand accesses 672system.cpu.l2cache.demand_mshr_miss_rate::total 0.615845 # mshr miss rate for demand accesses 673system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.507685 # mshr miss rate for overall accesses 674system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.981341 # mshr miss rate for overall accesses 675system.cpu.l2cache.overall_mshr_miss_rate::total 0.615845 # mshr miss rate for overall accesses |
| 784system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.601117 # average ReadReq mshr miss latency 785system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43638.854922 # average ReadReq mshr miss latency | 676system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33919.748089 # average ReadReq mshr miss latency 677system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43637.559585 # average ReadReq mshr miss latency |
| 786system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency 787system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 788system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 789system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency 790system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency | 678system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34910.000264 # average ReadReq mshr miss latency 679system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 680system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 681system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31046.469872 # average ReadExReq mshr miss latency 682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31046.469872 # average ReadExReq mshr miss latency |
| 791system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency 792system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency | 683system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency 684system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency |
| 793system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency | 685system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency |
| 794system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.601117 # average overall mshr miss latency 795system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33544.239979 # average overall mshr miss latency | 686system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33919.748089 # average overall mshr miss latency 687system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33543.983042 # average overall mshr miss latency |
| 796system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency 797system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 688system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33783.016829 # average overall mshr miss latency 689system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 690system.cpu.dcache.replacements 55 # number of replacements 691system.cpu.dcache.tagsinuse 1411.367257 # Cycle average of tags in use 692system.cpu.dcache.total_refs 67560996 # Total number of references to valid blocks. 693system.cpu.dcache.sampled_refs 1981 # Sample count of references to valid blocks. 694system.cpu.dcache.avg_refs 34104.490661 # Average number of references to valid blocks. 695system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 696system.cpu.dcache.occ_blocks::cpu.data 1411.367257 # Average occupied blocks per requestor 697system.cpu.dcache.occ_percent::cpu.data 0.344572 # Average percentage of cache occupancy 698system.cpu.dcache.occ_percent::total 0.344572 # Average percentage of cache occupancy 699system.cpu.dcache.ReadReq_hits::cpu.data 47046789 # number of ReadReq hits 700system.cpu.dcache.ReadReq_hits::total 47046789 # number of ReadReq hits 701system.cpu.dcache.WriteReq_hits::cpu.data 20514009 # number of WriteReq hits 702system.cpu.dcache.WriteReq_hits::total 20514009 # number of WriteReq hits 703system.cpu.dcache.demand_hits::cpu.data 67560798 # number of demand (read+write) hits 704system.cpu.dcache.demand_hits::total 67560798 # number of demand (read+write) hits 705system.cpu.dcache.overall_hits::cpu.data 67560798 # number of overall hits 706system.cpu.dcache.overall_hits::total 67560798 # number of overall hits 707system.cpu.dcache.ReadReq_misses::cpu.data 791 # number of ReadReq misses 708system.cpu.dcache.ReadReq_misses::total 791 # number of ReadReq misses 709system.cpu.dcache.WriteReq_misses::cpu.data 1722 # number of WriteReq misses 710system.cpu.dcache.WriteReq_misses::total 1722 # number of WriteReq misses 711system.cpu.dcache.demand_misses::cpu.data 2513 # number of demand (read+write) misses 712system.cpu.dcache.demand_misses::total 2513 # number of demand (read+write) misses 713system.cpu.dcache.overall_misses::cpu.data 2513 # number of overall misses 714system.cpu.dcache.overall_misses::total 2513 # number of overall misses 715system.cpu.dcache.ReadReq_miss_latency::cpu.data 37144000 # number of ReadReq miss cycles 716system.cpu.dcache.ReadReq_miss_latency::total 37144000 # number of ReadReq miss cycles 717system.cpu.dcache.WriteReq_miss_latency::cpu.data 76853000 # number of WriteReq miss cycles 718system.cpu.dcache.WriteReq_miss_latency::total 76853000 # number of WriteReq miss cycles 719system.cpu.dcache.demand_miss_latency::cpu.data 113997000 # number of demand (read+write) miss cycles 720system.cpu.dcache.demand_miss_latency::total 113997000 # number of demand (read+write) miss cycles 721system.cpu.dcache.overall_miss_latency::cpu.data 113997000 # number of overall miss cycles 722system.cpu.dcache.overall_miss_latency::total 113997000 # number of overall miss cycles 723system.cpu.dcache.ReadReq_accesses::cpu.data 47047580 # number of ReadReq accesses(hits+misses) 724system.cpu.dcache.ReadReq_accesses::total 47047580 # number of ReadReq accesses(hits+misses) 725system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) 726system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) 727system.cpu.dcache.demand_accesses::cpu.data 67563311 # number of demand (read+write) accesses 728system.cpu.dcache.demand_accesses::total 67563311 # number of demand (read+write) accesses 729system.cpu.dcache.overall_accesses::cpu.data 67563311 # number of overall (read+write) accesses 730system.cpu.dcache.overall_accesses::total 67563311 # number of overall (read+write) accesses 731system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 732system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 733system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000084 # miss rate for WriteReq accesses 734system.cpu.dcache.WriteReq_miss_rate::total 0.000084 # miss rate for WriteReq accesses 735system.cpu.dcache.demand_miss_rate::cpu.data 0.000037 # miss rate for demand accesses 736system.cpu.dcache.demand_miss_rate::total 0.000037 # miss rate for demand accesses 737system.cpu.dcache.overall_miss_rate::cpu.data 0.000037 # miss rate for overall accesses 738system.cpu.dcache.overall_miss_rate::total 0.000037 # miss rate for overall accesses 739system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46958.280657 # average ReadReq miss latency 740system.cpu.dcache.ReadReq_avg_miss_latency::total 46958.280657 # average ReadReq miss latency 741system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44630.081301 # average WriteReq miss latency 742system.cpu.dcache.WriteReq_avg_miss_latency::total 44630.081301 # average WriteReq miss latency 743system.cpu.dcache.demand_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency 744system.cpu.dcache.demand_avg_miss_latency::total 45362.912853 # average overall miss latency 745system.cpu.dcache.overall_avg_miss_latency::cpu.data 45362.912853 # average overall miss latency 746system.cpu.dcache.overall_avg_miss_latency::total 45362.912853 # average overall miss latency 747system.cpu.dcache.blocked_cycles::no_mshrs 86 # number of cycles access was blocked 748system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 749system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 750system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 751system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked 752system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 753system.cpu.dcache.fast_writes 0 # number of fast writes performed 754system.cpu.dcache.cache_copies 0 # number of cache copies performed 755system.cpu.dcache.writebacks::writebacks 14 # number of writebacks 756system.cpu.dcache.writebacks::total 14 # number of writebacks 757system.cpu.dcache.ReadReq_mshr_hits::cpu.data 374 # number of ReadReq MSHR hits 758system.cpu.dcache.ReadReq_mshr_hits::total 374 # number of ReadReq MSHR hits 759system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits 760system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits 761system.cpu.dcache.demand_mshr_hits::cpu.data 376 # number of demand (read+write) MSHR hits 762system.cpu.dcache.demand_mshr_hits::total 376 # number of demand (read+write) MSHR hits 763system.cpu.dcache.overall_mshr_hits::cpu.data 376 # number of overall MSHR hits 764system.cpu.dcache.overall_mshr_hits::total 376 # number of overall MSHR hits 765system.cpu.dcache.ReadReq_mshr_misses::cpu.data 417 # number of ReadReq MSHR misses 766system.cpu.dcache.ReadReq_mshr_misses::total 417 # number of ReadReq MSHR misses 767system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1720 # number of WriteReq MSHR misses 768system.cpu.dcache.WriteReq_mshr_misses::total 1720 # number of WriteReq MSHR misses 769system.cpu.dcache.demand_mshr_misses::cpu.data 2137 # number of demand (read+write) MSHR misses 770system.cpu.dcache.demand_mshr_misses::total 2137 # number of demand (read+write) MSHR misses 771system.cpu.dcache.overall_mshr_misses::cpu.data 2137 # number of overall MSHR misses 772system.cpu.dcache.overall_mshr_misses::total 2137 # number of overall MSHR misses 773system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22474000 # number of ReadReq MSHR miss cycles 774system.cpu.dcache.ReadReq_mshr_miss_latency::total 22474000 # number of ReadReq MSHR miss cycles 775system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73299500 # number of WriteReq MSHR miss cycles 776system.cpu.dcache.WriteReq_mshr_miss_latency::total 73299500 # number of WriteReq MSHR miss cycles 777system.cpu.dcache.demand_mshr_miss_latency::cpu.data 95773500 # number of demand (read+write) MSHR miss cycles 778system.cpu.dcache.demand_mshr_miss_latency::total 95773500 # number of demand (read+write) MSHR miss cycles 779system.cpu.dcache.overall_mshr_miss_latency::cpu.data 95773500 # number of overall MSHR miss cycles 780system.cpu.dcache.overall_mshr_miss_latency::total 95773500 # number of overall MSHR miss cycles 781system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses 782system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses 783system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for WriteReq accesses 784system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000084 # mshr miss rate for WriteReq accesses 785system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses 786system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses 787system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses 788system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses 789system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53894.484412 # average ReadReq mshr miss latency 790system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53894.484412 # average ReadReq mshr miss latency 791system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42615.988372 # average WriteReq mshr miss latency 792system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42615.988372 # average WriteReq mshr miss latency 793system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency 794system.cpu.dcache.demand_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency 795system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44816.799251 # average overall mshr miss latency 796system.cpu.dcache.overall_avg_mshr_miss_latency::total 44816.799251 # average overall mshr miss latency 797system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
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| 798 799---------- End Simulation Statistics ---------- | 798 799---------- End Simulation Statistics ---------- |